IRFIB7N50LPBF [INFINEON]
SMPS MOSFET, HEXFET Power MOSFET; 开关电源MOSFET ， HEXFET功率MOSFET
| 型号： | IRFIB7N50LPBF |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET, HEXFET Power MOSFET |
| 文件： | 总9页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95750
IRFIB7N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
Trr typ.
VDSS RDS(on)
ID
typ.
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
500V
85ns 6.8A
320mΩ
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
immunity.
TO-220 Full-Pak
Absolute Maximum Ratings
Parameter
Max.
6.8
4.3
27
Units
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM
Pulsed Drain Current
PD @TC = 25°C
Power Dissipation
46
W
Linear Derating Factor
Gate-to-Source Voltage
0.37
±30
W/°C
V
VGS
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
24
V/ns
-55 to + 150
TSTG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
10lb in (1.1N m)
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
––– ––– 6.8
Conditions
MOSFET symbol
D
I
S
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
I
––– –––
27
SM
S
(Body Diode)
p-n junction diode.
V
t
T = 25°C, I = 6.8A, V = 0V
J S GS
Diode Forward Voltage
––– ––– 1.5
––– 85 130
––– 130 200
V
SD
T = 25°C, I = 6.8A
Reverse Recovery Time
Reverse Recovery Charge
ns
rr
J
F
TJ = 125°C, di/dt = 100A/µs
Q
T = 25°C, I = 6.8A, V = 0V
––– 280 420 nC
––– 570 860
rr
J
S
GS
TJ = 125°C, di/dt = 100A/µs
IRRM
T = 25°C
J
Reverse Recovery Current
Forward Turn-On Time
––– 5.9
8.9
A
t
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
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1
8/23/04
IRFIB7N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500
–––
–––
3.0
–––
–––
V
∆
∆
V(BR)DSS/ TJ
0.44
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
IDSS
0.32 0.38
V
GS = 10V, ID = 4.1A
VDS = VGS, ID = 250µA
VDS = 500V, VGS = 0V
Ω
V
–––
–––
–––
–––
5.0
50
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
µA
2.0
100
mA VDS = 400V, VGS = 0V, TJ = 125°C
nA VGS = 30V
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
––– -100
0.88 –––
VGS = -30V
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 4.1A
gfs
Qg
4.7
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
23
–––
S
92
ID = 6.8A
Qgs
Qgd
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
24
nC VDS = 400V
44
V
GS = 10V, See Fig. 7 & 16
td(on)
–––
–––
–––
–––
VDD = 250V
ns ID = 6.8A
tr
36
td(off)
Ω
Turn-Off Delay Time
Fall Time
47
RG = 9.0
GS = 10V, See Fig. 11a & 11b
VGS = 0V
DS = 25V
tf
19
V
Ciss
Input Capacitance
––– 2220 –––
Coss
Output Capacitance
–––
–––
230
23
–––
–––
V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss
––– 2780 –––
pF
Coss
Output Capacitance
–––
–––
–––
63
–––
–––
–––
Coss eff.
Coss eff. (ER)
Effective Output Capacitance
Effective Output Capacitance
140
100
VGS = 0V,VDS = 0V to 400V
(Energy Related)
Avalanche Characteristics
Symbol
Parameter
Typ.
–––
–––
–––
Max.
550
6.8
Units
mJ
A
Single Pulse Avalanche Energy
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
4.6
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Junction-to-Ambient
Typ.
–––
Max.
2.69
65
Units
°C/W
RθJC
RθJA
–––
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 12).
Starting TJ = 25°C, L = 24mH, RG = 25Ω,
IAS = 6.8A, (See Figure 14).
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS
.
ISD ≤ 6.8, di/dt ≤ 650A/µs, VDD ≤ V(BR)DSS
dv/dt = 24V/ns, TJ ≤ 150°C.
,
.
2
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IRFIB7N50LPbF
100
10
1
100
10
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
TOP
TOP
BOTTOM
BOTTOM
5.0V
1
5.0V
5.0V
0.1
0.01
60µs PULSE WIDTH
≤
Tj = 150°C
60µs PULSE WIDTH
Tj = 25°C
≤
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
I
= 6.8A
D
V
= 10V
GS
2.5
2.0
1.5
1.0
0.5
0.0
T = 175°C
J
10
1
T
= 25°C
= 50V
J
V
DS
≤
60µs PULSE WIDTH
0.1
3
4
5
6
7
8
9
-60 -40 -20
0
20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRFIB7N50LPbF
12
10
8
100000
V
= 0V,
= C
f = 1 MHZ
GS
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
rss
oss
gd
= C + C
ds
gd
10000
1000
100
C
iss
6
C
oss
4
2
C
rss
0
10
0
50 100 150 200 250 300 350 400 450 500 550
Drain-to-Source Voltage (V)
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
DS,
Fig 5. Typical Capacitance vs.
Fig 6. Typ. Output Capacitance
Drain-to-Source Voltage
Stored Energy vs. VDS
12.0
10.0
8.0
100.00
10.00
1.00
I = 6.8A
D
V
= 400V
DS
T
= 150°C
J
6.0
4.0
T
= 25°C
J
0.10
2.0
V
= 0V
GS
0.0
0.01
0
10
20
30
40
50
60
70
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Q
Total Gate Charge (nC)
V
, Source-to-Drain Voltage (V)
G
SD
Fig 8. Typical Source-Drain Diode
Fig 7. Typical Gate Charge vs.
ForwardVoltage
Gate-to-SourceVoltage
4
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IRFIB7N50LPbF
100
10
7
6
5
4
3
2
1
0
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100µsec
1
DC
0.1
0.01
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1000
25
50
T
75
100
125
150
1
10
100
10000
V
, Drain-to-Source Voltage (V)
, Case Temperature (°C)
C
DS
Fig 9. Maximum Safe Operating Area
Fig 10. Maximum Drain Current vs.
CaseTemperature
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+VDD
-
10%
10V
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
t
t
r
t
t
f
d(on)
d(off)
Fig 11b. Switching Time Waveforms
Fig 11a. Switching Time Test Circuit
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IRFIB7N50LPbF
10
D = 0.50
1
0.20
0.10
0.05
0.1
R1
R1
R2
R2
R3
R3
0.02
0.01
Ri (°C/W) τi (sec)
τ
J τJ
τ
τ
Cτ
0.2965
0.9847
1.4118
0.001144
0.151939
1.705500
0.01
τ
1τ1
τ
2 τ2
3τ3
Ci= τi/Ri
SINGLE PULSE
0.001
Notes:
( THERMAL RESPONSE )
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5.0
4.0
I
= 250µA
D
3.0
2.0
1.0
-75 -50 -25
0
25
50
75 100 125 150
T
, Temperature ( °C )
J
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB7N50LPbF
2500
2000
1500
1000
500
I
D
TOP
1.4A
1.7A
BOTTOM 6.8A
0
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
Fig 14. Maximum Avalanche Energy
vs. Drain Current
15V
V
(BR)DSS
t
p
DRIVER
L
V
DS
D.U.T
AS
R
G
+
-
V
DD
I
A
20V
0.01Ω
t
p
I
AS
Fig 15b. Unclamped Inductive Waveforms
Fig 15a. Unclamped Inductive Test Circuit
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
10 V
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 16b. Basic Gate Charge Waveform
Fig 16a. Gate Charge Test Circuit
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7
IRFIB7N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET® Power MOSFETs
8
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IRFIB7N50LPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
EXAMP LE: THIS IS AN IRFI840 G
WITH AS S EMBLY
LO T CO DE 3 43 2
INT E RNAT IO NAL
P ART NUMBER
IRFI84 0G
9 24 K
3 2
AS S EMBLED O N WW 24 199 9
RE CT IF IE R
LO G O
IN THE AS S EMBLY LINE "K"
34
DATE CO DE
YEAR 9 = 199 9
WEEK 24
Note: "P" in assembly line
position indicates "Lead-Free"
AS S EMBLY
LO T CO DE
LINE K
TO-220AB FullPak package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/04
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