IRFP4468 [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
| 型号： | IRFP4468 |
| 厂家： | 
Infineon |
| 描述： | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
| 文件： | 总9页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD -97134
IRFP4468PbF
HEXFET® Power MOSFET
Applications
D
VDSS
RDS(on) typ.
100V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
2.0m
2.6m
:
:
max.
G
ID
ID
290A
c
(Silicon Limited)
195A
S
(Package Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
D
G
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
290c
200
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current d
195
1120
520
PD @TC = 25°C
Maximum Power Dissipation
Linear Derating Factor
W
3.4
W/°C
V
VGS
± 20
Gate-to-Source Voltage
10
Peak Diode Recovery f
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
740
mJ
A
Avalanche Currentꢀd
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.29
–––
40
Units
RθJC
RθCS
RθJA
Junction-to-Case k
Case-to-Sink, Flat Greased Surface
0.24
–––
°C/W
Junction-to-Ambient jk
www.irf.com
1
5/21/08
IRFP4468PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
100 ––– –––
––– 0.09 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250μA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
2.0
2.0
2.6
4.0
20
VGS = 10V, ID = 180A g
VDS = VGS, ID = 250μA
mΩ
V
VGS(th)
–––
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 125°C
nA VGS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = -20V
–––
0.8
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 180A
310 ––– –––
S
Qg
––– 360 540
nC ID = 180A
VDS =50V
Qgs
Gate-to-Source Charge
–––
–––
81
89
–––
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
V
GS = 10V g
ID = 180A, VDS =0V, VGS = 10V
ns VDD = 65V
Qsync
––– 270 –––
––– 52 –––
td(on)
tr
Rise Time
––– 230 –––
––– 160 –––
––– 260 –––
––– 19860 –––
––– 1360 –––
––– 540 –––
––– 1550 –––
––– 900 –––
ID = 180A
td(off)
Turn-Off Delay Time
RG = 2.7Ω
VGS = 10V g
tf
Fall Time
Ciss
Input Capacitance
pF VGS = 0V
Coss
Output Capacitance
VDS = 50V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)h
ƒ = 100 kHz, See Fig. 5
VGS = 0V, VDS = 0V to 80V i, See Fig. 11
VGS = 0V, VDS = 0V to 80V h
Coss eff. (ER)
Coss eff. (TR)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
290c
D
(Body Diode)
showing the
ISM
Pulsed Source Current
––– ––– 1120
A
integral reverse
G
(Body Diode)ꢀd
p-n junction diode.
S
VSD
trr
Diode Forward Voltage
––– –––
––– 100
––– 110
––– 370
––– 420
1.3
V
TJ = 25°C, IS = 180A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
Reverse Recovery Time
Reverse Recovery Charge
ns
IF = 180A
di/dt = 100A/μs g
Qrr
nC
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
6.9
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
ISD ≤ 180A, di/dt ≤ 600A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.045mH
RG = 25Ω, IAS = 180A, VGS =10V. Part not recommended for use
above this value .
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
2
www.irf.com
IRFP4468PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
TOP
TOP
BOTTOM
BOTTOM
4.0V
4.0V
≤ 60μs PULSE WIDTH
Tj = 25°C
≤ 60μs PULSE WIDTH
Tj = 175°C
1
0.01
0.1
1
10
100
0.1
1
10
, Drain-to-Source Voltage (V)
DS
100
V
, Drain-to-Source Voltage (V)
V
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 180A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
V
DS
≤ 60μs PULSE WIDTH
1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
16
35000
30000
25000
20000
15000
10000
5000
0
V
C
= 0V,
f = 100 kHz
GS
I
= 180A
D
= C + C , C SHORTED
iss
gs
gd ds
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
C
= C
rss
gd
C
= C + C
ds
12
8
oss
gd
Ciss
4
Coss
Crss
0
0
50 100 150 200 250 300 350 400 450
Total Gate Charge (nC)
1
10
100
Q
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
www.irf.com
3
IRFP4468PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100μsec
1msec
T
= 25°C
J
LIMITED BY PACKAGE
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
300
250
200
150
100
50
120
110
100
90
LIMITED BY PACKAGE
I
= 5mA
D
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3000
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
I
D
TOP
30A
2500
2000
1500
1000
500
41A
180A
BOTTOM
0
25
50
75
100
125
150
175
0
20
40
60
80
100
Starting T , Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
www.irf.com
IRFP4468PbF
1
0.1
D = 0.50
0.20
0.10
R1
R1
R2
R2
R3
R3
0.05
0.02
τι (sec)
Ri (°C/W)
0.01
τ
J τJ
τ
τ
Cτ
0.063359 0.000278
0.110878 0.005836
0.114838 0.053606
τ
1 τ1
τ
2 τ2
3τ3
0.01
Ci= τi/Ri
Ci= τi/Ri
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1% Duty Cycle
= 180A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRFP4468PbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
32
24
16
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
I
= 72A
= 85V
F
V
R
T
= 125°C
J
T
= 25°C
J
0
1.0
100 200 300 400 500 600 700 800 900 1000
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
di / dt - (A / μs)
T
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
1500
40
32
24
16
1000
500
0
I
= 72A
= 85V
I
= 108A
= 85V
F
F
V
V
R
R
8
0
T
= 125°C
T
= 125°C
= 25°C
J
J
T
= 25°C
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
2000
I
= 108A
= 85V
F
V
T
R
= 125°C
= 25°C
J
1500
1000
500
0
T
J
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
www.irf.com
IRFP4468PbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
www.irf.com
7
IRFP4468PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: THIS IS AN IRFPE30
WIT H AS S E MB L Y
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 5657
ASSEMBLED ON WW 35, 2001
IN THE ASSEMBLY LINE "H"
IRFPE30
135H
57
56
DATE CODE
YEAR 1 = 2001
WEEK 35
AS S E MB L Y
LOT CODE
Note: "P" in assembly lineposition
indicates "Lead-F ree"
LINE H
TO-247AC packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/08
www.irf.com
8
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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