IRFR1018ETRPBF [INFINEON]
Power Field-Effect Transistor, 56A I(D), 60V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, DPAK-3;
| 型号： | IRFR1018ETRPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 56A I(D), 60V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, DPAK-3 |
| 文件： | 总10页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97129A
IRFR1018EPbF
IRFU1018EPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in
SMPS
D
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
60V
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
7.1m
8.4m
:
:
G
79A
c
56A
Benefits
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
l Enhanced body diode dV/dt and dI/dt
Capability
D-Pak
I-Pak
IRFR1018EPbF IRFU1018EPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
79c
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
56c
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current d
56
A
315
PD @TC = 25°C
110
Maximum Power Dissipation
Linear Derating Factor
W
0.76
W/°C
V
VGS
± 20
Gate-to-Source Voltage
21
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
88
47
11
mJ
A
Avalanche Current d
IAR
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
–––
–––
Max.
1.32
50
Units
RθJC
RθJA
RθJA
Junction-to-Case k
°C/W
Junction-to-Ambient (PCB Mount) jk
Junction-to-Ambient k
110
Notes through are on page 2
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1
4/21/09
IRFR/U1018EPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
60 ––– –––
––– 0.073 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250μA
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
2.0
7.1
8.4
4.0
20
VGS = 10V, ID = 47A g
VDS = VGS, ID = 100μA
mΩ
V
VGS(th)
–––
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 60V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 48V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
110 ––– –––
Conditions
VDS = 50V, ID = 47A
S
Qg
–––
–––
–––
–––
–––
46
10
12
34
69
nC ID = 47A
VDS = 30V
Qgs
Gate-to-Source Charge
–––
–––
–––
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Internal Gate Resistance
Turn-On Delay Time
VGS = 10V g
Qsync
ID = 47A, VDS =0V, VGS = 10V
RG(int)
0.73 –––
Ω
td(on)
–––
–––
–––
–––
13
35
55
46
–––
–––
–––
–––
ns
VDD = 39V
tr
Rise Time
ID = 47A
td(off)
Turn-Off Delay Time
RG = 10Ω
VGS = 10V g
VGS = 0V
tf
Fall Time
Ciss
Input Capacitance
––– 2290 –––
––– 270 –––
––– 130 –––
––– 390 –––
––– 630 –––
Coss
Output Capacitance
VDS = 50V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)h
Effective Output Capacitance (Time Related)g
pF ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V i
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
79c
D
S
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 315
(Body Diode)ꢁd
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
39
V
TJ = 25°C, IS = 47A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
26
31
24
35
1.8
ns
IF = 47A
di/dt = 100A/μs g
47
Qrr
36
nC
53
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
.
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
.
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 47A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 47A, di/dt ≤ 1668A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
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IRFR/U1018EPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
≤60μs PULSE WIDTH
Tj = 25°C
≤60μs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 47A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
V
J
1
= 25V
DS
≤60μs PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
V
, Gate-to-Source Voltage (V)
GS
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
4000
3000
2000
1000
0
V
C
= 0V,
f = 1 MHZ
GS
16
= C + C , C SHORTED
I = 47A
D
iss
gs
gd ds
C
= C
rss
gd
V
V
V
= 48V
= 30V
= 12V
DS
DS
DS
C
= C + C
oss
ds
gd
12
8
C
iss
4
C
oss
C
rss
0
1
10
100
0
10
20
30
40
50
60
V
, Drain-to-Source Voltage (V)
Q
Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFR/U1018EPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100
T
= 175°C
J
1msec
100μsec
10
1
T
= 25°C
J
LIMITED BY PACKAGE
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
DC
10
GS
0.1
0.1
0.1
1
100
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
80
80
LIMITED BY PACKAGE
Id = 5mA
60
40
20
0
75
70
65
60
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T , Case Temperature (°C)
C
T
, Temperature ( °C )
J
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
0.8
400
I
D
350
300
250
200
150
100
50
TOP
5.3A
11A
47A
0.6
0.4
0.2
0.0
BOTTOM
0
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFR/U1018EPbF
10
1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
τι (sec)
Ri (°C/W)
0.1
τJ
0.026741 0.000007
0.28078 0.000091
0.606685 0.000843
0.406128 0.005884
τC
τJ
τ1
τ
τ
τ
3τ3
τ4
2 τ2
0.02
0.01
τ1
τ4
Ci= τi/Ri
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
100
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 10% Duty Cycle
= 47A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFR/U1018EPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
14
12
10
8
I
I
I
I
= 1.0A
D
D
D
D
I
= 32A
= 51V
F
= 1.0mA
= 250μA
= 100μA
V
R
T = 25°C
J
T = 125°C
J
6
4
2
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
0
200
400
600
800
1000
T
J
di /dt (A/μs)
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
14
12
10
8
320
280
240
200
160
120
80
I
= 47A
= 51V
I
= 32A
V = 51V
R
F
F
V
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
6
4
2
40
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
320
I
= 47A
= 51V
F
280
240
200
160
120
80
V
R
T = 25°C
J
T = 125°C
J
40
0
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFR/U1018EPbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
V***
=10V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
*
VDD
**
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
0.01
Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+VDD
-
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFR/U1018EPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
RECTIFIER
ASSEMBLED ON WW 16, 2001
INTERNATIONAL
DATE CODE
YEAR 1 = 2001
WEEK 16
IRFR120
116A
LOGO
IN THE ASSEMBLY LINE "A"
12
34
LINE A
Note: "P" in assembly line position
indicates "L ead-F ree"
ASSEMBLY
LOT CODE
"P" in assembly line position indicates
"Lead-F ree" qualification to the cons umer-level
PART NUMBER
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
OR
IRFR120
LOGO
12
34
P = DE S IGNAT E S L E AD-F R E E
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
AS S E MB L Y
LOT CODE
YEAR 1 = 2001
WEEK 16
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
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IRFR/U1018EPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
WITH ASSEMBLY
RECTIFIER
DATE CODE
YEAR 1 = 2001
WEEK 19
IRFU120
119A
78
LOT CODE 5678
LOGO
ASSEMBLED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
ASSEMBLY
56
LINE A
LOT CODE
Note: "P" in assembly lineposition
indicates Lead-Free"
OR
PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 1 = 2001
ASSEMBLY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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9
IRFR/U1018EPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/09
10
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相关型号：
IRFR1018ETRRPBF
Power Field-Effect Transistor, 56A I(D), 60V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, DPAK-3
INFINEON
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