IRFR3711ZTRPBF [INFINEON]

Power Field-Effect Transistor, 30A I(D), 20V, 0.0057ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3;


型号：	IRFR3711ZTRPBF
厂家：	Infineon
描述：	Power Field-Effect Transistor, 30A I(D), 20V, 0.0057ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3 开关脉冲晶体管
文件：	总12页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD - 95074A

IRFR3711ZPbF

IRFU3711ZPbF

HEXFET^®Power MOSFET

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

l Lead-Free

V_DSSR_DS(on)max

18nC

5.7m

20V

Benefits

l Very Low RDS(on) at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

D-Pak

IRFR3711Z

I-Pak

IRFU3711Z

Absolute Maximum Ratings

Parameter

Drain-to-Source Voltage

Max.

Units

V_DS

Gate-to-Source Voltage

± 20

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

@ T_C= 25°C

@ T_C= 100°C

370

Maximum Power Dissipation

@T_C= 25°C

@T_C= 100°C

Linear Derating Factor

Operating Junction and

0.53

W/°C

°C

-55 to + 175

Storage Temperature Range

STG

Soldering Temperature, for 10 seconds

300 (1.6mm from case)

Thermal Resistance

Parameter

Typ.

–––

Max.

1.9

Units

R_θ

Junction-to-Case

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

°C/W

110

Notes through ꢀ are on page 11

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12/13/04

IRFR/U3711ZPbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

Conditions

BV_DSS

Drain-to-Source Breakdown Voltage

–––

V_GS= 0V, I_D= 250µA

∆ΒV_DSS/∆T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient –––

––– mV/°C Reference to 25°C, I_D= 1mA

Ω

Static Drain-to-Source On-Resistance

–––

1.55

–––

4.5

6.2

2.0

-5.4

–––

5.7

7.8

V_GS= 10V, I_D= 15A

V_GS= 4.5V, I_D= 12A

V_DS= V_GS, I_D= 250µA

V_GS(th)

Gate Threshold Voltage

2.45

∆V_GS(th)/∆T_J

I_DSS

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

––– mV/°C

1.0

150

100

-100

–––

µA

_DS= 16V, V_GS= 0V

V_DS= 16V, V_GS= 0V, T_J= 125°C

nA V_GS= 20V

_GS= -20V

V_DS= 10V, I_D= 12A

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

gfs

Q_g

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

t_d(on)

t_r

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

5.1

1.8

6.5

4.6

8.3

9.8

–––

_DS= 10V

_GS= 4.5V

I_D= 12A

Gate Charge Overdrive

See Fig. 16

Switch Charge (Q_gs2+ Q_gd)

Output Charge

nC V_DS= 10V, V_GS= 0V

_DD= 15V, V_GS= 4.5V

Turn-On Delay Time

Rise Time

I_D= 12A

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

ns Clamped Inductive Load

5.2

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 2160 –––

V_GS= 0V

–––

700

360

–––

pF V_DS= 10V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Single Pulse Avalanche Energy

Typ.

–––

Max.

Units

E_AS

I_AR

140

Avalanche Current

Repetitive Avalanche Energy

E_AR

7.9

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

I_S

Continuous Source Current

–––

MOSFET symbol

(Body Diode)

showing the

I_SM

Pulsed Source Current

–––

370

integral reverse

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

1.0

T = 25°C, I = 12A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

ns T = 25°C, I = 12A, V_DD= 10V

J F

Q_rr

t_on

di/dt = 100A/µs

9.4

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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IRFR/U3711ZPbF

1000

100

1000

100

VGS

10V

VGS

10V

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

TOP

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

BOTTOM 2.5V

2.5V

20µs PULSE WIDTH

Tj = 175°C

20µs PULSE WIDTH

Tj = 25°C

0.1

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

2.0

1000

= 30A

= 10V

= 25°C

= 175°C

1.5

1.0

0.5

100

= 10V

20µs PULSE WIDTH

2.0

3.0

4.0

5.0

6.0

7.0

8.0

-60 -40 -20

20 40 60 80 100 120 140 160 180

, Gate-to-Source Voltage (V)

, Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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IRFR/U3711ZPbF

10000

= 0V,

f = 1 MHZ

I = 12A

= 18V

= C + C

SHORTED

VDS= 10V

iss

gs gd

= C

rss

= C + C

oss

Ciss

1000

Coss

Crss

100

, Drain-to-Source Voltage (V)

100

Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000

100

1000.0

OPERATION IN THIS AREA

LIMITED BY R

(on)

100.0

10.0

1.0

= 175°C

100µsec

1msec

= 25°C

Tc = 25°C

Tj = 175°C

Single Pulse

10msec

= 0V

0.1

1.0

10.0

100.0

1000.0

0.0

0.5

1.0

1.5

2.0

2.5

, Drain-toSource Voltage (V)

, Source-toDrain Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

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IRFR/U3711ZPbF

100

2.5

2.0

1.5

1.0

0.5

0.0

LIMITED BY PACKAGE

= 250µA

100

125

150

175

-75 -50 -25

25 50 75 100 125 150 175

, Temperature ( °C )

, Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

D = 0.50

0.1

0.20

0.10

R₁

R₂

R₃

Ri (°C/W) τi (sec)

R₁

0.05

^Jτ_J

^Cτ

0.805

0.606

0.492

0.000237

0.001005

0.101628

0.02

0.01

¹τ₁

²τ₂

³τ₃

Ci= τi/Ri

0.01

0.001

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U3711ZPbF

15V

600

500

400

300

200

100

7.7A

8.9A

12A

TOP

DRIVER

BOTTOM

D.U.T

V0_GV_S

Ω

0.01

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

100

125

150

175

Starting T , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

L_D

V_DS

Fig 12b. Unclamped Inductive Waveforms

V_DD

D.U.T

Current Regulator

V_GS

Same Type as D.U.T.

Pulse Width < 1µs

Duty Factor < 0.1%

50KΩ

.2µF

12V

.3µF

Fig 14a. Switching Time Test Circuit

V_DS

D.U.T.

90%

3mA

10%

V_GS

Current Sampling Resistors

t_d(on)

t_d(off)

t_r

t_f

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

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IRFR/U3711ZPbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

P.W.

=10V

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 16. Gate Charge Waveform

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IRFR/U3711ZPbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

×V × f + Q × V × f

(

)

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

⎛ Q_oss

⎞

⎠

×V × f

⎝

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

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IRFR/U3711ZPbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WIT H AS S EMB LY

LOT CODE 1234

INTERNATIONAL

RECTIFIER

LOGO

DAT E CODE

YEAR 9 = 1999

WE E K 16

IRFU120

916A

ASSEMBLED ON WW 16, 1999

IN THE ASSEMBLY LINE "A"

LINE A

Note: "P" in assembly line position

AS S E MB L Y

LOT CODE

indi cates "L ead- F ree"

PART NUMBER

DAT E CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

LOGO

IRFU120

12 34

YEAR 9 = 1999

AS S E MB L Y

LOT CODE

WE E K 16

A = AS S E MB L Y S I T E CODE

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IRFR/U3711ZPbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

PART NUMBER

EXAMPLE: THIS IS AN IRFU120

INTERNATIONAL

WIT H AS S E MB L Y

DAT E CODE

YEAR 9 = 1999

WEEK 19

RECTIFIER

LOGO

IRFU120

919A

LOT CODE 5678

ASSEMBLED ON WW 19, 1999

IN THE ASSEMBLYLINE "A"

LINE A

ASSEMBLY

LOT CODE

Note : "P" in assembly line

pos ition indicates "L ead-F ree"

PART NUMBER

DATE CODE

INTERNATIONAL

RECTIFIER

LOGO

IRFU120

56 78

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

YEAR 9 = 1999

AS S E MB L Y

LOT CODE

WE E K 19

A = AS S E MB L Y S I T E CODE

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IRFR/U3711ZPbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Notes:

Calculated continuous current based on maximum allowable

Repetitive rating; pulse width limited by

max. junction temperature.

junction temperature. Package limitation current is 30A.

Starting T_J= 25°C, L = 1.9mH, R_G= 25Ω,

I_AS= 12A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.12/04

www.irf.com

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/

IRFR3711ZTRPBF [INFINEON]

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