IRFS3607 [INFINEON]
75V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装;
| 型号： | IRFS3607 |
| 厂家： | 
Infineon |
| 描述： | 75V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装 |
| 文件： | 总12页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97308C
IRFB3607PbF
IRFS3607PbF
Applications
l High Efficiency Synchronous Rectification in
IRFSL3607PbF
HEXFET® Power MOSFET
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
75V
7.34m
9.0m
80A
G
Benefits
ID
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
D
D
D
l Enhanced body diode dV/dt and dI/dt
Capability
S
S
S
D
D
G
G
G
D2Pak
TO-262
TO-220AB
IRFB3607PbF
IRFS3607PbF
IRFSL3607PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Max.
80
Units
56
A
310
140
0.96
± 20
PD @TC = 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
V
VGS
TJ
Gate-to-Source Voltage
-55 to + 175
Operating Junction and
°C
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy
120
46
mJ
A
Avalanche Current
IAR
Repetitive Avalanche Energy
14
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
1.045
–––
62
Units
R
R
R
R
Junction-to-Case
–––
0.50
–––
–––
JC
CS
JA
JA
Case-to-Sink, Flat Greased Surface, TO-220
°C/W
Junction-to-Ambient, TO-220
Junction-to-Ambient (PCB Mount) , D2Pak
40
www.irf.com
1
01/20/12
IRFB/S/SL3607PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
75 ––– –––
––– 0.096 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V
(BR)DSS/ TJ Breakdown Voltage Temp. Coefficient
V
V
μA
RDS(on)
VGS(th)
IDSS
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
––– 7.34 9.0
m
VGS = 10V, ID = 46A
2.0
––– –––
–––
4.0
20
VDS = VGS, ID = 100μA
V
DS = 75V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 125°C
GS = 20V
VGS = -20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Internal Gate Resistance
Turn-On Delay Time
Min. Typ. Max. Units
115 ––– –––
Conditions
VDS = 50V, ID = 46A
S
Qg
–––
–––
–––
–––
56
13
16
40
84
nC ID = 46A
VDS = 38V
Qgs
Qgd
Qsync
–––
–––
–––
V
GS = 10V
ID = 46A, VDS =0V, VGS = 10V
––– 0.55 –––
––– 16 –––
––– 110 –––
RG(int)
td(on)
tr
ns VDD = 49V
ID = 46A
Rise Time
RG = 6.8
td(off)
tf
Turn-Off Delay Time
–––
–––
43
96
–––
–––
Fall Time
VGS = 10V
pF VGS = 0V
VDS = 50V
Ciss
Coss
Crss
Input Capacitance
––– 3070 –––
––– 280 –––
––– 130 –––
––– 380 –––
––– 610 –––
Output Capacitance
Reverse Transfer Capacitance
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
C
oss eff. (ER) Effective Output Capacitance (Energy Related)
Coss eff. (TR) Effective Output Capacitance (Time Related)
VGS = 0V, VDS = 0V to 60V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
S
IS
Continuous Source Current
––– ––– 80
A
MOSFET symbol
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 310
(Body Diode)
p-n junction diode.
VSD
dv/dt
trr
Diode Forward Voltage
Peak Diode Recovery
Reverse Recovery Time
––– –––
1.3
V
TJ = 25°C, IS = 46A, VGS = 0V
–––
–––
–––
–––
–––
–––
27
33
39
32
47
1.9
––– V/ns TJ = 175°C, IS = 46A, VDS = 75V
50
59
ns TJ = 25°C
TJ = 125°C
VR = 64V,
IF = 46A
di/dt = 100A/μs
Qrr
Reverse Recovery Charge
48
nC TJ = 25°C
TJ = 125°C
A
71
–––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ISD 46A, di/dt 1920A/μs, VDD V(BR)DSS, TJ 175°C.
ꢀ Pulse width 400μs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
Calculated continuous current based on maximum allowable junction
temperature. Note that current limitations arising from heating of the
device leads may occur with some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.12mH
RG = 25, IAS = 46A, VGS =10V. Part not recommended for use
above this value.
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-
mended footprint and soldering techniques refer to application note #AN-994.
Ris measured at TJ approximately 90°C.
2
www.irf.com
IRFB/S/SL3607PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60μs PULSE WIDTH
60μs PULSE WIDTH
Tj = 25°C
Tj = 175°C
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 80A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
60μs PULSE WIDTH
0.1
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12.0
100000
10000
1000
V
C
= 0V,
f = 1 MHZ
GS
I = 46A
D
= C + C , C SHORTED
iss
gs gd ds
C
= C
10.0
rss
gd
V
V
= 24V
= 15V
DS
DS
C
= C + C
ds gd
oss
8.0
6.0
4.0
2.0
0.0
C
C
iss
oss
C
rss
100
0
10
20
30
40
50
60
1
10
, Drain-to-Source Voltage (V)
100
Q
, Total Gate Charge (nC)
V
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL3607PbF
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100
100μsec
T
= 175°C
J
1msec
10
1
T
= 25°C
J
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
DC
GS
1
0.1
1
10
100
0.0
0.5
1.0
1.5
2.0
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
100
95
90
85
80
75
70
80
70
60
50
40
30
20
10
0
Id = 5mA
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Case Temperature (°C)
T , Temperature ( °C )
C
J
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1.20
500
I
D
450
400
350
300
250
200
150
100
50
TOP
5.6A
11A
BOTTOM 46A
1.00
0.80
0.60
0.40
0.20
0.00
0
-10
0
10 20 30 40 50 60 70 80
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB/S/SL3607PbF
10.00
1.00
0.10
0.01
0.00
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) i (sec)
0.01109 0.000003
J J
C
0.26925 0.000130
0.49731 0.001301
0.26766 0.008693
11
Ci= iRi
0.02
0.01
2 2
33
44
Notes:
SINGLE PULSE
( THERMAL RESPONSE )
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
150
125
100
75
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0% Duty Cycle
= 46A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
50
tav = Average time in avalanche.
25
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL3607PbF
4.5
4.0
3.5
3.0
20
15
10
5
I = 31A
F
V
= 64V
R
T = 25°C
J
T = 125°C
J
I
I
I
I
= 100μA
= 250μA
= 1.0mA
= 1.0A
2.5
2.0
1.5
1.0
D
D
D
D
0
-75 -50 -25
0
25 50 75 100125 150175 200
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt (A/μs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
560
20
I = 46A
I = 31A
F
F
480
400
320
240
160
80
V
= 64V
V
= 64V
R
R
T = 25°C
T = 25°C
J
J
15
10
5
T = 125°C
J
T = 125°C
J
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
560
I = 46A
F
V
480
400
320
240
160
80
= 64V
R
T = 25°C
J
T = 125°C
J
0
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB/S/SL3607PbF
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB/S/SL3607PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFB/S/SL3607PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRFB/S/SL3607PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFB/S/SL3607PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/12
www.irf.com
11
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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