IRFS4115-7P [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
| 型号： | IRFS4115-7P |
| 厂家： | 
Infineon |
| 描述： | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
| 文件： | 总10页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD -97147
IRFS4115-7PPbF
HEXFET® Power MOSFET
Applications
D
VDSS
150V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
RDS(on) typ.
10.0m
11.8m
:
G
max.
:
ID
105A
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
D
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
S
S
S
S
G
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
Max.
105
74
Units
A
420
380
2.5
PD @TC = 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
V
VGS
± 20
32
Gate-to-Source Voltage
Peak Diode Recovery e
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy d
EAS (Thermally limited)
230
mJ
A
Avalanche Current c
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy f
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
°C/W
RθJC
Junction-to-Case jk
RθJA
Junction-to-Ambient (PCB Mount) ij
–––
www.irf.com
1
11/7/08
IRFS4115-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
150 ––– –––
––– 0.18 ––– V/°C Reference to 25°C, ID = 3.5mAc
Conditions
VGS = 0V, ID = 250μA
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
3.0
10. 11.8
VGS = 10V, ID = 63A f
VDS = VGS, ID = 250μA
mΩ
V
VGS(th)
–––
5.0
20
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 150V, VGS = 0V
VDS = 150V, VGS = 0V, TJ = 125°C
nA VGS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = -20V
RG(int)
–––
2.1
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 62A
93
––– –––
S
Qg
–––
–––
–––
–––
–––
–––
–––
–––
73
28
28
45
18
50
37
23
110
–––
–––
–––
–––
–––
–––
–––
nC ID = 63A
VDS = 75V
Qgs
Gate-to-Source Charge
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
V
GS = 10V f
ID = 63A, VDS =0V, VGS = 10V
ns VDD = 98V
Qsync
td(on)
tr
Rise Time
ID = 63A
td(off)
Turn-Off Delay Time
RG = 2.1Ω
VGS = 10V f
VGS = 0V
tf
Fall Time
Ciss
Input Capacitance
––– 5320 –––
––– 490 –––
––– 110 –––
––– 450 –––
––– 520 –––
Coss
Output Capacitance
VDS = 50V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)h
Effective Output Capacitance (Time Related)g
pF ƒ = 1.0MHz
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 120V h
VGS = 0V, VDS = 0V to 120V g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
104
D
S
(Body Diode)
Pulsed Source Current
showing the
integral reverse
ISM
––– ––– 420
G
(Body Diode)ꢁc
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
–––
–––
V
TJ = 25°C, IS = 63A, VGS = 0V f
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 130V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
82
99
ns
IF = 63A
di/dt = 100A/μs f
Qrr
––– 271 –––
––– 385 –––
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
6.0
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.115mH
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
.
RG = 25Ω, IAS = 63A, VGS =10V. Part not recommended for
use above this value.
.
ISD ≤ 63A, di/dt ≤ 2510A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
2
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IRFS4115-7PPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM
BOTTOM
1
5.0V
0.1
0.01
5.0V
≤60μs PULSE WIDTH
Tj = 25°C
≤60μs PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 63A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 50V
J
1
V
DS
≤ 60μs PULSE WIDTH
0.1
3.0
4.0
V
5.0
6.0
7.0
8.0
9.0
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
, Gate-to-Source Voltage (V)
GS
T
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
8000
6000
4000
2000
0
16
V
C
= 0V,
f = 1 MHZ
GS
I
= 63A
D
= C + C , C SHORTED
iss
gs
gd ds
V
V
V
= 120V
= 75V
= 30V
C
= C
DS
DS
DS
rss
gd
C
= C + C
oss
ds
gd
12
8
C
iss
4
C
oss
C
0
rss
0
20
40
60
80
100
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS4115-7PPbF
10000
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100
T
= 175°C
J
100μsec
10
1
1msec
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
DC
GS
0.1
0.1
0.1
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
DS
V
, Source-to-Drain Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
120
190
180
170
160
150
140
Id = 3.5mA
100
80
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, CaseTemperature (°C)
C
T
, Temperature ( °C )
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1000
4
3
2
1
0
I
D
TOP
14A
24A
63A
800
600
400
200
0
BOTTOM
25
50
75
100
125
150
175
0
20
40
60
80
100
120
140
Starting T , Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFS4115-7PPbF
1
D = 0.50
0.1
0.20
0.10
R1
R1
R2
R2
R3
R3
R4
R4
τι (sec)
Ri (°C/W)
τJ
0.015402 0.00001
0.056989 0.000065
0.180208 0.001377
0.146323 0.010705
τC
τJ
τ1
τ
0.05
τ
2 τ2
τ
3 τ3
τ4
τ1
τ4
0.02
0.01
0.01
Ci= τi/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
240
200
160
120
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1% Duty Cycle
= 63A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
40
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS4115-7PPbF
6.0
50
40
30
20
10
0
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
5.0
4.0
3.0
2.0
1.0
I
= 42A
F
V
= 127V
R
T
= 125°C
= 25°C
J
T
J
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di / dt - (A / μs)
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
2400
50
2000
1600
1200
800
400
0
40
30
20
I
= 42A
I
= 63A
F
F
V
= 127V
R
V
= 127V
= 125°C
= 25°C
R
10
0
T
= 125°C
T
J
J
J
T
T
= 25°C
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
2400
2000
1600
1200
800
400
0
I
= 63A
F
V
T
= 127V
= 125°C
= 25°C
R
J
J
T
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFS4115-7PPbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFS4115-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS4115-7PPbF
D2Pak - 7 Pin Part Marking Information
ꢀ25
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/08
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9
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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