IRFS4410TRR [INFINEON]
Power Field-Effect Transistor, 96A I(D), 100V, 0.01ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, D2PAK-3;
| 型号： | IRFS4410TRR |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 96A I(D), 100V, 0.01ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, D2PAK-3 开关 脉冲 晶体管 |
| 文件： | 总12页 (文件大小：799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95707E
IRFB4410PbF
IRFS4410PbF
IRFSL4410PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
100V
8.0m
10m
88A
G
ID
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
S
S
D
D
D
G
G
G
D2Pak
IRFS4410PbF
TO-262
IRFSL4410PbF
TO-220AB
IRFB4410PbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
88
A
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
63
380
Pulsed Drain Current
PD @TC = 25°C
200
W
Maximum Power Dissipation
Linear Derating Factor
1.3
W/°C
V
VGS
± 20
Gate-to-Source Voltage
19
Peak Diode Recovery
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
220
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 16a, 16b
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.61
–––
62
Units
Rθ
Junction-to-Case
JC
CS
JA
JA
Rθ
Rθ
Rθ
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
Junction-to-Ambient (PCB Mount) , D2Pak
–––
40
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1
05/02/07
IRFB/S/SL4410PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
100 ––– –––
––– 0.094 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
V
/ T
∆
J
∆
(BR)DSS
RDS(on)
VGS(th)
IDSS
–––
2.0
8.0
10
4.0
20
VGS = 10V, ID = 58A
m
Ω
–––
V
VDS = VGS, ID = 150µA
Drain-to-Source Leakage Current
––– –––
µA
VDS = 100V, VGS = 0V
––– ––– 250
––– ––– 200
––– ––– -200
V
DS = 100V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA VGS = 20V
GS = -20V
f = 1MHz, open drain
V
RG
–––
1.5
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 58A
nC ID = 58A
DS = 80V
120 ––– –––
S
Qg
––– 120 180
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
31
44
24
80
55
50
–––
–––
–––
–––
–––
–––
V
VGS = 10V
ns VDD = 65V
ID = 58A
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 4.1Ω
VGS = 10V
Ciss
Coss
Crss
Input Capacitance
––– 5150 –––
––– 360 –––
––– 190 –––
––– 420 –––
––– 500 –––
pF VGS = 0V
Output Capacitance
Reverse Transfer Capacitance
VDS = 50V
ƒ = 1.0MHz
Coss eff. (ER)
V
GS = 0V, VDS = 0V to 80V , See Fig.11
GS = 0V, VDS = 0V to 80V , See Fig. 5
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Coss eff. (TR)
V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
––– –––
A
88
D
S
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 380
A
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
56
77
92
V
TJ = 25°C, IS = 58A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
–––
–––
–––
38
51
61
ns
IF = 58A
di/dt = 100A/µs
Qrr
Reverse Recovery Charge
nC
A
––– 110 170
––– 2.8 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.14mH
RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 58A, di/dt ≤ 650A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC (end of life) for D2Pak and TO-262 = 0.75°C/W. Note: This is the maximum
measured value after 1000 temperature cycles from -55 to 150°C and is
accounted for by the physical wearout of the die attach medium.
2
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IRFB/S/SL4410PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
1
4.5V
1
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
0.1
1
0.1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 58A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
10
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
12.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 58A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
V
V
V
= 80V
= 50V
= 20V
10.0
8.0
6.0
4.0
2.0
0.0
rss
oss
gd
DS
DS
DS
= C + C
ds
gd
C
iss
C
oss
C
rss
100
1
10
, Drain-to-Source Voltage (V)
100
0
20
40
60
80
100
120
V
Q
Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL4410PbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100µsec
1msec
100
T
= 175°C
J
10msec
DC
T
= 25°C
J
10
1
Tc = 25°C
Tj = 175°C
V
= 0V
GS
Single Pulse
1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-to-Drain Voltage (V)
0
1
10
100
1000
V
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
130
125
120
115
110
105
100
100
Limited By Package
75
50
25
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
25
50
75
100
125
150
175
T , Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
2.0
900
I
D
800
700
600
500
400
300
200
100
0
TOP
6.7A
9.7A
BOTTOM 58A
1.5
1.0
0.5
0.0
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB/S/SL4410PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
Ri (°C/W) τi (sec)
0.2736 0.000376
0.02
0.01
0.01
τ
J τJ
τ
τ
Cτ
1 τ1
Ci= τi/Ri
τ
2τ2
0.3376 0.004143
SINGLE PULSE
0.001
0.0001
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1% Duty Cycle
= 58A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
25
50
75
100
125
150
175
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Starting T , Junction Temperature (°C)
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL4410PbF
20
15
10
5
5.0
4.5
4.0
3.5
3.0
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
2.5
2.0
1.5
1.0
I
= 19A
= 85V
F
V
R
T
= 25°C _____
= 125°C ----------
J
T
J
0
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di /dt (A/µs)
f
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
400
20
350
300
250
200
150
100
50
15
10
5
I
= 19A
= 85V
I
= 38A
= 85V
F
F
V
V
T
R
R
T
= 25°C _____
= 125°C ----------
= 25°C _____
= 125°C ----------
J
J
T
T
J
J
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di /dt (A/µs)
f
di /dt (A/µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
400
350
300
250
200
150
100
50
I
= 38A
= 85V
F
V
R
T
= 25°C _____
= 125°C ----------
J
T
J
0
100 200 300 400 500 600 700 800 900 1000
di /dt (A/µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB/S/SL4410PbF
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB/S/SL4410PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRFB/S/SL4410PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
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9
IRFB/S/SL4410PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
10
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IRFB/S/SL4410PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/07
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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