IRFS4510TRLPBF [INFINEON]
Power Field-Effect Transistor, 61A I(D), 100V, 0.0139ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, D2PAK-3/2;
| 型号： | IRFS4510TRLPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 61A I(D), 100V, 0.0139ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, D2PAK-3/2 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97771
IRFS4510PbF
IRFSL4510PbF
HEXFET® Power MOSFET
D
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
VDSS
RDS(on) typ.
100V
11.3m
13.9m
61A
Ω
Ω
G
max.
l Hard Switched and High Frequency Circuits
ID (Silicon Limited)
S
Benefits
D
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
S
D
S
D
SOA
G
G
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
D2Pak
IRFS4510PbF
TO-262
IRFSL4510PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Max.
61
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
43
A
250
PD @TC = 25°C
140
W
Maximum Power Dissipation
Linear Derating Factor
0.95
W/°C
V
VGS
± 20
Gate-to-Source Voltage
3.2
Peak Diode Recovery
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
130
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Parameter
Typ.
–––
Max.
1.05
40
Units
Rθ
Junction-to-Case
JC
°C/W
RθJA
–––
Junction-to-Ambient
www.irf.com
1
4/10/12
IRFS/SL4510PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.11 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V
ΔV(BR)DSS/ΔTJ
RDS(on)
––– 11.3 13.9
VGS = 10V, ID = 37A
mΩ
V
VGS(th)
2.0
–––
4.0
20
VDS = VGS, ID = 100μA
IDSS
Drain-to-Source Leakage Current
––– –––
μA
V
V
V
V
DS = 100V, VGS = 0V
DS = 80V, VGS = 0V, TJ = 125°C
GS = 20V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
GS = -20V
RG
–––
0.6
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max. Units
100 ––– –––
Conditions
S
VDS = 25V, ID = 37A
nC ID = 37A
DS =50V
Qg
Total Gate Charge
–––
–––
–––
–––
–––
–––
–––
–––
58
14
18
40
13
32
28
28
87
Qgs
Qgd
Qsync
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
–––
V
VGS = 10V
–––
–––
–––
–––
–––
ID = 37A, VDS =0V, VGS = 10V
ns VDD = 65V
Rise Time
ID = 37A
RG =2.7Ω
VGS = 10V
td(off)
tf
Turn-Off Delay Time
Fall Time
Ciss
Coss
Crss
Input Capacitance
––– 3180 –––
––– 220 –––
––– 120 –––
––– 260 –––
––– 325 –––
pF VGS = 0V
Output Capacitance
VDS = 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz, See Fig.5
Coss eff. (ER)
oss eff. (TR)
V
GS = 0V, VDS = 0V to 80V , See Fig.11
GS = 0V, VDS = 0V to 80V
C
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
D
S
Continuous Source Current
––– –––
A
MOSFET symbol
61
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 250
A
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
81
V
TJ = 25°C, IS = 37A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
Reverse Recovery Time
–––
–––
–––
54
60
95
ns
IF = 37A
di/dt = 100A/μs
90
Qrr
Reverse Recovery Charge
140
nC
––– 130 195
––– 3.3 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.192mH
RG = 25Ω, IAS = 37A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 37A, di/dt ≤ 1550A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
Rθ is measured at TJ approximately 90°C.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
2
www.irf.com
IRFS/SL4510PbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
TOP
TOP
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
BOTTOM
BOTTOM
4.0V
1
4.0V
60μs PULSE WIDTH
≤
Tj = 175°C
60μs PULSE WIDTH
Tj = 25°C
≤
0.1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
100
10
I
= 37A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 50V
DS
60μs PULSE WIDTH
≤
0.1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
100
14
V
C
= 0V,
f = 1 MHZ
I
= 37A
GS
D
= C + C , C SHORTED
iss
gs
gd ds
V
V
V
= 80V
= 50V
= 20V
12
10
8
DS
DS
DS
C
= C
rss
gd
C
= C + C
ds
oss
gd
Ciss
6
Coss
Crss
4
2
0
10
0
20
40
60
80
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
www.irf.com
3
IRFS/SL4510PbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100
100μsec
T
= 175°C
1msec
J
10
1
10msec
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
1.4
GS
0.1
0.1
1
10
, Drain-toSource Voltage (V)
100
0.2
0.4
V
0.6
0.8
1.0
1.2
1.6
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
70
60
50
40
30
20
10
0
125
120
115
110
105
100
95
Id = 5mA
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T , Junction Temperature (°C)
J
T
, Temperature ( °C )
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0.0
600
I
D
500
400
300
200
100
0
TOP
4.7A
12A
BOTTOM 37A
0
20
40
60
80
100
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
DS,
Starting T , Junction Temperature (°C)
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
www.irf.com
IRFS/SL4510PbF
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
140
120
100
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1% Duty Cycle
= 37A
Single Pulse
I
D
60
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
40
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
20
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRFS/SL4510PbF
4.5
4.0
3.5
3.0
2.5
24
20
16
12
8
I
I
I
I
= 100μA
= 250μA
= 1.0mA
= 1.0A
I
= 24A
= 80V
D
D
D
D
F
2.0
1.5
1.0
V
R
4
T
= 125°C
= 25°C
J
T
J
0
100 200 300 400 500 600 700 800 900 1000
-75 -50 -25
0
25 50 75 100 125150 175 200
di / dt - (A / μs)
T , Temperature ( °C )
f
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
600
500
400
300
200
24
20
16
12
8
I
= 24A
= 80V
I
= 37A
= 80V
F
F
V
V
R
R
100
0
4
0
T
= 125°C
= 25°C
T
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
600
500
400
300
200
100
0
I
= 37A
F
V
T
= 80V
R
= 125°C
= 25°C
J
J
T
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
www.irf.com
IRFS/SL4510PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
t
15V
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
D.U.T
10%
VGS
VGS
Second Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
www.irf.com
7
IRFS/SL4510PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WE EK 02
ASSEMBLY
LOT CODE
LINE L
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
F530S
DAT E CODE
P = DE S IGNAT E S LE AD - F RE E
PRODUCT (OPTIONAL)
YEAR 0 = 2000
AS S E MB LY
LOT CODE
WEE K 02
A = AS S E MB L Y S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS/SL4510PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 = 1997
WEEK 19
ASSEMBLY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WEEK 19
A = AS S E MBLY S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRFS/SL4510PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 101N Sepulveda., El Segundo, California 90245, USA Tel: (310) 252-
7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/2012
10
www.irf.com
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