IRLR3103PBF [INFINEON]
HEXFET㈢ Power MOSFET; HEXFET㈢功率MOSFET
| 型号： | IRLR3103PBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET㈢ Power MOSFET |
| 文件： | 总11页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95085A
IRLR/U3103PbF
HEXFET® Power MOSFET
l Logic-Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR3103)
l Straight Lead (IRLU3103)
l Advanced Process Technology
l Fast Switching
D
VDSS = 30V
RDS(on) = 0.019Ω
G
l Fully Avalanche Rated
l Lead-Free
ID = 55Aꢀ
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
D-PAK
TO-252AA
I-PAK
TO-251AA
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
55ꢀ
39ꢀ
220
107
0.71
± 16
240
34
A
PD @TC = 25°C
Power Dissipation
W
W/°C
V
Linear Derating Factor
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
11
mJ
V/ns
5.0
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
1.4
Units
°C/W
1
RθJC
RθJA
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
50
RθJA
110
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12/7/04
IRLR/U3103PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
30 ––– –––
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.037 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.019
––– ––– 0.024
VGS = 10V, ID = 33A
VGS = 4.5V, ID = 25A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 34A
Ω
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
1.0
23
––– –––
––– –––
V
S
Forward Transconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 50
––– ––– 14
––– ––– 28
VDS = 30V, VGS = 0V
IDSS
IGSS
Drain-to-Source Leakage Current
µA
nA
VDS = 18V, VGS = 0V, TJ = 150°C
VGS = 16V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
VGS = -16V
Qg
ID = 34A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 24V
VGS = 4.5V, See Fig. 6 and 13
–––
9.0 –––
VDD = 15V
––– 210 –––
ID = 34A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
20 –––
54 –––
RG = 3.4Ω, VGS = 4.5V
RD = 0.43Ω, See Fig. 10
Between lead,
D
S
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
VGS = 0V
Ciss
Coss
Crss
Input Capacitance
––– 1600 –––
––– 640 –––
––– 320 –––
Output Capacitance
pF
VDS = 25V
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
S
IS
55ꢀ
––– –––
––– –––
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
220
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 81 120
––– 210 310
V
TJ = 25°C, IS = 28A, VGS = 0V
TJ = 25°C, IF = 34A
ns
nC
Qrr
ton
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 15V, starting TJ = 25°C, L = 300µH
RG = 25Ω, IAS = 34A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%
ꢀ Calculated continuous current based on maximum allowable junction
temperature; Package limitation current = 20A
This is applied for I-PAK, LS of D-PAK is measured between lead and
center of die contact
ISD ≤ 34A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
Uses IRL3103 data and test conditions
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRLR/U3103PbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 25°C
T
= 175°C
J
J
1
1
0.1
A
A
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
2.0
1.5
1.0
0.5
0.0
1000
I
= 56A
D
TJ = 25°C
TJ = 175°C
100
10
1
VDS = 15V
20µs PULSE WIDTH
9.0A
V
= 10V
GS
A
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
T , Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRLR/U3103PbF
3200
15
12
9
V
C
C
C
= 0V,
f = 1MHz
GS
iss
rss
oss
I
= 34A
D
= C + C
,
C
SHORTED
gs
gd
gd
ds
V
V
= 24V
= 15V
DS
DS
2800
2400
2000
1600
1200
800
= C
= C + C
ds
gd
C
C
iss
oss
6
C
rss
3
400
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
0
A
1
10
100
0
10
20
30
40
50
60
70
V
, Drain-to-Source Voltage (V)
DS
Q
, Total Gate Charge (nC)
G
Fig 5. Typical Capacitance Vs.
Fig 6. Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
1000
100
10
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
100
10
1
100µs
T = 175°C
J
1ms
T = 25°C
J
10ms
T
T
= 25°C
= 175°C
Single Pulse
C
J
V
= 0V
GS
A
A
0.4
0.8
1.2
1.6
2.0
2.4
2.8
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4
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IRLR/U3103PbF
60
50
40
30
20
10
0
RD
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+VDD
-
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
0.10
0.05
P
2
DM
0.1
0.01
t
1
0.02
0.01
SINGLE PULSE
t
2
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
1
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3103PbF
600
500
400
300
200
100
0
I
D
TOP
14A
24A
BOTTOM 34A
15V
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
-
I
A
AS
10V
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
= 15V
50
DD
A
175
25
75
100
125
150
Starting T , Junction Temperature (°C)
V
(BR)DSS
J
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
.2µF
12V
.3µF
Q
G
+
5.0 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U3103PbF
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U3103PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WEE K 16
IRFU120
916A
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
12
34
LINE A
Note: "P" in assembly lineposition
ASSEMBLY
LOT CODE
indicates "L ead-Free"
OR
PART NUMBER
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEE K 16
A= ASSEMBLY SITE CODE
8
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IRLR/U3103PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
RECTIFIER
LOGO
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW19, 1999
IN THE ASSEMBLY LINE "A"
DATE CODE
YEAR 9 = 1999
WEEK 19
IRFU120
919A
78
56
LINE A
ASSEMBLY
LOT CODE
Note: "P" inassemblyline
position indicates "Lead-Free"
OR
PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
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9
IRLR/U3103PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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