IRLR3303PBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRLR3303PBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总10页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD- 95086A
IRLR/U3303PbF
HEXFET® Power MOSFET
l Logic-Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR3303)
l Straight Lead (IRLU3303)
l Advanced Process Technology
l Fast Switching
D
VDSS = 30V
RDS(on) = 0.031Ω
G
l Fully Avalanche Rated
l Lead-Free
ID = 35Aꢀ
S
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
35 ꢀ
25
140
68
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
A
PD @TC = 25°C
PowerDissipation
W
W/°C
V
LinearDeratingFactor
0.45
± 16
130
20
VGS
EAS
IAR
Gate-to-SourceVoltage
Single Pulse Avalanche Energy
AvalancheCurrent
mJ
A
EAR
dv/dt
TJ
RepetitiveAvalancheEnergy
Peak Diode Recovery dv/dt
OperatingJunctionand
6.8
mJ
V/ns
5.0
-55 to + 175
TSTG
StorageTemperatureRange
SolderingTemperature, for10seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
2.2
Units
RθJC
RθJA
RθJA
Case-to-Ambient(PCBmount)**
Junction-to-Ambient
–––
50
°C/W
–––
110
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
www.irf.com
1
12/7/04
IRLR/U3303PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
30 ––– –––
––– 0.035 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-SourceBreakdownVoltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ BreakdownVoltageTemp.Coefficient
––– ––– 0.031
––– ––– 0.045
VGS = 10V, ID = 21A
VGS = 4.5V, ID = 17A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 20A
VDS = 30V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 150°C
VGS = 16V
Ω
RDS(on)
StaticDrain-to-SourceOn-Resistance
VGS(th)
gfs
GateThresholdVoltage
1.0
12
––– –––
––– –––
V
S
ForwardTransconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 26
––– ––– 8.8
––– ––– 15
IDSS
IGSS
Drain-to-SourceLeakageCurrent
µA
nA
Gate-to-SourceForwardLeakage
Gate-to-SourceReverseLeakage
Total Gate Charge
VGS = -16V
Qg
ID = 20A
Qgs
Qgd
td(on)
tr
Gate-to-SourceCharge
Gate-to-Drain("Miller")Charge
Turn-On Delay Time
Rise Time
nC VDS = 24V
VGS = 4.5V, See Fig. 6 and 13
–––
7.4 –––
VDD = 15V
––– 200 –––
ID = 20A
ns
td(off)
tf
Turn-Off Delay Time
FallTime
–––
–––
14 –––
36 –––
RG = 6.5Ω, VGS = 4.5V
RD = 0.70Ω, See Fig. 10
Betweenlead,
D
S
LD
LS
InternalDrainInductance
InternalSourceInductance
–––
4.5
–––
nH
6mm(0.25in.)
G
frompackage
––– 7.5 –––
and center of die contact
VGS = 0V
Ciss
Coss
Crss
InputCapacitance
––– 870 –––
––– 340 –––
––– 170 –––
OutputCapacitance
pF
VDS = 25V
ReverseTransferCapacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
S
IS
––– –––
35 ꢀ
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 140
p-n junction diode.
VSD
trr
DiodeForwardVoltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 72 110
––– 180 280
V
TJ = 25°C, IS = 20A, VGS = 0V
TJ = 25°C, IF = 20A
ns
nC
Qrr
ton
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 15V, starting TJ = 25°C, L =470µH
RG = 25Ω, IAS = 20A. (See Figure 12)
ꢀ Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
ISD ≤ 20A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
Uses IRL3303 data and test conditions.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
www.irf.com
IRLR/U3303PbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
1
1
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 25°C
J
T
= 175°C
J
0.1
0.1
0.1
A
A
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
1000
I
= 34A
D
1.5
1.0
0.5
0.0
100
10
1
TJ = 25°C
TJ = 175°C
V DS= 15V
20µs PULSE WIDTH
V
= 10V
GS
0.1
A
10A
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
2
3
4
5
6
7
8
9
T , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRLR/U3303PbF
1600
15
12
9
V
C
C
C
= 0V,
f = 1MHz
I
= 20A
D
GS
iss
rss
oss
= C + C
,
C
SHORTED
V
V
= 24V
= 15V
gs
gd
gd
ds
DS
DS
1400
1200
1000
800
600
400
200
0
= C
= C + C
ds
gd
C
C
iss
oss
6
C
rss
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
10
20
30
40
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
DS
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
T = 175°C
J
100µs
T = 25°C
J
1ms
10ms
T
T
= 25°C
= 175°C
C
J
V
= 0V
Single Pulse
GS
A
1
1
A
0.0
0.5
1.0
1.5
2.0
2.5
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
SD
DS
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating
Forward Voltage
Area
4
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IRLR/U3303PbF
RD
35
30
25
20
15
10
5
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+VDD
-
4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
1
0.20
0.10
0.05
P
2
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.1
t
1
t
2
Notes:
1. Duty factor D =
t / t
1
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.01
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3303PbF
300
250
200
150
100
50
I
D
TOP
8.3A
14A
BOTTOM 20A
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
= 15V
50
DD
0
A
175
25
75
100
125
150
Starting T , Junction Temperature (°C)
J
V
(BR)DSS
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
.2µF
12V
Q
G
.3µF
+
10 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
6
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IRLR/U3303PbF
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U3303PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WE EK 16
IRFU120
916A
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
12
34
LINE A
Note: "P" in assembly lineposition
ASSEMBLY
LOT CODE
indicates "L ead-F ree"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 16
A= ASSEMBLY SITE CODE
8
www.irf.com
IRLR/U3303PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
RECTIFIER
LOGO
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW19, 1999
IN THE ASSEMBLY LINE "A"
DATE CODE
YEAR 9 = 1999
WEEK 19
IRFU120
919A
78
56
LINE A
AS S EMB L Y
LOT CODE
Note: "P" inassemblyline
position indicates "Lead-Free"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S LE AD-F R EE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
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9
IRLR/U3303PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10
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