IRLR3715ZTRL [INFINEON]
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Infineon 
PD - 94177
SMPS MOSFET
IRLR3715
IRLU3715
HEXFET® Power MOSFET
Applications
l High Frequency Isolated DC-DC
VDSS RDS(on) max
ID
Converters with Synchronous Rectification
for Telecom and Industrial Use
20V
14mΩ
54A
l High Frequency Buck Converters for
Computer Processor Power
Benefits
l Ultra-Low Gate Impedance
l Very Low RDS(on) at 4.5V VGS
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRLR3715
I-Pak
IRLU3715
Absolute Maximum Ratings
Symbol
VDS
Parameter
Drain-Source Voltage
Max.
Units
V
20
± 20
54
38
210
71
VGS
Gate-to-Source Voltage
V
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
ID @ TC = 100°C
IDM
A
PD @TC = 25°C
PD @TA = 25°C
Maximum Power Dissipation
Maximum Power Dissipationꢀ
Linear Derating Factor
W
W
3.8
0.48
W/°C
°C
TJ , TSTG
Junction and Storage Temperature Range
-55 to + 175
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
2.1
Units
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient
Junction-to-Ambient (PCB mount)ꢀ
110
50
°C/W
Notes through ꢀare on page 10
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1
06/28/01
IRLR/U3715
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
20 ––– –––
––– 0.022 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
–––
–––
1.0
11
15
14
20
VGS = 10V, ID = 26A
mΩ
V
RDS(on)
VGS(th)
IDSS
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
VGS = 4.5V, ID = 21A
VDS = VGS, ID = 250µA
––– 3.0
––– ––– 20
––– ––– 100
––– ––– 200
––– ––– -200
VDS = 16V, VGS = 0V
µA
Drain-to-Source Leakage Current
VDS = 16V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
VGS = 16V
IGSS
nA
VGS = -16V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
26
––– –––
11 17
S
VDS = 10V, ID = 21A
ID = 21A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
Qgs
Qgd
Qoss
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Output Gate Charge
Turn-On Delay Time
Rise Time
3.8 –––
4.4 –––
nC VDS = 10V
VGS = 4.5V
11
17
VGS = 0V, VDS = 10V
6.4 –––
73 –––
12 –––
5.1 –––
VDD = 10V
ID = 21A
ns
pF
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 1.8Ω
VGS = 4.5V
VGS = 0V
Ciss
Coss
Crss
Input Capacitance
––– 1060 –––
––– 700 –––
––– 120 –––
Output Capacitance
Reverse Transfer Capacitance
VDS = 10V
ƒ = 1.0MHz
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Typ.
–––
–––
Max.
110
21
Units
mJ
IAR
A
Diode Characteristics
Symbol
IS
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
Continuous Source Current
(Body Diode)
––– ––– 54
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
––– ––– 210
S
––– 0.9 1.3
––– 0.8 –––
V
TJ = 25°C, IS = 21A, VGS = 0V
TJ = 125°C, IS = 21A, VGS = 0V
TJ = 25°C, IF = 21A, VR=20V
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
––– 37
––– 28
––– 38
––– 30
56
42
57
45
ns
Qrr
trr
nC di/dt = 100A/µs
ns TJ = 125°C, IF = 21A, VR=20V
nC di/dt = 100A/µs
Qrr
2
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IRLR/U3715
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
10V
10V
4.5V
3.5V
3.3V
3.0V
2.7V
4.5V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
BOTTOM2.5V
2.5V
2.5V
1
20µs PULSE WIDTH
T = 175 C
J
20µs PULSE WIDTH
T = 25 C
J
°
°
1
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
1000
52A
=
I
D
2.0
1.5
1.0
0.5
0.0
°
T = 25 C
J
100
°
T = 175 C
J
V
= 15V
DS
20µs PULSE WIDTH
V
=10V
GS
10
2.0
3.0
V
4.0
5.0
6.0 7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
, Gate-to-Source Voltage (V)
T , Junction Temperature ( C)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRLR/U3715
14
12
10
8
10000
1000
100
V
= 0V,
f = 1 MHZ
GS
I
D
= 21A
V
V
= 16V
= 10V
DS
DS
C
= C + C
,
C
SHORTED
iss
gs
gd
ds
C
= C
rss
gd
C
= C + C
oss
ds gd
Ciss
Coss
6
Crss
4
2
FOR TEST CIRCUIT
SEE FIGURE 13
10
0
0
5
10
15
20
25
1
10
, Drain-to-Source Voltage (V)
100
Q
, Total Gate Charge (nC)
G
V
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
°
T = 175 C
J
100
10
1
100µsec
°
1msec
T = 25 C
J
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0 V
GS
2.0
0.1
0.0
0.4
0.8
1.2
1.6
2.4
1
10
, Drain-toSource Voltage (V)
100
V
,Source-to-Drain Voltage (V)
SD
V
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRLR/U3715
RD
60
50
40
30
20
10
0
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+VDD
-
4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
0.02
0.01
0.1
t
1
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.01
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3715
240
200
160
120
80
I
15V
D
TOP
8.5A
15A
21A
BOTTOM
DR IV ER
L
V
D S
D.U .T
R
+
G
V
D D
-
I
A
A S
V
2
GS
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
40
V
(BR)DSS
t
p
0
25
50
75
100
125
150
175
°
Starting T , Junction Temperature ( C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
4.5 V
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U3715
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRLR/U3715
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.09 4)
2.19 (.08 6)
6.73 (.265 )
6.35 (.250 )
1.14 (.045)
0.89 (.035)
- A
-
1.27 (.050 )
0.88 (.035 )
5 .46 (.215 )
5 .21 (.205 )
0.58 (.02 3)
0.46 (.01 8)
4
6.4 5 (.2 45)
5.6 8 (.2 24)
6.2 2 (.2 45)
5.9 7 (.2 35)
10 .42 (.4 10 )
9.40 (.37 0)
1.02 (.04 0)
1.64 (.02 5)
LE AD A SS IG N M E NTS
1 - G A TE
1
2
3
2 - D R A IN
0 .51 (.02 0)
M IN.
- B
-
3 - S O U R CE
4 - D R A IN
1 .5 2 (.06 0)
1 .1 5 (.04 5)
0.89 (.035 )
0.64 (.025 )
3X
0 .5 8 (.0 23)
0 .4 6 (.0 18)
1.1 4 (.0 45)
0.7 6 (.0 30)
2X
0.25 (.01 0)
M
A M B
N O TE S :
2.28 (.09 0)
1
2
3
4
D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5 M , 1 982 .
C O N TR O LL ING D IM EN SIO N : IN C H .
4 .57 (.18 0)
C O N FO R MS TO JE D E C O U TLIN E TO -252 AA .
D IM E N S IO N S SH O W N A R E B EF O R E S O LD ER D IP ,
S O LD ER D IP M A X. +0.16 (.0 06).
D-Pak (TO-252AA) Part Marking Information
8
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IRLR/U3715
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .73 (.26 5)
6 .35 (.25 0)
2.38 (.094)
2.19 (.086)
- A
-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5 .4 6 (.21 5)
5 .2 1 (.20 5)
L EAD A SSIG N MEN TS
1 - G ATE
4
2 - D RA IN
6.4 5 (.245)
5.6 8 (.224)
3 - SO U R C E
4 - D RA IN
6 .22 (.2 45)
5 .97 (.2 35)
1.52 (.060)
1.15 (.045)
1
2
3
- B
-
N O TE S:
1
2
3
4
D IM EN SIO N IN G & TO LER AN C IN G P ER AN SI Y14.5M , 198 2.
C O NTR OL LIN G D IM EN SIO N : IN C H .
2.28 (.0 90)
1.91 (.0 75)
9.65 (.380)
8.89 (.350)
C O NF O R MS TO JEDE C O UTLINE TO -25 2AA.
D IM EN SIO N S S HO W N A R E BE FO RE SO L DE R D IP,
SO LDE R DIP M AX. +0.16 (.006).
1.14 (.045 )
0.76 (.030 )
1 .14 (.04 5)
0 .89 (.03 5)
3X
0.89 (.0 35)
0.64 (.0 25)
3X
0.25 (.010 )
M
A M B
0.58 (.023)
0.46 (.018)
2.28 (.09 0)
2X
I-Pak (TO-251AA) Part Marking Information
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9
IRLR/U3715
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TR L
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIR ECTIO N
N O TES :
1. CO NTRO LLING DIMEN SIO N : MILLIMETER.
2. ALL D IM EN SIO N S ARE SH O W N IN M ILLIM ETERS ( IN CHES ).
3. O UTLINE C O NFO RMS TO EIA-481 & EIA-541.
13 INC H
16 m m
NO TES :
1. OU TLINE CO NFO RM S TO EIA-481.
Notes:
ꢀWhen mounted on 1" square PCB (FR-4 or G-10 Material) .
Repetitive rating; pulse width limited by
max. junction temperature.
For recommended footprint and soldering techniques refer
to application note #AN-994
Starting TJ = 25°C, L = 0.51mH
RG = 25Ω, IAS = 21A,VGS=10V
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum
allowable junction temperature. Package limitation
current is 30A.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/01
10
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