IRLU3105PBF [INFINEON]
AUTOMOTIVE MOSFET; 汽车MOSFET
| 型号： | IRLU3105PBF |
| 厂家： | 
Infineon |
| 描述： | AUTOMOTIVE MOSFET |
| 文件： | 总11页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95553A
IRLR3105PbF
AUTOMOTIVE MOSFET
IRLU3105PbF
HEXFET® Power MOSFET
Features
D
l
l
l
l
l
l
l
Logic-Level Gate Drive
VDSS = 55V
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
RDS(on) = 0.037Ω
G
ID = 25A
S
Description
®
Specifically designed for Automotive applications, this HEXFET Power
MOSFET utilizes the latest processing techniques to achieve extremely
low on-resistance per silicon area. Additional features of this design are
a 175°C junction operating temperature, fast switching speed and im-
proved repetitive avalanche rating . These features combine to make this
design an extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
D-Pak
IRLR3105
I-Pak
IRLU3105
The D-Pak is designed for surface mounting using vapor phase, infrared,
or wave soldering techniques. The straight lead version (IRLU series) is
for through-hole mounting applications. Power dissipation levels up to
1.5 watts are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
25
18
A
100
57
PD @TC = 25°C
Power Dissipation
W
W/°C
V
Linear Derating Factor
0.38
± 16
61
VGS
Gate-to-Source Voltage
EAS
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
mJ
EAS (tested)
IAR
94
See Fig.12a, 12b, 15, 16
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
dv/dt
TJ
3.4
V/ns
-55 to + 175
°C
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
2.65
Units
RθJC
RθJA
RθJA
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
50
°C/W
110
www.irf.com
1
12/7/04
IRLR/U3105PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
55 ––– –––
––– 0.056 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
–––
–––
1.0
15
30
35
37
43
VGS = 10V, ID = 15A
VGS = 5.0V, ID = 13A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 15A
VDS = 55V, VGS = 0V
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
––– 3.0
––– –––
V
S
Forward Transconductance
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
––– ––– 20
––– ––– 5.6
––– ––– 9.0
µA
IDSS
Drain-to-Source Leakage Current
VDS = 44V, VGS = 0V, TJ = 150°C
VGS = 16V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
IGSS
VGS = -16V
ID = 15A
Qg
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 44V
VGS = 5.0V, See Fig. 6 and 13
–––
–––
–––
–––
8.0 –––
57 –––
25 –––
37 –––
VDD = 28V
ID = 15A
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 24Ω
VGS = 5.0V, See Fig. 10
Between lead,
6mm (0.25in.)
from package
D
S
LD
Internal Drain Inductance
––– 4.5 –––
nH
G
LS
Internal Source Inductance
––– 7.5 –––
and center of die contact
VGS = 0V
Ciss
Input Capacitance
––– 710 –––
––– 150 –––
Coss
Output Capacitance
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
–––
28 –––
pF
ƒ = 1.0MHz, See Fig. 5
Coss
––– 890 –––
––– 110 –––
––– 210 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 44V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
25
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 100
––– ––– 1.3
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
V
TJ = 25°C, IS = 15A, VGS = 0V
TJ = 25°C, IF = 15A, VDD = 28V
––– 52
––– 82 120
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
78
ns
Qrr
ton
nC di/dt = 100A/µs
*
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to application note #AN-994
Notes through are on page 11
2
www.irf.com
IRLR/U3105PbF
100
10
1
1000
100
10
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
TOP
TOP
BOTTOM2.0V
BOTTOM2.0V
1
2.0V
0.1
0.01
2.0V
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
30
T
= 175°C
T
= 25°C
J
J
25
20
15
10
5
100.00
10.00
1.00
T
= 175°C
J
T
= 25°C
J
0.10
V
= 25V
V
= 25V
DS
20µs PULSE WIDTH
DS
20µs PULSE WIDTH
0.01
0
2.0
4.0
6.0 8.0
0
10
20
30
40
V
, Gate-to-Source Voltage (V)
I
Drain-to-Source Current (A)
GS
D,
Fig 4. Typical Forward Transconductance
Fig 3. Typical Transfer Characteristics
Vs. Drain Current
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3
IRLR/U3105PbF
1600
20
16
12
8
V
C
= 0V,
f = 1 MHZ
GS
I = 15A
D
= C + C
,
C
ds
SHORTED
iss
gs
gd
V
= 44V
DS
C
= C
rss
gd
VDS= 28V
VDS= 11V
C
= C + C
1200
800
400
0
oss
ds
gd
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
G
20
30
40
1
10
100
Q
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100.0
10.0
1.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
1
10
100
1000
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-toDrain Voltage (V)
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRLR/U3105PbF
30
25
20
15
10
5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25A
=
I
D
V
= 10V
GS
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T , Junction Temperature
(
C)
T
J
C
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
D = 0.50
0.20
1
0.10
0.05
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
0.02
0.01
0.1
t
1
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3105PbF
100
80
60
40
20
0
I
15V
D
TOP
6.1A
11A
15A
BOTTOM
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
2
V0GVS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
°
( C)
150
175
Starting Tj, Junction Temperature
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
2.0
V
G
I
= 250µA
D
1.5
1.0
0.5
0.0
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
3mA
T
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U3105PbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
∆
0.01
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
70
60
50
40
30
20
10
0
TOP
BOTTOM 50% Duty Cycle
= 15A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRLR/U3105PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRLR/U3105PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WE EK 16
IRFU120
916A
12
34
LINE A
Note: "P" in assembly lineposition
ASSEMBLY
LOT CODE
indicates "L ead-F ree"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 16
A= ASSEMBLY SITE CODE
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9
IRLR/U3105PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
RECTIFIER
LOGO
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW19, 1999
IN THE ASSEMBLY LINE "A"
DATE CODE
YEAR 9 = 1999
WEEK 19
IRFU120
919A
78
56
LINE A
ASSEMBLY
LOT CODE
Note: "P" inassemblyline
position indicates "Lead-Free"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S LE AD-F R EE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
10
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IRLR/U3105PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.55mH
ꢀ
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
Limited by TJmax ' see Fig 12a, 12b, 15, 16 for typical repetitive
avalanche performance.
RG = 25Ω, IAS = 15A, VGS =10V
ISD ≤ 25A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
This value determined from sample failure population. 100%
tested to this value in production.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
www.irf.com
11
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INFINEON
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