IRMCK371TY_技术文档

Data Sheet No. PD60336

IRMCK371

Sensorless Motor Control IC for Appliances

Features

Product Summary

MCE^TM(Motion Control Engine) - Hardware based

computation engine for high efficiency sinusoidal

sensorless control of permanent magnet AC motor

Support Induction motor sensorless FOC control

Supports both interior and surface permanent

magnet motors

Maximum crystal frequency

60 MHz

Maximum internal clock (SYSCLK) frequency 128 MHz

Maximum 8051 clock frequency

Sensorless control computation time

MCE^TMcomputation data range

8051 OTP Program memory

MCE program and Data RAM

GateKill latency (digital filtered)

PWM carrier frequency counter

A/D input channels

33 MHz

11 μsec typ

16 bit signed

64K bytes

8K bytes

2 μsec

Built-in hardware peripheral for single shunt

current feedback reconstruction

No external current or voltage sensing operational

amplifier required

Three/two-phase Space Vector PWM

Analog output (PWM)

16 bits/ SYSCLK

4

Embedded 8-bit high speed microcontroller (8051)

for flexible I/O and man-machine control

JTAG programming port for emulation/debugger

Serial communication interface (UART)

I²C/SPI serial interface

Watchdog timer with independent analog clock

Three general purpose timers/counters

Two special timers: periodic timer, capture timer

A/D converter resolution

12 bits

A/D converter conversion speed

8051 instruction execution speed

Analog output (PWM) resolution

UART baud rate (typ)

2 μsec

2 SYSCLK

8 bits

57.6K bps

13

Number of I/O (max)

Package (lead-free)

QFP48

Internal ‘One-Time Programmable’ (OTP) memory

and internal RAM for final production usage

Operating temperature

85°C

-40°C ~

Pin compatible with IRMCF371, RAM version

1.8V/3.3V CMOS

Description

IRMCK371 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK371 is

designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control.

IRMCK371 contains two computation engines. One is Motion Control Engine (MCE^TM) for sensorless control of permanent

magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one

monolithic chip. The MCE^TMcontains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle

estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by

connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the

Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit

and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle

instruction execution (16MIPS at 33MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process

signal monitoring and command input. An advanced graphic compiler for the MCE^TMis seamlessly integrated into the

MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments.

IRMCK371 comes with a small QFP48 pin lead-free package..

Rev 1.0

IRMCK371

TABLE OF CONTENTS

1

2

3

4

Overview....................................................................................................................................5

IRMCK371 Block Diagram and Main Functions.........................................................................6

Pinout.........................................................................................................................................8

Input/Output of IRMCK371.........................................................................................................9

4.1 8051 Peripheral Interface Group.......................................................................................10

4.2 Motion Peripheral Interface Group ....................................................................................10

4.3 Analog Interface Group .....................................................................................................11

4.4 Power Interface Group ......................................................................................................11

4.5 Test Interface Group .........................................................................................................11

Application Connections ..........................................................................................................12

DC Characteristics...................................................................................................................13

6.1 Absolute Maximum Ratings...............................................................................................13

6.2 System Clock Frequency and Power Consumption..........................................................13

6.3 Digital I/O DC Characteristics............................................................................................14

6.4 PLL and Oscillator DC characteristics...............................................................................14

6.5 Analog I/O DC Characteristics ..........................................................................................15

6.6 Under Voltage Lockout DC characteristics........................................................................15

6.7 AREF Characteristics........................................................................................................15

AC Characteristics ...................................................................................................................16

7.1 PLL AC Characteristics .....................................................................................................16

7.2 Analog to Digital Converter AC Characteristics.................................................................17

7.3 Op Amp AC Characteristics ..............................................................................................17

7.4 SYNC to SVPWM and A/D Conversion AC Timing...........................................................18

7.5 GATEKILL to SVPWM AC Timing.....................................................................................19

7.6 Interrupt AC Timing ...........................................................................................................19

7.7 I²C AC Timing....................................................................................................................20

7.8 SPI AC Timing...................................................................................................................21

7.8.1 SPI Write AC timing....................................................................................................21

7.8.2 SPI Read AC Timing...................................................................................................22

7.9 UART AC Timing...............................................................................................................23

5

6

7

7.10

7.11

7.12

CAPTURE Input AC Timing ...........................................................................................24

JTAG AC Timing ............................................................................................................25

OTP Programming Timing .............................................................................................26

8

9

10

11

12

I/O Structure.............................................................................................................................27

Pin List .....................................................................................................................................30

Package Dimensions............................................................................................................32

Part Marking Information ......................................................................................................33

Order Information .................................................................................................................33

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IRMCK371

TABLE OF FIGURES

Figure 1. Typical Application Block Diagram Using IRMCK371.....................................................5

Figure 2. IRMCK371 Internal Block Diagram.................................................................................6

Figure 3. IRMCK371 Pin Configuration..........................................................................................8

Figure 4. Input/Output of IRMCK371 .............................................................................................9

Figure 5. Application Connection of IRMCK371 ..........................................................................12

Figure 6. Clock Frequency vs. Power Consumption....................................................................13

Figure 7 Crystal oscillator circuit..................................................................................................16

Figure 8 Voltage droop of sample and hold.................................................................................17

Figure 9 SYNC to SVPWM and A/D Conversion AC Timing .......................................................18

Figure 10 GATEKILL to SVPWM AC Timing ...............................................................................19

Figure 11 Interrupt AC Timing .....................................................................................................19

Figure 12 I²C AC Timing..............................................................................................................20

Figure 13 SPI write AC Timing.....................................................................................................21

Figure 14 SPI read AC Timing.....................................................................................................22

Figure 15 UART AC Timing .........................................................................................................23

Figure 16 CAPTURE Input AC Timing.........................................................................................24

Figure 17 JTAG AC Timing..........................................................................................................25

Figure 18 OTP Programming Timing...........................................................................................26

Figure 19 All digital I/O except motor PWM output.........................................................................27

Figure 20 RESET, GATEKILL I/O ..................................................................................................27

Figure 21 Analog input ...................................................................................................................28

Figure 22 Analog operational amplifier output and AREF I/O structure.......................................28

Figure 23 VPP programming pin I/O structure ..........................................................................28

Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................29

Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................29

Figure 26 XTAL0/XTAL1 pins structure .......................................................................................29

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IRMCK371

TABLE OF TABLES

Table 1. Absolute Maximum Ratings ...........................................................................................13

Table 2. System Clock Frequency...............................................................................................13

Table 3. Digital I/O DC Characteristics........................................................................................14

Table 4. PLL DC Characteristics .................................................................................................14

Table 5. Analog I/O DC Characteristics.......................................................................................15

Table 6. UVcc DC Characteristics ...............................................................................................15

Table 7. AREF DC Characteristics ..............................................................................................15

Table 8. PLL AC Characteristics..................................................................................................16

Table 9. A/D Converter AC Characteristics .................................................................................17

Table 10. Current Sensing OP amp Amp AC Characteristics......................................................17

Table 11. SYNC AC Characteristics ............................................................................................18

Table 12. GATEKILL to SVPWM AC Timing ...............................................................................19

Table 13. Interrupt AC Timing......................................................................................................19

Table 14. I²C AC Timing ..............................................................................................................20

Table 15. SPI Write AC Timing....................................................................................................21

Table 16. SPI Read AC Timing....................................................................................................22

Table 17. UART AC Timing .........................................................................................................23

Table 18. CAPTURE AC Timing..................................................................................................24

Table 19. JTAG AC Timing..........................................................................................................25

Table 20. OTP Programming Timing ...........................................................................................26

Table 21. Pin List.........................................................................................................................31

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IRMCK371

1 Overview

IRMCK371 is a new International Rectifier integrated circuit device primarily designed as a one-

chip solution for complete inverter controlled appliance motor control applications. Unlike a

traditional microcontroller or DSP, the IRMCK371 provides a built-in closed loop sensorless

control algorithm using the unique Motion Control Engine (MCE^TM) for permanent magnet motors.

The MCE^TMconsists of a collection of control elements, motion peripherals, a dedicated motion

control sequencer and dual port RAM to map internal signal nodes. IRMCK371 also employs a

unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and

enables a direct shunt resistor interface to the IC. Motion control programming is achieved using

a dedicated graphical compiler integrated into the MATLAB/Simulink^TMdevelopment environment.

Sequencing, user interface, host communication, and upper layer control tasks can be

implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped

with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application

schematic using the IRMCK371.

IRMCF371 is intended for development purpose and contains 48K bytes of RAM, which can be

loaded from external EEPROM for 8051 program execution. For high volume production,

IRMCK371 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCK371 and

IRMCK371 come in the same 48-pin QFP package with identical pin configuration to facilitate PC

board layout and transition to mass production

Figure 1. Typical Application Block Diagram Using IRMCK371

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IRMCK371

2 IRMCK371 Block Diagram and Main Functions

IRMCK371 block diagram is shown in Figure 2.

Figure 2. IRMCK371 Internal Block Diagram

IRMCK371 contains the following functions for sensorless AC motor control applications:

•

Motion Control Engine (MCE^TM)

o Proportional plus Integral block

o Low pass filter

o Differentiator and lag (high pass filter)

o Ramp

o Limit

o Angle estimate (sensorless control)

o Inverse Clark transformation

o Vector rotator

o Bit latch

o Peak detect

o Transition

o Multiply-divide (signed and unsigned)

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IRMCK371

o Divide (signed and unsigned)

o Adder

o Subtractor

o Comparator

o Counter

o Accumulator

o Switch

o Shift

o ATAN (arc tangent)

o Function block (any curve fitting, nonlinear function)

o 16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)

o MCE^TMprogram and data memory (6K byte). ^{Note 1}

o MCE^TMcontrol sequencer

•

8051 microcontroller

o Three 16-bit timer/counters

o 16-bit periodic timer

o 16-bit analog watchdog timer

o 16-bit capture timer

o Up to 13 discrete I/Os

o Four-channel 12-bit A/D

One buffered channel for current sensing (0 – 1.2V input)

Three unbuffered channels (0 – 1.2V input)

o JTAG port (4 pins)

o One channel of analog output (8-bit PWM)

o UART

o I²C/SPI port

o 64K byte program OTP

o 2K byte data RAM. ^{Note 1}

Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051

data. Different sizes can be allocated depending on applications.

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IRMCK371

3 Pinout

48 47 46 45 44 43 42 41 40 39 38 37

XTAL0

1

2

36

35

34

33

32

31

30

29

28

27

26

25

P3.0/INT2/CS1

XTAL1

PWMUH

PWMUL

3

P1.0/T2

P1.1/RXD

P1.2/TXD

P1.3/SYNC/SCK

P1.4/CAP

VDD2

PWMVH

4

5

PWMVL

PWMWH

PWMWL

GATEKILL

VDD1

6

7

8

(Top View)

9

VSS

10

11

12

VDD1

VSS

VDD2

P2.0/NMI

P2.1

AIN2

13 14 15 16 17 18 19 20 21 22 23 24

Figure 3. IRMCK371 Pin Configuration

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IRMCK371

4 Input/Output of IRMCK371

All I/O signals of IRMCK371 are shown in Figure 4. All I/O pins are 3.3V logic interface except

A/D interface pins.

XTAL0

Crystal

XTAL1

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

GATEKILL

RS232C

Interface

PWM gate signal

Interface

P1.2/TXD

P1.1/RXD

SDA/CS0

I2C

SCL/SO-S/VPPI

Interface

P1.0/T2

P1.3/SYNC/SCK

P1.4/CAP

AVDD

AVSS

Discrete I/O

P2.0/NMI

AREF

P2.1

CMEXT

P3.0/INT2/CS1

P3.2/INT0

RESET

IFB+

IFB-

System Reset

A/D Interface

IFBO

AIN0

AIN1

AIN2

P5.3/TDI

TCK

P5.1/TSM

P5.2/TDO

JTAG port

D/A Interface

(PWM output)

P2.6/AOPWM

VDD1

VDD2

VSS

Digital power/

ground

PLLVDD

PLLVSS

PLL power/

ground

SCL/SO-S/VPPI

OTP programming

Figure 4. Input/Output of IRMCK371

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4.1 8051 Peripheral Interface Group

UART Interface

P1.2/TXD

P1.1/RXD

Output, Transmit data from IRMCK371, can be configured as P1.2

Input, Receive data to IRMCK371, can be configured as P1.1

Discrete I/O Interface

P1.0/T2

Input/output port 1.0, can be configured as Timer 2 input

Input/output port 1.1, can be configured as RXD input

Input/output port 1.2, can be configured as TXD output

P1.1/RXD

P1.2/TXD

P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock

P1.4/CAP

P2.0/NMI

P2.1

Input/output port 1.4, can be configured as Capture Timer input

Input/output port 2.0, can be configured as non-maskable interrupt input

Input/output port 2.1

P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select

1

P3.2/INT0

Input/output port 3.2, can be configured as INT0 input

Analog Output Interface

AOPWM

Output, PWM output 0, 8-bit resolution, configurable carrier frequency

Crystal Interface

XTAL0

Input, connected to crystal

Output, connected to crystal

XTAL1

Reset Interface

RESET

Inout, system reset, needs to be pulled up to VDD1 but doesn’t require

external RC time constant

I²C/SPI Interface

SCL/SO-SI

Input/output, I²C clock output or SPI data

SDA/CS0

Input/output, I²C Data line or SPI chip select 0

P3.0/INT2/CS1 Input/output, INT2 or SPI chip select 1

P1.3/SYNC/SCK Input/output, SYNC output or SPI clock, needs to be pulled up to VDD1

in order to boot from I²C EEPROM

4.2 Motion Peripheral Interface Group

PWM

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

Output, PWM phase U high side gate signal

Output, PWM phase U low side gate signal

Output, PWM phase V high side gate signal

Output, PWM phase V low side gate signal

Output, PWM phase W high side gate signal

Output, PWM phase W low side gate signal

Fault

GATEKILL

Input, upon assertion, this negates all six PWM signals, programmable

logic sense

Rev 1.0

IRMCK371

4.3 Analog Interface Group

AVDD

AVSS

AREF

CMEXT

Analog power (1.8V)

Analog power return

0.6V buffered output

Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be

connected.

IFB+

IFB-

Input, Operational amplifier positive input for shunt resistor current

sensing

Input, Operational amplifier negative input for shunt resistor current

sensing

IFBO

AIN0

Output, Operational amplifier output for shunt resistor current sensing

Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus

voltage input

AIN1

AIN2

Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to

AVSS if unused

Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to

AVSS if unused

4.4 Power Interface Group

VDD1

Digital power for I/O (3.3V)

VDD2

VSS

Digital power for core logic (1.8V)

Digital common

PLLVDD

PLLVSS

PLL power (1.8V)

PLL ground return

4.5 Test Interface Group

TSTMOD

P5.1/TSM

P5.2/TDO

P5.3/TDI

TCK

Must be tied to VSS, used only for factory testing.

Input/output port 5.1, configured as JTAG port by default

Input/output port 5.2, configured as JTAG port by default

Input/output port 5.3, configured as JTAG port by default

Input, JTAG test clock

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IRMCK371

5 Application Connections

Typical application connection is shown in Figure 5. All components necessary to implement a

complete sensorless drive control algorithm are shown connected to IRMCK371.

XTAL0

System

Clock

4MHz

Crystal

XTAL1

PLLVDD

PLL

Logic

System

clock

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

1.8V

PLLVSS

Host

Microcontroller

(RS232C)

Motion

Control

Modules

Low Loss

Space

Vector

PWM

P1.2/TXD

P1.1/RXD

RS232C

I²C/SPI

Dual

Port

SDA/CS0

Other Communication

(I²C or SPI)

GATEKILL

SCL/SO-SI

Memory

(1Kbyte)

&

MCE

Memory

(3kByte)

P1.0/T2

P1.3/SYNC/SCK

P1.4/CAP

PORT1

PORT2

PORT3

Motion

Control

Sequencer

P2.0/NMI

P2.1

P3.0/INT2/CS1

P3.2/INT0

Digital I/O

Control

0.6V

IFBC+

Motor

DC bus shunt

resistor

P2.6/AOPWM0

S/H

IFBC-

PWM0

Analog Output

IFBCO

Timers

AIN0

DC bus

voltage

Watchdog

Timer

12bit

A/D

&

AIN1

AIN2

TCLK

Other analog input (0-1.2V)

P5.3/TDI

P5.1/TSM

JTAG Port

JTAG

Local

RAM

4kByte

MUX

Interface

5

Control

P5.2/TDO

RESET

AREF

Optional External Voltage

Reference (0.6V)

System

Reset

CMEXT

RESET

Program

OTP ROM

(64kByte)

OTP Programming

6.5V

SCL/SO-SI

Power

AVDD

AVSS

VDD1

VDD2

3.3V

1.8V

VSS

System

clock

8051

CPU

Clock

divider

Figure 5. Application Connection of IRMCK371

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IRMCK371

6 DC Characteristics

6.1 Absolute Maximum Ratings

Symbol

V_DD1

V_DD2

V_IA

Parameter

Supply Voltage

Analog Input Voltage

Digital Input Voltage

Ambient Temperature

Storage Temperature

Min

Typ

Max

3.6 V

1.98 V

3.65 V

85 ˚C

Condition

-0.3 V

-40 ˚C

-65 ˚C

-

Respect to VSS

Respect to AVSS

Respect to VSS

V_ID

T_A

T_S

150 ˚C

Table 1. Absolute Maximum Ratings

Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent

damage to the device. These are stress ratings only and function of the device at these or any

other conditions beyond those indicated in the operational sections of the specifications are not

implied.

6.2 System Clock Frequency and Power Consumption

Symbol

SYSCLK

8051CLK

Parameter

System Clock

8051 Clock

Min

32

-

Typ

-

Max

128

32

Unit

MHz

Table 2. System Clock Frequency

Power Consumption

180

160

140

120

100

80

1.8V

3.3V

60

Total Power

40

20

0

20

40

60

80

100

120

140

Figure 6. Clock Fre^Mq^Cu^Ee^Fn^rec^quy^env^cs^{y (}.^MP^Hzo⁾wer Consumption

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IRMCK371

6.3 Digital I/O DC Characteristics

Symbol

V_DD1

Parameter

Supply Voltage

Input Low Voltage

Input High Voltage

Input capacitance

Input leakage current

Low level output

current

High level output

current

Low level output

current

Min

3.0 V

1.62 V

-0.3 V

2.0 V

-

Typ

3.3 V

1.8 V

-

Max

3.6 V

1.98 V

0.8 V

3.6 V

-

Condition

Recommended

V_DD2

V_IL

V_IH

C_IN

I_L

Recommended

(1)

3.6 pF

±10 nA

13.2 mA

±1 μA

15.2 mA

V_O= 3.3 V or 0 V

V_OL= 0.4 V

(2)

I_OL1

8.9 mA

12.4 mA

17.9 mA

24.6 mA

(1)

(2)

I_OH1

24.8 mA

26.3 mA

49.5 mA

38 mA

33.4 mA

81 mA

V_OH= 2.4 V

(1)

(3)

I_OL2

V_OL= 0.4 V

(1)

(3)

I_OH2

High level output

current

V_OH= 2.4 V

(1)

Table 3. Digital I/O DC Characteristics

Note:

(1) Data guaranteed by design.

(2) Applied to SCL/SO-SI, SDA/CS0 pins.

(3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P2.0/NMI, P2.1,

P2.6/AOPWM0, P3.0/INT2/CS1, P3.2/INT0, P5.1/TMS, P5.2/TDO, P5.3/TDI, GATEKILL,

PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, PWMWH pins.

6.4 PLL and Oscillator DC characteristics

Symbol

V_PLLVDD

V_{IL OSC}

Parameter

Supply Voltage

Oscillator Input Low

Voltage

Min

1.62 V

V_PLLVSS

Typ

1.8 V

-

Max

1.92 V

0.2*

Condition

Recommended

V_PLLVDD= 1.8 V

(1)

V_PLLVDD

V_{IH OSC}

Oscillator Input High

Voltage

0.8*

V_PLLVDD

V_PLLVDD= 1.8 V

(1)

Table 4. PLL DC Characteristics

Note:

(1) Data guaranteed by design.

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IRMCK371

6.5 Analog I/O DC Characteristics

- OP amp for current sensing (IFB+, IFB-, IFBO)

C_AREF= 1nF, C_MEXT= 100nF. Unless specified, Ta = 25˚C.

Symbol

Parameter

Supply Voltage

Input Offset Voltage

Input Voltage Range

OP amp output

operating range

Input capacitance

OP amp feedback

resistor

Min

1.71 V

-

Typ

1.8 V

-

Max

1.89 V

26 mV

1.2 V

Condition

V_AVDD

V_OFFSET

V_I

Recommended

V_AVDD= 1.8 V

Recommended

V_AVDD= 1.8 V

0 V

V_OUTSW

50 mV

-

1.2 V

(1)

C_IN

R_FDBK

-

3.6 pF

-

Requested

between IFBO

5 kΩ

20 kΩ

and IFB-

(1)

OP _GAINCL

CMRR

I_SRC

Operating Close loop

Gain

80 db

-

(1)

Common Mode

Rejection Ratio

Op amp output

source current

Op amp output sink

current

-

80 db

1 mA

100 μA

V_OUT= 0.6 V

(1)

I_SNK

V_OUT= 0.6 V

(1)

Table 5. Analog I/O DC Characteristics

Note:

(1) Data guaranteed by design.

6.6 Under Voltage Lockout DC characteristics

Unless specified, Ta = 25˚C, AVDD (1.8V)

Symbol

UV_CC+

Parameter

UVcc positive going

Threshold¹⁾

Min

1.53 V

Typ

1.66 V

Max

1.71 V

Condition

V_DD1= 3.3 V

UV_CC-

UV_CCH

Note:

UVcc negative going

Threshold

UVcc Hysteresys

1.52 V

1.62 V

1.71 V

V_DD1= 3.3 V

-

40 mV

-

Table 6. UVcc DC Characteristics

(1) Data guaranteed by design.

6.7 AREF Characteristics

C_AREF= 1nF, C_MEXT= 100nF. Unless specified, Ta = 25˚C.

Symbol

V_AREF

ΔV_o

Parameter

AREF Output Voltage

Load regulation (V_DC-0.6)

Power Supply Rejection

Ratio

Min

495 mV

Typ

600 mV

1 mV

Max

700 mV

Condition

V_AVDD= 1.8 V

(1)

-

(1)

PSRR

75 db

Table 7. AREF DC Characteristics

Note: (1) Data guaranteed by design.

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IRMCK371

7 AC Characteristics

7.1 PLL AC Characteristics

Symbol

F_CLKIN

Parameter

Crystal input

frequency

Internal clock

frequency

Sleep mode output F_CLKIN÷ 256

frequency

Short time jitter

Duty cycle

Min

3.2 MHz

Typ

4 MHz

Max

60 MHz

Condition

(1)

(see figure below)

(1)

F_PLL

32 MHz

50 MHz

-

128 MHz

-

(1)

F_LWPW

(1)

J_S

D

T_LOCK

-

200 psec

50 %

-

PLL lock time

500 μsec

Table 8. PLL AC Characteristics

Note:

(1) Data guaranteed by design.

R₁=1M

R₂=10

Xtal

C₁=30PF

C₂=30PF

Figure 7 Crystal oscillator circuit

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16

IRMCK371

7.2 Analog to Digital Converter AC Characteristics

Unless specified, Ta = 25˚C.

Symbol

T_CONV

T_HOLD

Parameter

Conversion time

Sample/Hold

Min

-

Typ

-

Max

2.05 μsec

10 μsec

Condition

(1)

Voltage droop ≤

15 LSB

maximum hold time

(see figure below)

Table 9. A/D Converter AC Characteristics

Note:

(1) Data guaranteed by design.

Input Voltage

Voltage droop

S/H Voltage

t_SAMPLE

T_HOLD

Figure 8 Voltage droop of sample and hold

7.3 Op Amp AC Characteristics

- OP amps for current sensing (IFB+, IFB-, IFBO)

Unless specified, Ta = 25˚C.

Symbol

OP_SR

Parameter

OP amp slew rate

Min

-

Typ

10 V/μsec

Max

-

Condition

V_AVDD= 1.8 V, CL

= 33 pF ⁽¹⁾

(1)

OP_IMP

T_SET

OP input impedance

Settling time

-

10⁸Ω

400 ns

-

V_AVDD= 1.8 V, CL

= 33 pF ⁽¹⁾

Table 10. Current Sensing OP amp Amp AC Characteristics

Note:

(1) Data guaranteed by design.

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17

IRMCK371

7.4 SYNC to SVPWM and A/D Conversion AC Timing

t_wSYNC

SYNC

t_dSYNC1

IU,IV,IW

t_dSYNC2

AINx

t_dSYNC3

PWMUx,PWMVx,PWMWx

Figure 9 SYNC to SVPWM and A/D Conversion AC Timing

Unless specified, Ta = 25˚C.

Symbol

t_wSYNC

Parameter

SYNC pulse width

SYNC to current

feedback conversion

time

SYNC to AIN0-6

analog input

conversion time

SYNC to PWM output

delay time

Min

-

Typ

32

-

Max

-

100

Unit

SYSCLK

t_dSYNC1

t_dSYNC2

t_dSYNC3

-

200

2

SYSCLK

(1)

SYSCLK

Table 11. SYNC AC Characteristics

Note:

(1) AIN1 through AIN6 channels are converted once every 6 SYNC events

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18

IRMCK371

7.5 GATEKILL to SVPWM AC Timing

Figure 10 GATEKILL to SVPWM AC Timing

Unless specified, Ta = 25˚C.

Symbol

t_wGK

t_dGK

Parameter

GATEKILL pulse width

GATEKILL to PWM

output delay

Min

32

-

Typ

-

Max

-

100

Unit

SYSCLK

Table 12. GATEKILL to SVPWM AC Timing

7.6 Interrupt AC Timing

Figure 11 Interrupt AC Timing

Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

Typ

Max

Unit

t_wINT

INT0, INT1 Interrupt

Assertion Time

INT0, INT1 latency

4

-

SYSCLK

t_dINT

-

4

SYSCLK

Table 13. Interrupt AC Timing

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19

IRMCK371

7.7 I²C AC Timing

T_I2CLK

SCL

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

t_I2EN1

t_I2ST1

t_I2ST2

t_I2EN2

SDA

Figure 12 I²C AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_I2CLK

t_I2ST1

Parameter

Min

10

0.25

Typ

Max

8192

Unit

SYSCLK

T_I2CLK

SYSCLK

I²C clock period

-

I²C SDA start time

I²C SCL start time

I²C write setup time

I²C write hold time

I²C read setup time

I²C read hold time

-

t_I2ST2

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

I²C filter time⁽¹⁾

1

Table 14. I²C AC Timing

Note:

(1) I²C read setup time is determined by the programmable filter time applied to I²C

communication.

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20

IRMCK371

7.8 SPI AC Timing

7.8.1 SPI Write AC timing

Figure 13 SPI write AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_SPICLK

t_SPICLKHT

t_SPICLKLT

t_CSDELAY

t_WRDELAY

Parameter

SPI clock period

SPI clock high time

SPI clock low time

CS to data delay time

CLK falling edge to data

delay time

Min

4

-

Typ

Max

-

10

Unit

-

1/2

-

SYSCLK

T_SPICLK

nsec

-

nsec

t_CSHIGH

t_CSHOLD

CS high time between two

consecutive byte transfer

CS hold time

1

-

T_SPICLK

1

Table 15. SPI Write AC Timing

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21

IRMCK371

7.8.2 SPI Read AC Timing

Figure 14 SPI read AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_SPICLK

t_SPICLKHT

t_SPICLKLT

t_CSRD

t_RDSU

t_RDHOLD

t_CSHIGH

Parameter

SPI clock period

SPI clock high time

Min

4

-

10

1

Typ

-

1/2

-

Max

-

10

-

Unit

SYSCLK

T_SPICLK

nsec

T_SPICLK

SPI clock low time

CS to data delay time

SPI read data setup time

SPI read data hold time

CS high time between two

consecutive byte transfer

CS hold time

-

t_CSHOLD

-

1

-

T_SPICLK

Table 16. SPI Read AC Timing

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22

IRMCK371

7.9 UART AC Timing

T_BAUD

TXD

Data and Parity Bit

Stop Bit

Start Bit

RXD

T_UARTFIL

Figure 15 UART AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_BAUD

T_UARTFIL

Parameter

Baud Rate Period

UART sampling filter

period ⁽¹⁾

Min

-

Typ

57600

1/16

Max

-

Unit

bit/sec

T_BAUD

Table 17. UART AC Timing

Note:

(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval

of 1/16 T_BAUD. If three sampled values do not agree, then UART noise error is generated.

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23

IRMCK371

7.10 CAPTURE Input AC Timing

Figure 16 CAPTURE Input AC Timing

Unless specified, Ta = 25˚C.

Symbol Parameter

T_CAPCLK

Min

8

4

Typ

-

Max

-

Unit

SYSCLK

CAPTURE input period

CAPTURE input high

time

t_CAPHIGH

t_CAPLOW

t_CRDELAY

CAPTURE input low

time

CAPTURE falling edge

to capture register latch

time

4

-

4

t_CLDELAY

CAPTURE rising edge

to capture register latch

time

CAPTURE input

interrupt latency time

-

4

SYSCLK

t_INTDELAY

Table 18. CAPTURE AC Timing

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24

IRMCK371

7.11 JTAG AC Timing

T_JCLK

t_JLOW

t_JHIGH

TCK

t_CO

TDO

t_JSETUP

t_JHOLD

TDI/TMS

Figure 17 JTAG AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_JCLK

t_JHIGH

t_JLOW

t_CO

Parameter

TCK Period

TCK High Period

TCK Low Period

TCK to TDO propagation

delay time

Min

-

10

0

Typ

Max

50

-

5

Unit

MHz

nsec

-

t_JSETUP

t_JHOLD

TDI/TMS setup time

TDI/TMS hold time

4

0

-

nsec

Table 19. JTAG AC Timing

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25

7.12 OTP Programming Timing

Figure 18 OTP Programming Timing

Unless specified, Ta = 25˚C.

Symbol Parameter

T_VPS

Min

10

15

Typ

-

Max

-

Unit

nsec

VPP Setup Time

VPP Hold Time

T_VPH

Table 20. OTP Programming Timing

Rev 1.0

IRMCK371

8 I/O Structure

The following figure shows the motor PWM and digital I/O structure

VDD1

(3.3V)

Internal digital circuit

Low true logic

70k

6.0V

100

6.0V

VSS

Figure 19 All digital I/O except motor PWM output

The following figure shows RESET and GATEKILL I/O structure.

VDD1

(3.3V)

RESET

GATEKILL

70k

I/O

6.0V

100

6.0V

VSS

Figure 20 RESET, GATEKILL I/O

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27

IRMCK371

The following figure shows the analog input structure.

AVDD

Analog input

6.0V

100

Analog Circuit

6.0V

AVSS

Figure 21 Analog input

The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.

1.8V

Analog output

6.0V

Analog Circuit

6.0V

AVSS

Figure 22 Analog operational amplifier output and AREF I/O structure

The following figure shows the VPP pin I/O structure

VPP input

100

Analog Circuit

8.0V

VSS

Figure 23 VPP programming pin I/O structure

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28

The following figure shows the VSS, AVSS and PLLVSS pin structure

Figure 24 VSS, AVSS and PLLVSS pin structure

The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure

Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure

The following figure shows the XTAL0 and XTAL1 pins structure

VDD1

6.0V

VSS

Figure 26 XTAL0/XTAL1 pins structure

Rev 1.0

IRMCK371

9 Pin List

Internal

Number

Pin Name

Pull-up

Type Description

/Pull-down

1

2

3

XTAL0

XTAL1

P1.0/T2

I

O

I/O

Crystal input

Crystal output

Discrete programmable I/O or Timer/Counter 2

input

4

5

P1.1/RXD

P1.2/TXD

I/O

Discrete programmable I/O or UART receive input

Discrete programmable I/O or UART transmit

output

6

P1.3/SYNC/

SCK

I/O

Discrete programmable I/O or SYNC output or SPI

clock output

7

8

P1.4/CAP

VDD2

I/O

P

Discrete programmable I/O or Capture Timer input

1.8V digital power

9

VSS

P

Digital common

10

11

12

13

VDD1

P2.0/NMI

P2.1

P2.6/AOPW

M

P

3.3V digital power

Discrete I/O or Non Maskable Interrupt

Discrete I/O

I/O

Discrete I/O or PWM digital output

14

15

16

VDD2

VSS

AIN0

P

I

1.8V digital power

Digital common

Analog input channel 0, 0-1.2V range, needs to be

pulled down to AVSS if unused

1.8V analog power

17

18

19

AVDD

AVSS

AIN1

P

I

Analog common

Analog input channel 1, 0-1.2V range, needs to be

pulled down to AVSS if unused

Unbuffered 0.6V output. Capacitor needs to be

connected.

20

CMEXT

O

21

22

23

24

25

AREF

IFB-

IFB+

IFBO

AIN2

O

I

O

I

Analog reference voltage output (0.6V)

Single shunt current sensing OP amp input (-)

Single shunt current sensing OP amp input (+)

Single shunt current sensing OP amp output

Analog input channel 2, 0-1.2V range, needs to be

pulled down to AVSS if unused

1.8V digital power

26

27

28

29

VDD2

VSS

VDD1

GATEKILL

P

I

Digital common

3.3V digital power

PWM shutdown input, 2-μsec digital filter,

configurable either high or low true.

PWM gate drive for phase W low side, configurable

either high or low true

PWM gate drive for phase W high side,

configurable either high or low true

30

31

PWMWL

PWMWH

70 kΩ Pull

up

70 kΩ Pull

up

O

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30

IRMCK371

Number

Internal

Pull-up

/Pull-down

70 kΩ Pull

up

70 kΩ Pull

up

70 kΩ Pull

up

Pin Name

PWMVL

PWMVH

PWMUL

PWMUH

Type Description

32

33

34

35

36

37

O

PWM gate drive for phase V low side, configurable

either high or low true

PWM gate drive for phase V high side, configurable

either high or low true

PWM gate drive for phase U low side, configurable

either high or low true

PWM gate drive for phase U high side, configurable

either high or low true

Discrete programmable I/O or external interrupt 2

input or SPI chip select 1

Discrete programmable I/O or external interrupt 0

input

O

70 kΩ Pull

up

O

P3.0/INT2/C

S1

P3.2/NINT0

I/O

38

39

40

41

42

43

44

45

VSS

P

I/O

I

Digital common

I2C clock or SPI data

I2C data or SPI chip select 0

Discrete I/O or JTAG test mode select

Discrete I/O or JTAG test data output

Discrete I/O or JTAG test data input

JTAG test clock input

SCL/SO-SI

SDA/CS0

P5.1/TMS

P5.2/TDO

P5.3/TDI

TCK

TSTMOD

58 kΩ pull

I

Test mode input, must be tied to VSS

down

46

47

48

RESET

PLLVDD

PLLVSS

I/O

P

Reset, low true, Schmitt trigger input

1.8V PLL power

PLL ground

Table 21. Pin List

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31

IRMCK371

10 Package Dimensions

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32

IRMCK371

11 Part Marking Information

12 Order Information

Lead-Free Part in 48-lead QFP

Moisture Sensitivity Rating – MSL3

Part number

IRMCK371TR

IRMCK371TY

Order quantities

2000 parts on tape and reel in dry pack

2500 parts on trays (160 parts per tray) in dry pack

The LQFP-48 is MSL3 qualified

This product has been designed and qualified for the industrial level

Qualification standards can be found at www.irf.com <http://www.irf.com>

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105

Data and specifications subject to change without notice. 12/25/2007

www.irf.com

33


型号：	IRMCK371TY
厂家：	Infineon
描述：	Sensorless Motor Control IC for Appliances 无传感器电机控制IC，适用于家电传感器电机
文件：	总33页 (文件大小：557K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRMCK371TY [INFINEON]

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