IRS2001 [INFINEON]
200 V 高边和低边驱动器 IC,具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 8 引脚 PDIP 封装，适用于 IGBT 和 MOSFET。也有 8 引脚 SOIC和 14 引脚 MLPQ 4x4 封装可选。;
| 型号： | IRS2001 |
| 厂家： | 
Infineon |
| 描述： | 200 V 高边和低边驱动器 IC,具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 8 引脚 PDIP 封装，适用于 IGBT 和 MOSFET。也有 8 引脚 SOIC和 14 引脚 MLPQ 4x4 封装可选。 驱动 双极性晶体管 光电二极管 驱动器 |
| 文件： | 总15页 (文件大小：1258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
Data Sheet No. PD60268 revA
IRS2001(S)PbF
HIGH AND LOW SIDE DRIVER
Features
Product Summary
• Floating channel designed for bootstrap operation
• Fully operational to +200 V
• Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout
V
200 V max.
200 mA/420 mA
10 V - 20 V
160 ns/150 ns
50 ns
OFFSET
I +/-
O
V
OUT
• 3.3 V, 5 V, and 15 V logic input compatible
• Matched propagation delay for both channels
• Outputs in phase with inputs
t
(typ.)
on/off
• RoHS compliant
Delay Matching
Description
Packages
The IRS2001 is a high voltage, high speed power
MOSFET and IGBT driver with independent high-side
and low-side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input
is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high-
side configuration which operates up to 200 V.
8-Lead SOIC
IRS2001S
8-Lead PDIP
IRS2001
Typical Connection
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IRS2001
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
B
High-side floating supply voltage
-0.3
- 25
B
225
V + 0.3
B
V
S
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
V
V
HO
V
- 0.3
V
B
+ 0.3
25
S
V
V
CC
-0.3
-0.3
-0.3
—
V
LO
V + 0.3
CC
V
IN
Logic input voltage (HIN & LIN)
V + 0.3
CC
dV /dt
S
Allowable offset supply voltage transient
50
V/ns
W
(8 lead PDIP)
(8 lead SOIC)
(8 lead PDIP)
(8 lead SOIC)
—
1.0
0.625
125
200
150
150
P
D
Package power dissipation @ T ≤ +25 °C
A
—
—
°C/W
Rth
JA
Thermal resistance, junction to ambient
—
T
J
Junction temperature
—
°C
T
S
Storage temperature
-55
—
T
L
Lead temperature (soldering, 10 seconds)
300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V offset rating is tested with all supplies biased at a 15 V differential.
S
Symbol
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Min.
Max.
Units
V
B
V
+ 10
V + 20
S
S
V
S
Note 1
200
V
HO
V
S
V
B
V
V
CC
10
0
20
V
LO
V
CC
V
IN
Logic input voltage (HIN & LIN)
0
V
CC
T
A
Ambient temperature
-40
125
°C
Note 1: Logic operational for V of -5 V to +200 V. Logic state held for V of -5 V to -V . (Please refer to the Design
S S BS
Tip DT97-3 for more details).
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2
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Dynamic Electrical Characteristics
V
(V , V ) = 15 V, C = 1000 pF and T = 25 °C unless otherwise specified.
BIAS CC BS
L
A
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
—
—
—
—
—
160
150
70
220
220
100
60
V = 0 V
S
on
t
V = 200 V
S
off
ns
t
r
t
f
Turn-off fall time
35
MT
Delay matching, HS & LS turn-on/off
—
50
Static Electrical Characteristics
V
(V , V ) = 15 V and T = 25 °C unless otherwise specified. The V , V
and I parameters are referenced to
IN TH, IN
BIAS CC BS
A
COM. The V and I parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
O
O
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “1” input voltage
2.5
—
—
—
—
—
—
—
—
—
0.8
0.1
0.05
50
IH
V
= 10 V to 20 V
CC
V
Logic “0” input voltage
IL
V
V
OH
High level output voltage, V
Low level output voltage, V
- V
O
0.05
0.02
—
BIAS
I
O
= 2 mA
V
OL
O
I
LK
Offset supply leakage current
V
= V = 200 V
B S
I
Quiescent V supply current
BS
30
55
QBS
V
= 0 V or 5 V
IN
µA
I
Quiescent V
supply current
CC
150
270
QCC
I
Logic “1” input bias current
Logic “0” input bias current
VIN = 5 V
VIN = 0 V
—
—
8
3
10
5
IN+
I
—
IN-
V
V
V
supply undervoltage positive going threshold
supply undervoltage negative going threshold
8.9
8.2
9.8
CCUV+
CC
CC
V
V
7.4
9
CCUV-
V
O
= 0 V
I
Output high short circuit pulsed current
200
420
290
600
—
V =Logic “1”
IN
O+
PW ≤ 10 µs
mA
V
O
= 15 V
I
Output low short circuit pulsed current
—
V = Logic “0”
IN
O-
PW ≤ 10 µs
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3
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Functional Block Diagram
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IRS2001
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4
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Lead Definitions
Symbol Description
HIN
LIN
Logic input for high-side gate driver output (HO), in phase
Logic input for low-side gate driver output (LO), in phase
High-side floating supply
V
B
HO
High-side gate drive output
V
S
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
V
CC
LO
COM
Low-side return
Lead Assignments
8 Lead PDIP
8 Lead SOIC
IRS2001PbF
IRS2001SPbF
Part Number
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5
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
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Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
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Figure 3. Delay Matching Waveform Definitions
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6
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
500
400
300
200
100
0
500
400
300
200
100
0
Max
.
Max
.
Typ.
Typ.
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
V
Supply Voltage (V)
BIAS
Figure 6A. Turn-On Time vs. Temperature
Figure 6B. Turn-On Time vs. Supply Voltage
500
400
300
500
400
300
200
100
0
M ax.
Typ.
200
100
0
0
2
4
6
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Input Voltage (V)
Temperature (°C)
Figure 6C. Turn-On Time vs. Input Voltage
Figure 7A. Turn-Off Time vs. Temperature
500
400
500
400
300
200
100
0
300
Max.
Typ.
Max.
200
100
Typ
.
0
0
2
4
6
8
10 12 14 16 18 20
10
12
14
16
18
20
V
Supply Voltage (V)
BIAS
Input Voltage (V)
Figure 7C. Turn-Off Time vs. Input Voltage
Figure 7B. Turn-Off Time vs. Supply Voltage
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
500
400
300
200
100
0
500
400
300
200
100
0
Max.
Typ.
Max.
Typ.
10
12
14
16
18
20
-50
-25
0
25
50
75
100 125
Temperature (°C)
V
Supply Voltage (V)
BIAS
Figure 9A. Turn-On Rise Time vs. Temperature
Figure 9B. Turn-On Rise Time vs. Voltage
200
200
150
150
100
50
100
Max.
Typ.
Max.
50
Typ.
0
0
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (°C)
V
Supply Voltage (V)
BIAS
Figure 10A. Turn-Off Fall Time vs. Temperature
Figure 10B. Turn-Off Fall Time vs. Voltage
8
7
6
5
4
3
8
7
6
5
4
3
Min.
Min.
2
2
1
0
1
0
-50 -25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
V
BIAS Supply Voltage (V)
Figure 12A. Logic "1" Input Voltage
vs. Temperature
Figure 12B. Logic "1" Input Voltage
vs. Voltage
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
4
3.2
2.4
1.6
0.8
0
4
3.2
2.4
1.6
0.8
0
M ax
.
M ax
.
10
12
14
16
18
20
-50
-25
0
25
50
75
100
125
Temperature (°C)
V
Supply Voltage (V)
cc
Figure 13B. Logic "0" Input Voltage
vs. Supply Voltage
Figure 13A. Logic "0" Input Voltage
vs. Temperature
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0.0
Max.
Max.
Typ.
Typ.
-50
-25
0
25
50
75
100 125
10
12
14
16
VBIAS Supply Voltage (V)
18
20
Temperature (oC)
Figure 14B. High Level Output
vs. Supply Voltage
Figure 14A. High Level Output Voltage
vs. Temperature
0.5
0.5
0.4
0.3
0.2
0.1
0.0
0.4
0.3
0.2
0.1
0
Max.
Max.
Typ.
Typ.
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
V
BIAS Supply Voltage (V)
Figure 15A. Low Level Output Voltage
vs. Temperature
Figure 15B. Low level Output
vs.Supply Voltage
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
0
500
400
300
200
100
0
M ax.
Max.
-50
-25
0
25
50
75
100
125
125
125
0
100
200
300
400
500
600
V
Boost Voltage (V)
Temperature (°C)
B
Figure 16B. Offset Supply Current
vs. Voltage
Figure 16A. Offset Supply Current
vs. Temperature
150
120
90
60
30
0
150
120
90
60
30
0
M ax.
Typ.
Max.
Typ.
-50
-25
0
25
50
75
100
10
12
14
16
18
20
Temperature (°C)
V
BS
Floating Supply Voltage (V)
Figure 17B. VBS Supply Current
vs. Voltage
Figure 17A. VBS Supply Current
vs. Temperature
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
M ax.
Typ.
M ax.
Typ.
-50
-25
0
25
50
75
100
10
12
14
16
18
20
Temperature (°C)
V
Supply Voltage (V)
cc
Figure 18A. V Supply Current
cc
Figure 18B. V Supply Current
cc
vs. Temperature
vs. Voltage
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
30
25
20
15
10
5
30
25
20
15
10
5
Max.
Typ.
Max.
Typ.
0
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
V
cc
Supply Voltage (V)
Temperature (°C)
Figure 19A. Logic"1" Input Current
vs. Temperature
Figure 19B. Logic"1" Input Current
vs. Voltage
6
5
4
3
2
1
0
6
5
4
3
Max
Max
2
1
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Supply Voltage (V)
Temperature (°C)
Figure 20B. Logic "0" Input Bias Current
vs. Voltage
Figure 20A. Logic "0" Input Bias Current
vs. Temperature
11
11
Max.
10
9
10
9
Max.
Typ.
Typ.
Min.
8
8
7
7
Min.
6
6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 21A. V Undervoltage Threshold(+)
cc
Figure 21B. V Undervoltage Threshold(-)
cc
vs. Temperature
vs. Temperature
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
500
400
300
200
100
0
500
400
300
200
100
0
Typ.
Typ.
Min.
Min.
-50
-25
0
25
Temperature (oC)
50
75
100 125
10
12
14
16
18
20
V
Supply Voltage (V)
BIAS
Figure 22A. Output Source Current
vs. Temperature
Figure 22B. Output Source Current
vs. Supply Voltage
1000
800
600
400
200
0
1000
800
600
400
200
0
Typ.
Typ.
Min.
Min.
-50 -25
0
25
50
75 100 125
10
12
14
16
18
20
Temperature (°C)
V
Supply Voltage (V)
BIAS
Figure 23A. Output Sink Current
vs. Temperature
Figure 23B. Output Sink Current
vs. Supply Voltage
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Case Outlines
01-6014
8 Lead PDIP
01-3003 01 (MS-001AB)
IN C H E S
MILLIMETERS
DIM
A
D
B
MIN
.0532
MAX
.0688
.0098
.020
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
FOOTPRINT
8X 0.72 [.028]
5
A
E
A1 .0040
b
c
.013
.0075
.189
.0098
.1968
.1574
8
1
7
2
6
3
5
6
D
E
e
H
.1497
0.25 [.010]
A
.050 BASIC
1.27 BASIC
6.46 [.255]
4
e 1 .025 BASIC
0.635 BASIC
H
K
L
y
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
3X 1.27 [.050]
e
6X
8X 1.78 [.070]
K x 45°
e1
A
C
y
0.10 [.004]
8X c
8X L
A1
B
8X b
0.25 [.010]
7
C
A
NOTES:
5
6
7
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
8 Lead SOIC
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13
Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
Tape & Reel
LOADED TA PE FEED DIRECTION
8-lead SOIC
A
B
H
D
F
C
N OTE : CONTROLLING
D IMENSION IN MM
E
G
CA R RIE R TA P E D IM E NS IO N FO R 8 S O ICN
M etr ic
Im p erial
Co d e
M in
7 .9 0
3 .9 0
11 .7 0
5 .4 5
6 .3 0
5 .1 0
1 .5 0
1 .5 0
M ax
8.1 0
4.1 0
1 2. 30
5.5 5
6.5 0
5.3 0
n/a
M in
M ax
0 .3 18
0 .1 61
0 .4 84
0 .2 18
0 .2 55
0 .2 08
n/a
A
B
C
D
E
F
0.31 1
0.15 3
0 .4 6
0.21 4
0.24 8
0.20 0
0.05 9
0.05 9
G
H
1.6 0
0 .0 62
F
D
B
C
A
E
G
H
RE E L D IM E NS IO N S FO R 8 S O IC N
M etr ic
Im p erial
Co d e
M in
32 9.60
20 .9 5
12 .8 0
1 .9 5
98 .0 0
n /a
14 .5 0
12 .4 0
M ax
3 30 .2 5
2 1. 45
1 3. 20
2.4 5
1 02 .0 0
1 8. 40
1 7. 10
1 4. 40
M in
1 2 .9 76
0.82 4
0.50 3
0.76 7
3.85 8
n /a
M ax
13 .0 0 1
0 .8 44
0 .5 19
0 .0 96
4 .0 15
0 .7 24
0 .6 73
0 .5 66
A
B
C
D
E
F
G
H
0.57 0
0.48 8
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Not recommended for new designs. For new designs, we recommend IRS2005SPBF.
IRS2001(S)PbF
LEADFREEPARTMARKINGINFORMATION
Part number
IRSxxxxx
Date code
IR logo
YWW?
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode - 4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002
ORDERINFORMATION
8-LeadPDIPIRS2001PbF
8-LeadSOICIRS2001SPbF
8-LeadSOICTape&ReelIRS2001STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 8/18/2008
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15
相关型号：
IRS2003S
200 V 半桥驱动器 IC，具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 8 引脚 SOIC 封装，适用 MOSFET。也有 8 引脚 PDIP 封装可选。
INFINEON
IRS2004STRPBF
Half Bridge Based Peripheral Driver, CMOS, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
INFINEON
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