IRS2003S [INFINEON]
200 V 半桥驱动器 IC，具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 8 引脚 SOIC 封装，适用 MOSFET。也有 8 引脚 PDIP 封装可选。;
| 型号： | IRS2003S |
| 厂家： | 
Infineon |
| 描述： | 200 V 半桥驱动器 IC，具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 8 引脚 SOIC 封装，适用 MOSFET。也有 8 引脚 PDIP 封装可选。 驱动 光电二极管 驱动器 |
| 文件： | 总14页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60269
IRS2003(S)PbF
HALF-BRIDGE DRIVER
Features
Product Summary
• Floating channel designed for bootstrap operation
• Fully operational to +200 V
V
200 V max.
130 mA/270 mA
10 V - 20 V
OFFSET
• Tolerant to negative transient voltage, dV/dt
immune
I +/-
O
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout
V
OUT
• 3.3 V, 5 V, and 15 V logic compatible
• Cross-conduction prevention logic
• Matched propagation delay for both channels
• Internal set deadtime
t
(typ.)
680 ns/150 ns
520 ns
on/off
Deadtime (typ.)
• High-side output in phase with HIN input
Packages
• Low-side output out of phase with
ꢀꢁꢂ input
• RoHS compliant
Description
The IRS2003 is a high voltage, high speed power
MOSFET and IGBT drivers with dependent high- and
low-side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge-
dized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output, down
8-Lead SOIC
IRS2003S
8-Lead PDIP
IRS2003
to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates up to 200 V.
Typical Connection
ꢊꢋꢌꢍꢎꢌꢏꢐꢐꢌꢃ
ꢃ
ꢄꢄ
ꢃ
ꢄꢄ
ꢃ
ꢅ
ꢇꢁꢂ
ꢀꢁꢂ
ꢇꢁꢂ
ꢀꢁꢂ
ꢇꢈ
ꢑꢈ
ꢀꢈꢒꢓ
ꢃ
ꢆ
ꢄꢈꢉ
ꢀꢈ
(Refer to Lead Assignments for correct configuration). This diagram shows electrical connections only. Please refer to
our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1
IRS2003(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
High-side floating absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Min.
Max.
Units
V
B
-0.3
225
V
S
V
- 25
V
+ 0.3
B
B
B
V
HO
V
- 0.3
S
V
+ 0.3
25
V
V
CC
-0.3
-0.3
-0.3
—
V
LO
V
V
+ 0.3
CC
V
IN
Logic input voltage (HIN & ꢀꢁꢂ)
+ 0.3
CC
dV /dt
s
Allowable offset supply voltage transient
50
V/ns
W
(8 Lead PDIP)
(8 Lead SOIC)
(8 Lead PDIP)
(8 Lead SOIC)
—
1.0
0.625
125
200
150
150
P
D
Package power dissipation @ T ≤ +25 °C
A
—
—
Rth
JA
Thermal resistance, junction to ambient
°C/W
—
T
J
Junction temperature
—
T
S
Storage temperature
-55
—
°C
T
L
Lead temperature (soldering, 10 seconds)
300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V offset rating is tested with all supplies biased at a 15 V differential.
S
Symbol
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Min.
Max.
Units
V
B
V
+ 10
V + 20
S
S
V
S
Note 1
200
V
HO
V
S
V
B
V
V
CC
10
0
20
V
LO
V
CC
V
IN
Logic input voltage (HIN & ꢀꢁꢂ)
0
V
CC
°C
T
A
Ambient temperature
-40
125
Note 1: Logic operational for V of -5 V to +200 V. Logic state held for V of -5 V to -V . (Please refer to the Design Tip
S
S
BS
DT97-3 for more details).
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2
IRS2003(S)PbF
Dynamic Electrical Characteristics
V
(V , V ) = 15 V, C = 1000 pF and T = 25 °C unless otherwise specified.
BIAS CC BS
L
A
Symbol
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Min. Typ. Max. Units Test Conditions
t
—
—
—
—
680
150
70
820
220
170
90
V = 0 V
S
on
t
V = 200 V
S
off
t
r
t
f
Turn-off fall time
35
ns
Deadtime, LS turn-off to HS turn-on &
HS turn-on to LS turn-off
400
—
520
—
650
60
DT
MT
Delay matching, HS & LS turn-on/off
Static Electrical Characteristics
V
(V , V ) = 15 V and T = 25 °C unless otherwise specified. The V , V
and I parameters are referenced to
IN TH, IN
BIAS CC BS
A
COM. The V and I parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
O
O
Symbol
Definition
Min. Typ. Max. Units Test Conditions
ꢀꢁꢂ
ꢀꢁꢂ
V
Logic “1” (HIN) & Logic “0” (
Logic “0” (HIN) & Logic “1” (
High level output voltage, V
) input voltage
) input voltage
2.5
—
—
—
—
—
—
—
—
—
—
—
0.8
0.2
0.1
50
IH
V
= 10 V to 20 V
CC
V
IL
V
V
OH
- V
BIAS O
0.05
0.02
—
I
= 2 mA
O
V
OL
Low level output voltage, V
O
I
LK
Offset supply leakage current
V
= V = 200 V
B S
I
Quiescent V supply current
BS
30
55
QBS
V
= 0 V or 5 V
IN
I
Quiescent V
supply current
CC
150
3
270
10
µA
QCC
ꢀꢁꢂ
ꢀꢁꢂ
I
Logic “1” input bias current
Logic “0” input bias current
HIN = 5 V,
= 0 V
= 5 V
IN+
I
IN-
—
5
HIN = 0 V,
V
supply undervoltage positive going
CC
V
8
8.9
8.2
9.8
CCUV+
threshold
supply undervoltage negative going
CC
V
V
V
7.4
130
270
9
CCUV-
threshold
V
O
= 0 V,V =V
IN IH
I
Output high short circuit pulsed current
Output low short circuit pulsed current
290
600
—
—
O+
PW ≤ 10 µs
mA
V
O
= 15 V, V = V
IN
IL
I
O-
PW ≤ 10 µs
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3
IRS2003(S)PbF
Functional Block Diagram
VB
HV
LEVEL
SHIFT
Q
HO
R
S
PULSE
FILTER
VS
IHN
PULSE
GEN
UV
DETECT
DEAD TIME &
SHOOT-THROUGH
PREVENTION
VCC
LO
VCC
LIN
COM
Lead Definitions
Symbol Description
HIN
ꢀꢁꢂ
Logic input for high-side gate driver output (HO), in phase
Logic input for low-side gate driver output (LO), out of phase
High-side floating supply
V
B
HO
High-side gate drive output
V
S
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
V
CC
LO
COM
Low-side return
Lead Assignments
V
V
1
2
3
4
V
1
2
3
4
V
B
8
7
B
8
7
CC
CC
HO
HO
HIN
LIN
HIN
LIN
V
S
V
S
6
5
6
5
LO
LO
COM
COM
8 Lead PDIP
8 Lead SOIC
IRS2003PbF
IRS2003SPbF
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4
IRS2003(S)PbF
ꢀꢁꢂ
ꢇꢁꢂ
ꢔꢐꢕ
ꢔꢐꢕ
ꢀꢁꢂ
ꢍ
ꢍ
ꢍ
ꢚ
ꢍ
ꢘ
ꢎꢙ
ꢎꢚꢚ
ꢖꢐꢕ
ꢖꢐꢕ
ꢇꢈ
ꢗꢐꢕ
ꢗꢐꢕ
ꢀꢈ
ꢀꢈ
Figure 1. Input/Output Timing Diagram
ꢔꢐꢕ
ꢔꢐꢕ
ꢇꢁꢂ
ꢍ
ꢍ
ꢍ
ꢚ
ꢍ
ꢎꢙ
ꢎꢚꢚ
ꢘ
ꢖꢐꢕ
ꢖꢐꢕ
ꢗꢐꢕ
ꢗꢐꢕ
ꢇꢈ
Figure 2. Switching Time Waveform Definitions
ꢔꢐꢕ
ꢔꢐꢕ
ꢇꢁꢂ
ꢀꢁꢂ
ꢖꢐꢕ
ꢗꢐꢕ
ꢇꢈ
ꢀꢈ
ꢓꢑ
ꢖꢐꢕ
ꢓꢑ
ꢗꢐꢕ
Figure 3. Deadtime Waveform Definitions
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5
IRS2003(S)PbF
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
Max.
Typ.
M ax
.
Typ
.
10
12
V
14
16
18
20
-50
-25
0
25
50
75
100
125
Temperature (oC)
Supply Voltage (V)
BIAS
Figure 4A. Turn-On Time vs. Temperature
Figure 4B. Turn-On Time vs. Supply Voltage
500
400
300
1000
Max.
800
600
Typ
.
M ax
Typ.
.
200
100
0
400
200
0
-5 0
-2 5
0
2 5
5 0
7 5
1 0 0
1 2 5
0
2
4
6
8
10 12 14 16 18 20
Temperature (oC)
Input Voltage (V)
Figure 4C. Turn-On Time vs. Input Voltage
Figure 5A. Turn-Off Time vs. Temperature
1000
500
400
300
800
600
400
200
0
M ax
.
Max.
Typ.
200
100
0
Typ
.
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
V
BIAS
Supply Voltage (V)
Input Voltage (V)
Figure 5C. Turn-Off Time vs. Input Voltage
Figure 5B. Turn-Off Time vs. Supply Voltage
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6
IRS2003(S)PbF
500
400
300
200
100
0
500
400
300
Max.
200
Max.
Typ.
100
Typ.
0
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
V
Supply Voltage (V)
BIAS
Figure 6A. Turn-On Rise Time
vs. Temperature
Figure 6B. Turn-On Rise Time
vs. Voltage
200
150
100
50
200
150
100
50
Max.
Typ.
Max.
Typ.
0
0
-50
-25
0
25
50
75
100 125
10
12
14
Input Voltage (V)
Figure 7B. Turn-Off Fall Time vs. Voltage
16
18
20
Temperature (oC)
Figure 7A. Turn-Off Fall Time
vs. Temperature
1400
1200
1000
800
600
400
200
0
14 00
12 00
10 00
80 0
60 0
40 0
20 0
0
Max
.
M ax
.
Typ
.
Typ.
Min
.
M in.
-50
- 25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC)
V
BIAS
Supply Voltage (V)
Figure 8A. Deadtime vs. Temperature
Figure 8B. Deadtime vs. Voltage
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7
IRS2003(S)PbF
5
4
3
2
1
5
4
3
2
1
Min.
Min.
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
VBIAS Supply Voltage (V)
Figure 9A. Logic "1" Input Voltage
vs. Temperature
Figure 9B. Logic "1" Input Voltage
vs. Supply Voltage
4
4
3.2
2.4
1.6
0.8
0
3.2
2.4
1.6
0.8
0
Max.
Max.
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC)
V
Supply Voltage (V)
cc
Figure 10B. Logic "0"(HIN) & Logic "1" (
Input Voltage vs. Voltage
)
Figure 10A. Logic "0"(HIN) & Logic "1" (
Input Voltage vs. Temperature
)
LIN
LIN
0.5
0.4
0.3
0.5
0.4
0.3
Max.
0.2
0.2
0.1
0.1
Typ.
0.0
0.0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
8
Temperature (oC)
VBIAS Supply Voltage (V)
Figure 11B. High Level Output Voltage
vs. Supply Voltage
Figure 11A. High Level Output Voltage
vs. Temperature
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IRS2003(S)PbF
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0
Max.
Max.
Typ.
Typ.
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
VBIAS Supply Voltage (V)
Figure 12A. Low Level Output Voltage
vs. Temperature
Figure 12B. Low Level Output Voltage
vs. Supply Voltage
500
500
400
300
200
100
0
400
300
200
100
0
Max.
M ax
.
-50
-25
0
25
50
75
100 125
0
200
400
600
800
Temperature (oC)
V
Boost Voltage (V)
B
Figure 13A. Offset Supply Current
vs. Temperature
Figure 13B. Offset Supply Current vs. Voltage
150
1 20
9 0
150
120
90
6 0
60
Max.
M ax .
3 0
30
T yp .
-25
Typ.
0
0
-
50
0
2 5
5 0
7 5
1 00
1 25
10
12
14
16
18
20
Temperature (oC)
V
BS
Floating Supply Voltage (V)
Figure 14A. VBS Supply Current
vs. Temperature
Figure 14B. VBS Supply Current vs. Voltage
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9
IRS2003(S)PbF
700
600
500
400
300
200
100
0
700
600
500
400
Max.
Typ.
300 Max.
200
100
Typ.
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC)
Vcc Supply Voltage (V)
Figure 15A. Vcc Supply Current
vs. Temperature
Figure 15B. Vcc Supply Current vs. Voltage
30
25
20
30
25
20
15
10
5
15
Max.
10
Max
5
0
Typ.
Typ.
0
10
12
14
16
18
20
-50
-25
0
25
50
75
100
125
Temperature (oC)
Vcc Supply Voltage (V)
Figure 16A. Logic "1" Input Current
vs. Temperature
Figure 16B. Logic "1" Input Current
vs. Voltage
6
5
4
3
6
5
4
3
2
1
0
Max
Max
2
1
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
Supply Voltage (V)
Figure 17B. Logic "0" Input Bias Current
vs. Voltage
Figure 17A. Logic "0" Input Bias Current
vs. Temperature
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10
IRS2003(S)PbF
1 1
1 0
9
11
10
9
Max.
Max.
Typ.
Typ.
Min.
8
8
7
7
Min.
6
6
-5 0 - 2 5
0
2 5
5 0
7 5
1 0 0
1 2 5
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 18A. V Undervoltage Threshold(+)
cc
Figure 18B. V UndervoltageThreshold (-)
cc
vs. Temperature
vs. Temperature
500
400
500
400
300
200
Typ.
300
200
Min.
Typ.
100
100
Min.
0
0
-50
-25
0
25
50
75
100 125
10
12
14
16
18
20
Temperature (oC)
V
BIAS Supply Voltage (V)
Figure 19A. Output Source Current
vs. Temperature
Figure 19B. Output Source Current
vs. Supply Voltage
1000
800
600
400
200
0
1000
800
600
400
200
0
Typ.
Typ.
Min.
Min.
10
12
14
16
18
20
-50 -25
0
25
50
75 100 125
Temperature (oC)
VBIAS Supply Voltage (V)
Figure 20A. Output Sink Current
vs. Temperature
Figure 20B. Output Sink Current
vs. Supply Voltage
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11
IRS2003(S)PbF
Case Outlines
01-6014
8-Lead PDIP
01-3003 01 (MS-001AB)
IN C H E S
MILLIMETERS
DIM
A
D
B
MIN
.0532
MAX
.0688
.0098
.020
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
FOOTPRINT
8X 0.72 [.028]
5
A
A1 .0040
b
c
.013
.0075
.189
.0098
.1968
.1574
8
1
7
2
6
3
5
6
D
E
e
H
E
.1497
0.25 [.010]
A
.050 BASIC
1.27 BASIC
6.46 [.255]
4
e 1 .025 BASIC
0.635 BASIC
H
K
L
y
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
3X 1.27 [.050]
e
6X
8X 1.78 [.070]
K x 45°
e1
A
C
y
0.10 [.004]
8X c
8X L
A1
B
8X b
7
0.25 [.010]
C A
NOTES:
5
6
7
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
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12
IRS2003(S)PbF
Tape & Reel
8-lead SOIC
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
N OTE : CONTROLLING
D IMENSION IN MM
E
G
CAR RIER TAPE D IM ENSION FOR 8SOICN
M etr ic
Im p erial
Co d e
M in
7 .9 0
3 .9 0
11 .7 0
5 .4 5
6 .3 0
5 .1 0
1 .5 0
1 .5 0
M ax
8.1 0
4.1 0
1 2. 30
5.5 5
6.5 0
5.3 0
n/a
M in
M ax
0 .3 18
0 .1 61
0 .4 84
0 .2 18
0 .2 55
0 .2 08
n/a
A
B
C
D
E
F
0.31 1
0.15 3
0 .4 6
0.21 4
0.24 8
0.20 0
0.05 9
0.05 9
G
H
1.6 0
0 .0 62
F
D
B
C
A
E
G
H
REEL D IM ENSION S FOR 8SOIC N
M etr ic
Im p erial
Co d e
M in
M ax
3 30 .2 5
2 1. 45
1 3. 20
2.4 5
1 02 .0 0
1 8. 40
1 7. 10
1 4. 40
M in
1 2 .9 76
0.82 4
0.50 3
0.76 7
3.85 8
n /a
M ax
13 .0 0 1
0 .8 44
0 .5 19
0 .0 96
4 .0 15
0 .7 24
0 .6 73
0 .5 66
A
B
C
D
E
F
32 9.60
20 .9 5
12 .8 0
1 .9 5
98 .0 0
n /a
G
H
14 .5 0
12 .4 0
0.57 0
0.48 8
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13
IRS2003(S)PbF
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRSxxxxx
IR logo
YWW?
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode - 4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS2003PbF
8-LeadSOICIRS2003SPbF
8-LeadSOICTape&ReelIRS2003STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 11/27/2006
www.irf.com
14
相关型号：
IRS2004STRPBF
Half Bridge Based Peripheral Driver, CMOS, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
INFINEON
IRS2005M
200 V 高边和低边驱动器 IC,具有典型的 0.29 A 拉电流和 0.6 A 灌电流，采用 MLPQ 4x4 14L 封装，适用于 IGBT 和 MOSFET。也有 8 引脚 SOIC 封装可选。
INFINEON
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