IRS2130303DTRPBF [INFINEON]
Interface Circuit,;
| 型号： | IRS2130303DTRPBF |
| 厂家： | 
Infineon |
| 描述： | Interface Circuit, |
| 文件： | 总23页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Data Sheet No. PD60256
IRS2130D/ IRS21303D /IRS2132D
3-PHASE BRIDGE DRIVER
Product Summary
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
VOFFSET
600 V max.
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Three Independent half-bridge drivers
Matched propagation delay for all channels
2.5 V logic compatible
IO+/-
200 mA / 420 mA
VOUT
10 V – 20 V (IRS213(0,2)D)
13 V – 20 V (IRS21303D)
500 ns
ton/off (typ.)
Deadtime (typ.)
2.5 µs (IRS2130D)
0.8 µs (IRS213(2,03)D)
Outputs out of phase with inputs
Cross-conduction prevention logic
All parts are LEAD-FREE
Integrated bootstrap diode function
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Description
Packages
The IRS213(0, 03, 2)D are high voltage, high speed
power MOSFET and IGBT drivers with three independent
high and low side referenced output channels. Proprietary
HVIC technology enables ruggedized monolithic
construction. Logic inputs are compatible with CMOS or
LSTTL outputs, down to 2.5 V logic. A ground-referenced
operational amplifier provides analog feedback of bridge
current via an external current sense resistor. A current trip
function which terminates all six outputs is also derived from
this resistor. An open drain FAULT signal indicates if an
over-current or undervoltage shutdown has occurred. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power
28-Lead SOIC
28-Lead PDIP
44-Lead PLCC w/o 12 Leads
MOSFETs or IGBTs in the high side configuration which operates up to 600 volts.
Up to 600V
Typical Connection
Vcc
VB1,2,3
Vcc
HIN1,2,3
LIN1,2,3
HO1,2,3
VS1,2,3
HIN1,2,3
LIN1,2,3
FAULT
FAULT
ITRIP
CAO
CA-
TO
LOAD
CAO
LO1,2,3
VSS
VS0
GND
(Refer to Lead Assignments for correct pin configuration ). This diagram shows electrical connections only.
Please refer to our Application Notes and Design Tips for proper circuit board layout.
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1
IRS213(0, 03, 2)D(S & J)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB1,2,3
High Side Floating Supply Voltage
-0.3
620
VS1,2,3
VHO1,2,3
VCC
VSS
VLO1,2,3
High Side Floating Offset Voltage
High Side Floating Output Voltage
Low Side and Logic Fixed Supply Voltage
Logic Ground
VB1,2,3 - 20
VS1,2,3 - 0.3
-0.3
VCC - 20
-0.3
VB1,2,3 + 0.3
VB1,2,3 + 0.3
20
VCC + 0.3
VCC + 0.3
Low Side Output Voltage
V
(VSS + 15) or
(VCC + 0.3),
whichever is
lower
Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)
VIN
VSS -0.3
VFLT
VCAO
VCA-
FAULT Output Voltage
VSS -0.3
VCC +0.3
VCC +0.3
VCC +0.3
50
Operational Amplifier Output Voltage
Operational Amplifier Inverting Input Voltage
Allowable Offset Supply Voltage Transient
VSS -0.3
VSS -0.3
—
dVS/dt
V/ns
W
(28 lead PDIP)
—
—
—
—
—
—
—
-55
1.5
1.6
2.0
83
78
63
150
150
PD
Package Power Dissipation @ TA ≤ +25 °C
(28 lead SOIC)
(44 lead PLCC)
(28 lead PDIP)
(28 lead SOIC)
(44 lead PLCC)
Rth,JA
Thermal Resistance, Junction to Ambient
°C/W
°C
TJ
TS
TL
Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 seconds)
—
300
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2
IRS213(0, 03, 2)D(S & J)PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is
tested with all supplies biased at a 15 V differential.
Symbol
Definition
High Side Floating Supply Voltage IRS213(0,2)D
High Side Floating Supply Voltage IRS21303D
High Side Floating Offset Voltage
Min.
Max.
Units
VS1,2,3 +10
VB1,2,3
VS1,2,3 +20
V
S1,2,3 +13
Note 1
VS1,2,3
600
VHO1,2,3
High Side Floating Output Voltage
VS1,2,3
10
VB1,2,3
Low Side and Logic Fixed Supply Voltage IRS213(0,2)D
Low Side and Logic Fixed Supply Voltage IRS21303D
Logic Ground
Low Side Output Voltage
Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
VCC
20
13
V
VSS
VLO1,2,3
VIN
VFLT
VCAO
VCA-
TA
-5
0
5
VCC
VSS
VSS
VSS
VSS
-40
VSS + 5
VCC
VSS + 5
VSS + 5
125
FAULT Output Voltage
Operational Amplifier Output Voltage
Operational Amplifier Inverting Input Voltage
Ambient Temperature
°C
Note 1: Logic operational for VS of (VSO -5 V) to (VSO +600 V). Logic state held for VS of (VSO -5 V) to (VSO – VBS .
)
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2 V zener diode.
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3
IRS213(0, 03, 2)D(S & J)PbF
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
VIH
VIL
VIT,TH+
Logic “0” Input Voltage (OUT = LO)
Logic “1” Input Voltage (OUT = HI)
ITRIP Input Positive Going Threshold
2.2
—
—
—
—
0.8
V
400 490 580
mV
VOH
VOL
ILK
IQBS
IQCC
High Level Output Voltage, VBIAS - VO
Low Level Output Voltage, VO
Offset Supply Leakage Current
Quiescent VBS Supply Current
Quiescent VCC Supply Current
Logic “1” Input Bias Current (OUT = HI)
Logic “0” Input Bias Current (OUT = LO)
“High” ITRIP Bias Current
—
—
—
—
—
—
—
—
—
—
—
—
30
4
100
100
50
50
VIN = 0 V, IO = 0 A
VIN = 5 V, IO = 0 A
VB = VS = 600 V
µA
mA
µA
nA
VIN = 0 V
6
IIN+
IIN-
300 400
220 300
VIN = 5 V
ITRIP = 5 V
ITRIP = 0 V
IITRIP+
5
—
10
10
IITRIP-
“Low” ITRIP Bias Current
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
VBS Supply Undervoltage
7.5 8.35 9.2
VBSUV+
VBSUV-
VCCUV+
VCCUV-
VCCUVH
Positive Going Threshold
VBS Supply Undervoltage
Negative Going Threshold
11
—
13
7.1 7.95 8.8
9
8.3
11
8
—
9
—
8.7
—
0.3
2
0.4
2
55
11
9.7
13
9.4
11
—
VCC Supply Undervoltage
Positive going Threshold
V
VCC Supply Undervoltage
Negative Going Threshold
9
—
—
—
Hysteresis
—
—
VBSUVH
Ron, FLT
IO+
Hysteresis
FAULT Low On-Resistance
—
75
—
Ω
VO = 0 V, VIN = 0 V
PW ≤ 10 µs
VO = 15 V, VIN = 5 V
PW ≤ 10 µs
Output High Short Circuit Pulsed Current
200 250
mA
IO-
Output Low Short Circuit Pulsed Current
420 500
—
RBS
VOS
ICA-
Integrated Bootstrap Diode resistance
Operational Amplifier Input Offset Voltage
CA- Input Bias Current
—
—
—
200
—
—
—
10
4
Ω
mV
nA
VSO = VCA- = 0.2 V
VCA- = 2.5 V
Operational Amplifier Common Mode
Rejection Ratio
VSO = VCA- = 0.1 V &
1.1 V
CMRR
60
55
4.9
—
80
75
5.2
—
—
dB
Operational Amplifier Power Supply
Rejection Ratio
VSO = VCA- = 0.2 V
VCC = 10 V & 20 V
PSRR
—
Operational Amplifier High Level Output
Voltage
VOH,AMP
VOL,AMP
5.4
30
V
VCA- = 0 V, VSO =1 V
Operational Amplifier Low Level Output
Voltage
mV
VCA- = 1 V, VSO =0 V
Note: Please refer to integrated bootstrap functionality information on pg. 11 for application recommendations.
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4
IRS213(0, 03, 2)D(S & J)PbF
Static Electrical Characteristics - (Continued)
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
VCA- = 0 V, VSO =1 V
ISRC,AMP
Operational Amplifier Output Source Current
4
7
2.1
10
4
—
—
—
—
VCAO = 4 V
VCA- = 1 V, VSO =0 V
VCAO = 2 V
ISNK,AMP
IO+,AMP
IO-,AMP
Operational Amplifier Output Sink Current
1
mA
Operational Amplifier Output High Short Circuit
VCA- = 0 V, VSO =5 V
VCAO = 0 V
—
—
Current
Operational Amplifier Output Low Short Circuit
Current
VCA- = 5 V, VSO =0 V
VCAO = 5 V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Min Typ Max Units Test Conditions
400 500 700
400 500 700
ton
toff
t r
—
—
80
35
125
55
VS1,2,3 = 0 V to 600 V
tf
Turn-off fall time
titrip
tbl
tflt
ITRIP to Output Shutdown Propagation Delay
ITRIP Blanking Time
ITRIP to FAULT Indication Delay
400 660 920
400
350 550 870
325
—
—
ns
tflt, in
Input Filter Time (All Six Inputs)
—
—
LIN1,2,3 to FAULT Clear Time IRS213(0,2)D
LIN1,2,3 & HIN1,2,3 to FAULT Clear Time
IRS21303D
tfltclr
5300 8500 13700
1300 2000 3100
500 700 1100
Deadtime: (IRS2130D
DT
(IRS213(2,03)D
SR+
SR-
Operational Amplifier Slew Rate (+)
Operational Amplifier Slew Rate (-)
5
2.4
10
3.2
—
—
V/µs
1 V input step
NOTE: For high side PWM, HIN pulse width must be > 1.5 µs
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5
IRS213(0, 03, 2)D(S & J)PbF
Functional Block Diagram
IRS2130D/IRS2132D
VB1
H1
SET
PULSE
GENERATOR
LEVEL
LATCH
INPUT
HIN1
SIGNAL
DRIVER
HO1
L1
UV
DETECTOR
GENERATOR
HIN2
HIN3
SHIFTER
RESET
VS1
Integrated BS
Diode
LIN1
LIN2
LIN3
VB2
HO2
VS2
H2
L2
PULSE
GENERATOR
LEVEL
SET
LATCH
INPUT
SIGNAL
DRIVER
UV
DETECTOR
GENERATOR
SHIFTER
RESET
Integrated BS
Diode
FAULT
LATCH
VB3
PULSE
GENERATOR
LEVEL
H3
SET
FAULT
LOGIC
INPUT
SIGNAL
GENERATOR
CLEAR
LOGIC
HO3
DRIVER
UV
DETECTOR
L3
SHIFTER
C
S
RESET
VS3
Integrated BS
Diode
VCC
LO1
DRIVER
ITRIP
UNDER
VOLTAGE
0.5V
DETECTOR
CURRENT
COMPARATOR
LO2
DRIVER
CAO
CURRENT
AMP
LO3
DRIVER
CA-
VSO
VSS
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6
IRS213(0, 03, 2)D(S & J)PbF
Functional Block Diagram
IRS21303D
VB1
H1
SET
PULSE
GENERATOR
LEVEL
LATCH
INPUT
HIN1
HO1
SIGNAL
DRIVER
L1
UV
DETECTOR
GENERATOR
HIN2
HIN3
SHIFTER
RESET
VS1
Integrated BS
Diode
LIN1
LIN2
LIN3
VB2
H2
L2
PULSE
GENERATOR
LEVEL
SET
LATCH
INPUT
SIGNAL
HO2
DRIVER
UV
DETECTOR
GENERATOR
SHIFTER
RESET
VS2
Integrated BS
Diode
FAULT
LATCH
VB3
PULSE
GENERATOR
LEVEL
H3
SET
FAULT
LOGIC
INPUT
SIGNAL
GENERATOR
CLEAR
LOGIC
HO3
DRIVER
UV
DETECTOR
L3
SHIFTER
C
S
RESET
VS3
Integrated BS
Diode
VCC
LO1
DRIVER
ITRIP
UNDER
VOLTAGE
0.5V
DETECTOR
CURRENT
COMPARATOR
LO2
DRIVER
CAO
CURRENT
AMP
LO3
DRIVER
CA-
VSO
VSS
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7
IRS213(0, 03, 2)D(S & J)PbF
Lead Definitions
Symbol
Description
HIN1,2,3
LIN1,2,3
FAULT
VCC
ITRIP
CAO
Logic input for high side gate driver outputs (HO1,2,3), out of phase
Logic input for low side gate driver output (LO1,2,3), out of phase
Indicates over-current or undervoltage lockout (low side) has occurred, negative logic
Low side and logic fixed supply
Input for over-current shutdown
Output of current amplifier
CA-
Negative input of current amplifier
VSS
Logic Ground
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
VSO
High side floating supply
High side gate drive output
High side floating supply return
Low side gate drive output
Low side return and positive input of current amplifier
Lead Assignments
1
VCC
28
HO1 27
1
VCC
28
HO1 27
VB1
VB1
2
3
4
2
3
4
HIN1
HIN2
HIN3
HIN1
HIN2
HIN3
6
5
4
3
43
41
26
25
42
26
25
VS1
VS1
7
VB2 24
VB2 24
HO2 23
8
5
6
LIN1
LIN2
5
6
LIN1
LIN2
LIN1
LIN2
37 VB2
9
HO2 23
36
35
HO2
VS2
10
11
12
13
14
15
16
17
LIN3
VS2 22
VS2 22
7
8
9
LIN3
7
8
9
LIN3
FAULT
ITRIP
21
21
FAULT
FAULT
VB3
VB3
20
19
18
17
16
20
19
18
17
16
ITRIP
CAO
CA-
ITRIP
CAO
CA-
31
30
29
VB3
10
11
12
13
HO3
VS3
10
11
12
13
HO3
VS3
CAO
HO3
VS3
VSS
VSO
LO3
VSS
VSO
LO3
18 19
20 21 22 23 24 25
LO1
LO1
LO2 15
LO2 15
14
14
44 Lead PLCC w /o 12 Leads
28 Lead PDIP
28 Lead SOIC (Wide Body)
IRS213(0,03,2)D
IRS213(0,03,2)DJ
Part Number
IRS213(0,03,2)DS
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8
IRS213(0, 03, 2)D(S & J)PbF
HIN1,2,3
LIN1,2,3
ITRIP
FAULT
HO1,2,3
LO1,2,3
Fig. 1. Input/Output Timing Diagram
HIN1,2,3
LIN1,2,3
50%
50%
LO1,2,3
HO1,2,3
50%
DT
50%
DT
Fig. 2. Deadtime Waveform Definitions
HIN1,2,3
LIN1,2,3
50%
50%
ton
toff
tr
tf
90%
90%
HO1,2,3
LO1,2,3
10%
10%
Fig. 3. Input/Output Switching Time Waveform Definitions
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9
IRS213(0, 03, 2)D(S & J)PbF
50%
LIN1,2,3
50%
ITRIP
FAULT
50%
50%
LO1,2,3
50%
tflt
tfltclr
titrip
Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions
tin,fil
tin,fil
n
Off
Off
On
On
On
Off
HIN/LIN
HO/LO
High
Low
Fig. 5. Input Filter Function
VCC
VSO
CA-
CAO
VSS
VSS
Fig. 6. Diagnostic Feedback Operational Amplifier Circuit
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10
IRS213(0, 03, 2)D(S & J)PbF
-
at very high PWM duty cycle due to
bootstrap FET equivalent resistance (RBS
see page 4).
,
1 Features Description
1.1 Integrated Bootstrap Functionality
In these cases better performances can be achieved
using IRS213(0,03,2)x non D version with external
bootstrap network.
IRS213(0,03,2)D family embeds an integrated
bootstrap FET that allows an alternative drive of the
bootstrap supply for a wide range of applications.
2 PCB Layout Tips
There is one Bootstrap FET for each channel and it is
connected between each of the floating supply (VB1,
VB2, VB3) and VCC (see Fig. 7).
2.1 Distance From H to L Voltage
The IRS213(0,03,2)D family pin out lack some pins
(only applies to PLCC package) (see page 8) in order
to maximizing the distance between the high voltage
and low voltage pins. It’s strongly recommended to
place the components tied to the floating voltage in
the respective high voltage portions of the device
(VB1,2,3, VS1,2,3) side.
The bootstrap FET of each channel follows the state
of the respective low side output stage (i.e., bootFet
is ON when LO is high, it is OFF when LO is low),
unless the VB voltage is higher than approximately 17
V. In that case the bootstrap FET keeps being off until
VB voltage returns below that threshold (see Fig. 8).
2.2 Ground Plane
BootFet1
VB1
To minimize noise coupling ground plane must not be
placed under or near the high voltage floating side.
VCC
2.3 Gate Drive Loops
Current loops behave like an antenna able to receive
and transmit EM noise (see Fig. 9). In order to reduce
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
much as possible. Moreover, current can be injected
inside the gate drive loop via the IGBT collector-to-
gate parasitic capacitance. The parasitic auto-
inductance of the gate loop contributes to develop a
voltage across the gate-emitter increasing the
possibility of self turn-on effect.
BootFet2
VB2
BootFet3
VB3
Fig. 7. Simplified BootFet Connection
IGC
VBX (VCC
)
Vth~17V
Vcc=15V
gate
CGC
resistance
Phase voltage
LO
HOX (LOX)
Gate Drive
Loop
VGE
BootFet
OFF
Bootstrap FET
state
BootFet
ON
BootFet
ON
(COM)
VSX
Fig. 8. State Diagram
Fig. 9. Antenna Loops
Bootstrap FET is suitable for most of the PWM
modulation schemes and can be used either in
parallel with the external bootstrap network
(diode+resistor) or as a replacement of it.
2.4 Supply Capacitors
Supply capacitors must be placed as close as
possible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
The use of the integrated bootstrap as a replacement
of the external bootstrap network may have some
limitations in the following situations:
supply)
in
order
to
minimize
parasitic
-
when used in non-complementary PWM
schemes (typically 6-step modulations)
inductance/resistance.
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11
IRS213(0, 03, 2)D(S & J)PbF
In order to avoid such undervoltage it is highly
recommended to minimize high side emitter to low
side collector distance and low side emitter to
negative bus rail stray inductance. See DT04-4 at
www.irf.com for more detailed information.
2.5 Routing and Placement
Power stage PCB parasitic may generate dangerous
voltage transients for the gate driver and the control
logic. In particular it’s recommended to limit phase
voltage negative transients.
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12
IRS213(0, 03, 2)D(S & J)PbF
Figures 10-40 provide information on the experimental performance of the IRS2132D HVIC. The line plotted in each
figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled
Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected
together to illustrate the understood trend. The individual data points on the curve were determined by calculating the
averaged experimental value of the parameter (for a given temperature).
1000
800
600
400
200
0
1500
1200
900
600
300
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 11. Turn-Off Propagation Delay vs. Temperature
Fig. 10. Turn-On Propagation Delay vs. Temperature
125
100
75
250
200
150
50
100
Exp.
Exp.
50
0
25
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 12. Turn-On Rise Time vs. Temperature
Fig. 13. Turn-Off Fall Time vs. Temperature
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13
IRS213(0, 03, 2)D(S & J)PbF
1500
1200
900
600
300
0
1500
1200
900
600
300
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 15. TITRIP Propagation Delay vs. Temperature
Fig. 14. DL TON1 Propagation Delay vs. Temperature
1500
1200
250
200
150
100
900
Exp.
600
300
0
50
Exp.
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 16. ITRIP to FAULT Propagation Delay vs.
Temperature
Fig.17. FAULT Low On Resistance vs. Temperature
10
100
8
6
4
2
0
80
60
40
20
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 18. VCC Quiescent Current vs. Temperature
Fig. 19. VBS Quiescent Current vs. Temperature
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14
IRS213(0, 03, 2)D(S & J)PbF
11
10
9
11
10
9
Exp.
Exp.
8
8
7
7
6
6
-50
-25
0
25
50
75
100
125
125
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 20. VCCUV+ Threshold vs. Temperature
Fig. 21. VCCUV- Threshold vs. Temperature
11
10
9
11
10
9
Exp.
Exp.
8
8
7
7
6
6
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 22. VBSUV+ Threshold vs. Temperature
Fig. 23. VBSUV- Threshold vs. Temperature
750
500
250
0
750
500
250
0
EXP.
Exp.
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 24. ITRIP Positive Going Threshold vs. Temperature
Fig. 25. ITRIP Negative Going Threshold vs.
Temperature
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15
IRS213(0, 03, 2)D(S & J)PbF
750
600
450
300
150
0
500
400
300
200
100
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 27. Output Low Short Circuit Current vs.
Temperature
Fig. 26. Output High Short Circuit Pulsed Current vs.
Temperature
25
20
15
10
25
20
15
10
5
Exp.
5
Exp.
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 29. "Low" ITRIP Bias Current vs. Temperature
Fig. 28. "High" ITRIP Bias Current vs. Temperature
8
25
20
15
10
5
Exp.
6
Exp.
4
2
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 30. VOH,AMP vs. Temperature
Fig. 31. VOL,AMP vs. Temperature
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16
IRS213(0, 03, 2)D(S & J)PbF
20
15
10
5
5
4
3
2
1
0
Exp.
Exp.
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 32. SR+,AMP vs. Temperature
Fig. 33. SR-,AMP vs. Temperature
12
5
4
3
2
1
0
10
8
Exp.
Exp.
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 34. ISNK,AMP vs. Temperature
Fig. 35. ISRC,AMP vs. Temperature
15
20
16
12
8
12
9
Exp.
6
Exp.
3
4
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 37. IO+,AMP vs. Temperature
Fig. 36. IO-,AMP vs. Temperature
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17
IRS213(0, 03, 2)D(S & J)PbF
90
70
50
30
10
-10
125
100
75
50
25
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 39. PSRR vs. Temperature
Fig. 38. VOS,AMP vs. Temperature
150
125
100
75
Exp.
50
25
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 40. CMRR vs. Temperature
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18
IRS213(0, 03, 2)D(S & J)PbF
Case Outlines
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19
IRS213(0, 03, 2)D(S & J)PbF
Case Outlines
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20
IRS213(0, 03, 2)D(S & J)PbF
LOADED TAPE FEED DIRECTION
B
A
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 28SOICW
Metric
Imperial
Code
A
Min
Max
12.10
4.10
Min
Max
0.476
0.161
0.956
0.456
0.433
0.724
n/a
11.90
3.90
0.468
0.153
0.933
0.448
0.425
0.716
0.059
0.059
B
C
23.70
11.40
10.80
18.20
1.50
24.30
11.60
11.00
18.40
n/a
D
E
F
G
H
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 28SOICW
Metric
Imperial
Min
Code
A
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
102.00
30.40
29.10
26.40
Max
13.001
0.844
0.519
0.096
4.015
1.196
1.145
1.039
12.976
0.824
0.503
0.767
3.858
n/a
B
C
D
E
98.00
n/a
26.50
24.40
F
G
1.04
0.96
H
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21
IRS213(0, 03, 2)D(S & J)PbF
LOADED TAPE FEED DIRECTION
B
A
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 44PLCC
Metric
Imperial
Code
A
Min
Max
24.10
4.10
Min
Max
0.948
0.161
1.271
0.562
0.712
0.712
n/a
23.90
3.90
0.94
B
0.153
1.248
0.555
0.704
0.704
0.078
0.059
C
31.70
14.10
17.90
17.90
2.00
32.30
14.30
18.10
18.10
n/a
D
E
F
G
H
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Imperial
Code
A
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
1.511
1.409
1.303
B
C
D
E
98.00
n/a
102.00
38.4
F
G
34.7
35.8
1.366
1.283
H
32.6
33.1
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22
IRS213(0, 03, 2)D(S & J)PbF
LEAD-FREE PART MARKING INFORMATION
Part number
IRSxxxxx
YWW?
Date code
IR logo
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode – 4 digit SPN code)
?
P
MARKING CODE
Lead Free Released
Non-Lead Free
Relased
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
28-Lead PDIP IRS2130DPbF
28-Lead PDIP IRS21303DPbF
28-Lead PDIP IRS2132DPbF
28-Lead SOIC IRS2130DSPbF
28-Lead SOIC IRS21303DSPbF
28-Lead SOIC IRS2132DSPbF
44-Lead PLCC IRS2132DJPbF
44-Lead PLCC IRS21303DJPbF
44-Lead PLCC IRS2132DJPbF
28-Lead PDIP Tape & Reel IRS2130DTRPbF
28-Lead PDIP Tape & Reel IRS2130303DTRPbF
28-Lead PDIP Tape & Reel IRS2132DTRPbF
28-Lead SOIC Tape & Reel IRS2130DSTRPbF
28-Lead SOIC Tape & Reel IRS21303DSTRPbF
28-Lead SOIC Tape & Reel IRS2132DSTRPbF
44-Lead PLCC Tape & Reel IRS2130DJTRPbF
44-Lead PLCC Tape & Reel IRS21303DJTRPbF
44-Lead PLCC Tape & Reel IRS2132DJTRPbF
WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105
This part has been qualified per industrial level
http://www.irf.com Data and specifications subject to change without notice.4/10/2006
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23
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