IRS2453 [INFINEON]

Integrated 600 V full-bridge gate driver;


型号：	IRS2453
厂家：	Infineon
描述：	Integrated 600 V full-bridge gate driver
文件：	总18页 (文件大小：514K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRS2453(1)D(S)

Product Summary

Features

Integrated 600 V full-bridge gate driver

CT, RT programmable oscillator



Topology

Full-bridge

600 V



V_OFFSET

15.6 V Zener clamp on

V_CC



Micropower startup

I_o+& I _o-(typical)

180 mA & 260 mA

Logic level latched shutdown pin

Non-latched shutdown on CT pin (1/6th V_CC)

Internal bootstrap FETs

1.0 μs (IRS2453D)

0.5 μs (IRS24531D)

Deadtime (typical)

Excellent latch immunity on all inputs & outputs

ESD protection on all pins

14-lead SOIC or PDIP package

0.5 or 1.0μs (typ.) internal dead time

RoHS compliant

Package Options



14 Lead PDIP

IRS2453DPbF

14 Lead SOIC

(Narrow Body)

IRS2453(1)DSPbF

Ordering Information

Standard Pack

Base Part Number

Package Type

PDIP14

Complete Part Number

Form

Quantity

Tube/Bulk

IRS2453DPBF

IRS2453DSPBF

IRS2453DSTRPBF

IRS24531DSPBF

IRS2453D(S)

Tube/Bulk

Tape and Reel

Tube/Bulk

2500

SOIC14N

IRS24531DS

SOIC14N

Tape and Reel

2500

IRS24531DSTRPBF

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April 27, 2016

IRS2453(1)D(S)

Table of Contents

Page

Ordering Information

Description

Typical Connection Diagram

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Recommended Component Values

Electrical Characteristics

Functional Block Diagram

Input / Output Pin Equivalent Circuit Diagram

Lead Definitions

Lead Assignments

Application Information and Additional Details

Package Details

Tape and Reel Details

Part Marking Information

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April 27, 2016

IRS2453(1)D(S)

Description

The IRS2453(1)D is based on the popular IR2153 self-oscillating half-bridge gate driver IC, and incorporates a

high voltage full-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer.

HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The output driver

features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is

achieved with low di/dt peak of the gate drivers, and with an under voltage lockout hysteresis greater than 1.5 V.

The IRS2453(1)D also includes latched and non-latched shutdown pins.

Typical Connection Diagram

+ AC rectified line

15 V

VCC

VB1

HO1

VS1

COM

VB2

HO2

LO1

LO2

VS2

LOAD

- AC rectified line

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April 27, 2016

IRS2453(1)D(S)

Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

Qualification Level

MSL2^†††260°C

SOIC14

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

Not applicable

(non-surface mount package style)

PDIP14

Class C

Machine Model

ESD

(per JEDEC standard JESD22-A115)

Class 2

Human Body Model

(per EIA/JEDEC standard EIA/JESD22-A114)

Class I, Level A

(per JESD78)

Yes

IC Latch-Up Test

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

††

Higher qualification ratings may be available should the user have such requirements. Please contact

your International Rectifier sales representative for further information.

†††

Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

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April 27, 2016

IRS2453(1)D(S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition

Min.

Max.

Units

B1,

High side floating supply voltage

-0.3

625

S1,

- 25

V + 0.3

High side floating supply offset voltage

High side floating output voltage

Low side output voltage

V_HO1

V_HO2

V - 0.3

V + 0.3

V_LO1

V_LO2

+ 0.3

-0.3

R pin voltage

+ 0.3

-0.3

-5

C pin voltage

SD pin voltage

R pin current

†

---

Supply current ( )

dV_S/dt

Allowable offset voltage slew rate

-50

---

V/ns

Maximum power dissipation @ T +25 ºC, PDIP14

1.6

1.0

A≤

Maximum power dissipation @ T ≤ +25 ºC, SOIC14N

---

Thermal resistance, junction to ambient, PDIP14

Thermal resistance, junction to ambient, SOIC14N

Junction temperature

---

θJA

ºC/W

---

120

150

300

θJA

-55

---

Storage temperature

ºC

Lead temperature (soldering, 10 seconds)

†

This IC contains a zener clamp structure between the chip V

and COM which has a nominal

breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low

impedance power source greater than the V specified in the Electrical Characteristics section.

CLAMP

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April 27, 2016

IRS2453(1)D(S)

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol

Definition

Min.

Max.

Units

BS1,

BS2

- 0.7

High side floating supply voltage

CLAMP

†

, V

Steady state high side floating supply offset voltage

Supply voltage

600

CLAMP

S1 S2

-3.0 ( )

V_CCUV+

††

Supply current

ºC

(

)

Junction temperature

-25

125

†

It is recommended to avoid output switching conditions where negative-going spikes at the V_Snode

would decrease V_Sbelow ground by more than -5V.

†† Enough current should be supplied to the

pin of the IC to keep the internal 15.6 V zener diode

clamping the voltage at this pin.

Recommended Component Values

Symbol

Component

Min.

Max.

---

Units

Timing resistor value

C pin capacitor value

k

330

---

VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO1=CLO2 = CHO1=CHO2 = 1nF.

IRS2453(1)D Frequency vs. RT

IRS2453D Frequency vs. RT

1000000

100000

10000

1000

CT Values

330pf

470pF

1nF

2.2nF

4.7nF

10nF

100

1000

10000

100000

1000000

RT (Ohm)

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April 27, 2016

IRS2453(1)D(S)

Electrical Characteristics

V_BIAS(V_CC, V_BS) = 14 V, C_T= 1nF and T_A= 25 °C unless otherwise specified. The V_Oand I_Oparameters are

referenced to COM and are applicable to the respective output leads:

HO or LO. CLO1=CLO2=CHO1=CHO2=1nF.

Symbol

Definition

Min

Typ

Max

Units Test Conditions

Low Voltage Supply Characteristics

Rising V

under voltage lockout threshold

10.0

8.0

1.5

---

11.0

9.0

12.0

10.0

2.4

CCUV

Falling V

CCUV

under voltage lockout hysteresis

2.0

CCUVH

Micropower startup V

supply current

140

1.3

200

2.0

µA

 V

QCCUV

IQCC

CCUV-

Quiescent V_CCsupply current

---

I_{CC_20K}

I_CCFLT

V_CCsupply current at f_osc(R_T= 36.5 kΩ)

V_CCsupply current when SD > V_SD

---

3.0

3.5

---

360

15.6

500

16.6

µA

Zener clamp voltage

14.6

= 5 mA

CLAMP

Floating Supply Characteristics

 V

CC BS

QBS1UV,

QBS2UV

CCUV-

Micropower startup V

supply current

---

, V = V

µA

QBS1,

Quiescent V

supply current

---

100

QBS2

supply under voltage positive going

BS1UV+,

BS2UV+

threshold

8.0

9.0

10.0

supply under voltage negative going

BS1UV-,

BS2UV-

threshold

7.0

---

8.0

---

9.0

V = V = 600

LK1, ILK2 Offset supply leakage current

A

Oscillator I/O Characteristics

R = 36.5 k

19.6

---

20.2

20.8

100

Oscillator frequency

kHz

OSC

R = 7.15 k

R pin duty cycle

A

f_o< 100 kHz

V_CC= 7 V

C pin current

0.05

1.0

---

UV-mode C pin pull down current

CTUV

Upper C ramp voltage threshold

---

9.3

4.7

---

CT+

Lower C ramp voltage threshold

---

CT-

RT = 100 A

R = 140 k

---

100

300

RT+

High level R output voltage, V - V

CC RT

RT = 1 mA

R = 14 k

RT = 100 A

R = 140 k

Low level R output voltage

RT-

RT = 1 mA

---

100

300

100

R = 14 k

UV-mode R output voltage

 V

RTUV

CCUV-

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April 27, 2016

IRS2453(1)D(S)

Electrical Characteristics

V_BIAS(V_CC, V_BS) = 14 V, C_T= 1nF and T_A= 25 °C, unless otherwise specified. The V_Oand I_Oparameters are

referenced to COM and are applicable to the respective output leads:

HO or LO. CLO1=CLO2=CHO1=CHO2=1nF.

Symbol

Definition

Min

Typ

Max

Units Test Conditions

Gate Driver Output Characteristics

High level output voltage, V

Low level output voltage, V

- V

---

V_CC

---

BIAS

O = 0 A

COM

O = 0 A

UV-mode output voltage, V



---

COM

---

OL_UV

CCUV-

t_r

t_f

Output rise time

Output fall time

---

120

200

---

250

1.0

0.5

100

---

t_sd

Shutdown propagation delay

IRS2453D

0.8

0.4

1.40

0.7

t_d

Output dead time (HO or LO)

s

IRS24531D

I_O+

I_O-

Output source current

Output sink current

---

180

260

---

Shutdown

V_SD

Shutdown threshold at SD pin (latched)

1.8

2.2

2.0

2.3

2.5

C voltage shutdown threshold (non-latched)

CTSD

RT = 100 A,

---

R = 140 k

V_CT= 0 V

SD mode R output voltage, V

- V

RTSD

RT = 1 mA,

100

300

R = 14 k

V_CT= 0 V

Bootstrap FET Characteristics

V_{B1_ON}

V_Bwhen the bootstrap FET is on

13.7

14.0

---

V_{B2_ON}

I_{B1_CAP}

I_{B2_CAP}

V_Bsource current when FET is on

C_BS=0.1 μF

I_{B1_10 V}

I_{B2_10 V}

---

V_B=10 V

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April 27, 2016

IRS2453(1)D(S)

Functional Block Diagram

14 VB1

Level

Shift

13 HO1

12 VS1

PULSE

FILTER

DEAD

TIME

PULSE

GEN

BOOTSTRAP

DRIVE

R/2

DEAD

TIME

DELAY

LO1

10 VB2

2.0V

Level

Shift

HO2

PULSE

FILTER

PULSE

GEN

VS2

BOOTSTRAP

DRIVE

DETECT

VCC

15.4V

DELAY

LO2

COM

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April 27, 2016

IRS2453(1)D(S)

Input / Output Pin Equivalent Circuit Diagrams:

VB1

VB2

HO2

ESD

Diode

ESD

Diode

25V

HO1

25V

ESD

Diode

ESD

Diode

VS1

VS2

600V

VCC

ESD

Diode

ESD

Diode

LO2

25V

LO1

25V

ESD

Diode

ESD

Diode

COM

VCC

ESD

Diode

ESD

Diode

25V

R_ESD

ESD

Diode

ESD

Diode

COM

VCC

ESD

Diode

R_ESD

ESD

Diode

COM

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April 27, 2016

IRS2453(1)D(S)

Lead Definitions

Symbol

VCC

COM

Description

Logic and internal gate drive supply voltage

IC power and signal ground

Oscillator timing capacitor input

Oscillator timing resistor input

Shutdown input

LO1

LO2

VS2

HO2

VB2

Low side gate driver output

High voltage floating supply return

High side gate driver output

High side gate driver floating supply

No connect

VS1

HO1

VB1

High voltage floating supply return

High side gate driver output

High side gate driver floating supply

Lead Assignment

VCC

COM

14 VB1

13 HO1

12 VS1

VB2

LO1

LO2

HO2

VS2

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April 27, 2016

IRS2453(1)D(S)

Application Information and Additional Details

Timing Diagram

VCCUV+

VCC

Fault mode

VCT<1/6*VCC

2/3 VCC

1/3 VCC

1/6 VCC

VCC

LO1

VCC

LO2

VCC

HO1

VCC

HO2

VCC

VRT

1mA

IRT

-1mA

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April 27, 2016

IRS2453(1)D(S)

Functional Description

Under-Voltage Lock-Out Mode (UVLO)

The under-voltage lockout mode (UVLO) is defined as the state the IC is in when V_CCis below the turn-on

threshold of the IC. The IRS2453(1)D under-voltage lock-out is designed to maintain an ultra low supply current of

e the high and low side output drivers are

activated. During under-voltage lock-out mode, the high and low side driver outputs LO1, LO2, HO1, HO2 are all

low. With V_CCabove the V_CCUV+threshold, the IC turns on and the output begin to oscillate.

Normal Operating Mode

Once V_CCreaches the start-up threshold V_CCUV+, the MOSFET M1 opens, RT increases to approximately V_CC

(V_CC-V_RT+) and the external CT capacitor starts charging. Once the CT voltage reaches V_CT-(about 1/3 of V_CC),

established by an internal resistor ladder, LO1 and HO2 turn on with a delay equivalent to the dead time (t_d).

Once the CT voltage reaches V_CT+(approximately 2/3 of V_CC), LO1 and HO2 go low, RT goes down to

approximately ground (V_RT-), the CT capacitor starts discharging and the dead time circuit is activated. At the end

of the dead time, LO2 and HO1 go high. Once the CT voltage reaches V_CT-, LO2 and HO1 go low, RT goes to

high again, the dead time is activated. At the end of the dead time, LO1 and HO2 go high and the cycle starts

over again.

The frequency is best determined by the graph, Frequency vs. RT, page 3, for different values of CT. A first order

approximate of the oscillator frequency can also be calculated by the following formula:

f 

1.453 RT CT

This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot

delays.

Bootstrap MOSFET

The internal bootstrap FET and supply capacitor (C_BOOT) comprise the supply voltage for the high side driver

circuitry. The internal bootstrap FET only turns on when the corresponding LO is high. To guarantee that the high-

side supply is charged up before the first pulse on HO1 and HO2, LO1 and LO2 outputs are both high when CT

ramps between zero and 1/3*V_CC. LO1 and LO2 are also high when CT is grounded below 1/6*V_CCto ensure that

the bootstrap capacitor is charged when CT is brought back over 1/3*V_CC

Non-Latched Shutdown

If CT is pulled down below

(approximately 1/6 of V_CC) by an external circuit, CT is not able to charge up

CTSD

and oscillation stops. HO1 and HO2 outputs are held low. LO1 and LO2 outputs remain high while VCT remains

below V_CT-enabling the bootstrap capacitors to charge. This state remains until the CT input is released and

oscillation can resume.

Latched Shutdown

When the SD pin is brought above 2 V, the IC goes into fault mode and all outputs are low. V_CChas to be recycled

below V_CCUV-to restart. The SD pin can be used for over-current or over-voltage protection using appropriate

external circuitry.

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April 27, 2016

IRS2453(1)D(S)

50%

HO1

LO1

td_LO1

td_HO1

50%

ton_LO

Deadtime Waveform

tr tf

90%

10%

Rise and Fall Time Waveform

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April 27, 2016

IRS2453(1)D(S)

Package Details

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April 27, 2016

IRS2453(1)D(S)

Tape and Reel Details

LOADED TAPE FEED DIRECTION

NOTE : CONTROLLING

DIMENSION IN MM

CARRIER TAPE DIMENSION FOR 14SOICN

Metric

Imperial

Min

Code

Min

7.90

3.90

15.70

7.40

6.40

9.40

1.50

Max

8.10

4.10

16.30

7.60

6.60

9.60

n/a

Max

0.318

0.161

0.641

0.299

0.260

0.378

n/a

0.311

0.153

0.618

0.291

0.252

0.370

0.059

1.60

0.062

REEL DIMENSIONS FOR 14SOICN

Metric

Imperial

Code

Min

329.60

20.95

12.80

1.95

98.00

n/a

18.50

16.40

Max

330.25

21.45

13.20

2.45

102.00

22.40

21.10

18.40

Min

12.976

0.824

0.503

0.767

3.858

n/a

Max

13.001

0.844

0.519

0.096

4.015

0.881

0.830

0.724

0.728

0.645

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April 27, 2016

IRS2453(1)D(S)

Part Marking Information

Part number

Date code

IRS2453(1)D

YWW ?

IR logo

Pin 1

Identifier

? XXXX

Lot Code

(Prod mode –

4 digit SPN code)

MARKING CODE

Lead Free Released

Assembly site code

Per SCOP 200-002

Non-Lead Free Released

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April 27, 2016

IRS2453(1)D(S)

The information provided in this document is believed to be accurate and reliable. However, International

Rectifier assumes no responsibility for the consequences of the use of this information. International

Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which

may result from the use of this information. No license is granted by implication or otherwise under any

patent or patent rights of International Rectifier. The specifications mentioned in this document are subject

to change without notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

101N Sepulveda Blvd., El Segundo, California 90245

Tel: (310) 252-7105

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April 27, 2016

IRS2453 [INFINEON]

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