IRS2540SPBF [INFINEON]
LED BUCK REGULATOR CONTROL IC; LED降压稳压器控制IC
| 型号： | IRS2540SPBF |
| 厂家： | 
Infineon |
| 描述： | LED BUCK REGULATOR CONTROL IC |
| 文件： | 总14页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60293
IRS254(0,1)(S)PbF
LED BUCK REGULATOR CONTROL IC
Description
Features
The IRS254(0,1) are high voltage, high frequency
buck control ICs for constant LED current regulation.
They incorporate a continuous mode time-delayed
hysteretic buck regulator to directly control the
average load current, using an accurate on-chip
bandgap voltage reference.
• 200 V (IRS2540) and 600 V (IRS2541) half bridge
driver
• Micropower startup (<500 µA)
• ±2% voltage reference
• 140 ns deadtime
• 15.6 V zener clamp on VCC
• Frequency up to 500 kHz
• Auto restart, non-latched shutdown
• PWM dimmable
The application is inherently protected against short
circuit conditions, with the ability to easily add open-
circuit protection. An external high-side bootstrap
circuit drives the buck switching element at high
frequencies. A low-side driver is also provided for
synchronous rectifier designs. All functions are
realized within a simple 8 pin DIP or SOIC package.
• Small 8-Lead DIP/8-Lead SOIC packages
Packages
8-Lead PDIP
8-LeadSOIC
IRS254(0,1)PbF
IRS254(0,1)SPbF
Typical Application Diagram
VBUS
L2
VOUT+
RS1
RS2
DBOOT
IC1
VCC
VB
HO
VS
LO
CVCC1
ROV1
1
2
3
4
8
7
6
5
COM
RG1
M1
M2
DCLAMP
DOV
CVCC2
CBUS2
CBOOT
L1
IFB
CBUS1
ENN
RG2
ROV2
COUT
CEN
VOUT-
RCS
RF
ROUT
CF
COM
EN
DEN1
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IRS254(0,1)(S)PbF
Alternate application circuit using a single MOSFET
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IRS254(0,1)(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
IRS2540
IRS2541
-0.3
225
VB
High-side floating supply voltage
-0.3
VB – 25
VS – 0.3
-0.3
-0.3
-0.3
-20
625
VB + 0.3
VB + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
20
VS
VHO
VLO
High-side floating supply offset voltage
High-side floating output voltage
Low-side output voltage
V
VIFB
VENN
ICC
Feedback voltage
Enable voltage
Supply current (Note 1)
mA
dV/dt
Allowable offset voltage slew rate
-50
50
V/ns
(8-Pin DIP)
---
1
Package power dissipation @ TA ≤ +25 ºC
PD
W
PD = (TJMAX-TA)/RTHJA
(8-Pin SOIC)
(8-Pin DIP)
---
0.625
125
---
RTHJA
Thermal resistance, junction to ambient
ºC/W
(8-Pin SOIC)
---
200
TJ
TS
TL
Junction temperature
-55
150
ºC
Storage temperature
-55
150
Lead temperature (soldering, 10 seconds)
---
300
Note 1: This IC contains a zener clamp structure between the chip VCC and COM, with a nominal breakdown voltage of
15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater than VCLAMP
specified in the electrical characteristics section.
Recommended Operating Conditions
For proper operation the device should be used within recommended conditions.
Symbol
Definition
Min.
Max.
Units
VBS
High side floating supply voltage
VCC – 0.7
VCLAMP
IRS2540
IRS2541
-1
-1
200
600
V
VS
Steady state high-side floating supply offset voltage
VCC
ICC
TJ
Supply voltage
VCCUV+
Note 2
-25
VCLAMP
10
Supply current
mA
ºC
Junction temperature
125
Note 2: Sufficient current should be supplied to VCC to keep the internal 15.6 V zener regulating at VCLAMP
.
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IRS254(0,1)(S)PbF
Electrical Characteristics
VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 µF, TA=25 °C unless otherwise specified.
Symbol
Definition
Min Typ Max
Units Test Conditions
Supply Characteristics
VCC supply undervoltage positive going
threshold
VCCUV+
VCCUV-
VUVHYS
8.0
6.5
1.0
9.0
7.5
1.2
10.0
8.5
VCC rising from 0 V
VCC supply undervoltage negative going
threshold
V
VCC falling from 14 V
VCC supply undervoltage lockout hysteresis
2.0
IQCCUV
IQCCENN
IQCC
UVLO mode quiescent current
Diesabled mode quiescent current
Quiescent VCC supply current
VCC supply current, f = 50 kHz
VCC zener clamp voltage
---
---
50
1.0
150
2.0
µA
mA
V
VCC=6 V
EN>VENTH+
IFB = 1 V
---
1.0
2.0
Duty Cycle = 50%
f = 50 kHz
ICC50k
---
2.0
3.0
VCLAMP
14.6
15.6
16.6
ICC = 10 mA
Floating Supply Characteristics
IQBS0
IQBS1
VBSUV+
VBSUV-
Quiescent VBS supply current
---
---
1.0
2.0
2.0
3.0
VHO = VS
IFB = 0 V
mA
Quiescent VBS supply current
VBS supply undervoltage positive going
threshold
6.5
6.0
7.5
7.0
8.5
8.0
V
VBS supply undervoltage negative going
threshold
IRS2540:VB=VS=200 V
IRS2541:VB=VS=600 V
ILK
Offset supply leakage current
---
1
50
µA
Current Control Operation
VENNTH+ ENN pin positive threshold
2.5
1.7
490
455
---
2.7
2.0
3.0
2.3
510
540
---
V
VENNTH-
V0.5
VIFBTH
f
ENN pin negative threshold
0.5 V voltage reference (die level test)
IFB pin threshold
500
500
500
mV
Maximum frequency
kHz
Gate Driver Output Characteristics
VOL
Low level output voltage (HO or LO)
High level output voltage (HO or LO)
Turn-on rise time
---
---
---
---
---
---
---
---
---
---
COM
VCC
---
---
V
VHL
tr
50
120
50
---
ns
A
tf
Turn-off fall time
30
IO+/-
Output source/sink short circuit pulsed current
Deadtime
0.5/0.7
140
320
180
320
180
DT
---
tLO,ON
tLO,OFF
tHO,ON
tHO,OFF
Delay between VIFB>VIFBTH and LO turn-on
Delay between VIFB<VIFBTH and LO turn-off
Delay between VIFB<VIFBTH and HO turn-on
Delay between VIFB>VIFBTH and HO turn-off
---
IFB = 50 kHz square
wave, 200 mV pk-pk
DC offset = 400 mV
Duty Cycle = 50%
ns
---
---
---
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IRS254(0,1)(S)PbF
Electrical Characteristics
VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 µF, TA=25 °C unless otherwise specified.
Symbol
Definition
Min Typ Max
Units Test Conditions
Watchdog timer
tWD
Watchdog timer period
---
---
20
---
---
µs
IFB =1 V
PWWD
LO pulse width
1.0
Functional Block Diagram
8
7
6
VB
HO
VS
PULSE
LEVEL
DELAY
FILTER &
SHIFT
LATCH
3
IFB
1
5
VCC
LO
UVN
DELAY
UVLO
15.6 V
4
ENN
2 V
BANDGAP
REFERENCE
100 K
Watchdog
Timer20 µS
1
µS Pulse
Generator
0. 5 V
2
COM
Values in block diagram are typical values
Lead Assignment
Pin # Symbol
Description
Supply voltage
Pin Assignments
1
2
3
4
5
6
VCC
IC power & signal ground
Current feedback
COM
IFB
1
2
3
8
7
6
5
VB
HO
VS
LO
VCC
COM
IFB
ENN
LO
Disable outputs (LO=High, HO=Low)
Low
-side gate driver output
VS
High-side floating return
ENN
4
7
8
HO
VB
High-side gate driver output
High-side gate driver floating supply
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IRS254(0,1)(S)PbF
STATE DIAGRAM
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Page 6
IRS254(0,1)(S)PbF
is large enough to maintain a low ripple on IFB, Iout,avg
can be calculated:
Functional Description
Operating Mode
VIFBTH
The IRS254(0,1) operates as
hysteritic buck controller. During normal operating
conditions the output current is regulated via the IFB
a
time-delayed
Iout(avg) =
RCS
pin voltage (nominal value of 500 mV).
This
feedback is compared to an internal high precision
bandgap voltage reference. An on-board dV/dt filter
has also been used to ignore erroneous
transitioning.
Once the supply to the IC reaches VCCUV+, the LO
output is held high and the HO output low for a
predetermined period of time. This initiates charging
of the bootstrap capacitor, establishing the VBS
floating supply for the high-side output. The IC then
begins toggling HO and LO outputs as needed to
regulate the current.
(A)
(B)
Fig.2 (A) Storing Energy in Inductor
(B) Releasing Inductor Stored Energy
50%
HO
50%
50%
t_HO_off
t_HO_on
DT2
DT1
Iout
HO
LO
50%
50%
LO
t_LO_off
t_LO_on
IFB
IFBTH
Fig.3 IRS254(0,1) Time Delayed Hysterisis
Fig.1 IRS254(0,1) Control Signals, Iavg=1.2 A
The control method is based upon a free running
frequency, in constrast to a more widely used fixed
frequency regulation. This reduces the part count
since there is no need for frequency setting
components and also provides an inherently stable
sytem, which acts as a current source.
As long as VIFB is below VIFBTH, HO is on, modulated
by the watchdog timer described below, the load is
receiving current from VBUS, which simultaneously
stores energy in the inductor, as VIFB increases,
unless the load is open. Once VIFB crosses VIFBTH
,
the control loop switches HO off after the delay
tHO,OFF. Once HO is off, LO will turn on after the
deadtime (DT), the inductor releases the stored
energy into the load and VIFB starts decreasing.
When VIFB crosses VIFBTH again, the control loop
switches HO on after the delay tHO,ON and LO off
after the delay tHO,ON + DT. The switching continues
to regulate the current at an average value
determined as follows. When the inductance value
A deadtime of approximately 140 ns between the
two gate drive signals is necessary to prevent a
“shoot-through” condition. At higher frequencies, the
switching losses become very large in the absence
of this deadtime. The deadtime has been adjusted to
maintain precise current regulation, while still
preventing shoot-through.
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IRS254(0,1)(S)PbF
Design Tip (DT 98-2), “Bootstrap Component
Selection For Control ICs” at www.irf.com under
Design Support
Watchdog Timer
During an open circuit condition, without the
watchdog timer, the HO output would remain high at
all times and the charge stored in the bootstrap
capacitor CBOOT would gradually discharge the
floating power supply for the high-side driver, which
would then be unable to fully switch on the upper
Disable (ENN) Pin
The disable pin can be used for dimming and open-
circuit protection. When the ENN pin is held low, the
chip remains in a fully functional state with no
alterations to the operating environment. To disable
the control feedback and regulation, a voltage
greater than VENTH (approximately 2.5 V) needs to be
applied to the ENN pin. With the chip in a disabled
state, HO output will remain low, whereas the LO
output will remain high to prevent VS from floating, in
addition to maintaining charge on the bootstrap
MOSFET causing high losses.
To maintain
sufficient charge on the bootstrap capacitor, a
watchdog timer has been implemented. In the
condition where VIFB remains below VIFBTH, the HO
output will be forced low after 20 µs and the LO
output forced high. This toggling of the outputs will
last for approximately 1 µs to maintain and replenish
sufficient charge on CBOOT
.
capacitor.
The threshold for disabling the
IRS254(0,1) has been set to 2.5 V to enhance
immunity to any externally generated noise, or
application ground noise. This 2.5 V threshold also
makes it ideal to receive a drive signal from a local
microcontroller.
HO
LO
Dimming Mode
To achieve dimming,
a
signal with constant
frequency and set duty cycle can be fed into the
ENN pin. There is a direct linear relationship
between the average load current and duty cycle. If
the ratio is 50%, 50% of the maximum set light
output will be realized. Likewise if the ratio is 30%,
70% of the maximum set light output will be realized.
A sufficiently high frequency of the dimming signal
must be chosen to avoid flashing or “strobe light”
effect. A signal on the order of a few kHz should be
sufficient.
Fig.4 Illustration of Watchdog Timer
The minimum amount of dimming achievable (light
output approaches 0%) will be determined by the
“on” time of the HO output, when in a fully functional
regulating state. To maintain reliable dimming, it is
recommended to keep the “off” time of the enable
signal at least 10 times that of the HO “on” time. For
example, if the application is running at 75 kHz with
an input voltage of 100 V and an output voltage of
20 V, the HO “on” time will be 3.3 µs (one-fourth of
the period – see calculations below) according to
standard buck topology theory. This will set the
minimum “off” time of the enable signal to 33 µs.
Bootstrap Capacitor and Diode
The bootstrap capacitor value needs to be chosen
so that it maintains sufficient charge for at least the
approximately 20 µs interval until the watchdog timer
allows the capacitor to recharge. If the capacitor
value is too small, the charge will dissipate in less
than 20 µs. The typical bootstrap capacitor is
approximately 100 nF.
The bootstrap diode should be a fast recovery or
ultrafast recovery component to maintain good
efficiency. Since the cathode of the bootstrap diode
will be switching between zero and to the high
voltage bus, the reverse recovery time of this diode
is of critical importance. For additional information
concerning the bootstrap components, refer to the
Vout
Vin
20V
Duty Cycle =
∗100 =
*100 = 20%
100V
1
HOon time = 20%*
= 3.3µs
75kHz
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IRS254(0,1)(S)PbF
form the voltage clamp. The repetition of the spikes
can be reduced by simply increasing the capacitor
size.
Enable Duty Cycle Relationship to Light Output
100
90
80
70
60
50
40
30
20
10
0
The two resistors form a voltage divider for the
output, which is then fed into the cathode of the
zener diode. The diode will only conduct, flooding
the enable pin, when its nominal voltage is
exceeded. The chip will enter a disabled state once
the divider network produces a voltage at least 2.5 V
greater than the zener rating. The capacitor serves
only to filter and slow the transients/switching at the
positive output terminal.
The clamped output
0
10
20
30
40
50
60
70
80
90
100
Percentage of Light Output
voltage can be determined by the following analysis.
The choice of capacitor is at the designer’s
discretion.
Fig.5 Light Output vs Enable Pin Duty Cycle
2.5V + DZ)(R1 + R2
)
Vout
=
EN
R2
DZ = Zener Diode Nominal Rated Voltage
HO
LO
Fig.6 IRS254(0,1) Dimming Signals
Open Circuit Protection Mode
By using the suggested
Vout
R1
voltage
capacitor, and zener
diode, the output
divider,
IFB
EN
voltage can be clamped
at any desired value. In
3
4
Fig.8 Open Circuit Fault Signals, with Clamp
open-circuit
without output clamp,
the positive output
terminal will float at the
high-side input voltage.
condition
R2
Under-voltage Lock-out Mode
Fig.7 Open Circuit
Protection Scheme
The under-voltage lock-out mode (UVLO) is defined
as the state IRS254(0,1) is in when
turn-on threshold of the IC.
is below the
During startup
V
CC
Switching will still occur
between the HO and LO
outputs, whether due to the
conditions, if the IC supply remains below CCUV+, the
V
IRS254(0,1) will enter the UVLO mode. This state is
very similar to when the IC has been disabled via
control signals, except that LO is also held low.
When the supply is increased to VCCUV+, the IC enters
the normal operation mode. If already in normal
output voltage clamp or the watchdog timer.
Transients and switching will be observed at the
positive output terminal as seen in Fig. 8. The
difference in signal shape, between the output
voltage and the IFB, is due to the capacitor used to
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IRS254(0,1)(S)PbF
operation, the IC does not enter UVLO unless the
add capacitance no longer has a significant effect on
the operating frequency or current regulation, as can
be seen in Figs. 13 and 14.
supply voltage falls below VCCUV-
.
-
Inductance Selection
To maintain tight hysteretic current regulation the
inductor and output capacitor COUT (in parallel with
the LEDs) need to be large enough to maintain the
supply to the load during tHO,ON and avoid significant
undershooting of the load current, which in turn
causes the average current to fall below the desired
value.
400
390
380
470uH
370
680uH
1mH
1.5mH
360
350
First, we are going to look at the effect of the
inductor when there is no output capacitor to clearly
demonstrate the impact of the inductor. In this case,
the load current is identical to the inductor current.
Fig. 9 shows how the inductor value impacts the
frequency over a range of input voltages. As can be
seen, the input voltage has a great impact on the
frequency and the inductor value has the greatest
impact at reducing the frequency for smaller input
voltages.
340
330
30
80
130
180
Vin (V)
Fig.10 Current Regulation for Chosen Inductances
Iout = 350 mA, Vout = 16.8 V
400
380
360
340
425
375
470uH
470uH
320
300
280
260
240
220
200
325
680uH
1mH
680uH
1mH
275
1.5mH
1.5mH
225
175
13
18
23
28
33
30
80
130
180
Vout (V)
Vin (V)
Fig.11 Frequency Response for Chosen Inductances
Iout = 350 mA, Vin = 50 V
Fig.9 Frequency Response for Chosen Inductances
Iout = 350 mA, Vout = 16.8 V
Fig. 10 shows how the variation in load current
increases over a span of input voltages, as the
inductance is decreased. Fig. 11 shows the variation
of frequency over different output voltages and
different inductance values. Finally Fig. 12 shows
how the load current variation increases with lower
inductance over a range of output voltages.
345
343
341
339
470uH
337
335
333
331
329
327
325
680uH
1mH
1.5mH
The output capacitor can be used simultaneously to
achieve the target frequency and current control
accuracy. Fig. 11 shows how the capacitance
reduces the frequency over a range of input voltage.
A small capacitance of 4.7 µF has a large effect on
reducing the frequency. Fig. 12 shows how the
current regulation is also improved with the output
capacitance. There is a point at which continuing to
13
18
23
28
33
Vout (V)
Fig.12 Current Regulation for Chosen Inductances
out = 350 mA, Vin = 50 V
I
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Page 10
IRS254(0,1)(S)PbF
from the output needs to be implemented, as seen in
Fig. 16.
0uF
1000
100
10
4.7uF
10uF
22uF
33uF
47uF
30
50
70
90
110
130
150
170
Vin (V)
Fig. 13 Iout = 350 mA, Vout = 16.8 V, L = 470 µH
400
350
300
250
200
150
100
50
Fig. 15 Iout = 350 mA, Vin = 100 V, Vout = 16.85 V, L = 470 µH,
C out = 33 µF
40V
100V
160V
The resistance between VBUS and VCC supply should
be large enough to minimize the current sourced
directly from the input voltage line; value should be
on the order of hundreds of kΩ. Through the supply
0
0
resistor, a current will flow to charge the
VCC
10
20
30
40
50
capacitor. Once the capacitor is charged up to the
threshold, the IRS254(0,1) enters the micro
start-up regime and begins to operate, activating the
LO and HO outputs. After the first few cycles of
switching, the resistor connected between the output
Capacitance (uF)
VCCUV+
Fig. 14 I out = 350 mA, Vout = 16.8 V, L = 470 µH
The addition of the COUT increases the amount of
energy that can be stored in the output stage, which
also means it can supply current for an increased
period of time. Therefore by slowing down the di/dt
transients in the load, the frequency is effectively
decreased.
and
will take over and source all necessary
VCC
current for the IC. The resistor connecting the
output to the supply should be carefully designed
according to its power rating.
Vout −15.6V
RS2 =
10mA
With the COUT capacitor, the inductor current is no
longer identical to that seen in the load. The
inductor current will still have a perfectly triangular
shape, where as the load will see the same basic
trend in the current, but all sharp corners will be
rounded with all peaks significantly reduced, as can
be seen in Fig. 15
PRS2_ Rated
PRS2 = (10mA)2 RS2 ≤
2
Icc ≈ 10mA
VBUS
VB
HO
VS
LO
VCC
Supply
V
CC
1
2
3
4
8
7
6
5
COM
IFB
Since the IRS245(0,1) is rated for 200 V (or 600 V),
VBUS can reach values of this magnitude. If only a
supply resistor to VBUS is used, it will experience
extremely high power losses. For higher voltage
applications an alternate VCC supply scheme utilizing
the micro-power start-up and a resistor feed-back
ENN
ENN
COM
Fig. 16 Alternate Supply Diagram
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IRS254(0,1)(S)PbF
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Page 12
IRS254(0,1)(S)PbF
8-Lead SOIC
Tape & Reel
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Min
0.311
0.153
0.46
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
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Page 13
IRS254(0,1)(S)PbF
ORDER INFORMATION
8-Lead PDIP IRS2540PbF
8-Lead PDIP IRS2541PbF
8-Lead SOIC IRS2540SPbF
8-Lead SOIC IRS2541SPbF
8-Lead SOIC Tape & Reel IRS2540STRPbF
8-Lead SOIC Tape & Reel IRS2541STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com <http://www.irf.com>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice 2/2/2007
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Page 14
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