IRS2548D_技术文档

September 29, 2011

IRS2548D

SMPS/LED DRIVER PFC + HALF-BRIDGE CONTROL IC

Product Summary

Features

Topology

V_OFFSET

V_OUT

Half Bridge

600V

• PFC, system control and half-bridge driver in

one IC

• Critical-conduction mode boost-type PFC

• Programmable PFC over-current protection

• Half Bridge Driver

• Half Bridge Over Current Protection

• Variable Frequency Oscillator

• Fixed internal 1.6us HO and LO deadtime

• Internal bootstrap MOSFET

VCC

I_o+& I _o-(typical)

500mA/500mA

120nS/50nS

1.6uS

t_ON& t_OFF(typical)

Deadtime (typical)

• Internal 15.6V zener clamp diode on Vcc

• Micropower startup (250µA)

• Latch immunity and ESD protection

Package

Typical Applications

• Isolated LED Drivers

• Power Supplies

14-Lead SOIC

Typical Connection Diagram

DPFC

LPFC

RVBUS1

RVCC

RVBUS2

CVBUS

F1

RV1

L

U1

C1

RHO

VBUS

HO

VS

L1

MHS

1

14

13

N

+

CVBUS1

RPU

RVBUS

RFMIN

BR1

FMIN

COMP

ZX

LED+

2

3

CBS

DOUT1

U3

VB

GND

CVS

12

11

+5V

Reg

CCOMP

RZX

RLM2

RLM1

CY

VCC

COM

4

5

+

RV1

DCP2

CVS

PFC

CVCC2

CVCC1

RLO

C2

10

9

MPFC

RPFC

ROC

RD1

LO

CS

OC

MLS

DOUT2

6

7

U2A

DCP1

COUT

CF1

RF1

ENN

RMAX

7

8

+

CVBUS2

CRES

RD2

CF2

LED-

RV2

RFMAX

R_CS

RF2

CMAX

RO C

COC

U2B

CCS

R_CL

RD3

DO1

DO2

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IRS2548D

Page

3

Table of Contents

Description

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Functional Block Diagram

State Diagram

4

5

6

9

10

11

12

13

19

20

21

22

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

Lead Assignments

Application Information and Additional Details

Package Details

Tape and Reel Details

Part Marking Information

Ordering Information

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2

IRS2548D

Description

The IRS2548D is a fully integrated, fully protected 600V LED or switched mode power supply control IC with

integrated PFC control for a Boost pre-regulator. The IRS2548D is based on the popular IRS2168D

electronic ballast control IC re-designed for use in LED driver or half-bridge power supply applications. The

PFC circuitry operates in critical conduction mode and provides high PF, low THD and DC bus regulation.

The IRS2548D features include programmable minimum run frequency and adjustable oscillator frequency

that can be driven by an opto isolator or other feedback circuit in a feedback loop for frequency modulation in

resonant systems. The IRS2548D also includes PFC over-voltage and over-current protection, half bridge

over current protection and a logic level enable input that can be used for PWM dimming in LED drivers or

general burst mode operation.

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3

IRS2548D

Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s Industrial

qualification. IR’s Consumer qualification level is granted by

Qualification Level

extension of the higher Industrial level.

MSL2^†††260°C

(per IPC/JEDEC J-STD-020)

Class A

Moisture Sensitivity Level

Machine Model

Human Body Model

(per JEDEC standard JESD22-A115)

Class 1C

(per EIA/JEDEC standard EIA/JESD22-A114)

ESD

Class I, Level A

(per JESD78)

IC Latch-Up Test

RoHS Compliant

Yes

†

††

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

Higher qualification ratings may be available should the user have such requirements. Please contact

your International Rectifier sales representative for further information.

Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

†††

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4

IRS2548D

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All

voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.

The thermal resistance and power dissipation ratings are measured under board mounted and still air

conditions.

Symbol

Definition

Min.

-0.3

Max.

625

V + 0.3

B

Units

VB Pin High-Side Floating Supply Voltage

VS Pin High-Side Floating Supply Offset Voltage

HO Pin High-Side Floating Output Voltage

LO Pin Low-Side Output Voltage

V

B

S

V – 25

B

V

HO

V - 0.3

S

V + 0.3

B

V

LO

-0.3

V

+ 0.3

CC

V

PFC

PFC Gate Driver Output Voltage

Maximum allowable output current (HO, LO, PFC)

due to external power transistor miller effect

IO

-500

0

500

25

mA

MAX

†

VCC current

ICC

V

VBUS Pin Voltage

COMP Pin Voltage

OC Pin Voltage

VBUS

COMP

VOC

-0.3

V

+ 0.3

V

CC

V

VZX

SD/EOL Pin Voltage

CS Pin Voltage

ZX Pin Voltage

FMIN Pin Current

COMP Pin Current

ZX Pin Current

OC Pin Current

ENN Pin Current

CS Pin Current

Allowable VS Pin Offset Voltage Slew Rate

Package Power Dissipation @ TA ≤ +25ºC

ENN

CS

VZX_CLAMP+ 0.3

I

FMIN

I

COMP

I

ZX

OC

-5

5

mA

I

ENN

I

CS

dV/dt

-50

---

50

V/ns

W

P

D

1.0

PD = (T

-T )/R

JMAX

θJA

A

Thermal Resistance, Junction to Ambient

Junction Temperature

---

-55

---

120

150

300

ºC/W

R

θJA

T

J

ºC

T

S

Storage Temperature

Lead Temperature (soldering, 10 seconds)

T

L

†

This IC contains a zener clamp structure between the chip V_CCand COM, with a nominal breakdown

voltage of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source

greater than V_CLAMPspecified in the electrical characteristics section.

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5

IRS2548D

Recommended Operating Conditions

For proper operation the device should be used within recommended conditions.

Symbol

V -V

Definition

High Side Floating Supply Voltage

Steady State High-side Floating Supply Offset

Voltage

Min.

BSUV+

Max.

CLAMP

Units

V

B

S

V

S

-1

600

V

Supply Voltage

V

CLAMP

10

CC

ENN

CCUV+

††

I

V

Supply Current

CC

ENN Pin Current

I

CS Pin Current

OC Pin Current

ZX Pin Current

FMIN Pin Programming Resistor

mA

I

CS

-1

1

I

OC

ZX

KOhm

ºC

R

V -V

10

-25

300

125

FMIN

High Side Floating Supply Voltage

B

S

††

Sufficient current should be supplied to

to keep the internal 15.6 V zener regulating at V_CLAMP.

V_CC

Electrical Characteristics

V

= V

BS

= V

=14V +/- 0.25V, C

= C

= 1000pF, RFMIN = 42.2kOhm,

PFC

A

CC

BIAS

= V

CS

LO

HO

VENN = V

= V

OC

= VBUS = VZX = 0V, T =25C unless otherwise specified.

COMP

Symbol

Definition

Min

Typ

Max Units Test Conditions

Supply Characteristics

Supply Undervoltage Positive

V

rising from

falling from

CC

Going Threshold

Supply Undervoltage Negative

CC

0V

V

+

11.5

9.5

12.5

10.5

2.0

13.5

11.5

3.0

V

CCUV

V

CC

14V

CC

Going Threshold

Supply Undervoltage Lockout

V

-

CCUV

V

CC

V

1.5

UVHYS

Hysteresis

I

UVLO Mode V

Quiescent Current

---

250

400

---

µA

V

= 8V

CC

QCCUV

CC

IQCCFLT VCC Quiescent current in fault mode

MODE=FAULT

MODE = RUN

VBUS=4V

I

Run Mode V

CC

Supply Current

---

5.5

---

mA

CCRUN

ENN=1nF

PFC off time = 5us

Zener Clamp Voltage

V

CC

14.6

15.6

16.6

V

I

= 10mA

CLAMP

CC

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6

IRS2548D

Electrical Characteristics (cont’d)

V

= V

BS

= V

=14V +/- 0.25V, C

= C

= 1000pF, RFMIN = 42.2kOhm,

PFC

A

CC

BIAS

= V

CS

LO

HO

VENN = V

= V

OC

= VBUS = VZX = 0V, T =25C unless otherwise specified.

COMP

Symbol

Definition

Min

Typ

Max Units Test Conditions

Floating Supply Characteristics

I

V

Supply Current

Supply Undervoltage Positive Going

---

0.9

9.0

1.3

mA

V

MODE=RUN

BS

V

BS

0V

rising from

V

8.0

10.0

BSUV+

Threshold

Supply Undervoltage Negative

V

falling from

BS

Going Threshold

V Offset Supply Leakage Current

BS

14V

V = V = 600V

V

7.0

---

8.0

---

9.0

50

BSUV-

I

uA

LKVS

S

B

S

PFC Error Amplifier Characteristics

MODE = RUN

V = 3.5V

VBUS

I

COMP Pin OTA Error Amplifier Output

Current Sourcing

COMP

SOURCE

---

30

-30

---

uA

V

VCOMP=4.0V

MODE = RUN

I

COMP Pin OTA Error Amplifier Output

Current Sinking

COMP

SINK

V

= 4.5V

VBUS

VCOMP=4.0V

VBUS=3.5V

OTA Error Amplifier Output Voltage

Swing (high state)

V

12.5

ICOMP=ICOMP_

SOURCE - 5uA

VBUS=5.0V

ICOMP=ICOMP_

SINK + 5uA

COMPOH

OTA Error Amplifier Output Voltage

Swing (low state)

V

---

0.4

0

---

COMPOL

OTA Error Amplifier Output Voltage in

Fault Mode

VCOMPFLT

VBUS=4.0V

PFC Control Characteristics

V

REG

VBUS

VBUS Internal Reference Voltage

3.93

4.1

50

4.03

4.3

4.13

4.5

V

VBUS Over-voltage Comparator

Threshold

V

= 4.0V

COMP

V

VBUSOV

VBUS Over-voltage Comparator

Hysteresis

VBUSOV

HYS

150

300

mV

V

ZX Pin Threshold Voltage

1.8

---

2.0

300

6.7

2.2

---

V

mV

V

ZX

V

ZX pin Comparator Hysteresis

ZX pin Clamp Voltage (high state)

ZXhys

V

---

I

= 1mA

ZX

ZXclamp

VBUS=4.0V

VCOMP=4.0V

t

OC pin current-sensing blank time

PFC Watch-dog Pulse Interval

---

300

400

---

ns

us

BLANK

ZX = 0, V

= 4.0V

COMP

t

WD

PFC Protection Circuitry Characteristics

OC Pin Over-current Sense Threshold

VBUS=VCOMP

=4.0V

V

1.1

1.2

1.3

OCTH+

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7

IRS2548D

Electrical Characteristics (cont’d)

V

= V

BS

= V

=14V +/- 0.25V, C

= C

= 1000pF, RFMIN = 42.2kOhm,

PFC

A

CC

BIAS

= V

CS

LO

HO

VENN = V

= V

OC

= VBUS = VZX = 0V, T =25C unless otherwise specified.

COMP

Symbol

Definition

Min

Typ

Max Units Test Conditions

System Control Oscillator Characteristics

f

MODE = RUN

OSCRUN Half-bridge Oscillator Run Frequency

42.5

---

1.9

44.5

50

1.6

2.0

46.5

---

2.1

kHz

us

V

d

Oscillator duty cycle

LO Output Deadtime

HO Output Deadtime

FMIN Pin Voltage

td

LO

td

V

HO

FMIN

VCC = 14.0V

MODE = FAULT

or UVLO

V

FMINFLT FMIN Pin Fault or UVLO Mode Voltage

---

0

---

System Control Protection Circuitry Characteristics

V

CSTH+ CS Pin Over-current Sense Threshold

1.15

---

1.25

65

1.35

---

V

n

EVENTS CS Pin Fault Counter No. of Events

SD Pin Rising Non-latched Shutdown

MODE = RUN

V

ENNTH+

2.0

Threshold Voltage

V

ENNTH- SD Pin Falling Reset Threshold Voltage

---

1.5

0V

0

---

V

EOL Pin Internal Bias Voltage

V

ENNBIAS

V

FMINFLT FMIN Pin Fault Mode Voltage

MODE = FAULT

Gate Driver Output Characteristics (HO, LO and PFC pins)

---

0

V

Low-Level Output Voltage

100

I

V

= 0

BIAS

= 0

OL

O

mV

-

V

O

,

---

V

OH

High-Level Output Voltage

I

O

t

r

---

120

50

180

260

Turn-On Rise Time

Turn-Off Fall Time

Source Current

Sink Current

---

nsec

mA

t

f

I0+

I0-

Bootstrap FET Characteristics

VB_ON

IB_CAP

IB_10V

VB when the bootstrap FET is on

---

35

8

13.7

55

---

V

VB source current when FET is on

mA

CBS=0.1uF

VB=10V

12

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8

IRS2548D

Functional Block Diagram

VCC

COM

VCC

I_FMIN

10

11

12

14

13

VB

HO

VS

Bootstrap

Control

Driver

and

Deadtime

Logic

Oscillator

15.6V

High-

Side

Driver

2V

2

FMIN

2V

R_RFMIN

I_FMIN=

Low-

Side

Driver

9

8

LO

CS

60 Event

Fault

Counter

R

OUT

IN

1.25V

VCC

Fault

Logic

+/-10uA

UVLO

0V

Half Bridge

Control

Q

S

R

2V

6

OC

7

ENN

1.25V

200ns

1.5V

Blank Time

1

VBUS

OVP

PFC Control

VCC

OTA1

4.0V

4.3V

5

PFC

3

COMP

S

R

Q

300us

Watchdog

Timer

S

Q

R1

R2

Q

4

ZX

2V

5.5V

Values in block diagram are typical values

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9

IRS2548D

State Diagram

All values are typical.

Please refer to application diagram on page 1.

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10

IRS2548D

Input/Output Pin Equivalent Circuit Diagrams

VCC

VBUS,

FMIN,

COMP,

ZX,

PFC,

OC,

ESD

Diode

15V

ESD

Diode

ENN,

CS

COM

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11

IRS2548D

Lead Definitions

Symbol

VBUS

FMIN

COMP

ZX

Description

DC Bus Sensing Input

Oscillator Minimum Frequency Setting

PFC Error Amplifier Compensation

PFC Zero-Crossing Detection

PFC Gate Driver Output

PFC

OC

PFC Current Sensing Input

ENN

CS

LO

COM

VCC

VB

Enable / PWM Dimming Input

Half-Bridge Current Sensing Input

Low-Side Gate Driver Output

IC Power & Signal Ground

Logic & Low-Side Gate Driver Supply

High-Side Gate Driver Floating Supply

High Voltage Floating Return

High-Side Gate Driver Output

VS

HO

Lead Assignments

HO

VBUS

1

2

3

4

5

67

7

14

FMIN

VS

VB

13

12

11

10

COMP

ZX

VCC

COM

PFC

LO

CS

9

8

OC

ENN

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12

IRS2548D

Application Information and Additional

Details

V_C1

C_VCC

DISCHARGE

INTERNAL VCC

ZENER CLAMP VOLTAGE

V_UVLO+

I. LED Driver Section

Functional Description

VHYST

V_UVLO-

DISCHARGE

TIME

Under-voltage Lock-Out Mode (UVLO)

CHARGE PUMP

OUTPUT

R_VCC& C_VCC1,2

TIME

CONSTANT

The under-voltage lock-out mode (UVLO) is defined

as the state the IC is in when VCC is below the

turn-on threshold of the IC. The IRS2548D

undervoltage lock-out is designed to maintain an

ultra low supply current and to guarantee the IC is

fully functional before the high and low-side output

drivers and PFC are activated. Figure 1 shows a

possible VCC supply voltage scheme using the

micro-power start-up current of the IRS2548D

together with a snubber charge pump from the half-

bridge output (R_VCC, C_VCC1, C_VCC2, C_SNUB, D_CP1and

t

Figure 2: VCC supply voltage.

When LO and HO are both oscillating, the external

MOSFETs (MHS and MLS) are turned on and off with

a 50% duty cycle and a non-overlapping deadtime of

1.6us. The half-bridge output (pin VS) begins to

switch between the DC bus voltage and COM. During

the deadtime between the turn-off of LO and the turn-

on of HO, the half-bridge output voltage transitions

from COM to the DC bus voltage at a dv/dt rate

determined by the snubber capacitor (C_SNUB). As the

snubber capacitor charges, current will flow through

the charge pump diode (D_CP2) to VCC. After several

switching cycles of the half-bridge output, the charge

pump and the internal 15.6V zener clamp of the IC

take over as the supply voltage. Capacitor C_VCC2

supplies the IC current during the VCC discharge

time and should be large enough such that VCC does

not decrease below UVLO- before the charge pump

takes over.

D

_CP2).

V_RECT(+)

V_BUS(+)

R_VCC

R_HO

HO

VS

14

13

12

11

10

9

MHS

C_VCC2R₁D_CP2

MLS

To Load

C_SNUB

BSFET

VB

C_BS

R₂

BSFET

CONTROL

VCC

C _VCC1

R_LO

R₃

COM

LO

D_CP1

CS

8

This scheme can be used in non-dimming

applications, however where PWM dimming is used

the charge pump may not supply enough current to

VCC at low dimming levels and in this case an

auxiliary power supply is required.

R

C

CS

IRS2548D

CS

IC _COM

Load

Return

V _BUS(-)

Figure 1: Start-up and supply circuitry.

Capacitor C_VCC1is required for noise filtering and

must be placed as close as possible and directly

between VCC and COM, and should not be lower

than 0.1uF. Resistors R₁and R₂are recommended

for limiting high currents that can flow to VCC from

the charge pump. The internal bootstrap MOSFET

and supply capacitor (C_BS) provide the floating supply

voltage for the high side driver circuitry. During

UVLO mode the high and low-side driver outputs HO

and LO are both low and the internal oscillator is

disabled.

The VCC capacitors (C_VCC1and C_VCC2) are charged

by the current through supply resistor (R_VCC) minus

the start-up current drawn by the IC. This resistor is

chosen to set the desired AC line input voltage turn-

on threshold for the system. When the voltage at

VCC exceeds the IC start-up threshold (VCCUV+)

and the ENN pin is below 1.5 volts, the IC turns on

and LO begins to oscillate. The capacitors at VCC

begin to discharge due to the increase in IC

operating current (Figure 2). The high-side supply

voltage, VB-VS, begins to increase as capacitor

C_BSis charged through the internal bootstrap

MOSFET during the LO on-time of each LO

switching cycle. When the VB-VS voltage exceeds

the high-side start-up threshold (VBSUV+), HO

then begins to oscillate. This may take several

cycles of LO to charge VB-VS above VBSUV+ due

to RDSon of the internal bootstrap MOSFET.

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13

IRS2548D

Run Mode (RUN)

After the VCC supply comes up and the IC starts,

the IC enters run mode. The operating frequency is DIM Mode (ENN Input)

set to the minimum limit, which is programmed by

the external resistor (RFMIN) at the FMIN pin. If the PWM dimming can be implemented via the ENN pin.

IRS2548D is used in series resonant If the voltage input to the ENN pin exceeds 2V during

a

configuration the frequency can be increased to run mode, the IC enters dim mode, LO, HO and PFC

regulate the system output voltage. This can be gate drivers go to the low state. This is similar to fault

implemented by sinking additional current from the mode except that the COMP pin is not internally

FMIN pin with an additional resistor, opto isolator or pulled to COM and so the COMP capacitor retains it's

other arrangement.

voltage. This allows the PFC to start up rapidly with

It should be noted that the FMIN pin input is very the on time close to where it was before the ENN

sensitive to noise and that traces connected to this signal shut off the IC outputs. When ENN goes below

pin should be very short and should be kept away 1.5V and therefore the bus voltage can be maintained

from high voltage switching nodes; HO, VB and VS. while the PFC gate drive being held low during the

An additional RC filter can also be added to the periods where the LED load is not being driven. This

FMIN pin if necessary as shown in the application minimizes ripple generated on the DC bus during

schematic on page 1.

PWM dimming.

Should hard-switching occur at the half-bridge at

any time or excessive current be drawn due to a

fault condition, the voltage across the current

sensing resistor (RCS) will exceed the internal

threshold of 1.2 volts (VCSTH+) and the fault

counter will begin counting (see Figure 3).

CS Fault Mode

The current sense function will force the IC to enter

fault mode only after the voltage at the CS pin has

been greater than 1.2V (VCSTH+) for 65

(nEVENTS) consecutive cycles of LO. The voltage

at the CS pin is AND-ed with LO (see Figure 3) so it

will work with pulses that occur during the LO on-

time or DC. If the over-current faults are not

consecutive, then the internal fault counter will

count back down each cycle when there is no fault.

Should an over-current fault occur only for a few

cycles and then not occur again, the counter will

eventually reset to zero.

65 Cycles

LO

CS

1.25V

Run Mode

Fault Mode

Figure 3: Fault counter timing diagram.

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14

IRS2548D

continuously monitoring the DC bus voltage and

adjusting the on-time of MPFC accordingly. For an

increasing DC bus the on-time is decreased and for a

decreasing DC bus the on-time is increased. This

negative feedback control is performed with a slow

loop speed such that the average inductor current

smoothly follows the low-frequency line input voltage

for high power factor and low THD. The on-time of

MPFC therefore appears to be fixed (except for on

time modulation which is discussed later) over

several cycles of the line voltage. With a fixed on-

time and an off-time determined by the inductor

current discharging to zero the switching frequency

and duty cycle vary to produce a high frequency near

the zero crossing of the AC input line voltage and a

lower frequency at the peak (Figure 5).

II. PFC Section

Functional Description

In most LED drivers rated at more than a few Watts

high power factor high power factor (PC) is a

requirement. The driver needs to appear as a

resistive load to the AC input line voltage. The

degree to which the circuit matches a purely

resistive load is measured by the phase shift

between the input voltage and input current

harmonic distortion of the input current waveform.

The cosine of the phase angle between the input

voltage and input current is defined as the

displacement power factor and the amount of

harmonic distortion determines the distortion power

factor and total harmonic distortion (THD). The

overall power factor is the ratio between real and

apparent power and includes both displacement

and distortion. A power factor of 1.0 corresponds to

zero phase shift and a THD of 0% representing a

pure sinusoidal current waveform. In order to

provide a high PF and a low THD the IRS2548D

includes an active power factor correction (PFC)

circuit.

V, I

The control method implemented in the IRS2548D

is designed for a PFC Boost converter (Figure 4)

running in critical-conduction mode, the boundary

between continuous and discontinuous mode.

During the off period of each switching cycle of the

PFC MOSFET the circuit waits until the inductor

current falls to zero before turning the PFC

MOSFET on again. The PFC MOSFET is turned on

and off at a much higher frequency (>10KHz) than

the line input frequency (50 to 60Hz).

t

Figure 5: Sinusoidal line input voltage (solid

line), triangular PFC Inductor current and

smoothed sinusoidal line input current

(dashed line) over one half-cycle of the AC line

input voltage.

When the line input voltage is low (near the zero

crossing), the inductor current will charge to a

lower peak level and therefore the discharge time

will be fast resulting in a high switching frequency.

When the input line voltage is high (near the

peak), the inductor current will charge up to a

higher amount and the discharge time will be

longer giving a lower switching frequency.

DPFC

LPFC

DC Bus

(+)

+

CBUS

MPFC

The PFC control circuit of the IRS2548D (Figure 6)

includes five control pins: VBUS, COMP, ZX, PFC

and OC. The VBUS pin measures the DC bus

voltage via an external resistor voltage divider.

The COMP pin voltage at the transconductance

error amplifier output sets the on-time of MPFC

where the speed of the feedback loop is

determined by the external COMP capacitor. The

ZX input detects when the inductor current has

discharged to zero each switching cycle using a

secondary winding from the PFC inductor. The

PFC output provides the gate driver output for the

external MOSFET, MPFC. The OC pin senses the

current flowing through MPFC and performs cycle-

by-cycle over-current protection.

(-)

Figure 4: Boost converter circuit.

When the switch MPFC is turned on the inductor

LPFC is connected between the rectified line input

(+) and (-) causing the current in LPFC to rise

linearly. When MPFC is turned off LPFC is

connected between the rectified line input (+) and

the DC bus capacitor CBUS through diode DPFC

and the stored energy in LPFC supplies a current

into CBUS. MPFC is turned on and off at a high

frequency and the voltage on CBUS charges up to

a specified voltage. The feedback loop of the

IRS2548D regulates this voltage to a fixed value by

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15

IRS2548D

negative transition of ZX pin voltage does not

occur. Should the negative edge at ZX not be

detected, MPFC will remain off until the watch-dog

timer forces it to turn-on again after a fixed delay.

LPFC

(+)

DFPC

Should the OC pin exceed the 1.2V (VOCTH+)

over-current threshold during the on-time, the PFC

output will turn off. The circuit will then wait for a

negative-going transition on the ZX pin or a forced

turn-on from the watch-dog timer to turn the PFC

output on again.

RVBUS1

RVBUS2

RZX

VBUS

ZX

CBUS

PFC

Control

RPFC

PFC

OC

MPFC

COMP

COM

ROC

CCOMP

RVBUS

I_LPFC

. . .

(-)

PFC

ZX

. . .

Figure 6: IRS2548D simplified PFC control circuit.

The VBUS pin is regulated against a fixed internal

4V reference voltage for regulating the DC bus

voltage (Figure 7). The feedback loop is performed

by an operational transconductance amplifier (OTA)

that sinks or sources a current to the external

capacitor at the COMP pin. The resulting voltage

on the COMP pin sets the threshold for the charging

of the internal timing capacitor and therefore

determines the on-time of MPFC.

1.2V

OC

. . .

Figure 8: Inductor current, PFC pin, ZX pin and

OC pin timing diagram.

Fault Mode Signal

On-time Modulation Circuit

1

VBUS

VCC

COMP4

OTA1

4.0V

A fixed on-time of MPFC over an entire cycle of the

line input voltage produces a peak inductor current

which naturally follows the sinusoidal shape of the

line input voltage. The smoothed averaged line

input current is in phase with the line input voltage

for high power factor but some harmonic distortion

is left. This is mostly due to cross-over distortion of

the line current near the zero-crossings of the line

input voltage. To achieve lower harmonics that

4.3V

5

PFC

OC

RS

3

COMP5

3

COMP

S

Q

R

Q

M1

COMP2

WATCH

DOG

TIMER

Discharge

VCC to

UVLO-

C1

M2

3.0V

6

1.2V

S

Q

RS

4

R

1

R

2

COMP3

4

ZX

2.0V

5.1V

comply with

EN61000-3-2 class

international standards such as

and general market

Figure 7: IRS2548D detailed PFC control

circuit.

C

requirements an additional on-time modulation

circuit in included in the PFC control. This circuit

dynamically increases the on-time of MPFC as the

line input voltage nears the zero-crossings (Figure

9). This causes the peak LPFC current and

therefore the smoothed line input current to

increase slightly near the zero-crossings of the line

input voltage to compensate for cross over

distortion which reduces the THD and higher

harmonics.

The off-time of MPFC is determined by the time it

takes the LPFC current to fall to zero. A positive-

going edge at the ZX input exceeding the internal

2V threshold (VZXTH+) signals the beginning of

the off-time and the following negative-going edge

falling below 1.7V (VZXTH+ - VZXHYS) occurs

when the LPFC current discharges to zero which

signals the end of the off-time and MPFC is turned

on again (Figure 8). The cycle repeats itself

indefinitely until the PFC section is disabled due to

a fault detected by the system section (Fault

Mode), an over-voltage on the DC bus or the

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16

IRS2548D

III. Design Equations (Half-Bridge)

Note: The results from the following design equations

can differ slightly from actual measurements due to IC

tolerances, component tolerances, and oscillator over-

and under-shoot due to internal comparator response

time.

I_LPFC

0

PFC

Step 1: Program Run Frequency

0

The run frequency is programmed with the timing

resistor RFMIN at the FMIN pin.

near peak region of

rectified AC line

near zero-crossing region

of rectified AC line

The graph in Figure 10 (RFMIN vs. Frequency) can be

used to select RFMIN value for desired run frequency.

Figure 9: On-time modulation circuit timing diagram

180

160

140

120

100

80

DC Bus Over-voltage Protection

Should over-voltage occur on the DC bus and the

VBUS pin exceeds the internal 4.3V threshold

(VBUSOV+), the PFC output is disabled (set to a

logic ‘low’). When the DC bus decreases again

and the VBUS pin decreases below the internal

4.15V threshold (VBUSOV-), a watch-dog pulse is

forced on the PFC pin and normal PFC operation

is resumed.

60

40

20

10

15

20

25

30

35

40

45

50

Equivalent RFMIN (Kohms)

Figure 10: Graph of frequency against RFMIN

Step 2: Program Maximum Current

The maximum current is programmed with the external

resistor RCS and an internal threshold of 1.25V

(VCSTH+). This threshold determines the over-current

limit of the system:

1.25

[Amps Peak]

I_MAX

=

R_CS

or

1.25

[Ohms]

R_CS

=

I_MAX

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17

IRS2548D

IV. PFC Design Equations

Step1: Calculate PFC inductor value:

(VBUS − 2 ⋅VAC_MIN)⋅VAC_M²_IN⋅η

L_PFC

=

[Henries]

2⋅ f_MIN⋅ P ⋅VBUS

OUT

where,

VBUS

= DC bus voltage

VAC_MIN= Minimum rms AC input voltage

= PFC efficiency (typically 0.95)

η

f_MIN

= Minimum PFC switching frequency at minimum AC input voltage

= System output power

P_OUT

Step 2: Calculate peak PFC inductor current:

2⋅ 2 ⋅ P

VAC_MIN⋅η

OUT

i_PK

=

[Amps Peak]

Note: The PFC inductor must not saturate at i_PKover the specified system operating temperature

range. Proper core sizing and air-gapping should be considered in the inductor design.

Step 3: Calculate PFC over-current resistor ROC value:

1.25

where VCSTH+ = 1.25V

[Ohms]

R_OC

=

i_PK

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18

IRS2548D

Package Details

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19

IRS2548D

Tape and Reel Details

www.irf.com

20

IRS2548D

Part Marking Information

www.irf.com

21

IRS2548D

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

Tube/Bulk

55

IRS2548DSPBF

SOIC14N

IRS2548D

Tape and Reel

2500

IRS2548DSTRPBF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no

responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement

of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or

otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to

change without notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

22


型号：	IRS2548D
厂家：	Infineon
描述：	SMPS/LED DRIVER PFC HALF-BRIDGE CONTROL IC 开关电源/ LED驱动器的PFC半桥控制IC 驱动器开关功率因数校正
文件：	总22页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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