IRS2552D_技术文档

July 7, 2009

IRS2552D

CCFL/EEFL BALLAST CONTROLLER IC

Features

Product Summary

•

Drives up to two IGBT/MOSFET power devices

Topology

Half-Bridge

600 V

Integrated programmable oscillator

•

Soft start function

V_OFFSET

15.6 V voltage clamp on

Micro-power startup

0 V to 5 V input analog dimming

Programmable ignition frequency

Programmable ignition time

V_CC

•

V_OUT

V_CC

I_O+& I_O-(typical)

300 mA & 450 mA

500ns ~ 2µs

Deadtime

(programmable)

Lamp current control

Programmable deadtime

Supports multi-lamp operation

Burst dimming with soft start at every burst

Latched open circuit protection

Integrated bootstrap functionality

Excellent latch immunity on all inputs & outputs

Integrated ESD protection on all pins

Package Options

Typical Application

•

CCFL/EEFL inverter

16-Lead PDIP

16-Lead SOIC (Narrow Body)

Typical Application Diagram

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23

IRS2552D

Table of Contents

Page

Typical Application Diagram

1

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Functional Block Diagram

Lead Definitions

4

5

6

7

10

12

13

14

15

29

30

32

Lead Assignments

State Diagram

Application Information and Additional Details

Package Details

Part Marking Information

Ordering Information

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2

IRS2552D

Description

The IRS2552D incorporates a high voltage half-bridge gate driver with a front end that incorporates full control

functionality for CCFL/EEFL ballasts. Includes a programmable ignition and supports dimming via analog or PWM

control voltage. HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The

output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise

immunity is achieved with low di/dt peak of the gate drivers, and with an undervoltage lockout hysteresis of

approximately 1 V. The IRS2552D also includes protection features for over-current and over-voltage of the lamps.

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3

IRS2552D

Qualification Information^†

Industrial^††

(per JEDEC JESD 47E)

Qualification Level

Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

MSL3^†††

SOIC16

(per IPC/JEDEC J-STD-020C)

Moisture Sensitivity Level

Not applicable

(non-surface mount package style)

PDIP16

Class C

Machine Model

Human Body Model

(per JEDEC standard EIA/JESD22-A115-A)

ESD

Class 3A

(per EIA/JEDEC standard JESD22-A114-B)

Class I, Level A

IC Latch-Up Test

RoHS Compliant

(per JESD78A)

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

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4

IRS2552D

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

V_B

Definition

High-side floating supply voltage

High-side floating supply offset voltage

High-side floating output voltage

Low-side output voltage

Min.

-0.3

V_B- 25

V_S– 0.3

-0.3

---

Max.

625

Units

V_S

V_B+ 0.3

V_CC+ 0.3

V_H

V_L

V_CO

V_CT

V_DT

MIN

DIM

CR

CD

SD

VCO pin voltage

C pin voltage

T

V

DT pin voltage

MIN pin voltage

DIM pin voltage

CR pin voltage

CD pin voltage

SD pin voltage

CS pin voltage

V

_CC+ 0.3

V_CC+ 0.3

CS

I_CC

Supply current^†

Allowable offset voltage slew rate

25

50

mA

V/ns

dV_S/dt

-50

16L-PDIP

16L-SOIC

16L-PDIP

16L-SOIC

---

1.3

1.4

70

Package power dissipation @ T_A≤ +25

P_D

W

ºC

R_ΘJA

Thermal resistance, junction to ambient

ºC/W

82

T_J

T_S

T_L

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

-55

---

150

300

ºC

†

This IC contains a voltage clamp structure between the chip V_CCand COM which has a nominal breakdown

voltage of 15.6 V. Please note that this supply pin should not be driven by a DC, low impedance power source

greater than the V_CLAMPspecified in the Electrical Characteristics section.

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IRS2552D

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol

Definition

High-side floating supply voltage

Steady-state high-side floating supply offset voltage

Supply voltage

Supply current

Junction temperature

Min.

V_CC– 0.7

Max.

V_CLAMP

Units

V_BS

-3.0^†

V_CCUV++0.1V

††

V_S

V_CC

I_CC

T_J

V

600

V_CLAMP

10

mA

ºC

-40

125

†

Care should be taken to avoid output switching conditions where the V node flies inductively below ground

S

by more than 5 V.

†† Enough current should be supplied to the

pin of the IC to keep the internal 15.6 V zener diode clamping

V_CC

the voltage at this pin.

Recommended Component Values

Symbol

R_MIN

R_MAX

R_DT

C_T

C_DT

Component

Min.

5

22

330

47

1

Max.

Units

MIN pin resistor value

MAX pin resistor value

DT pin resistor value

CT pin capacitor value

DT pin capacitor value

CR pin capacitor value

CD pin capacitor value

---

kΩ

---

pF

nF

C_R

C_D

1

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IRS2552D

Electrical Characteristics

V_BIAS(V_CC, V_BS) = 14 V, C_T= 1 nF and T_A= 25 °C unless otherwise specified. The input parameters are referenced to

COM. The V_Oand I_Oparameters are referenced to COM and are applicable to the respective output leads: HO or

LO.

Symbol

Low Voltage Supply Characteristics

V_CCUVRising V_CCundervoltage lockout threshold

Falling V_CCundervoltage lockout threshold

V_CCUVHYSV_CCundervoltage lockout hysteresis

Definition

Min

Typ

Max Units

Test Conditions

9.5

8.5

0.5

10.5

9.5

1

11.5

+

V_CCUV

V

N/A

10.5

1.5

-

V_CC= V_CCUV+

-100 mV rising

I_QCCUV

Micropower startup V_CCsupply current

Quiescent supply current

---

300

350

µA

R_MIN

MODE CT = 0 V

=

RUN

12 kΩ,

I_QCC

V_CC

V_CCsupply current

current @ f_osc= fMIN

---

4.0

0.9

4.5

1.3

I_QCCFLT

I_CC,FMIN

V_CLAMP

mA

V

Fault mode

R_MIN= 12 kΩ, RUN

V_CC

V_CCclamp voltage

---

4.7

5.3

MODE

I_CC= 19 mA

14.6

15.6

16.6

Floating Supply Characteristics

V_CC≤ V_CCUV-

_CC= V_BS

,

I_QBSUV

Micropower startup V_BSsupply current

---

6

20

µA

V

I_BS

V_BSsupply current

_BSsupply undervoltage positive going

---

1000 1200

HO oscillating

V

V_BSUV+

6.5

7.5

8.5

threshold

V

N/A

V_BSsupply undervoltage negative going

threshold

V_BSUV-

I_LK

6.0

---

7.0

---

8.0

50

Offset supply leakage current

V_B= V_S= 600 V

μA

Oscillator I/O Characteristics

R_MIN= 12 kΩ, RUN

f_MIN

Minimum oscillator frequency

Maximum oscillator frequency

36.5

67

39

69

42.5

71

MODE

kHz

R_MAX= 6.8 kΩ,

IGNITION MODE

f_MAX

V_CT+

V_CT-

Upper CT ramp voltage threshold

Lower CT ramp voltage threshold

4.8

---

5.0

0

5.2

---

V

N/A

R

_MIN=12 kΩ, RUN

I_CT

CT pin source current

350

410

470

μA

MODE

V_MIN

V_MAX

VMIN pin voltage

4.8

---

5.0

0

5.2

---

VMAX pin voltage

V

N/A

V_MIN,FLT

V_MAX,FLT

VMIN voltage in fault mode

VMAX voltage in fault mode

---

0

---

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IRS2552D

Electrical Characteristics

V_BIAS(V_CC, V_BS) = 14 V, C_T= 1 nF and T_A= 25 °C unless otherwise specified. The input parameters are referenced to

COM. The V_Oand I_Oparameters are referenced to COM and are applicable to the respective output leads: HO or

LO.

Symbol

Ignition

Definition

Min

Typ

Max

Units

Test Conditions

R

_MIN= 12 kΩ,

I_CR,IGN

Source current at CR pin in IGN mode

Ignition detection threshold

3.7

4.5

0.6

5.3

μA

IGNITION MODE

V_CS,IGN

0.57

0.63

V

N/A

Gate Driver Output Characteristics

V_OH

V_OL

High-level output voltage, V_BIAS– V_O

---

V_CC

---

V

I

_O= 0 A

Low-level output voltage, V

COM

O

mV

I

_O= 0 A,

V_OL,UV

UV-mode output voltage, V

---

COM

---

O

V_CC≤ V_CCUV-

t_R

t_F

Output rise time

Output fall time

---

80

45

150

100

ns

N/A

R_DT= 2.2 kΩ,

C_DT= 1 nF

t_D

Output deadtime (HO or LO)

1.0

1.1

1.2

μs

I_O+

I_O-

Output source current

Output sink current

---

300

450

---

mA

N/A

Bootstrap FET Characteristics

V_B,ONV_Bwhen the bootstrap FET is on

I_B,CAP

13.2

40

9

13.5

55

---

V

N/A

V_Bsource current when FET is on

mA

C_BS= 0.1 μF

V_B= 10 V

I_B,10V

12

Shutdown

V_SD,_TH

Shutdown threshold at SD pin

CD pin source current

1.9

3.7

4.8

2.0

4.5

5.0

2.1

5.3

5.2

V

μA

V

N/A

V_SD>V_SD,TH

,

I_CD,source

V_CD,TH

R_MIN= 12 kΩ

Threshold at which CD triggers shutdown

V_CC= 14 V

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IRS2552D

Electrical Characteristics

V_BIAS(V_CC, V_BS) = 14 V, C_T= 1 nF and T_A= 25 °C unless otherwise specified. The input parameters are

referenced to COM. The V_Oand I_Oparameters are referenced to COM and are applicable to the respective

output leads: HO or LO.

Symbol

Definition

Min

Typ

Max

Units

Test Conditions

Over-Current Compensation

V_CS,TH

Current compensation threshold at CS pin

1.15

3.7

1.21

4.5

1.27

5.3

V

N/A

V_CS>V_CS,TH

,

Source current at CD pin when the IC is in

current compensation mode

I_CD,OC

μA

R_MIN= 12 kΩ

Voltage on CD where duty cycle reaches

minimum

V_CD,oc

DC_MIN

4.8

---

5.0

5.2

---

V

N/A

V

_CD= 4.7 V,

Minimum HO duty cycle

10%

---

RUN MODE

Dimming

V_CR+

CR pin upper threshold voltage

CR pin lower threshold voltage

Source current at CR pin in RUN mode

4.8

---

5.0

0.2

5.2

---

V

N/A

V_CR-

I_CR,RUN

125

150

175

μA

R_MIN= 12 kΩ

C_R= 100 nF,

RUN MODE,

R_MIN= 12 kΩ

f_CR

Frequency at CR pin

240

310

370

Hz

Soft Start

V

_CR= 0 V,

DC_MIN

Minimum HO duty cycle

---

10%

---

V

_DIM< V_DIM,SS

V_CR,SS

V_DIM,SS

End of soft start voltage

0.88

---

0.96

4.8

1.04

---

V_DIM< V_DIM,SS

N/A

Soft start disable threshold

Enable

V_ENATH

Enable threshold

Enable hysteresis

1.9

---

2.2

2.5

---

V

N/A

V_ENAHYS

200

mV

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9

IRS2552D

Functional Block Diagram

12

CS

IMIN

ICD

ICR_IGN

ICR_RUN

0.6V

5V

1.21V

5

MIN

IGNITION

LOGIC

OVER

CURRENT

CONTROL

BAND

GAP

REF

IMAX

5V

6

MAX

SOFT

START

CONTROL

3

VBG

CT

S

Q

5V

0V

DUTY

CYCLE

CONTROL

R1

R2

DEAD TIME

CONTROL

EN

DT

4

16

15

14

VB

HO

VS

10

11

CD

SD

PULSE

FILTER &

LATCH

LEVEL

SHIFT

5V

2V

9

7

CR

BOOT

STRAP

DRIVE

Q

S

R

UV

DIM

1

VCC

LO

OUTPUT

LOGIC

13

5V

UV

UVLO

EN

15.6V

2

8

COM

ENA

0.2V

2.2V

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10

IRS2552D

Input/Output Pin Equivalent Circuit Diagrams: IRS2552D

VB

ESD

Diode

25V

HO

VCC

CT

ESD

Diode

ESD

Diode

VS

600V

R_ESD

ESD

Diode

VCC

ESD

Diode

COM

LO

25V

ESD

Diode

COM

VCC

ESD

Diode

MIN,

MAX

R_ESD

ESD

Diode

COM

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IRS2552D

Lead Definitions

Symbol

Description

Logic and internal gate drive supply voltage

VCC

COM

CT

IC power and signal ground

Oscillator timing capacitor

DT

Independent dead time R and C

RFMIN sets running frequency

RFMAX sets ignition mode frequency

MIN

MAX

DIM

ENA

CR

0 to 5 V DC burst mode dimming control input

Chip Enable (2 V logic threshold)

Burst dimming ramp

CD

Shutdown delay timing

SD

Open load detection

CS

Ignition detection (0.6 V threshold), over-current (1.2 V threshold)

Low side output

LO

VS

Half bridge

HO

VB

High side output

High side floating supply

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12

IRS2552D

Lead Assignments

VCC

COM

CT

VB

HO

VS

LO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DT

MIN

MAX

CS

SD

CD

DIM

ENA

CR

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IRS2552D

State Diagram^†

†

All values are typical. Applies to application circuit on page 1.

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14

IRS2552D

Application Information and Additional Details

Information regarding the following topics is included as subsections within this section of the datasheet.

•

IGBT/MOSFET Gate Drive

Undervoltage Lockout Protection

Oscillator

Deadtime

Ignition

Run Mode

Lamp Current Control

Frequency, Current and Deadtime Calculation

Dimming Function

Soft Start

PCB Layout Tips

Additional Documentation

IGBT/MOSFET Gate Drive

The IRS2552D HVICs are designed to drive up to two MOSFET or IGBT power devices. Figures 1 and 2 illustrate

several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to

drive the gate of the power switch, is defined as I_O. The voltage that drives the gate of the external power switch is

defined as V_HOfor the high-side power switch and V_LOfor the low-side power switch; this parameter is sometimes

generically called V_OUTand in this case does not differentiate between the high-side or low-side output voltage.

V_B

(or V_CC

)

I_O+

HO

(or LO)

+

V_HO(or V_LO)

-

V_S

(or COM)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

Undervoltage Lock-Out

The IRS2552D includes an under voltage lockout circuit such that it remains in micro-power mode until the

voltage at VCC pin exceeds the V_CCUV+threshold. When V_CCexceeds the V_CCUV+threshold the IRS2552D

oscillator starts up and gate drive signals appear at the LO and HO outputs, provided the ENABLE pin is

connected to a voltage source above V_ENATH. The LO output will always go high first in order to pre-charge the

bootstrap capacitor before the IRS2552D begins normal operation.

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IRS2552D

Oscillator

During UVLO and shutdown and the voltage at the MIN and MAX pins remain at 0 V. When V_CCis raised above

V_CCUV+the oscillator will start and LO and HO will produce output drive waveforms at frequency F_MAX. The MAX

pin sources 5 V and the resistance connected from this point to COM determines the C_Tcharging current and

consequently the frequency. R_MINis always connected from the MIN pin to COM, which sets the RUN mode

frequency. In IGNITION mode the MAX pin supplies 5 V to R_MAX, which is connected to COM setting a higher C_T

charging current and consequently a higher ignition frequency, as R_MAXis smaller than R_MIN. In RUN mode the

MAX pin is no longer active and the voltage will drop to 0V. C_Tcharges until the voltage reaches the 5 V

threshold and then it is discharged rapidly to V_CT-. It then begins to charge again, repeating this sequence and

producing a saw tooth waveform. The MIN pin sources 5 V during IGNITION and RUN modes. The current

flowing through F_MINto COM determines the charging current of C_Tduring RUN mode and also serves as a

current reference for the currents supplied from the CD and CR pins.

VCC

VCCUV+

CT

VCT+

VCT-

DT

1/3*VCC

LO

HO

Figure 3: Oscillator waveforms

Deadtime

In the IRS2552D the dead time is determined by an independent external timing circuit comprising of R_DTand

C_DTand is not affected by the values of C_T, R_MINor R_MAX. The DT pin voltage is held at COM when LO or HO is

high. C_DTis charged through R_DT, which is connected to VCC, when DT is internally disconnected from COM at

the start of the dead time. The dead time ends when C_DThas charged to 1/3 V_CC. This allows the dead time to

remain consistent over the working range of V_CC, i.e. from UVLO+ to the clamp voltage of 15.6 V.

Ignition

During the IGNITION phase the C_Rcapacitor is charged through an internal current source ICR_IGN. When C_R

reaches V_CR+then if the voltage at CS is greater than VCS_IGN, the IRS2552D will enter RUN mode. If the voltage

at the CS pin is less than VCS_IGNthe IRS2552D will enter FAULT mode whereby LO and HO will both go low and

the IRS2552D will shut down until V_CCis reduced below V_CCUV-and then increased above V_CCU+. The ignition

function is achieved by applying a frequency somewhat above resonance to the output step up transformer and

resonant load. This should develop sufficient voltage across the lamps to allow partial ignition and some arc

current to flow. The combined lamp current is fed back to the CS pin through a suitable isolating network to

determine whether the lamps have ignited successfully. If a successful ignition is detected after the voltage at C_R

has reached V_CR+then R_MAXis disconnected inside the IRS2552D and the frequency will switch immediately to

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16

IRS2552D

to F_MIN, therefore applying maximum power to the lamps. At this point the burst mode dimming function will be

enabled.

Run Mode

In RUN mode an additional current source ICR_RUN is also switched into the circuit. This causes C_Rto ramp up

to V_CR+much more rapidly than before. The C_Rpin is used to provide ignition timing as well as the burst mode

dimming low frequency ramp.

If the output is open circuit a very large voltage develops at the output. This is fed back to the SD pin through

some suitable isolated sensing network such that the voltage at the SD pin will exceed VSDTH during an over-

voltage condition. At this stage the capacitor C_Dbegins to charge through a current source. When VSD >

VSDTH the burst mode dimming function is disabled and the output will be continuous.

If the voltage at SD drops below VSDTH the capacitor C_Dwill be discharged to 0V again. If SD remains above

VSDTH long enough for the C_Dcapacitor voltage to reach VCDMAX or about 5 V then the IRS2552D will shut

down and go into fault mode.

Lamp Current Control

Additionally the half bridge current is monitored at the CS pin so that during running if too much power is

supplied to the lamps the IRS2552D is able to compensate by reducing the oscillator duty cycle while

maintaining the same run frequency. This prevents the lamps from being over driven preventing premature end

of life. When VCS > VCSTH the C_Dcapacitor will begin to charge and the CD pin voltage will rise. As this occurs

the duty cycle will begin to adjust, i.e. the HO on time will become gradually shorter and the LO on time will

become gradually longer. The dead time will remain constant at all times. In this way the power to the output will

be reduced while the frequency remains at f_MIN. As the CD voltage rises, the duty cycle will be further reduced. If

VCS then drops below VCSTH then the duty cycle will be regulated at that point and thus the current will be

maintained at this limit. If VCS remains above VCSTH then the voltage will continue to rise on C_Duntil it reaches

VCDMAX, at which point the duty cycle reaches its minimum limit DC_MINand the IRS2552D will enter FAULT

mode, requiring V_CCto fall below UVLO- and then rise above UVLO+ in order to re-start.

Frequency, Current, and Dead Time Calculation

The running frequency of the IRS2552D is given by the following formula:

1

f_MIN

=

2.09⋅C_T⋅ R_MIN

where V_MIN= 5 V, i.e. When the ignition ramp is complete and R_MAXhas no further effect on the oscillator.

The ignition frequency given by:

1

f_MAX

=

2.09⋅C_T⋅ R_MAX

and the dead time is calculated by:

t_DT= R_DT⋅C_DT⋅ln(1.5)

t_DT= 0.405⋅ R_DT⋅C_DT

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17

IRS2552D

Maximum duty cycle

DC_MAX= 0.5− (t_DT* f )

The ICR charging current during ignition mode and the ICD charging current are given by:

0.06

ICR_IGN

=

R_MIN

0.06

ICD =

R_MIN

The ICR charging current and frequency during run mode are given by:

1.8

ICR_RUN

=

R_MIN

0.36

R_MIN⋅C_CR

f_CR

=

Dimming Function

The IRS2552D supports burst mode dimming, meaning that the output drive to the lamps is pulsed on and off at

a low frequency and the burst duty cycle is adjusted to control the average current and therefore the light output

of the lamps. The IRS2552D contains a low frequency oscillator that generates a ramp waveform at the CR pin

from 0 V to 5 V. The ramp frequency is dependent on the value of the external C_Rcapacitor. A DC dimming

control voltage is fed into the DIM pin which is compared with the dimming ramp by means of an internal

comparator, which generates the PWM signal that is used internally to switch the outputs on and off. Thus when

the DIM voltage is at 5 V the outputs will be on all of the time and when it is at 0 V the outputs will be off all of the

time. Alternatively a PWM dimming control signal from 0 V to 5 V can be fed directly into the DIM pin to allow

external PWM control independent of the dimming ramp. During the off period the LO and HO outputs are both

low.

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18

IRS2552D

5V

DIM

CR

1V

0.2V

Soft Start

LO

HO

Duty cycle

increases from 10%

to 50%

Figure 4: Dimming waveform

RUN MODE

ICCRUN charges CR up to VCR+. CR oscillates at fCR (sawtooth)

Half-bridge oscillates at FMIN. VDC reset to 0V

SOFT START

ON

OFF

DC increases from DC

min to DC max

DC=DCmax

DC=0

VDIM <VCRSS

VCR<VCRSS

VCR>VDIM

VCRSS <VDIM<VDIMSS

VDIM>VDIMSS

VCR<VDIM

Soft start

In addition the IRS2552D includes a soft start function that operates at the start of each burst, during dimming

operation when VDIM < VDIM_SS. The soft start will operate during the portion of the dimming ramp CR at the

start of each burst from CR = 0 V to CR = VCR_SS. When VCR = 0 the duty cycle will be at minimum (DCMIN) and

will linearly increase to 50% (minus the dead time) when VCR reaches VCR_SS. This function is enabled only in

RUN mode and allows inrush currents to be eliminated during burst mode dimming, while always maintaining the

frequency at F_MIN

.

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19

IRS2552D

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to the

floating voltage pins (V_Band V_S) near the respective high voltage portions of the device.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 5).

In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must

be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-

to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage

across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 5: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand V_SSpins. A ceramic

1 μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to

the pins in order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients as

the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,

it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side

emitter to negative bus rail stray inductance. However, where negative V_Sspikes remain excessive, further steps

may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the V_Spin and the switch

node (see Figure 6), and in some cases using a clamping diode between V_SSand V_S(see Figure 7). See DT04-4 at

www.irf.com for more detailed information.

www.irf.com

20

IRS2552D

Figure 6: V_Sresistor

Figure 7: V_Sclamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search

function and the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

www.irf.com

21

IRS2552D

Programmable parameter characteristics

Figure 7 to 12 provide the characteristics of the programmable parameters as a function of the value of the

programming components.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

5

10 15 20 25 30 35 40 45 50

RMIN(k

0

300

600

900

1200

1500

)

Ω

CT(pF)

RMIN, RMAX=12.1K

Figure 7: FMIN, FMAX vs. CT

Figure 8: FMIN vs. RMIN

2000

100

90

80

70

60

50

40

30

20

10

0

1600

1200

800

400

0

5

10 15 20 25 30 35 40 45 50

RMAX(k

0

400

800

1200

1600

2000

)

Ω

CDT(pF)

RDT=2.21K

Figure 9: FMAX vs. RMAX

Figure 10: DT vs. CDT

100

90

80

70

60

50

40

30

20

10

0

3000

2500

2000

1500

1000

500

0

1

2

3

4

5

6

7

0

500 1000 1500 2000 2500 3000 3500

CR(pF)

RDT(K

)

Ω

Figure 11: DT vs. RDT

Figure 12: FCR vs. CR

www.irf.com

22

Parameter characteristics

Figure 13 to 18 provide the characteristics of the main parameters as a function of VCC or the oscillator

frequency

6

5

4

3

2

1

0

20

16

12

8

4

0

2

4

6

8

10 12 14 16

9

9.2

9.4

9.6

9.8

10

10.2

VCC(V)

Figure 13: ICC vs. VCC

Figure 14: IQCC vs. VCC (VCC raising and falling

2

1.75

1.5

80

70

60

50

40

30

20

10

0

FMAX

FMIN

1.25

1

0.75

0.5

0.25

0

10

11

12

13

14

15

16

10

11

12

13

14

15

16

VCC(V)

RMIN=12.1K, RNAX=6.81K

Figure15: FMIN, FMAX vs. VCC

Figure 16: td vs. VCC

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

30

34

38

42

46

50

30

34

38

42

46

50

FMIN(kHz)

FMAX(kHz)

Figure 17: ICC RUN vs. FMIN

Figure 18: ICC FMAX vs. FMAX

www.irf.com

23

IRS2552D

Parameter Temperature Trends

Figures 38-58 provide the characteristics of the main parameters over temperature based on three temperatures (-

40 ºC, 25 ºC, and 125 ºC) average testing.

350

300

250

200

150

100

50

11.5

11

10.5

10

VCCUV+

9.5

9

VCCUV-

8.5

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 19: VCCUV vs. temperature

Figure 20: IQCCUV vs. temperature

5.5

5

4

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3

4.5

4

3.5

3

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 21: IQCC vs. temperature

Figure 22: ICC,FMIN vs. temperature

www.irf.com

24

IRS2552D

8.5

8

16.6

16.1

15.6

15.1

14.6

VBSUV+

VBSUV-

7.5

7

6.5

6

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 23: VCLAMP vs. temperature

Figure 24: VBSUV vs. temperature

71

42.5

41.5

40.5

39.5

38.5

37.5

36.5

70.5

70

69.5

69

68.5

68

67.5

67

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (C)

Figure 25: fMIN vs. temperature

Figure 26: fMAX vs. temperature

5.2

5.15

5.1

5.2

5.15

5.1

5.05

5

5.05

5

4.95

4.9

4.95

4.9

4.85

4.8

4.85

4.8

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (C)

Figure 27: V_MINvs. temperature

Figure 28: VMAX vs. temperature

www.irf.com

25

IRS2552D

630

620

610

600

590

580

570

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 29: I_CR,IGNvs. temperature

Figure 30: V_cs,ignvs. temperature

14

13.9

13.8

13.7

13.6

13.5

13.4

13.3

13.2

13.1

13

1.2

1.18

1.16

1.14

1.12

1.1

1.08

1.06

1.04

1.02

1

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (C)

Figure 31: t_Dvs. temperature

Figure 32: V_B,ONvs. temperature

20

18

16

14

12

10

8

90

80

70

60

50

40

30

20

10

0

6

4

2

0

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (C)

Figure 33: I_B,CAPvs. temperature

Figure 34: I_B,10Vvs. temperature

www.irf.com

26

IRS2552D

2.1

2.05

2

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

1.95

1.9

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 35: V_SD,THvs. temperature

Figure 36: V_CD,SOURCEvs. temperature

1.27

1.25

1.23

1.21

1.19

1.17

1.15

5.2

5.15

5.1

5.05

5

4.95

4.9

4.85

4.8

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 37: V_CD,THvs. temperature

Figure 38: V_CDSTHvs. temperature

5.2

5.15

5.1

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

5.05

5

4.95

4.9

4.85

4.8

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 39: I_CD,OCvs. temperature

Figure 40: V_CD,OCvs. temperature

www.irf.com

27

IRS2552D

14

12

10

8

360

340

320

300

280

260

240

6

4

2

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Figure 41: DC_MINvs. temperature

Figure 42: f_CRvs. temperature

5

1040

1020

1000

980

4.95

4.9

4.85

4.8

960

4.75

4.7

940

4.65

4.6

920

900

4.55

4.5

880

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (C)

Figure 43: V_CR,SSvs. temperature

Figure 44: V_DIM,SSvs. temperature

1.2

1.1

1

2.5

2.4

2.3

2.2

2.1

2

ENATH+

ENATH-

0.9

0.8

0.7

0.6

0.5

1.9

1.8

1.7

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (C)

Figure 45: V_ENAvs. temperature

Figure 46: IBS vs. temperature

www.irf.com

28

IRS2552D

Package Details: PDIP16 and S016N

www.irf.com

29

IRS2552D

Package Details: SOIC16N, Tape and Reel

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 16SOICN

Metric

Imperial

Min

Code

A

B

C

D

E

F

G

H

Min

7.90

3.90

15.70

7.40

6.40

10.20

1.50

Max

8.10

4.10

16.30

7.60

6.60

10.40

n/a

Max

0.318

0.161

0.641

0.299

0.260

0.409

n/a

0.311

0.153

0.618

0.291

0.252

0.402

0.059

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 16SOICN

Metric

Imperial

Code

A

B

C

D

E

F

G

H

Min

329.60

20.95

12.80

1.95

98.00

n/a

18.50

16.40

Max

330.25

21.45

13.20

2.45

102.00

22.40

21.10

18.40

Min

12.976

0.824

0.503

0.767

3.858

n/a

Max

13.001

0.844

0.519

0.096

4.015

0.881

0.830

0.724

0.728

0.645

www.irf.com

30

IRS2552D

Part Marking Information

www.irf.com

31

IRS2552D

Ordering Information

Base Part Number

IRS2552D

Standard Pack

Package Type

Complete Part Number

Form

Quantity

PDIP16

Tube/Bulk

25

45

IRS2552DPBF

IRS2552DSPBF

IRS2552DSTRPBF

Tube/Bulk

SOIC16N

Tape and Reel

2500

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for

the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other

rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or

patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document

supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

32


型号：	IRS2552D
厂家：	Infineon
描述：	CCFL/EEFL BALLAST CONTROLLER IC CCFL / EEFL镇流器控制器IC 控制器
文件：	总32页 (文件大小：770K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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