IRS26072D [INFINEON]
HIGH AND LOW SIDE DRIVER; 高端和低端驱动器型号: | IRS26072D |
厂家: | Infineon |
描述: | HIGH AND LOW SIDE DRIVER |
文件: | 总28页 (文件大小:1055K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet No. PD 97408A
August 18, 2009
IRS26072DSPbF
HIGH AND LOW SIDE DRIVER
Product Summary
Features
•
Floating channel designed for bootstrap operation
Integrated bootstrap diode suitable for Complimentary
PWM switching schemes only
Topology
high and low side driver
≤ 600 V
•
VOFFSET
•
•
IRS26072DSPBF is suitable for sinusoidal motor control
applications
VOUT
10 V – 20 V
IRS26072DSPBF is NOT recommended for
Trapezoidal motor control applications
Fully operational to 600 V
Io+ & I o- (typical)
tON & tOFF (typical)
200 mA & 350 mA
200 ns
•
•
•
•
•
•
•
•
•
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V
Under-Voltage lockout for both channels
3.3 V, 5 V, and 15 V input logic compatible
Matched propagation delay for both channels
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs
Package Options
RoHS compliant
8-Lead SOIC
Typical Applications
•
•
•
•
Motor Control
Air Conditioners/ Washing Machines
General Purpose Inverters
Micro/Mini Inverter Drivers
Typical Connection Diagram
Up to600 V
Vcc
HIN
Vcc
VB
HO
HIN
LIN
TO
LOAD
VS
LO
LIN
COM
IRS26072D
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1
© 2009 International Rectifier
IRS26072DSPbF
Table of Contents
Page
3
Description
Simplified Block Diagram
Typical Application Diagram
Qualification Information
Absolute Maximum Ratings
Recommended Operating Conditions
Static Electrical Characteristics
Dynamic Electrical Characteristics
Functional Block Diagram
Input/Output Pin Equivalent Circuit Diagram
Lead Definitions
3
4
5
6
6
7
7
8
9
10
10
11
21
25
26
27
28
Lead Assignments
Application Information and Additional Details
Parameter Temperature Trends
Package Details
Tape and Reel Details
Part Marking Information
Ordering Information
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IRS26072DSPbF
Description
The IRS26072D is a high voltage, high speed power MOSFET and IGBT driver with independent high and low
side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized
monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V. The output
drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The floating
channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up to 600 V.
Simplified Block Diagram
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IRS26072DSPbF
Typical Application Diagram
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IRS26072DSPbF
Qualification Information†
Qualification Level
Industrial††
Comments: This IC has passed JEDEC industrial
qualification. IR consumer qualification level is granted by
extension of the higher Industrial level.
MSL2 , 260°C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
Class 2
(per JEDEC standard JESD22-A114)
Class B
Human Body Model
Machine Model
ESD
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
IC Latch-Up Test
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
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IRS26072DSPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and
power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB
VS
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
-0.3
620
VB - 20†
VS - 0.3
-0.3
VB + 0.3
VB + 0.3
20†
VCC + 0.3
VCC + 0.3
—
VHO
V
VCC
VLO
-0.3
VIN
Logic and analog input voltages
High-side input pulse width
-0.3
PWHIN
dVS/dt
500
ns
Allowable offset supply voltage slew rate
—
50
V/ns
PD
—
0.625
W
Package power dissipation @ TA +25°C
RthJA
TJ
Thermal resistance, junction to ambient
Junction temperature
—
—
200
150
150
°C/W
TS
Storage temperature
-50
°C
TL
Lead temperature (soldering, 10 seconds)
—
300
†
All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply.
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to COM unless otherwise specified. The VS offset ratings are tested with all supplies
biased at 15 V.
Symbol
Definition
Min.
Max.
Units
VB
VS
High side floating supply voltage
Static high side floating supply offset voltage†
Transient high side floating supply offset voltage††
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
VS +10
-8
VS + 20
600
600
VB
VS(t)
VHO
VCC
VLO
VIN
-50
VS
V
10
20
0
VCC
VCC
125
Logic input voltage
0
TA
Ambient temperature
-40
°C
†
V
V
Logic operation for S of –8 V to 600 V. Logic state held for S of –8 V to –VBS.
†† Operational for transient negative VS of -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the
Application Information section of this datasheet for more details.
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IRS26072DSPbF
Static Electrical Characteristics
(VCC-COM) = (VB-VS) = 15 V and TA = 25 oC unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to COM and VS and are applicable to the output leads LO and
HO respectively. The
and
parameters are referenced to COM and VS respectively.
VCCUV
VBSUV
Symbol
Definition
Min. Typ. Max. Units
Test Conditions
VIH
VIL
Logic “1” input voltage
2.5
—
—
—
—
—
—
—
—
0.8
—
Logic “0” input voltage
VIN,TH+
VIN,TH-
VOH
Input positive going threshold
Input negative going threshold
High level output voltage
Low level output voltage
1.9
1
—
0.8
0.2
1.4
0.6
IO = 20 mA
V
VOL
VCCUV+
VBSUV+
VCCUV-
VBSUV-
VCCUVH
VBSUVH
VCC and VBS supply under-voltage positive
going threshold
8.0
6.9
8.9
7.7
1.2
9.8
8.5
—
VCC and VBS supply under-voltage negative
going threshold
VCC and VBS supply under-voltage hysteresis
0.35
ILK
IQBS
IQCC
IIN+
IIN-
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
Logic “1” input bias current
—
—
1
50
70
1.8
20
2
VB =VS = 600 V
VIN = 0 V or 5 V
µA
mA
µA
45
—
1.1
5
—
VIN = 5 V
VIN = 0 V
Logic “0” input bias current
—
—
Io+
Output high short circuit pulsed current
Output low short circuit pulsed current
Bootstrap resistance ††
120
250
—
200
350
200
—
—
—
VO = 0 V or 15 V
PW ≤ 10 µs
mA
Io-
RBS
Ω
††
Integrated bootstrap diode is suitable for Complimentary PWM schemes only. IRS26072D is suitable for
sinusoidal motor control applications. IRS26072D is NOT recommended for Trapezoidal motor control
applications.
Refer to the Integrated Bootstrap Functionality section of this datasheet for more details.
Dynamic Electrical Characteristics
VCC = VB = 15 V, VS = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Test Conditions
VIN = 0V and 5V
PW input =10µs
ton
toff
tr
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
100
100
—
200
200
150
50
300
300
220
80
ns
tf
Turn-off fall time
—
MT
PM
ton, toff propagation delay matching time
PW pulse width distortion†
—
—
50
—
—
75
†
PM is defined as PWIN - PWOUT.
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IRS26072DSPbF
Functional Block Diagram
VB
UV
DETECT
R
HO
R
Q
HV
LEVEL
SHIFTER
PULSE
FILTER
S
HIN
PULSE
GENERATOR
VS
Integrated BS
DIODE
VCC
UV
DETECT
LO
DELAY
LIN
COM
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IRS26072DSPbF
Input/Output Pin Equivalent Circuit Diagrams
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IRS26072DSPbF
Lead Definitions
Symbol
Description
VCC
VB
Low side and logic power supply
High side floating power supply
High side floating supply return
VS
HIN
LIN
HO
Logic input for high side gate driver output HO, input is in-phase with output
Logic input for low side gate driver output LO, input is in-phase with output
High side gate driver output
LO
Low side gate driver output
COM
Low side supply return
Lead Assignments
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IRS26072DSPbF
Application Information and Additional Details
•
•
•
•
•
•
•
•
•
•
•
IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Matched Propagation Delays
Input Logic Compatibility
Under-Voltage Lockout Protection
Truth Table: Under-Voltage lockout
Integrated Bootstrap Functionality
Bootstrap Power Supply Design
Tolerant to Negative VS Transients
PCB Layout Tips
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS26072D HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and
2 show the definition of some of the relevant parameters associated with the gate driver output functionality. The
output current that drives the gate of the external power switches is defined as IO. The output voltage that drives
the gate of the external power switches is defined as VHO for the high side and VLO for the low side; this parameter
is sometimes generically called VOUT and in this case the high side and low side output voltages are not
differentiated.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
HO
(or LO)
+
IO-
VHO (or VLO)
-
VS
(or COM)
VS
(or COM)
Figure 1: HVIC sourcing current
Figure 2: HVIC sinking current
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IRS26072DSPbF
Switching and Timing Relationships
The relationship between the input and output signals of the IRS26072D HVIC is shown in Figure 3. The
definitions of some of the relevant parameters associated with the gate driver input to output transmission are
given.
LIN
or HIN
50%
50%
PW
IN
tOFF tF
90%
tON tR
PW
OUT
90%
10%
LO
or HO
10%
Figure 3: Switching time waveforms
During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at the
same time; correspondingly, the high and low side signals HO and LO turn on simultaneously.
Figure 4: Input/output timing diagram
Matched Propagation Delays
The IRS26072D HVIC is designed for propagation delay matching. With this feature, the input to output
propagation delays tON, tOFF are the same for the low side and the high side channels; the maximum difference
being specified by the delay matching parameter MT as defined in Figure 6.
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IRS26072DSPbF
Figure 6: Delay Matching Waveform Definition
Input Logic Compatibility
The IRS26072D HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5
V logic level signals. Figure 7 shows how an input signal is logically interpreted.
Figure 7: HIN & LIN input thresholds
Under-Voltage Lockout Protection
The IRS26072D HVIC provides under-voltage lockout protection on both the VCC low side and logic fixed power
supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the VCC (or
VBS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or
exited.
Upon power up, should the VCC voltage fail to reach the VCCUV+ threshold, the gate driver outputs LO and HO will
remain disabled. Additionally, if the VCC voltage decreases below the VCCUV- threshold during normal operation, the
under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO.
Upon power up, should the VBS voltage fail to reach the VBSUV threshold, the gate driver output HO will remain
disabled. Additionally, if the VBS voltage decreases below the VBSUV threshold during normal operation, the under-
voltage lockout circuitry will shutdown the high side gate driver output HO.
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IRS26072DSPbF
The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage
sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven
with a low voltage, which would result in power switches conducting current while with a high channel impedance,
which would produce very high conduction losses possibly leading to power device failure.
VCC
(or VBS
)
VCCUV +
(or VBSUV +
)
VCCUV
(or VBSUV -
-
)
Time
UVLO Protection
(Gate Driver Outputs Disabled)
Normal
Operation
Normal
Operation
Figure 8: UVLO protection
Truth Table: Under-Voltage lockout
Table 2 provides the truth table for the IRS26072D HVIC.
The 1st line shows that for VCC below the UVLO threshold both the gate driver outputs LO and HO are disabled.
fter V returns above , the gate driver outputs return functional.
CC
A
VCCUV
The 2nd line shows that for VBS below the UVLO threshold, the gate driver output HO is disabled. After VBS returns
above , HO remains low until a new rising transition of HIN is received.
VBSUV
The last line shows the normal operation of the HVIC.
outputs
LO
VCC
VBS
HO
<
UVLO VCC
UVLO VBS
0
0
0
VCCUV
<
15 V
15 V
LIN
LIN
VBSUV
15 V
Normal operation
HIN
Table 2: UVLO truth table
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IRS26072DSPbF
Integrated Bootstrap Functionality
The IRS26072D HVIC embeds an integrated bootstrap FET that eliminates the need of external bootstrap diodes
and resistors allowing an alternative drive of the bootstrap supply for a wide range of applications.
A bootstrap FET is connected between the high side floating power supply VB and the low side and logic fixed
power supply VCC (see Fig. 9).
Bootstrap FET
VCC
VB
Figure 9: Simplified Bootstrap FET connection
The bootstrap FET is suitable for complimentary PWM switching schemes only. Complimentary PWM refers to
PWM schemes where the HIN & LIN input signals are alternately switched on and off. IRS26072D is suitable for
sinusoidal motor control and the integrated bootstrap feature can be used either in parallel with the external
bootstrap network (diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a
replacement of the external bootstrap network may have some limitations at very high PWM duty cycle,
corresponding to very short LIN pulses, due to the bootstrap FET equivalent resistance RBS. IRS26072D is NOT
recommended for trapezoidal motor control, even if an external bootstrap network is employed in parallel.
The bootstrap FET is conditioned as follows:
bootstrap turns-off (immediately) or stays off when either:
•
-
-
HO goes/stays high;
VB goes/ stays high (> 1.1*VCC);
•
bootstrap turns-on when:
-
-
LO is high (low side is on) AND VB is low (<1.1*VCC);
LO and HO are low after a transition of LIN from high to low AND VB goes low (<1.1*VCC) before
a fixed time of 20us;
-
LO and HO are low after a transition of HIN from high to low AND VB goes low (<1.1*VCC) before
a re-triggerable time of 20us. In this case the time counter is kept in reset state until VB goes
high (>1.1VCC).
In Figure 10 the BootFET timing diagram details are represented.
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IRS26072DSPbF
20 us timer
counter
Timer is reset
Timer expired
Timer is reset
HIN
LIN
BootStrap
Fet
VB
+
-
1.1*Vcc
Figure 10: BootFET timing diagram
Bootstrap Power Supply Design
For information related to the design of the bootstrap power supply while using the integrated bootstrap
functionality of the IRS26072D, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network
Analysis: Focusing on the Integrated Bootstrap Functionality.” This application note is available at www.irf.com.
For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode)
please refer to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is
available at www.irf.com.
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IRS26072DSPbF
Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power devices switch on and off quickly while carrying a large current. A typical 3-phase inverter
circuit is shown in Figure 11; where we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 12 and 13) switches off, while the U phase current is flowing
to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the
low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC
bus voltage to the negative DC bus voltage.
Figure 11: Three phase inverter
DC+ BUS
Q1
ON
IU
VS1
D2
Q2
OFF
DC- BUS
Figure 12: Q1 conducting
Figure 13: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 14 and 15), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
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IRS26072DSPbF
Figure 14: D3 conducting
Figure 15: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 16 depicts one leg of the three phase inverter; Figures 17 and 18 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit
from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side
switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic
elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-
side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This
current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative
voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS
pin).
Figure 16: Parasitic Elements
Figure 17: VS positive
Figure 18: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is
greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the IRS26072D’s robustness can be seen in Figure 19, where there is represented
the IRS26072D Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient
voltage falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional
anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA.
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IRS26072DSPbF
At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will
hold by design the high-side outputs in the off state for 4.5 µs.
Figure 19: Negative VS transient SOA @ VBS=15V
Even though the IRS26072D has been shown able to handle these large negative VS transient conditions, it is
highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
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IRS26072DSPbF
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to
the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case
Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
20). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
IGC
VB
(or VCC)
CGC
G
R
HO
(or LO )
Gate Drive
VGE
Loop
VS
(or COM)
Figure 20: Antenna Loops
Supply Capacitor: It is recommended to place a bypass capacitor between the VCC and COM pins. This
connection is shown in Figure 21. A ceramic 1 µF ceramic capacitor is suitable for most applications. This
component should be placed as close as possible to the pins in order to reduce parasitic elements.
Up to 600V
Vcc
Vcc
HIN1,2,3
LIN1,2,3
V
B1,2,3
HIN1,2,3
LIN1,2,3
HO1,2,3
V
S1,2,3
TO
LOAD
LO1,2,3
COM
GND
Figure 21: Supply capacitor
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IRS26072DSPbF
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at
the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such
conditions, it is recommended to 1) minimize the high-side source to low-side collector distance, and 2) minimize
the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive,
further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin
and the switch node (see Figure 22), and in some cases using a clamping diode between COM and VS (see
Figure 23). See DT04-4 at www.irf.com for more detailed information.
DC+ BUS
DC+ BUS
VB
VB
CBS
CBS
HO
VS
LO
HO
VS
RVS
RVS
To
Load
To
Load
DVS
LO
COM
COM
DC- BUS
DC- BUS
Figure 22: VS resistor
Figure 23: VS clamping diode
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
Parameter Temperature Trends
Figures 24-41 provide information on the experimental performance of the IRS26072D HVIC. The line plotted
in each figure is generated from actual experimental data. A small number of individual samples were tested
at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line
labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood temperature trend. The individual data points on the curve
were determined by calculating the averaged experimental value of the parameter (for a given temperature).
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IRS26072DSPbF
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 24. Turn-on Propagation Delay vs. Temperature
Fig. 25. Turn-off Propagation Delay vs. Temperature
200
180
160
140
120
100
80
60
50
40
30
Exp.
Exp.
20
60
40
20
0
10
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 26. Turn-on Rise Time vs. Temperature
Fig.27. Turn-off Fall Time vs. Temperature
2.5
450
400
350
300
250
200
150
100
50
Exp.
2.0
1.5
1.0
0.5
0.0
Exp.
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 28. Input Negative Going Threshold vs. Temperature
Fig. 29. Low Level Output Voltage vs. Temperature
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IRS26072DSPbF
60
50
40
30
20
10
0
12
10
8
Exp.
6
4
2
Exp.
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 30. Offset Supply Leakage Current vs. Temperature
Fig. 31. Quiescent VCC Supply Current vs. Temperature
7
6
80
70
60
50
Exp.
5
4
3
2
1
0
Exp.
40
30
20
10
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 32. Quiescent VCC Supply Current vs. Temperature
Fig. 33. Quiescent VBS Supply Current vs. Temperature
80
70
60
50
9.6
9.4
9.2
9.0
8.8
Exp.
40
8.6
Exp.
30
20
10
0
8.4
8.2
8.0
7.8
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 34. Quiescent VBS Supply Current vs. Temperature
Fig. 35. VCC Supply Under-voltage Negative Going
Threshold vs. Temperature
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IRS26072DSPbF
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
9.0
8.5
8.0
7.5
7.0
6.5
6.0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 36. VCC Supply Under-voltage Positive Going
Threshold vs. Temperature
Fig. 37. VBS Supply Under-voltage Negative Going
Threshold vs. Temperature
9.5
0
-50
-25
0
25
50
75
100
125
-50
-100
-150
-200
-250
-300
-350
-400
-450
9.0
8.5
Exp.
8.0
7.5
7.0
6.5
6.0
Exp.
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 38. VBS Supply Under-voltage Positive Going
Threshold vs. Temperature
Fig. 39. Output High Short Circuit Pulsed Current vs.
Temperature
706
0
-50
-25
0
25
50
75
100
125
Exp.
606
-2
-4
506
406
306
206
106
6
-6
-8
Exp.
-10
-12
-14
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 41. Max –Vs vs. Temperature
Fig. 40. Output Low Short Circuit Pulsed Current vs.
Temperature
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© 2009 International Rectifier
24
IRS26072DSPbF
Package Details
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© 2009 International Rectifier
25
IRS26072DSPbF
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Min
0.311
0.153
0.46
Code
A
B
C
D
E
F
G
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.214
0.248
0.200
0.059
0.059
H
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Max
Code
A
B
C
D
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
Min
12.976
0.824
0.503
0.767
3.858
n/a
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
E
F
G
98.00
n/a
14.50
12.40
102.00
18.40
17.10
14.40
0.570
0.488
H
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© 2009 International Rectifier
26
IRS26072DSPbF
Part Marking Information
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© 2009 International Rectifier
27
IRS26072DSPbF
Ordering Information
Standard Pack
Base Part Number
Package Type
Complete Part Number
Form
Quantity
XXX
Tube/Bulk
IRS26072D SPBF
SOIC 8
IRS26072D
Tape and Reel
XXX
IRS26072D STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the
consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third
parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International
Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information
previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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© 2009 International Rectifier
28
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