IRU1015CDTR [INFINEON]
Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSSO2, PLASTIC, TO-252, DPAK-3;
| 型号： | IRU1015CDTR |
| 厂家： | 
Infineon |
| 描述： | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSSO2, PLASTIC, TO-252, DPAK-3 |
| 文件： | 总11页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94122
IRU1015
1.5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
DESCRIPTION
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
The IRU1015 is a low dropout three-terminal adjustable
regulator with minimum of 1.5A output current capabil-
ity. This product is specifically designed to provide well
regulated supply for low voltage IC applications such as
486DX4 processor, P55Cä I/O supply as well as high
speed bus termination and low current 3.3V logic sup-
ply. The IRU1015 is also well suited for other applica-
tions such as VGA and sound card. The IRU1015 is
guaranteed to have <1.3V dropout at full load current
making it ideal to provide well regulated outputs of 2.5V
to 3.3V with 4.75V to 7V input supply.
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
486DX4 Supply Voltage
P55 I/O Supply Voltage
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1
1500uF
V
IN
3
2
1
V
OUT
3.3V / 1.5A
IRU1015
R1
121
C2
1500uF
R2
200
Adj
Figure 1 - Typical application of IRU1015 in a 5V to 3.3V regulator.
Note:P55C is trademark of Intel Corp.
PACKAGE ORDER INFORMATION
TJ (°C)
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1015CD
3-PIN PLASTIC
TO-263 (M)
IRU1015CM
3-PIN PLASTIC
TO-220 (T)
0 To 150
IRU1015CT
Rev. 1.3
08/20/02
www.irf.com
1
IRU1015
ABSOLUTE MAXIMUM RATINGS
Input Voltage (VIN) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak)
3-PIN PLASTIC TO-263 (M)
3-PIN PLASTIC TO-220 (T)
FRONT VIEW
FRONT VIEW
FRONT VIEW
3
3
2
1
Tab is
VOUT
3
2
1
V
IN
V
IN
VIN
Tab is
VOUT
Tab is
VOUT
VOUT
VOUT
1
Adj
Adj
Adj
qJA=70°C/W for 0.5" Square pad
qJA=35°C/W for 1" Square pad
qJT=2.7°C/W qJA=60°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over CIN=1µF, COUT=10µF, and TJ=0 to 1508C.
Typical values refer to TJ=258C.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Reference Voltage
VREF Io=10mA, TJ=258C, (VIN-Vo)=1.5V
Io=10mA, (VIN-Vo)=1.5V
1.238 1.250 1.262
1.225 1.250 1.275
V
Line Regulation
Io=10mA, 1.3V<(VIN-Vo)<7V
VIN=3.3V, VADJ=0, 10mA<Io<1.5A
∆VO Note 2, Io=1.5A
0.2
0.4
1.3
%
%
V
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
1.1
VIN=3.3V, ∆Vo=100mV
VIN=3.3V, VADJ=0V
30ms Pulse, VIN-Vo=3V, Io=1.5A
f=120Hz, Co=25µF Tantalum,
Io=0.75A, VIN-Vo=3V
1.6
60
A
mA
%/W
5
0.01
10
0.02
70
dB
Adjust Pin Current
IADJ
Io=10mA, VIN-Vo=1.5V, TJ=258C,
Io=10mA, VIN-Vo=1.5V
55
0.2
0.5
120
5
µA
µA
%
Adjust Pin Current Change
Temperature Stability
Long Term Stability
Io=10mA, VIN-Vo=1.5V, TJ=258C
VIN=3.3V, VADJ=0V, Io=10mA
TJ=1258C, 1000Hrs
0.3
1
%
RMS Output Noise
TJ=258C, 10Hz<f<10KHz
0.003
%VO
Note 1: Low duty cycle pulse testing with Kelvin con- Note 3: Minimum load current is defined as the mini-
nections is required in order to maintain accurate data. mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
Note 2: Dropout voltage is defined as the minimum dif- dividers are selected such that it automatically main-
ferential voltage between VIN and VOUT required to main-
tain regulation at VOUT. It is measured when the output
voltage drops 1% below its nominal value.
tains this current.
Rev. 1.3
08/20/02
www.irf.com
2
IRU1015
PIN DESCRIPTIONS
PIN # PIN SYMBOL
PIN DESCRIPTION
1
2
Adj
A resistor divider from this pin to the VOUT pin and ground sets the output voltage.
VOUT
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
3
VIN
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than VOUT
in order for the device to regulate properly.
BLOCK DIAGRAM
VIN 3
2 VOUT
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
Figure 2 - Simplified block diagram of the IRU1015.
APPLICATION INFORMATION
Introduction
The IRU1015 adjustable Low Dropout (LDO) regulator is sors is the need to switch the load current from zero to
a three-terminal device which can easily be programmed full load in tens of nanoseconds at their pins, which
with the addition of two external resistors to any volt- translates to an approximately 300 to 500ns current step
ages within the range of 1.25 to 5.5 V.This regulator un- at the regulator. In addition, the output voltage toler-
like the first generation of the three-terminal regulators ances are sometimes tight and they include the tran-
such as LM117 that required 3V differential between the sient response as part of the specification.
input and the regulated output, only needs 1.3V differen-
tial to maintain output regulation. This is a key require- The IRU1015 is specifically designed to meet the fast
ment for today’s microprocessors that need typically current transient needs as well as provide an accurate
3.3V supply and are often generated from the 5V sup- initial voltage, reducing the overall system cost with the
ply. Another major requirement of these microproces- need for fewer output capacitors.
Rev. 1.3
08/20/02
www.irf.com
3
IRU1015
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+
R2/R1),or the effective resistance will be RP(eff)=RP×(1+
R2/R1). It is important to note that for high current appli-
cations, this can represent a significant percentage of
the overall load regulation and one must keep the path
from the regulator to the load as short as possible to
minimize this effect.
Output Voltage Setting
The IRU1015 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R2
R1
VOUT = VREF× 1+
+IADJ×R2
( )
Where:
PARASITIC LINE
RESISTANCE
VREF = 1.25V Typically
IADJ = 50µA Typically
R1 and R2 as shown in Figure 3:
R
P
VOUT
VIN
VIN
IRU1015
VOUT
VIN
VIN
VOUT
Adj
RL
R1
R2
IRU1015
Adj
VREF
R 1
R 2
IADJ = 50uA
Figure 4 - Schematic showing connection
for best load regulation.
Figure 3 - Typical application of the IRU1015
for programming the output voltage.
Stability
The IRU1015 keeps a constant 1.25V between the out- The IRU1015 requires the use of an output capacitor as
put pin and the adjust pin. By placing a resistor R1 across part of the frequency compensation in order to make the
these two pins a constant current flows through R1, add- regulator stable. Typical designs for microprocessor ap-
ing to the IADJ current and into the R2 resistor producing plications use standard electrolytic capacitors with a
a voltage equal to the (1.25/R1)×R2 + IADJ×R2 which typical ESR in the range of 50 to 100mΩ and an output
will be added to the 1.25V to set the output voltage. This capacitance of 500 to 1000µF. Fortunately as the ca-
is summarized in the above equation. Since the mini- pacitance increases, the ESR decreases resulting in a
mum load current requirement of the IRU1015 is 10mA, fixed RC time constant. The IRU1015 takes advantage
R1 is typically selected to be 121Ω resistor so that it of this phenomena in making the overall regulator loop
automatically satisfies the minimum current requirement. stable. For most applications a minimum of 100µF alu-
Notice that since IADJ is typically in the range of 50µA it minum electrolytic capacitor such as Sanyo MVGX se-
only adds a small error to the output voltage and should ries, Panasonic FA series as well as the Nichicon PL
only be considered when a very precise output voltage series insures both stability and good transient response.
setting is required. For example, in a typical 3.3V appli-
cation where R1=121Ω and R2=200Ω the error due to
Thermal Design
IADJ is only 0.3% of the nominal set point.
The IRU1015 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Load Regulation
Since the IRU1015 is only a three-terminal device, it is Although this device can operate with junction tempera-
not possible to provide true remote sensing of the output tures in the range of 1508C, it is recommended that the
voltage at the load. Figure 4 shows that the best load selected heat sink be chosen such that during maxi-
regulation is achieved when the bottom side of R2 is mum continuous load operation the junction tempera-
connected to the load and the top side of R1 resistor is ture is kept below this number. The example below
connected directly to the case or the VOUT pin of the shows the steps in selecting the proper regulator heat
regulator and not to the load. In fact, if R1 is connected sink for an AMD 486DX4-120 MHz processor.
Rev. 1.3
08/20/02
www.irf.com
4
IRU1015
Assuming the following specifications:
Air Flow (LFM)
100
0
VIN = 5V
Thermalloy 6041PB
No HS Required
No HS Required
VOUT = 3.45V
IOUT(MAX) = 1.2A
TA = 358C
AAVID
574602
Note: For further information regarding the above com-
panies and their latest product offerings and application
The steps for selecting a proper heat sink to keep the support contact your local representative or the num-
junction temperature below 135°C is given as:
bers listed below:
1) Calculate the maximum power dissipation using:
AAVID Thermalloy...............PH# (603) 528-3400
PD = IOUT×(VIN - VOUT)
Designing for Microprocessor Applications
As it was mentioned before the IRU1015 is designed
specifically to provide power for the new generation of
PD = 1.2×(5 - 3.45) = 1.86W
2) Select a package from the regulator data sheet and the low voltage processors requiring voltages in the range
record its junction to case (or Tab) thermal resistance. of 2.5V to 3.6V generated by stepping down the 5V sup-
ply. These processors demand a fast regulator that sup-
Selecting TO-220 package gives us:
ports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
θJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal- could happen when the processor transitions from “Stop
culate the maximum Heat sink temperature allowed: Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
Assume, θcs=0.05°C/W (heat-sink-to-case thermal der of 15 to 20ns, however, the de-coupling capacitors
resistance for black anodized)
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement, the selection of high
frequency low ESR and low ESL output capacitor is im-
perative in the design of these regulator circuits.
TS = TJ - PD×(θJC + θCS)
TS = 135 - 1.86×(2.7 + 0.05) = 1298C
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re- Figure 5 shows the effects of a fast transient on the
sistance (θSA) is calculated by first calculating the output voltage of the regulator. As shown in this figure,
temperature rise above the ambient as follows:
the ESR of the output capacitor produces an instanta-
neousdropequaltothe(DVESR=ESR×DI) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor (DVESL
=L×DI/Dt). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current
∆T = TS - TA = 129 - 35 = 948C
∆T = Temperature Rise Above Ambient
∆T
PD
94
1.86
θSA =
=
= 508C/W
5) Next, a heat sink with lower qSA than the one calcu- (DVC=Dt×DI/C ) where Dt is the response time of the
lated in step 4 must be selected. One way to do this regulator.
is to simply look at the graphs of the "Heat Sink Temp
Rise Above the Ambient" vs. the "Power Dissipation"
and select a heat sink that results in lower tempera-
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.3
08/20/02
www.irf.com
5
IRU1015
2) With the output capacitance being 1500µF:
V ESR
V ESL
∆t × ∆I
2 × 1.2
∆Vc =
=
= 1.6mV
V C
C
1500
T
Where:
∆t = 2µs is the regulator response time
LOAD
1015plt1-1.0
CURRENT
To set the output voltage, we need to select R1 and R2:
LOAD CURRENT RISE TIME
3) Assuming R1=121Ω, 1%
Figure 5 - Typical regulator response
to the fast load current step.
3.45
VOUT -1
-1
×121 = 213Ω
R2 =
×R1 =
(1.25 )
( VREF )
An example of a regulator design to meet the AMD speci-
fication for 486DX4-120MHz is given below.
Select R2 = 215Ω, 1%
Assume the specification for the processor as shown in
Table 1:
Selecting both R1 and R2 resistors to be 1% toler-
ance results in the least amount of error introduced
by the resistor dividers leaving a » ±2.5% error bud-
get for the IRU1015 reference which is well within the
initial accuracy of the device.
Type of
VOUT
Nominal
3.45 V
IMAX
Max Allowed
Output Tolerance
±150 mV
Processor
AMD 486DX4
1.2 A
Table 1 - GTL+ specification for Pentium Pro
Finally, the input capacitor is selected as follows:
The first step is to select the voltage step allowed in the 4) Assuming that the input voltage can drop 150mV be-
output due to the output capacitor’s ESR:
fore the main power supply responds, and that the
main power supply response time is » 50ms, then
the minimum input capacitance for a 1.2A load step
is given by:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is » ±86mV (±2.5% of 3.45V
nominal), then the total step allowed for the ESR and
the ESL, is -64mV.
1.2 × 50
CIN =
= 400µF
0.15
Assuming that the ESL drop is -10mV, the remaining
ESR step will be -54mV. Therefore the output ca-
pacitor ESR must be:
The ESR should be less than:
(VIN - VOUT - ∆V - VDROP)
ESR =
54
∆I
ESR ≤
= 45mΩ
1.2
Where:
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typi-
cal. Selecting a single capacitor achieves our design
goal.
VDROP L Input voltage drop allowed in step 4
∆V L Maximum regulator dropout voltage
∆I L Load current step
(5 - 3.45 - 1.2 - 0.15)
ESR =
= 0.167Ω
1.2
The next step is to calculate the drop due to the ca-
pacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
Select a single 1500µF the same type as the output
capacitors exceeds our requirements. Figure 6 shows
the completed schematic for our example.
Rev. 1.3
08/20/02
www.irf.com
6
IRU1015
Layout Consideration
VOUT
5V
VIN
3.45V
The output capacitors must be located as close to the
VOUT terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the VOUT pin to the output capacitors to
prevent any high frequency oscillation that may result
from excessive trace inductance.
C 1
1500uF
C 2
1500uF
IRU1015
R 1
Adj
121
1%
R 2
215
1%
Figure 6 - Final schematic for the regulator design.
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.3
08/20/02
www.irf.com
7
IRU1015
(D) TO-252 Package
2-Pin
K
A
B
C
L
M
N
78
458
D
J
E
O
P
Q
R
G
F
S
H
R1
SYMBOL MIN
MAX
A
B
6.477 6.731
5.004 5.207
0.686 0.838
7.417 8.179
C
D
E
C
L
9.703 10.084
0.635 0.889
2.286 BSC
F
G
H
J
4.521 4.623
∅1.52 ∅1.62
2.184 2.388
0.762 0.864
K
L
M
N
O
P
1.016
1.118
5.969 6.223
1.016
0
1.118
0.102
Q
R
R1
S
0.534 0.686
R0.31 TYP
R0.51 TYP
0.428 0.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
8
IRU1015
(M) TO-263 Package
3-Pin
A
E
U
K
S
V
B
M
H
L
P
D
G
N
R
C
C
L
SYMBOL
MIN
MAX
A
B
C
D
E
G
H
K
L
10.05 10.312
8.28
4.31
0.66
1.14
8.763
4.572
0.91
1.40
2.54 REF
14.73 15.75
1.40
0.00
2.49
0.33
1.68
0.254
2.74
M
N
P
R
S
U
V
0.58
2.286 2.794
08
88
2.41
2.67
6.50 REF
7.75 REF
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
9
IRU1015
(T) TO-220 Package
3-Pin
H1
Q
L
b1
e3
e
e1
C
L E
b
R
E-PIN
CP
a (5x)
C1
J1
A
C
L
F
D
SYMBOL
MIN
4.06
38
MAX
A
a
4.83
7.58
b
0.63
1.14
0.38
1.02
1.52
0.56
b1
C1
CP
D
3.71D 3.96D
14.22 15.062
E
9.78
2.29
4.83
1.14
1.14
5.94
2.29
10.54
2.79
5.33
1.40
1.40
6.55
2.92
e
e1
e3
F
H1
J1
L
13.716 14.22
Q
2.62
2.87
6.17
R
5.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.3
08/20/02
www.irf.com
10
IRU1015
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
D
M
T
TO-252, (D-Pak)
2
3
3
75
50
50
2500
750
---
Fig A
Fig B
---
TO-263
TO-220
1
1
1
1
1
1
Feed Direction
Figure A
Feed Direction
FigureB
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.3
08/20/02
www.irf.com
11
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