ISC750P10LM [INFINEON]
OptiMOS™ P-channel MOSFETs 100 V in SuperSO8 package represents the new technology targeted for battery management, load switch and reverse polarity protection applications. The main advantage of a P-channel device is the reduction of design complexity in medium and low power applications. Its easy interface to MCU, fast switching as well as avalanche ruggedness makes it suitable for high quality demanding applications. It is available in logic level featuring a wide RDS(on) range and improves efficiency at low loads due to low Qg.;
| 型号： | ISC750P10LM |
| 厂家： | 
Infineon |
| 描述： | OptiMOS™ P-channel MOSFETs 100 V in SuperSO8 package represents the new technology targeted for battery management, load switch and reverse polarity protection applications. The main advantage of a P-channel device is the reduction of design complexity in medium and low power applications. Its easy interface to MCU, fast switching as well as avalanche ruggedness makes it suitable for high quality demanding applications. It is available in logic level featuring a wide RDS(on) range and improves efficiency at low loads due to low Qg. |
| 文件： | 总11页 (文件大小：1235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISC750P10LM
MOSFET
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
SuperSO8
5
8
6
7
7
Features
6
5
8
•ꢀP-Channel
•ꢀVeryꢀlowꢀon-resistanceꢀRDS(on)ꢀ@ꢀVGS=4.5ꢀV
•ꢀ100%ꢀavalancheꢀtested
•ꢀLogicꢀLevel
•ꢀEnhancementꢀmode
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
4
3
1
2
2
3
1
4
Productꢀvalidation
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications
Drain
Pin 5-8
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
*1
Gate
Pin 4
Parameter
Value
-100
75
Unit
Source
Pin 1-3
VDS
V
*1: Internal body diode
RDS(on),max
ID
mΩ
A
-32
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
750P10LM
RelatedꢀLinks
ISC750P10LM
PG-TDSON-8
-
Final Data Sheet
1
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
-
-
-
-
-
-
-32
-28
-3.8
VGS=-10ꢀV,ꢀTC=25ꢀ°C
Continuous drain current1)
ID
A
VGS=-10ꢀV,ꢀTC=100ꢀ°C
VGS=-4.5ꢀV,TA=25°C,RthJA=50°C/W2)
Pulsed drain current3)
Avalanche energy, single pulse4)
ID,pulse
EAS
-
-
-
-
-129
710
20
A
TA=25ꢀ°C
-
mJ
V
ID=-25ꢀA,ꢀRGS=25ꢀΩ
Gate source voltage
VGS
-20
-
-
-
-
-
188
3
TA=25ꢀ°C
Power dissipation
Ptot
W
TA=25ꢀ°C,ꢀRthJA=50ꢀ°C/W2)
IEC climatic category; DIN IEC 68-1:
55/175/56
Operating and storage temperature
Tj,ꢀTstg
-55
-
175
°C
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction - case
RthJC
RthJA
-
0.8
°C/W -
°C/W -
Device on PCB,
6 cm² cooling area
-
-
50
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3) See Diagram 3 for more detailed information
4) See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
-100
-1
Max.
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
-
V
V
VGS=0ꢀV,ꢀID=-250ꢀµA
VDS=VGS,ꢀID=-2304ꢀµA
-1.6
-2
-
-
-0.1
-10
-1
-100
VDS=-100ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C
VDS=-100ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
IDSS
µA
nA
IGSS
-
-10
-100
VGS=-20ꢀV,ꢀVDS=0ꢀV
-
-
61
63
75
86
VGS=-10ꢀV,ꢀID=-25ꢀA
VGS=-4.5ꢀV,ꢀID=-20ꢀA
RDS(on)
mΩ
Gate resistance
RG
gfs
-
-
5.2
51
-
-
Ω
-
Transconductance
S
|VDS|≥2|ID|RDS(on)max,ꢀID=-25ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance1)
Output capacitance1)
Reverse transfer capacitance1)
Ciss
Coss
Crss
-
-
-
3600 4700 pF
VGS=0ꢀV,ꢀVDS=-50ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=-50ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=-50ꢀV,ꢀf=1ꢀMHz
230
50
300
88
pF
pF
VDD=-50ꢀV,ꢀVGS=-4.5ꢀV,ꢀID=-25ꢀA,
RG,ext=1.6ꢀΩ
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
-
-
-
-
35.6
47.2
100
-
-
-
-
ns
ns
ns
ns
VDD=-50ꢀV,ꢀVGS=-4.5ꢀV,ꢀID=-25ꢀA,
RG,ext=1.6ꢀΩ
VDD=-50ꢀV,ꢀVGS=-4.5ꢀV,ꢀID=-25ꢀA,
RG,ext=1.6ꢀΩ
Turn-off delay time
Fall time
VDD=-50ꢀV,ꢀVGS=-4.5ꢀV,ꢀID=-25ꢀA,
RG,ext=1.6ꢀΩ
24.8
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ
Values
Typ.
-11
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge1)
Switching charge
Gate charge total1)
Gate plateau voltage
Gate charge total1)
Output charge1)
Qgs
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-4.5ꢀV
VDD=-50ꢀV,ꢀID=-25ꢀA,ꢀVGS=0ꢀtoꢀ-10ꢀV
VDS=-50ꢀV,ꢀVGS=0ꢀV
Qg(th)
Qgd
-5.7
-23
-
-35
-
Qsw
Qg
-29
-46
-58
-
Vplateau
Qg
-3.1
-92
-122
nC
nC
Qoss
-28.3 -38
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
Max.
-32
Diode continuous forward current
Diode pulse current
IS
-
-
-
-
-
-
-
A
TC=25ꢀ°C
IS,pulse
VSD
trr
-129
A
TC=25ꢀ°C
Diode forward voltage
-0.84 -1
V
VGS=0ꢀV,ꢀIF=-25ꢀA,ꢀTj=25ꢀ°C
VR=-50ꢀV,ꢀIF=-25ꢀA,ꢀdiF/dt=-100ꢀA/µs
VR=-50ꢀV,ꢀIF=-25ꢀA,ꢀdiF/dt=-100ꢀA/µs
Reverse recovery time1)
Reverse recovery charge1)
86
172
580
ns
nC
Qrr
-290
1) Defined by design. Not subject to production test.
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
200
35
175
150
125
100
75
30
25
20
15
10
5
50
25
0
0
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
TCꢀ[°C]
TCꢀ[°C]
Ptot=f(TC)
ID=f(TC);ꢀ|VGS|≥10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
103
101
single pulse
0.01
0.02
0.05
0.1
1 µs
0.2
0.5
102
101
100
10-1
100
10 µs
100 µs
10-1
10-2
10-3
1 ms
10 ms
DC
10-1
100
101
102
103
10-6
10-5
10-4
10-3
10-2
10-1
100
-VDSꢀ[V]
tpꢀ[s]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
60
175
-10 V
150
50
-5 V
125
-2.8 V
-3 V
-4.5 V
40
-4 V
100
-3.5 V
-3.5 V
-5 V
30
-4.5 V
-4 V
75
-10 V
20
10
0
-3 V
50
25
0
-2.8 V
0
1
2
3
4
5
0
10
20
30
40
50
60
70
-VDSꢀ[V]
-IDꢀ[A]
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
60
200
175
50
25 °C
175 °C
150
40
125
100
30
175 °C
75
50
25
0
25 °C
20
10
0
0
2
4
6
8
10
12
14
4
6
8
10
12
14
16
-VGSꢀ[V]
-VGSꢀ[V]
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj
RDS(on)=f(VGS),ꢀID=-25ꢀA;ꢀparameter:ꢀTj
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
2.5
2.0
-23040 µA
2.0
1.5
1.0
0.5
0.0
1.6
1.2
-2304 µA
0.8
0.4
0.0
-75 -50 -25
0
25 50 75 100 125 150 175 200
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
Tjꢀ[°C]
RDS(on)=f(Tj),ꢀID=-25ꢀA,ꢀVGS=-10ꢀV
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
104
103
25 °C
25 °C, max
175 °C
175 °C, max
Ciss
103
102
101
102
101
100
Coss
Crss
0
20
40
60
80
100
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-VDSꢀ[V]
-VSDꢀ[V]
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
IF=f(VSD);ꢀparameter:ꢀTj
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
102
10
-20 V
-50 V
-80 V
8
6
4
2
0
25 °C
101
100 °C
150 °C
100
100
101
102
103
0
20
40
60
80
100
tAVꢀ[µs]
-Qgateꢀ[nC]
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj,start
VGS=f(Qgate),ꢀID=-25ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
116
112
108
104
100
96
92
88
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
VBR(DSS)=f(Tj);ꢀID=-250ꢀµA
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
5ꢀꢀꢀꢀꢀPackageꢀOutlines
DOCUMENT NO.
Z8B00003332
REVISION
08
MILLIMETERS
DIMENSION
MIN.
0.90
0.15
0.34
4.80
3.90
0.00
5.70
5.90
3.88
MAX.
1.20
0.35
0.54
5.35
4.40
0.22
6.10
6.42
4.31
SCALE 10:1
A
A1
b
3mm
0
1
2
D
D1
D2
E
EUROPEAN PROJECTION
E1
E2
e
1.27
L
0.45
0.45
0.71
0.69
ISSUE DATE
05.11.2019
M
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TDSON-8,ꢀdimensionsꢀinꢀmm
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2022-10-13
OptiMOSTMꢀPower-Transistor,ꢀ-100ꢀV
ISC750P10LM
RevisionꢀHistory
ISC750P10LM
Revision:ꢀ2022-10-13,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2022-10-13
Trademarks
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informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
11
Rev.ꢀ2.0,ꢀꢀ2022-10-13
相关型号：
ISC800P06LM
OptiMOS™ P-channel MOSFETs 60 V in SuperSO8 package represents the new technology targeted for battery management, load switch and reverse polarity protection applications. The main advantage of a P-channel device is the reduction of design complexity in medium and low power applications. Its easy interface to MCU, fast switching as well as avalanche ruggedness makes it suitable for high quality demanding applications. It is available in logic level featuring a wide RDS(on) range and improves efficiency at low loads due to low Qg.
INFINEON
ISCA1-11.000MHZ
Series - Fundamental Quartz Crystal, 11MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-2
MMD
ISCA1-11.999MHZ
Series - Fundamental Quartz Crystal, 11.999MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-2
MMD
ISCA1-11.999MHZ-T
Series - Fundamental Quartz Crystal, 11.999MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-2
MMD
ISCA1-15.999MHZ
Series - Fundamental Quartz Crystal, 15.999MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-2
MMD
ISCA1-15.999MHZ-T
Series - Fundamental Quartz Crystal, 15.999MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-2
MMD
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