ISO1H815G [INFINEON]
Coreless Transformer Isolated Digital Output 8 Channel 1.2A High-Side Switch; 空芯变压器隔离数字量输出通道8 1.2A高边开关
| 型号： | ISO1H815G |
| 厂家： | 
Infineon |
| 描述： | Coreless Transformer Isolated Digital Output 8 Channel 1.2A High-Side Switch |
| 文件： | 总20页 (文件大小：1157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet, Version 2.0, July 2009
ISOFACETM
ISO1H815G
Coreless Transformer Isolated
Digital Output 8 Channel 1.2A
High-Side Switch
Power Management & Drives
N e v e r s t o p t h i n k i n g .
ISO1H815G
Revision History:
2009-07-28
Version 2.0
Previous Version:
V1.0
V2.0
Final Datasheet
Edition 2009-07-28
Published by Infineon Technologies AG,
Am Campeon 1-12,
85579 Neubiberg, Germany
© Infineon Technologies AG 2009.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ISOFACETM
ISO1H815G
Coreless Transformer Isolated Digital
Output 8 Channel 1.2A High-Side Switch
Product Highlights
• Coreless transformer isolated data interface
• Galvanic isolation
• 8 High-side output switches 1,2A
• µC compatible 8-bit parallel peripheral
• Isolated return path for DIAG signal
Features
Typical Application
•
•
•
•
•
•
•
•
•
Interface 3.3/5V CMOS operation compatible
Parallel interface
Direct control mode
High common mode transient immunity
Short circuit protection
Maximum current internally limited
Overload protection
Overvoltage protection (including load dump)
Undervoltage shutdown with autorestart and
hysteresis
•
•
•
Isolated switch for industrial applications (PLC)
All types of resistive, inductive and capacitive loads
µC compatible power switch for 24V DC
applications
•
Driver for solenoid, relays and resistive loads
Description
The ISO1H815G is a galvanically isolated 8 bit data
interface in PG-DSO-36 package that provides 8 fully
protected high-side power switches that are able to
handle currents up to 1.2A.
•
•
•
•
•
•
•
•
•
Switching inductive loads
Common output disable pin
Thermal shutdown with restart
Thermal independence of separate channels
Common diagnostic output for overtemperature
ESD protection
Loss of GNDbb and loss of Vbb protection
Reverse Output Voltage protection
RoHS compliant
An 8 bit parallel µC compatible interface allows to
connect the IC directly to a µC system. The input
interface supports also a direct control mode and is
designed to operate with 3.3/5V CMOS compatible
levels.
The data transfer from input to output side is realized by
the integrated Coreless Transformer Technology.
Typical Application
VCC
DIS
Vbb
Vbb
VCC
CT
VCCP1.x
Control
Unit
CS
AD0
WR
WR
OUT0
DIAG
Control
&
Protectio
n Unit
D0
D1
D2
D3
D4
D5
D6
D7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
OUT1
Parallel
Interface
DIAG
µC (i.e
C166)
OUT7
GND
GNDCC
GNDbb
ISO1H815G
Type
On-state Resistance
Package
ISO1H815G
200mΩ
PG-DSO-36
Datasheet
3
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
Vbb
Pin Symbol
Function
N.C.
VCC
DIS
CS
WR
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 OUT0
35 OUT0
TAB
1
2
N.C.
VCC
Not connected
Positive 3.3/5V logic supply
Output disable
Chip select
34 OUT1
33 OUT1
32 OUT2
31 OUT2
30 OUT3
29 OUT3
28 OUT4
27 OUT4
26 OUT5
25 OUT5
24 OUT6
23 OUT6
22 OUT7
21 OUT7
20 N.C.
3
DIS
CS
WR
D0
D1
D2
D3
D4
D5
D6
D7
4
5
Parallel write
6
Data input bit0
Data input bit1
Data input bit2
Data input bit3
Data input bit4
Data input bit5
Data input bit6
Data input bit7
7
8
9
D5
D6
D7
10
11
12
13
14
DIAG
GNDCC
N.C.
N.C.
N.C.
Common diagnostic output for
overtemperature
DIAG
TAB
Vbb
19 GNDbb
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TAB
GNDCC Input logic ground
N.C.
N.C.
N.C.
Not connected
Not connected
Not connected
Figure 1
Power SO-36 (430mil)
.
GNDbb Output driver ground
N.C
Not connected
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
OUT4
OUT4
OUT3
OUT3
OUT2
OUT2
OUT1
OUT1
OUT0
OUT0
Vbb
High-side output of channel 7
High-side output of channel 7
High-side output of channel 6
High-side output of channel 6
High-side output of channel 5
High-side output of channel 5
High-side output of channel 4
High-side output of channel 4
High-side output of channel 3
High-side output of channel 3
High-side output of channel 2
High-side output of channel 2
High-side output of channel 1
High-side output of channel 1
High-side output of channel 0
High-side output of channel 0
Positive driver power supply voltage
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Pin Configuration and Functionality
driver that is supplied by Vbb.
1.2
Pin Functionality
VCC (Positive 3.3/5V logic supply)
OUT0 ... OUT7 (High side output channel 0 ... 7)
The output high side channels are internally connected
to Vbb and controlled by the corresponding data input
pins D0 ... D7 in parallel mode.
The VCC supplies the input interface that is
galvanically isolated from the output driver stage. The
input interface can be supplied with 3.3/5V.
TAB (Vbb, Positive supply for output driver)
The heatslug is connected to the positive supply port of
the output interface.
DIS (Output disable)
The high-side outputs OUT0...OUT7 can be
immediately switched off by means of the low active pin
DIS that is an asynchronous signal. The input registers
are also reset by the DIS signal. The Output remains
switched off after low-high transition of DIS signal, till
new information is written into the input register.
Current Sink to GNDCC.
CS (Chip select)
The system microcontroller selects the ISO1H815G by
means of the low active pin CS to activate the parallel
interface. By connecting the CS pin and WR pin to
ground the parallel direct control is activated. Current
Source to VCC.
WR (Parallel write)
In parallel mode data at the input pins (D0 ... D7) are
latched by means of the rising edge of the low active
signal WR (write). Current Source to VCC.
D0 ... D7 (Data input bit0 ... bit7)
The present data can be latched on the rising edge of
the write signal WR. D0 ... D7 control the corresponding
output channels OUT0 ...OUT7. By connecting CS and
WR to ground, the signals at D0 ... D7 directly control
the outputs. Current Sink to GNDCC.
DIAG (Common diagnostic output for
overtemperature)
The low active DIAG signal contains the OR-wired
information of the separated overtemperature detection
units for each channel.The output pin DIAG provides an
open drain functionality. A current source is also
connected to the pin DIAG. In normal operation the
signal DIAG is high. When overtemperature or Vbb
below ON-Limit is detected the signal DIAG changes to
low.
GNDCC (Ground for VCC domain)
This pin acts as the ground reference for the input
interface that is supplied by VCC.
GNDbb (Output driver ground domain)
This pin acts as the ground reference for the output
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Blockdiagram
2
Blockdiagram
n o i t a l o I s
i c n a l v a G
Figure 2
Blockdiagram
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Functional Description
3
Functional Description
3.1
Introduction
3.3.2
Power Transistor Overvoltage
Protection
The ISOFACE ISO1H815G includes 8 high-side power
switches that are controlled by means of the integrated Each of the eight output stages has it own zener clamp
parallel interface. The interface is 8bit µC compatible. that causes a voltage limitation at the power transistor
Furthermore a direct control mode can be selected that when solenoid loads are switched off. VON is then
allows the direct control of the outputs OUT0...OUT7 by clamped to 47V (min.).
means of the inputs D0...D7 without any additional logic
Vbb
signal. The IC can replace 8 optocouplers and the 8
high-side switches in conventional I/O-Applications as
a galvanic isolation is implemented by means of the
integrated coreless transformer technology. The µC
compatible interfaces allow a direct connection to the
ports of a microcontroller without the need for other
components. Each of the 8 high-side power switches is
Vbb
Vz
VON
OUTx
GNDbb
protected
against
short to
Vbb,
overload,
overtemperature and against overvoltage by an active
zener clamp.
The diagnostic logic on the power chip recognizes the
overtemperature information of each power transistor
The information is send via the internal coreless
transformer to the pin DIAG at the input interface.
Figure 3
Inductive and overvoltage output
clamp (each channel)
Energy is stored in the load inductance during an
inductive load switch-off.
2
3.2
Power Supply
EL = 1 ⁄ 2 × L × IL
The IC contains 2 galvanic isolated voltage domains
that are independent from each other. The input
interface is supplied at VCC and the output stage is
supplied at Vbb. The different voltage domains can be
switched on at different time. The output stage is only
enabled once the input stage enters a stable state.
Ebb
EAS
E
Load
Vbb
Dx
OUTx
L
E
V
GNDbb
L
3.3
Output Stage
bb
Z
L
Each channel contains a high-side vertical power FET
that is protected by embedded protection functions.
ER
R
L
The continuous current for each channel is 1.2A (all
channels ON).
Figure 4
Inductive load switch-off energy
dissipation (each channel)
3.3.1
Output Stage Control
While demagnetizing the load inductance, the energy
dissipation in the DMOS is
Each output is independently controlled by an output
latch and a common reset line via the pin DIS that
disables all eight outputs and reset the latches. The
parallel input data is transferred to the input latches
with a high-to-low transition of the signal WR (write)
while the CS is logic low. A low-to-high transition of CS
transfers then the data of the input latches to the output
buffer.
E
AS= Ebb + EL – ER= VON(CL) × iL(t)dt
with an approximate solution for RL > 0Ω:
IL × L
---------------
2 × RL
IL × RL
VON(CL)
EAS
=
× (Vbb + VON(CL) ) × ln 1 + ------------------------
3.3.3
Power Transistor Overcurrent
Protection
The outputs are provided with a current limitation that
enters a repetitive switched mode after an initial peak
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Functional Description
current has been exceeded. The initial peak short
circuit current limit is set to IL(SCp). During the repetitive
mode short circuit current the limit is set to IL(SCr). If this
operation leads to an overtemperature condition, a
second protection level (Tj > 135°C) will change the
output into a low duty cycle PWM (selective thermal
shutdown with restart) to prevent critical chip
temperatures.
IN
t
VOUT
IL
Normal
Output short to GND
IL(SCp)
operation
IN
t
t
t
IL(SCr)
t
VOUT
DIAG
Figure 7
3.4
t
T
J
Short circuit in on-state, shut down
down by overtemperature, restart by
cooling
t
DIAG
Common Diagnostic Output
t
The overtemperature detection information are OR-
wired in the common diagnostic output block. The
information is send via the integrated coreless
transformer to the input interface. The output stage at
pin DIAG has an open drain functionality combined with
a current source.
Figure 5
Overtemperature detection
The following figures show the timing for a turn on into
short circuit and a short circuit in on-state. Heating up
of the chip may require several milliseconds,
depending on external conditions.
VCC
IN
Common
Diagnostic
100µA
Output
CT
DIAG
t
VOUT
Output short to GND
t
t
t
IL
IL(SCp)
IL(SCr)
Figure 8
Common diagnostic output
DIAG
Figure 6
Turn on into short circuit, shut down by
overtemperature, restart by cooling
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Functional Description
3.5
Parallel Interface
3.5.2
uC Control Mode
The ISO1H815G contains a parallel interface that can
be directly controlled by the microcontroller output
ports. The parallel interface can also be switched over
to a direct control that allows direct changes of the
outputs OUT0 ... OUT7 by means of the corresponding
inputs D0 ... D7 without additional logic signals. To
activate the parallel direct control mode pin CS and pin
WR have to be connected both to ground.
AD0
WR
CS
WR
P0
D0
D1
D2
D3
D4
D5
D6
D7
P1
P2
P3
P4
P5
P6
P7
Output lines
3.5.1
Parallel Interface Signal
Description
DIAG
CS - Chip select. The system microcontroller selects
the ISO1H815G by means of the CS pin. Whenever the
pin is in a logic low state, data can be transferred from
the µC.
Parallel
Interface
IC1
µC(i.e C166)
Number of adressed ICs = n
CS High to low transition:
Number of necessary control and data ports = 9 n
Individual ICs are adressed by the chip select
•
Parallel input data can be written in from then on
Figure 9
Parallel bus configuration
CS Low to high transition:
3.5.3
Direct Control Mode
•
The data in the input latches is transferred to the
output buffer
Beside the use of the parallel µC compatible interface a
parallel direct control mode can be choosen. In this
mode the output OUT0...OUT7 can be directly
controlled via the inputs D0...D7 without the need for
additional logic signals. To activate this mode pin CS
and WR need to be connected to ground.
WR - Write. The system controller enables the write
procedure in the ISO1H815G by means of the signal
WR. A logic low state signal at pin WR writes the input
data into the input latches when the CS pin is in a logic
low state.
.
WR Logic low level:
VCC
VCC
VCC
•
Parallel input data at the pins D0 - D7 is written into
the input latches
CS
WR
P0
P1
P2
P3
P4
P5
P6
P7
D0
D1
D2
D3
D4
D5
D6
D7
DIAG
WR Logic high level:
Output lines
•
The parallel input data is latched in the input
latches. Any changes at the pins D0 - D7 after the
low-to-high transition of WR do not affect the input
latches.
D0 ... D7 - Parallel input. Parallel data bits are fed into
the pins D0 ... D7. The data is written into the input
latches when WR is logic low.
Controller
Parallel
Interface
IC1
Figure 10 Parallel Direct Control
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Functional Description
3.6
Parallel Interface Timing
tCSWR
tWHCS
CS
tCSD
tWRPW
WR
tDS
tDH
DATA
D0 - D7
ton/off
OUT0 - OUT7
OUTPUT
Figure 11 Parallel input - output timing diagram
3.7
Transmission Failure Detection
There is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless
transformer transmission. This unit decides wether the transmitted data is valid or not. If four times serial data
coming in from the internal registers is not accepted, the output stages are switched off until the next valid data is
received.
Datasheet
10
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
4
Electrical Characteristics
Note:All voltages at pins 2 to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to
pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other
ratings are not violated. The two voltage domains VCC and Vbb are internally galvanic isolated.
4.1
Absolute Maximum Ratings
Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2
(VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than
Vbb(AZ) require an external current limit for the GNDbb pin, e.g. with a 15Ω resistor in GNDbb connection.
Operating at absolute maximum ratings can lead to a reduced lifetime.
Parameter
at Tj = -40 ... 135°C, unless otherwise specified
Symbol
Limit Values
Unit
min.
max.
6.5
Supply voltage input interface (VCC)
Supply voltage output interface (Vbb)
Continuos voltage at data inputs (D0 ... D7)
Continuos voltage at pin CS
Continuos voltage at pin WR
Continuos voltage at pin DIS
Continuos voltage at pin DIAG
Load current (short-circuit current)
Reverse current through GNDbb1)
Operating Temperature
VCC
Vbb
-0.5
-11)
-0.5
-0.5
-0.5
-0.5
-0.5
-1.6
-25
-50
V
45
VDx
VCS
VWR
VDIS
VDIAG
IL
6.5
6.5
6.5
6.5
6.5
self limited
A
IGNDbb
Tj
internal limited °C
Storage Temperature
Power Dissipation2)
Inductive load switch-off energy dissipation3) single
Tstg
Ptot
150
3.3
W
J
EAS
pulse, Tj = 125°C, IL = 1.2A
one channel active
all channel simultaneously active (each channel)
5
0.5
Load dump protection3) VloadDump4)=VA + VS
VLoaddump
V
VIN = low or high
td = 400ms, RI = 2Ω, RL = 27Ω, VA = 13.5V
td = 350ms, RI = 2Ω, RL = 57Ω, VA = 27V
90
117
Electrostatic discharge voltage (Human Body Model)
according to JESD22-A114-B
VESD
kV
kV
A
2
Electrostatic discharge voltage (Charge Device Model) VESD
according to ESD STM5.3.1 - 1999
Continuos reverse drain current1)3), each channel
1
4
IS
1) defined by Ptot
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
3) not subject to production test, specified by design
4) VLoaddump is setup without the DUT connected to the generator per ISO7637-1 and DIN40839
Datasheet
11
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
4.2
Thermal Characteristics
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Thermal resistance junction - case
Thermal resistance @ min. footprint
Thermal resistance @ 6cm² cooling area1)
RthJC
1.5
50
38
K/W
Rth(JA)
Rth(JA)
1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
4.3
Load Switching Capabilities and Characteristics
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
On-state resistance, IL = 0.5A, each channel
Tj = 25°C
RON
mΩ
150
270
75
200
320
100
50
Tj = 125°C
two parallel channels, Tj = 25°C:1)
four parallel channels, Tj = 25°C:1)
38
Nominal load current
Device on PCB 38K/W, Ta = 85°C, Tj < 125°C
one channel:1)
IL(NOM)
1.4
2.2
4.4
A
two parallel channels:1)
four parallel channels:1)
2)
Turn-on time to 90% VOUT
RL = 47Ω, VDx = 0 to 5V
ton
toff
64
89
1
120 µs
170
2)
Turn-off time to 10% VOUT
RL = 47Ω, VDx = 5 to 0V
Slew rate on 10 to 30% VOUT
dV/dton
-dV/dtoff
2
2
V/µs
RL = 47Ω, Vbb = 15V
Slew rate off 70 to 40% VOUT
1
RL = 47Ω, Vbb = 15V
1) not subject to production test, specified by design
2) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless
transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time
can increase by up to 50µs.
4.4
Operating Parameters
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
otherwise specified
Common mode transient immunity1)
Magnetic field immunity1)
∆VISO/dt
-25
-
25
kV/µs ∆VISO = 200V
HIM
100
A/m IEC61000-4-8
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
Voltage domain Vbb Operating voltage
Vbb
11
7
35
10.5
11
V
0.5
1
(Output interface)
Undervoltage shutdown
Vbb(under)
Vbb(u_rst)
∆Vbb(under)
Ibb(uvlo)
IGNDL
Undervoltage restart
Undervoltage hysteresis
Undervoltage current
Operating current
2.5
14
mA
mA
Vbb < 7V
10
All Channels
ON - no load
Leakage output current
IL(off)
5
30
µA
V
(included in Ibb(off)
VDx = low, each channel
Voltage domain VCC Operating voltage
)
VCC
3.0
2.5
0.1
1
5.5
2.9
3
(Input interface)
Undervoltage shutdown
Undervoltage restart
Undervoltage hysteresis
Undervoltage current
Operating current
VCC(under)
VCC(u_rst)
∆VCC(under)
ICC(uvlo)
ICC(on)
2
mA
mA
Vcc < 2.5V
4.5
6
1) not subject to production test
Datasheet
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Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
4.5
Output Protection Functions
Parameter1)
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Initial peak short circuit current limit, each channel IL(SCp)
Tj = -25°C, Vbb = 30V, tm = 700µs
Tj = 25°C
A
1.4
3.0
4.5
Tj = 125°C
two parallel channels:3)
twice the current of one channel
four times the current of one channel
four parallel channels:3)
Repetitive short circuit current limit3)
Tj = Tjt (see timing diagrams)
IL(SCr)
each channel:
2.2
2.2
2.2
two parallel channels:3)
four parallel channels:3)
Output clamp (inductive load switch off)
VON(CL)
47
53
60
V
at VOUT = Vbb - VON(CL)
Overvoltage protection
Vbb(AZ)
Tjt
47
135
10
Thermal overload trip temperature2)3)
Thermal hysteresis3)
°C
K
∆Tjt
1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continous
repetitive operation.
2) Higher operating temperature at normal function for each channel available
3) not subject to production test, specified by design
4.6
Diagnostic Characteristics at pin DIAG
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Common diagnostic sink current
Idiagsink
5
mA Vdiagon
<
(overtemperature of any channel) Tj = 135°C
0.25xVCC
Common diagnostic source current
Idiagsource
100
µA
Datasheet
14
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
4.7
Input Interface
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Input low state voltage
(D0 ... D7, DIS, CS, WR)
Input high state voltage
(D0 ... D7, DIS, CS, WR)
Input voltage hysteresis
(D0 ... D7, DIS, CS, WR)
Input pull down current
(D0 ... D7, DIS)
VIL
VIH
-0.3
0.3 x
VCC
V
0.7 x
VCC
100
100
100
85
VCC
+
0.3
VIHys
IIdown
-IIup
tDIS
mV
µA
Input pull up current
(CS, WR)
Output disable time (transition DIS to logic low)1)2)
Normal operation
170 µs
230
---
---
Turn-off time to 10% VOUT
RL = 47Ω
Output disable time (transition DIS to logic low)1)2)3)
Disturbed operation
tDIS
---
Turn-off time to 10% VOUT
RL = 47Ω
1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer.
2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again.
3) The parameter is not subject to production test - verified by design/characterization
4.8
Parallel Interface Input Timing
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
otherwise specified
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
WR pulse width
tWRPW
tDS
20
20
10
0
ns
Data setup time before WR
Data hold time after WR
Chip select valid to WR
WR logic high to CS logic high
Delay to next CS cycle
tDH
tCSWR
tWHCS
tCSD
10
10
Datasheet
15
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
4.9
Reverse Voltage
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=3.0...5.5V, unless
Symbol
-Vbb
Limit Values
Unit Test Condition
min.
typ.
max.
otherwise specified
Reverse voltage1)2)
RGND = 0 Ω
V
1
45
RGND = 150 Ω
Diode forward on voltage
-VON
IF = 1.25A, VDx = low, each channel
1.2
1) defined by Ptot
2) not subject to production test, specified by design
4.10
Isolation and Safety-Related Specification
Parameter
Value
Unit
Conditions
Measured from input terminals to output terminals,
unless otherwise specified
Rated dielectric isolation voltage VISO
Short term temporary overvoltage
Minimum external air gap (clearance)
Minimum external tracking (creepage)
Minimum Internal Gap
500
1250
2.6
VAC
V
1 - minute duration1)
5s acc. DIN EN60664-1 1)
shortest distance through air.
shortest distance path along body.
mm
mm
mm
2.6
0.01
Insulation distance through
insulation
1) The parameter is not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration
4.11
Reliability
For Qualification Report please contact your local Infineon Technologies office!
Datasheet
16
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
Datasheet
17
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Electrical Characteristics
Datasheet
18
Version 2.0, 2009-07-28
ISOFACETM
ISO1H815G
Package Outlines
5
Package Outlines
1)
PG-DSO-36
0.15
11
B
(Plastic Dual Small
Outline Package)
2.8
0.1
1.1
0.1
15.74
6.3
(Mold)
(Heatslug)
Heatslug
0.65
0.25 +0.13
0.1 C
0.15
0.95
36x
M
0.25 A B C
0.3
14.2
0.25 B
Bottom View
36
19
19
36
Index Marking
Heatslug
1
18
1
10
13.7 -0.2
(Metal)
1 x 45˚
1)
0.1
15.9
A
(Mold)
1) Does not include plastic or metal protrusion of 0.15 max. per side
gps09181_1
Figure 12 PG-DSO-36
Datasheet
19
Version 2.0, 2009-07-28
Total Quality Management
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Ansprüchen in der bestmöglichen For us it means living up to each and
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Anstrengungen
gelten concerned with product quality. We
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Logistik, dem Service und Support supply and logistics, service and
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which we advise and attend to you.
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our staff. Total Quality in thought and
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and you, our customer. Our guideline is
“do everything with zero defects”, in an
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bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
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Published by Infineon Technologies AG
相关型号：
ISO1H816GAUMA1
Half Bridge Based Peripheral Driver, 8 Driver, 4.4A, PDSO36, GREEN, PLASTIC, SOP-36
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