ITS4060S-SJ-N_技术文档

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Features

•

CMOS compatible input

Switching all types of resistive, inductive and capacitive loads

Fast demagnetization of inductive loads

Very low standby current

Optimized Electromagnetic Compatibility (EMC)

Overload protection

Current limitation

Short circuit protection

Thermal shutdown with restart

Overvoltage protection (including load dump)

Reverse battery protection with external resistor

Loss of GND and loss of Vbb protection

Electrostatic Discharge Protection (ESD)

Green Product (RoHS compliant)

Applications

•

All types of resistive, inductive and capacitive loads

Power switch for 12V and 24V DC applications with CMOS compatible control interface

Driver for electromagnetic relays

Power management for high-side-switching with low current consumption in OFF-mode

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC.

Description

The ITS4060S-SJ-N is a protected single channel smart high-side NMOS power switch in a PG-DSO-8 package

with charge pump and CMOS compatible input. The device is monolithically integrated in Smart technology.

Data Sheet

Rev 1.1

2019-07-25

www.infineon.com/industrial-profets

1

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Table 1

Product summary

Parameter

Symbol

V_SAZmin

V_S

Values

Overvoltage protection

Operating voltage range

On-state resistance

41 V

5 < V_S< 34V

typ. 50 mΩ

2.6 A

R_DSON

I_L(nom)

T_j

Nominal load current

Operating temperature range

Stand-by current

-40°C to 125°C

15 µA

I_SSTB

Type

Package

Marking

ITS4060S-SJ-N

PG-DSO-8

I060SN

Data Sheet

2

Rev1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Table of Contents

1

Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

3.2

3.3

4

5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typical performance graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Special feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical application waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Protection behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1

6.2

6.3

7

8

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Sheet

3

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Block diagram and terms

1

Block diagram and terms

ITS4060S-SJ-N

VS

5

6

7

8

Bias

Supervision

Overvoltage

Protection

Current

Limiter

Gate

Control

Circuit

IN

Logic

2

4

ESD

Protection

NC

Temperature

Sensor

OUT

3

1

GND

Figure 1

Block diagram

Voltage- and Current-Definitions:

Switching Times and Slew Rate Definitions:

V_IN

H

ITS4060S-SJ-N

L

VS

5

6

7

8

t

I_S

V_OUT

+V_S

Bias

Supervision

Overvoltage

Protection

Current

Limiter

V_DS

90%

70%

SR_OFF

40%

30%

Gate

Control

Circuit

IN

Logic

2

4

I_IN

ESD

Protection

SR_ON

10%

NC

Temperature

Sensor

0

OUT

t_ON

t_OFF

t

3

I_OUT

I_L

1

0

GND

OFF

ON

OFF

GND

Figure 2

Terms - parameter definition

Data Sheet

4

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Pin configuration

2

Pin configuration

2.1

Pin assignment

GND

IN

1

2

3

4

8

7

6

5

VS

OUT

NC

VS

P-DSO-8

Figure 3

Pin configuration top view, PG-DSO-8

2.2

Pin definitions and functions

Symbol Function

1

GND

IN

Logic ground

2

Input, controls the power switch; the powerswitch is ON when high

3

OUT

NC

Output to the load

4

Not connected

5, 6, 7, 8

VS

Supply voltage (design the wiring for the maximum short circuit current

and also for low thermal resistance)

Data Sheet

5

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 2

Absolute maximum ratings ¹⁾at T_j= 25°C unless otherwise specified. Currents flowing into

the device unless otherwise specified in chapter “Block Diagram and Terms”

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Supply voltage VS

Voltage

V_S

–

40

36

V

–

4.1.1

Voltage for short circuit protection

Output stage OUT

V_SSC

-40°C < T_j< 150°C 4.1.2

Output current; (short circuit current I_OUT

–

self

A

–

4.1.3

see electrical characteristics)

limited

Input IN

Voltage

V_IN

I_IN

-10

-5

–

16

5

V

–

4.1.4

4.1.5

Current

mA

Temperatures

Junction temperature

Storage temperature

Power dissipation

Ta = 25 °C²⁾

T_j

-40

-55

–

125

°C

–

4.1.6

4.1.7

T_stg

P _tot

–

1.5

W

–

4.1.8

4.1.9

Inductive load switch-off energy dissipation

Tj = 125 °C; V_S=13.5V; IL= 1.5A³⁾

E_AS

900

mJ single pulse

ESD Susceptibility

ESD susceptibility (input pin IN)

ESD susceptibility (output pin OUT)

ESD susceptibility (all other pins)

V_ESD

-1

-6

-4

–

1

6

4

kV

HBM⁴⁾

4.1.10

4.1.12

4.1.11

1) Not subject to production test, specified by design

2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70mm thick) copper area for Vbb connection.

PCB is vertical without blown air

3) Not subject to production test, specified by design

4) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

Note:

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Integrated protection functions are designed to prevent IC destruction under fault conditions

described in the data sheet. Fault conditions are considered as “outside” the normal operating

range. Protection functions are neither designed for continuous nor repetitive operation.

Data Sheet

6

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

General product characteristics

3.2

Functional range

Table 3

Functional range

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Nominal operating voltage

V_S

5

34

V

V_Sincreasing

4.2.1

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

Thermal resistance¹⁾

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Thermal resistance - unction to R_thj-pin5

pin5

–

26.7

–

K/W

–

4.3.1

4.3.2

2)

Thermal resistance - junction to R_{thJA_1s0p}

ambient - 1s0p, minimal

footprint

–

140.1 –

K/W

3)

4)

5)

6)

Thermal resistance - junction to R_{thJA_1s0p_300mm}

–

85.8

74.7

78.2

76.6

–

K/W

4.3.3

4.3.4

4.3.5

4.3.6

ambient - 1s0p, 300mm²

Thermal resistance - junction to R_{thJA_1s0p_600mm}

ambient - 1s0p, 600mm²

Thermal resistance - junction to R_{thJA_2s2p}

ambient - 2s2p

Thermal resistance - junction to R_{thJA_2s2p}

ambient with thermal vias - 2s2p

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, footprint; the product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.

3) Specified R_thJAvalue is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, Cu, 300mm²; the

product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.

4) Specified R_thJAvalue is according to Jedec JESD51-3 at natural convection on FR4 1s0p board, 600mm²; the product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1x 70µm Cu.

5) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

6)Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board with two

thermal vias; the product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper

layers (2 x 70µm Cu, 2 x 35µm Cu. The diameter of the two vias are equal 0.3mm and have a plating of 25um

with a copper heatsink area of 3mm x 2mm). JEDEC51-7: The two plated-through hole vias should have a

solder land of no less than 1.25 mm diameter with a drill hole of no less than 0.85 mm diameter.

Data Sheet

7

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Electrical characteristics

4

Electrical characteristics

Table 5

V_S=13.5V; Tj = -40°C to 125°C; all voltages with respect to ground. Currents flowing into the

device unless otherwise specified in chapter “Block diagram and terms”. Typical values at

V_s= 13.5V, T_j= 25°C

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Powerstage

NMOS ON resistance

R_DSON

I_LNOM

–

50

95

3.1

60

120

–

mΩ I_OUT= 2A;T_j= 25°C;

9V < V_S< 34V;

5.0.1

5.0.2

5.0.3

V_IN= 5V

NMOS ON resistance

–

mΩ I_OUT= 2A;T_j= 125°C;

9V < V_S< 34V;

V_IN= 5V

Nominal load current;

device on PCB ¹⁾

2.6

A

T_pin5= 85°C

Timings of power stages²⁾

Turn ON time (to 90% of V_out);

L to H transition of V_IN

t_ON

–

90

180

230

1.5

µs

V_S=13.5V; R_L= 47Ω

5.0.4

5.0.5

5.0.6

Turn OFF time (to 10% of V_out);

H to L transition of V_IN

t_OFF

SR_ON

110

0.7

ON-slew rate; ∆V_OUT/ ∆t

(10 to 30% of V_out);

L to H transition of V_IN

V / µs V_S=13.5V; R_L= 47Ω

OFF-slew rate; ∆V_OUT/ ∆t

(70 to 40% of V_out);

SR_OFF

–

0.7

1.5

5.0.7

H to L transition of V_IN

Under voltage lockout (charge pump start-stop-restart)

Supply undervoltage;

charge pump stop voltage

V_SUV

–

5.5

V

V_Sdecreasing

V_Sincreasing

5.0.8

5.0.9

Supply startup voltage;

V_SSU

–

4.0

Charge pump restart voltage

Current consumption

Operating current

Standby current

I_GND

–

0.8

–

1.5

10

mA V_IN= 5V

5.0.10

5.0.11

I_SSTB

µA

V_IN= 0V; V_OUT= 0V

-40°C < T_j< 85°C

Standby current

I_SSTB

–

15

5

V_IN= 0V; V_OUT= 0V

T_j= 125°C

5.0.12

5.0.13

Output leakage current

I_OUTLK

V_IN= 0V; V_OUT= 0V

Protection functions ³⁾

Initial peak short circuit current

limit

I_LSCP

–

28

A

T_j= -40°C; V_S= 20V

5.0.14

V_IN= 5.0V; t_m=150µs

Data Sheet

8

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Electrical characteristics

Table 5

V_S=13.5V; Tj = -40°C to 125°C; all voltages with respect to ground. Currents flowing into the

device unless otherwise specified in chapter “Block diagram and terms”. Typical values at

V_s= 13.5V, T_j= 25°C

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Initial peak short circuit current

limit

I_LSCP

I_LSCR

V_DSCL

V_SAZ

T_jTrip

T_HYS

–

17

–

A

V

T_j= 25°C; V_S= 20V

_IN= 5.0V; t_m=150µs

T_j=125°C; V_S= 20V

_IN= 5.0V; t_m=150µs

5.0.15

5.0.16

5.0.17

5.0.18

5.0.19

5.0.20

5.0.21

V

Initial peak short circuit current

limit

9

–

V

Repetitive short circuit current

limit T_j= T_jTrip; see timing diagrams

–

12

47

–

V_IN= 5.0V

I_S= 4mA

–

Output clamp at V_OUT= V_S- V_DSCL

(inductive load switch off)

41

150

–

Overvoltage protection

V_OUT= V_S- V_ONCL

V

Thermal overload

trip temperature

–

°C

K

Thermal hysteresis

10

–

Reverse battery⁴⁾

Continuous reverse battery

voltage

V_SREV

V_FDS

- 32

–

V

–

5.0.22

5.0.23

Forward voltage of the drain-

source reverse diode

600

mV I_FDS= 200mA;

V_IN= 0V; T_j= 125°C

Input interface; pin IN

Input turn-ON voltage

(logic input high-level)

V_INON

2.2

–

V

–

5.0.24

5.0.25

Input turn-OFF voltage

(logic input low-level)

V_INOFF

0.8

–

Input threshold hysteresis

Off state input current

On state input current

Input resistance

V_INHYS

I_INOFF

I_INON

R_IN

–

0.3

–

V

–

5.0.26

5.0.27

5.0.28

5.0.29

1

30

5.0

µA

kΩ

V_IN= 0.7V

V_IN= 5.0V

–

1

–

1.5

3.5

1) Device on 50mm x 50mm x 1,5mm epoxy FR4 PCB with 6cm2 (one layer copper 70um thick) copper area for supply

voltage connection. PCB in vertical position without blown air.

2) Timing values only with high slewrate input signal; otherwise slower.

3) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data

sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed

for continuous repetitive operation.

4) Requires a 150 Ω resistor in GND connection. The reverse load current trough the intrinsic drain-source diode of the

power-MOS has to be limited by the connected load. Power dissipation is higher compared to normal operation due

to the voltage drop across the drain-source diode. The temperature protection is not functional during reverse

current operation! Input current has to be limited (see max ratings).

Data Sheet

9

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Typical performance graphs

5

Typical performance graphs

Typical characteristics

Transient thermal impedance Z_thJAversus

pulse time t_p@ 6cm2 heatsink area

pulse time t_p@ min. footprint

D = t_p/ T

On-resistance R_DSONversus

junction temperature T_j

On-resistance R_DSONversus

supply voltage V_S

120

100

80

70

60

50

40

30

20

10

60

40

T_j=−40°C;I_L=0.5A

T_j=25°C;I_L=0.5A

T_j=125°C;I_L=0.5A

20

0

V_s=13.5V

0

−40 −25

0

25

50

T_j[°C]

75

100

125

10

15

20

25

V_s[V]

30

35

40

Data Sheet

10

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Typical performance graphs

Typical characteristics

Switch ON time t_ONversus

junction temperature T_j

Switch OFF time t_OFFversus

junction temperature T_j

140

120

100

80

180

160

140

120

100

80

60

40

V_s=9V;R_L=47Ω

20

V_s=9V;R_L=47Ω

V_s=32V;R_L=47Ω

V_s=13.5V;R_L=47Ω

V_s=32V;R_L=47Ω

0

−40 −25

0

25

50

T[°C]

75

100

125

−40 −25

0

25

50

T[°C]

75

100

125

j

ON slewrate SR_ONversus

junction temperature T_j

OFF slewrate SR_OFFversus

junction temperature T_j

2

1.8

1.6

1.4

1.2

1

2

1.8

1.6

1.4

1.2

1

V_s=9V;R_L=47Ω

V_s=13.5V;R_L=47Ω

V_s=32V;R_L=47Ω

V_s=9V;R_L=47Ω

V_s=13.5V;R_L=47Ω

V_s=32V;R_L=47Ω

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

−40 −25

0

25

50

T_j[°C]

75

100

125

−40 −25

0

25

50

T_j[°C]

75

100

125

Data Sheet

11

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Typical performance graphs

Typical characteristics

Standby current I_SSTBversus

junction temperature T_j

Output leakage current I_OUTLKversus

junction temperature T_j

6

5

4

3

2

1

2.5

V_IN=0V;V_s=32V

2

1.5

1

0.5

V_IN=0V;V_s=32V

75 100

0

−40 −25

0

25

50

T_j[°C]

125

−40 −25

0

25

50

T_j[°C]

75

100

125

Initial peak short circuit current limit I_LSCPversus Initial short circuit shutdown time t_SCOFFversus

junction temperature T_j

25

3

2.5

2

20

15

10

5

1.5

1

0.5

V_s=20V

100

V_s=20V

0

−40 −25

0

25

50

T_j[°C]

75

125

0

25

50

T[°C]

75

100

125

j

Data Sheet

12

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Typical performance graphs

Typical characteristics

Input current consumption I_INversus

junction temperature T_j

Input current consumption I_INversus

input voltage V_IN

12

10

8

200

T_j=−40..25°C;V_s=13.5V

180

T_j=125°C;V_s=13.5V

160

140

120

100

80

6

4

60

40

2

V

_IN≤0.7V;V_s=13.5V

V_IN=5V;V_s=13.5V

75 100

20

0

−40 −25

0

25

50

T_j[°C]

125

0

2

4

6

8

V_IN[V]

Input threshold voltage V_INH,Lversus

junction temperature T_j

Input threshold voltage V_INH,Lversus

supply voltage V_S

2

1.8

1.6

1.4

1.2

1

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.8

0.6

0.4

OFF;T_j=25°C

OFF;V_s=13.5V

ON;V_s=13.5V

75 100

0.2

0

0.2

0

ON;T_j=25°C

−40 −25

0

25

50

T_j[°C]

125

10

15

20

25

30

35

V_s[V]

Data Sheet

13

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Typical performance graphs

Typical characteristics

Max. allowable load inductance L versus

load current I_L

Max. allowable inductive single pulse switch-off

energy E_ASversus load current I_L

2000

1400

T_jstart=125°C;V_s=13.5V;R_L=0Ω

T_jstart=125°C;V_s=13.5V

1800

1200

1000

800

600

400

200

0

1600

1400

1200

1000

800

600

400

200

0

1

1.5

2

2.5

3

1

1.5

2

2.5

3

I_L[A]

Data Sheet

14

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Application information

6

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Wire

Harness

ITS4060S-SJ-N

VS

5

6

Bias

Supervision

Overvoltage

Protection

Current

Limiter

7

8

C_S

GND3

220nF

Gate

Control

Circuit

IN

Logic

2

4

ESD

Protection

Wire

Harness

NC

Temperature

Sensor

OUT

3

C_OUT

1nF

Complex

LOAD

1

GND

GND1

GND2

Electronic Control Unit

Figure 4

Application diagram

The ITS4060S-SJ-N can be connected directly to a supply network. It is recommended to place a ceramic

capacitor (e.g. C_S= 220nF) between supply and GND of the ECU to avoid line disturbances. Wire harness

inductors/resistors are sketched in the application circuit above.

The complex load (resistive, capacitive or inductive) must be connected to the output pin OUT.

A built-in current limit protects the device against destruction.

The ITS4060S-SJ-N can be switched on and off with standard logic ground related logic signal at pin IN.

In standby mode (IN=L) the ITS4060S-SJ-N is deactivated with very low current consumption.

The output voltage slope is controlled during on and off transition to minimize emissions. Only a small

ceramic capacitor COUT=1nF is recommended to attenuate RF noise.

In the following chapters the main features, some typical waverforms and the protection behavior

of the ITS4060S-SJ-N is shown. For further details please refer to application notes on the Infineon homepage.

Note:

This is a very simplified example of an application circuit. The function must be verified in the real

application.

Data Sheet

15

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Application information

6.1

Special feature description

Supply over voltage:

Supply reverse voltage:

ITS4060S-SJ-N

V_S

5-8

R_IN

IN

I_Rev

2

4

2

ZD_IN

I_IN

ZD_IN

I_IN

ZD_SAZ

NC

4

OUT

R_OUTPD

3

I_Rev1

1

GND

Z_L

R_GND

I_Rev2

If over-voltage is applied to the V_S-Pin:

Voltage is limited to V_ZDSAZ; current can be calculated:

I_ZDSAZ= (V_S– V_ZDSAZ) / R_GND

If reverse voltage is applied to the device:

1.) Current via load resistance RL:

I_Rev1= (V_Rev– V_FDS) / R_L

2.) Current via Input pin IN and dignostic pin ST :

I_Rev2= I_ST+I_IN~ (V_Rev–V_CC)/R_IN+(V_Rev–V_CC)/R_ST1,2

Current I_STmust be limited with the extrernal series

resistor R_STS. Both currents will sum up to:

I_Rev= I_Rev1+ I_Rev2

A typical value for RGND is 150Ω.

In case of ESD pulse on the input pin there is in both

polarities a peak current I_INpeak~ V_ESD/ R_IN

Drain-Source power stage clamper V_DSCL

:

Energy calculation:

ITS4060S-SJ-N

V_S

5-8

R_IN

IN

E_Batt

2

4

2

4

ZD_IN

I_IN

ZD_IN

I_IN

ZD_SAZ

NC

E_Load

OUT

R_OUTPD

3

1

I_L

E_L

E_R

L_L

R_L

GND

L_L

R_GND

When an inductive load is switched off a current path must be

established until the current is sloped down to zero (all energy

removed from the inductive load). For that purpose the series

combination Z_DSCLis connected between Gate and Drain of the

power DMOS acting as an active clamp.

When the device is switched off, the voltage at OUT turns

negative until V_DSCLis reached.

Energy stored in the load inductance is given by :

E_L= I_L²*L/2

While demagnetizing the load inductance the energy

dissipated by the Power-DMOS is:

E_AS= E_S+ E_L– E_R

With an approximate solution for R_L=0Ω:

The voltage on the inductive load is the difference between

V_DSCLand V_S.

E_AS= ½ * L * I_L² * {(1- V_S/ (V_S- V_DSCL)

Figure 5

Special feature description

Data Sheet

16

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Application information

6.2

Typical application waveforms

General Input Output waveforms:

Waveforms switching a resistive load:

V_IN

H

L

t

V_S

V_OUT

+V_S

V_DS

90%

70%

SR_OFF= dV/dt

V_OUT

40%

30%

SR_ON= dV/dt

10%

0

t_ON

t_OFF

t

I_L

0

OFF

ON

OFF

ON

OFF

ON

OFF

Waveforms switching a capacitive load:

Waveforms switching an inducitive load :

V_IN

H

L

t

V_OUT

~ V_S

0

t

I_L

I_LSC

I_L

0

t

OFF

ON

OFF

ON

OFF

ON

OFF

ON

Figure 6

Typical application waveforms of the ITS4060S-SJ-N

Data Sheet

17

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Application information

6.3

Protection behavior

Overtemperature concept:

Overtemperature behavior:

V_IN

H

L

T_jRestart

T_jTrip

t

V_OUT

ON

heating

up

0

t

T_J

T_jTrip

OFF

cooling

down

T_J

T_HYS

Device

Status

T_HYS

Normal

Toggling

Overtemperature

t

OFF

ON

OFF

ON

OFF

Waveforms turn on into a short circuit :

Waveforms short circuit during on state :

V_IN

H

V_IN

H

L

t

V_OUT

0

t

I_peak

I_L

I_LSCP

Controlled

by the

current limit

by the

current limit

I_LSCR

circuit

t_m

t_SCOFF

0

t

Normal

operation

OFF

OUT shorted to GND

Overloaded

Shut down by overtemperature and

restart by cooling (toggling)

Shut down by overtemperature and

restart by cooling (toggling)

Figure 7

Protective behavior of the ITS4060S-SJ-N

Data Sheet

18

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Package information

7

Package information

0.35 x 45°

1)

4_-0.2

C

1.27

B

0.1

SEATING PLANE

±0.25

0.64

+0.1 2)

-0.06

0.41

±0.2

6

M

0.2

A

A B 8x

0.2

C 8x

8

5

1

4

1)

5_-0.2

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Lead width can be 0.61 max. in dambar area

Figure 8

PG-DSO-8¹⁾

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

1) Dimensions in mm

Data Sheet

19

Rev 1.1

2019-07-25

Smart high-side NMOS-power switch

ITS4060S-SJ-N

Revision history

8

Revision history

Revision Date

Changes

2019-07-25 Datasheet updated:

- ESD ratings for HBM updated according ANSI/ESDA/JEDEC JS-001

1.10

1.0

- Editorial changes

12-09-01

Datasheet release

Data Sheet

20

Rev 1.1

2019-07-25

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2019-07-25

Published by

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

Infineon Technologies AG

81726 Munich, Germany

Please note that this product is not qualified

according to the AEC Q100 or AEC Q101 documents of

the Automotive Electronics Council.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Z8F51106907

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.


型号：	ITS4060S-SJ-N
厂家：	Infineon
描述：	高边功率开关，集成了垂直功率 FET，提供嵌入式保护和诊断功能。开关
文件：	总21页 (文件大小：736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ITS4060S-SJ-N [INFINEON]

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