OPTIGA TRUST CHARGE AUTO [INFINEON]
OPTIGA™ Trust Charge Automotive is a highly optimized solution for in-car wireless charging up to 15 W. This solution also offers AEC Q100 automotive qualification. It enables manufacturers of in-car wireless chargers to develop chargers compliant with the latest Qi 1.3 specification.;
| 型号： | OPTIGA TRUST CHARGE AUTO |
| 厂家： | 
Infineon |
| 描述： | OPTIGA™ Trust Charge Automotive is a highly optimized solution for in-car wireless charging up to 15 W. This solution also offers AEC Q100 automotive qualification. It enables manufacturers of in-car wireless chargers to develop chargers compliant with the latest Qi 1.3 specification. |
| 文件： | 总38页 (文件大小：1901K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLS37CSAE20TC
OPTIGA™ Trust Charge Automotive
Datasheet
Trusted authentication for Qi charging
Easy-to-integrate solution for Qi authentication in automotive wireless charging
applications
Devices
SLS37CSAE20TC
This document describes a solution for Qi authentication. The Qi standard is
issued by the WPC (http://www.wirelesspowerconsortium.com). Please refer
to WPC website for protocol details. Requirements for this Provisioned
Secure Storage Subsystems are also defined in the Manufacturer CA
Agreement between WPC and the provider of the HSM. This agreement may
be confidential.
Key features
SLS37CSAE20TC Qi authentication solution
Easy integration
•
•
•
•
•
Full turnkey solution for authentication for wireless charging (Qi 1.3 and higher)
Full system integration support
Customer specific certificate provided (provisioning)
Host code and application notes for common host controller available
Evaluation kit available
Certificates and cryptographic algorithms
•
•
•
X.509/WPC certificate format supported
Authentication based on ECDSA NIST-P256
Cryptography support: ECC256, RNG (GET_RANDOM), SCP03
Other key features
•
•
•
•
•
SPI GP protocol
Secure Channel over SPI using GlobalPlatform SCP03 (optional)
In-field Update Mechanism (optional)
32 pin VQFN Package (5 mm x 5 mm)
AEC-Q100 REV.G (Grade 2)
Deliverables
•
Secure Storage Subsystem in line with Qi Specification
•
Provisioned with device-unique key material and certificate(s) (in certified manufacturing site, Drivers and
host softare for integration with host controller)
WPC Qi compliant certificate chain
•
Infineon offers the service to act as a "WPC Manufacturer CA". Infineon will create Manufacturer
CA certificates for Secure Storage Subsystems in Qi certified devices; Creation and loading of unit
specific keys and certificates will take place in certified and audited production sites
Security certification
Hardware platform certified according to Common Criteria Protection Profile (PP0084)
•
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Revision 1.0
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OPTIGA™ Trust Charge Automotive
Datasheet
Target applications
Hardware
•
•
•
•
Tamper resistant security controller providing highest proven assets protection
High performance crypto accelerator
Shielding and sensors against physical and logical attacks, internal memory and bus encryption
Memory
-
Based on reliable, certifiable SOLID FLASH™ NVM technology and protected by encryption and
additional error detection
-
17 years of data retention
•
•
High-speed SPI interface up to 10 MHz
Single voltage supply from 1.62 V to 3.6 V
Target applications
SLS37CSAE20TC is a provisioned secure storage subsystem as defined by the Qi version 1.3 (and higher)
standard. It offers core functionality for the authentication procedure to establish and verify the authenticity of
a certified Power Transmitter to a Power Receiver. Being AEC-Q100 REV.G (Grade 2) qualified, SLS37CSAE20TC is
optimized for use in automotive applications.
Figure 1 shows simplified the components of a power transmitter and power receiver according to the Qi
authentication protocol.
Figure 1
Exemplary Wireless Charging System Architecture
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Datasheet
About this document
About this document
Scope and purpose
This datasheet provides an overview of the hardware, the softare features and functionalities and information
about the package characteristics of the OPTIGA™ Trust Charge Automotive.
Note:
OPTIGA™ Trust Charge Automotive secure storage subsystem is also referred to as HSM or
SLS37CSAE20TC.
Intended audience
This datasheet is primarily intended for system developers. Target customers are automotive Original
Equipment Manufacturers (OEMs), their Tier 1 suppliers as well as softare partners.
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Datasheet
Table of contents
Table of contents
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Main features and benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip side hardware features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip side softare features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Infineon OPTIGA™ Trust Charge Automotive host softare package . . . . . . . . . . . . . . . . . . . . . . . . 11
Applications and use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Abbreviations in pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pad-to-signal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CAD files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
4
HSM firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5
5.1
5.2
5.2.1
5.2.2
5.2.2.1
5.3
5.3.1
5.3.2
5.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operational characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Particular interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GPIO interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Storage and transport conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.5
5.6
6
6.1
6.1.1
Package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Table of contents
6.1.2
6.1.3
6.1.4
Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Tape and reel packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Production sample marking pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Datasheet
List of tables
List of tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Not connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GPIO operation supply and input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GPIO DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
GPIO AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DC characteristics for 3.3 V supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC characteristics for 1.8 V supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC characteristics for 1.8 V and 3.3 V supply voltage range (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Storage and transport conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Marking table for PG-VQFN-32-13 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Datasheet
List of figures
List of figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Exemplary Wireless Charging System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
OPTIGA™ Trust Charge Automotive Softare Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block diagram of the HSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PG-VQFN-32-13 package layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recommended power-up behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing diagram Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PG-VQFN-32-13 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PG-VQFN-32-13 package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PG-VQFN-32-13 tape and reel packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PG-VQFN-32-13 sample marking pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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1 General description
1
General description
1.1
Overview
The Infineon SLS37CSAE20TC OPTIGA™ Trust Charge Automotive is a provisioned secure storage subsystem in
line with the WPC Qi 1.3 (and higher) standard. OPTIGA™ Trust Charge Automotive offers core functions for the
authentication of a Qi Power Transmitter to a Qi Power Receiver. Being based on a highly-secured, tamper
resistant security controller with highest proven asset protection, this secure storage subsystem protects the
private key that is associated with the public key in the Product Unit Certificate of Qi certified products and
offers functions to prove the authenticity via ECDSA signing operations.
The hardware architecture is based on 32-bit ARM® SecureCore® SC300 CPU with an additional high
performance asymmetric cryptographic engine and the latest generation of an hardware co-processor for
symmetric cryptography.
The OPTIGA™ Trust Charge Automotive herein called Provisioned Secure Storage Subsystem, is interfacing to a
host processor via SPI. With the OPTIGA™ Trust Charge Automotive hardware certification according to Common
Criteria (CC) EAL6+ high and AEC-Q100 (Grade 2) qualification, it is optimized for Automotive Security, meeting
both the requirements of the harsh environment in the automotive industry as well as the highest security
levels for the implementation of security and cryptography in cars. In addition, it fully meets the requirements
for a Provisioned Secure Storage Subsystem in line with the WPC Qi Specification version 1.3 and higher.
The CC certificate can be found at https://www.tuv-nederland.nl/common-criteria/certificates.html by
searching for the Hardware Identifier IFX_CCI_00005Ah and referring to the latest CC certificate.
The Qi standard is issued by the WPC (www.wirelesspowerconsortium.com). Please refer to WPC website
for protocol details. Requirements for this Provisioned Secure Storage Subsystems are also defined in the
Manufacturer CA Agreement between WPC and the provider of the Qi authenticator. This agreement may be
confidential.
SLS37CSAE20TC comes pre-programmed with Infineon OPTIGA™ Trust Charge Automotive firmware and is
ready-to-use.
Major blocks of the OPTIGA™ Trust Charge Automotive firmware in SLS37CSAE20TC are the embedded
operating system and the Qi authentication protocol. In combination, they are providing high performance
functionality including cryptographic operations (e.g. ECDSA signature generation), certificate and key storage/
management. Both, the Qi authentication and the underlying operating system, are based on the latest WPC
standards and market requirements. This softare is developed according to secure coding standards and
security certifications.
For ease of use and faster time-to-market the SLS37CSAE20TC is complemented with a Host Softare Package.
This softare package encompasses demo code to be included into the softare running on the host- or
application processor the SLS37CSAE20TC is connected to intending to facilitate an easy integration.
Within this setup SLS37CSAE20TC, provides the host-processor with secured storage of private keys and
performs the respective cryptographic operations.
This includes but is not limited to:
•
•
•
•
ECC private key management (generation, import, and deletion)
ECDSA signature generation
Storage of private keys and certificate data
Infineon PKI provides customer-individual keys enabling a secured pairing between SLS37CSAE20TC and
the respective host processor as well as secured in-field updates
Figure 1 shows a typical wireless charging system. The SLS37CSAE20TC in combination with the Host Softare
Package provide prepared communication messages according to the WPC Qi 1.3 Authentication Protocol.
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Datasheet
1 General description
1.2
Main features and benefits
Easy integration
•
•
•
•
•
Full turnkey solution for Qi authentication for wireless charging
Full system integration support
Customer and chip unique certificates provided (provisioning)
Host code and application notes for common host controllers available
Evaluation kit available
Security features
•
Tamper resistant hardware platform enabling secured key storage and trusted execution of the respective
cryptographic operations
•
•
•
X.509 certificate format according to the WPC Qi 1.3 supported
Authentication based on ECDSA NIST-P256
Cryptography support: ECC256, RNG (GET_RANDOM), SCP03
Key features
•
Optimized for use in automotive Qi certified systems, i.e. harsh automotive environments as well as highest
security levels
•
•
•
•
•
SPI GP protocol
Secure Channel over SPI using GlobalPlatform SCP03
In-field Update Mechanism
VQFN32 package
AEC-Q100 REV.G Grade 2
SLS37CSAE20TC is a Provisioned Secure Storage Subsystem in line with the WPC Qi version 1.3 standard. It is
a plug-and-play security solution that allows manufacturers of Qi certified devices to implement the standard
compliant (WPC Qi version 1.3 and higher) authentication procedure with very limited additional efforꢀ in
softare development and system integration and thus helps to reduce the total cost of ownership of the
complete system.
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1 General description
1.2.1
Chip side hardware features
•
•
32-bit ARM® SecurCore® SC300 @100 MHz
Secured storage inside the security controller leveraging SOLID FLASH™ which combines flexible flash
memory technology with a sophisticated security mechanism and highest reliability
•
•
•
•
•
•
Ultra Low Power design CMOS technology
SPI Interface up to 10 MHz
Symmetric co-processor (AES)
Asymmetric co-processors: High Performance Cryptographic Engine (Crypto@2304T) for ECC calculations
True and Pseudo Random Number Generator
Hybrid Random Number Generation (TRNG and PRNG) according to latest BSI AIS20/31 and NIST SP800- A
and B statistical tests
•
•
•
•
•
•
•
•
•
•
•
Supply voltage range: 1.62 V to 3.63 V
Extended temperature range: -40°C to +105°C
All memories are protected by hardware Error Correction Code and Error Detection Code
Security Sensors (Frequency, Light, Temperature, Glitch, Voltage)
Unique chip tracking number stored into each chip
High Endurance
Data retention of 17 years
Qualification according to AEC-Q100 (Grade 2)
PPAP documentation
ESD protection 2 kV (HBM)
Package: VQFN32-13 SMD package (5 mm x 5 mm), CAD files available on request
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1 General description
1.2.2
Chip side softare features
The OPTIGA™ Trust Charge Automotive application of SLS37CSAE20TC exposes its features to the host by
providing an APDU Command Interface (API).
This API includes a set of features including reporting, management, storage and crypto functionalities required
for the WPC Qi 1.3 Authentication protocol including but not limited to the following:
•
•
•
•
•
ECC key pair generation on the chip
ECDSA sign
NIST P-256/P-384
Secured storage for up to 4 private keys
Secured storage for up to 4 certificate chains – each 2048 Bytes with configurable access conditions per
user (write/read/change)
•
•
RNG (GET_RANDOM)
Secure Channel Protocol 03 (SCP03) based on GlobalPlatform Card Specification v2.3 – Amendment D
Version 1.1.2
•
Authentication scheme and user rights management including:
-
-
Differenꢀ users with configurable access rights
Each user with key/password enabling dedicated encrypted and authenticated messaging channel
(based on AES-256-CBC and AES-256-CMAC)
•
•
Life cycle management: Supporting differenꢀ life cycle states with differenꢀ access conditions for each state
and transition
Secured and protected in-field update mechanism with rollback-prevention
-
Minimal downtime during firmware update:
-
-
Fast image signature verification
Fast verified image installation (replaces current image)
-
Data (private keys and certificate chains) stored in NVM is not impacted by the firmware update
SPI Device Drivers and Protocols
•
SPI protocol implementing "GlobalPlatform APDU Transport over SPI/I2C Version 1.0" standard
•
APDU compatible with ISO/IEC 7816-4: 2013
1.2.3
Infineon OPTIGA™ Trust Charge Automotive host softare package
For ease of integration OPTIGA™ Trust Charge Automotive offers a host softare package abstracting its
functionality and offering the corresponding functions to a host controller. The host softare is developed with
high re-usability in mind. Therefore the integration is split into two parts:
•
The platform-independent core (OPTIGA™ Trust Charge Automotive – Host Softare.zip) contains the main
logic for the OPTIGA™ Trust Charge Automotive host integration as well as examples on how to use the
provided API
It uses a custom platform abstraction layer (PAL) to be as generic as possible. When porting the integration
to a new hardware platform the core can be reused as is.
•
Platform-specific integrations (for example: OPTIGA™ Trust Charge Automotive – Host Softare – AURIX™
TC3xx.zip) build on top of the core and add platform-specific implementations of the PAL
To be able to use the OPTIGA™ Trust Charge Automotive host integration you will at least need the core package
as well as a platform integration matching your desired host platform and toolchain.
For more information on the core package please refer to its provided documentation. For an overview of the
available platform integrations refer to your Infineon downloads or contact Infineon sales representative.
An overview of the components of the host softare package is shown in Figure 2.
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1 General description
SPI
SLS37CSAE20TC Hardware
Figure 2
OPTIGA™ Trust Charge Automotive Softare Stack
Figure 2 shows a generic wireless charging system, the middle section represents the code running on the host
processor (OPTIGA™ Trust Charge Automotive host softare package), the section on the right side reflects the
softare or firmware residing on the chip (SLS37CSAE20TC).
The OPTIGA™ Trust Charge Automotive Host Softare Package consists of a demo module, which shows how
to integrate and use the security controller or the target wireless charging system on a host platform. The Host
Softare Package is delivered as demo source code for the Evaluation Kit. Due to the modular approach, it is
easy to use, to adapt or to integrate in other embedded systems.
Features
•
Complete OPTIGA™ Trust Charge Automotive API Library with access to all APDU commands delivered as
C source code including SPI protocol implementation and GlobalPlatform Secure Channel Protocol 03
(SCP03)
•
•
Example scripts for Initialization, WPC Qi Authentication messages preparation Application Note, In-Field
Update, etc. delivered as C source code
Wrapper functions for Host-side crypto (mbedTLS) and Host SPI driver for easy porting onto other
platforms
1.3
Applications and use cases
The Infineon security controller is a Provisioned Secure Storage Subsystem in line with WPC Qi version 1.3 (and
higher) and as such is a turnkey authentication solution offering core functions for the authentication of a Qi
certified Power Transmitter to a Power Receiver for the wireless charging use case.
Power Transmitter authentication according to the WPC Qi Authentication
The secure storage subsystem offers core functions for the authentication procedure of a Qi certified power
transmitter according to the latest WPC Qi 1.3 Specification. Functions include, but are not limited to, secured
storage of ECC private keys, Product Unit Certificate(s) and related certificate chain(s) and ECDSA signature
generation as core function in order to prove the authenticity of a Qi certified device. Each chip has up to 4
private key and 4 file slots to store WPC Qi compliant certificate chains.
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2 Block diagram
2
Block diagram
Figure 3 shows the hardware block diagram of the HSM.
Core
Memories
Coprocessors
Security Peripherals
Sensors
ISS
Crypto
SCP
ROM
RAM
UMSLC
&
NVM
@2304T
Filters
CPU
Cache
MED
MPU
NVIC
IMM
Clock and
Power
Management
Timer
Tick
Counter
Hybrid
RNG
CRC
&
WDT
SPI
GPIO
GPIO Mapping
Control
Peripherals
Figure 3
Block diagram of the HSM
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3 Pin description
3
Pin description
The pad usage of the HSM in a 32 pin VQFN package is illustrated by the next figure and table. A detailed
description of the package can be found in Package description.
3.1
Abbreviations in pin description
The abbreviations listed here are used in the package description to classify each pin.
Table 1
Abbreviations for pin type
Abbreviation
Description
DNC
I
Do Not Connect. Must be lef floating. Please do not connect externally
Input. Digital levels
O
Output. Digital levels
I/O
PWR
GND
NCI
Input/Output bi-directional. Digital levels
Power
Ground
Not Connected Internally. May be connected externally
Table 2
Abbreviations for buffer type
Abbreviation
GPIO_I
Description
GPIO input pad
GPIO output pad
SPI input pad
SPI output pad
GPIO_O
SPI_I
SPI_O
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3 Pin description
3.2
Pad-to-signal reference
For the integration of OPTIGA™ Trust Charge Automotive onto a dedicated PCB board, the power supply,
ground, the SPI interface pins and the additional pins have to be connected as shown in the following layout
and tables:
5
24 23 22 21 20 19 18 17
17 18 19 20 21 22 23 24
16
NC
NC
25
26
27
28
29
30
31
32
VSSP
SPI-MISO
NC
15
14
13
12
11
10
9
NC
NC
NC
(C)
VDDP1
VDDP2
NC
NC
NC
NC
VSSP
VSSP
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
Figure 4
Table 3
PG-VQFN-32-13 package layout
I/O signals
Pad
Name
Pin type
Buffer type Signal function/remark
2
Sense-SS
I
GPIO_I
Shortcut to Pin 22 (SPI-SS sensing). Reserved for
future use.
3
7
SPI-IRQ
O
I
GPIO_O
Interrupt Request, active high, host interrupt
triggered on rising edge (SPI response ready)
This pin is optional and does not have to be used. In
this case, do not connect the pin and leave the pin
floating
RST
GPIO_I
SPI_I
Reset, active low,
Evaluated by softare afer start-up,
Internal pull-up
This pin is optional and does not have to be used. In
this case, do not connect the pin and leave the pin
floating
21
SPI-SCLK
I
SPI Clock
The SPI clock signal. Only SPI mode 0 (CPOL = 0, CPHA
= 0) is supported by the device.
(table continues...)
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3 Pin description
Table 3
(continued) I/O signals
Pad
Name
Pin type
Buffer type Signal function/remark
22
SPI-SS
I
SPI_I
Slave Select, active low
The SPI chip slave select signal
No internal pull-up
23
26
SPI-MOSI
SPI-MISO
I
SPI_I
SPI Master Out Slave In (SPI Data)
SPI data which is received from the master
O
SPI_O
SPI Master In Slave Out (SPI Data)
SPI data which is sent to the SPI bus master
Table 4
Pad
Power supply
Name
Pin type
Buffer type Signal function/remark
9, 17, 25, VSSP
32
GND
-
Power supply: Common ground reference (VSS)
12
VDDP1
VDDP2
PWR
PWR
-
-
Power supply: Chip power
Power supply: Chip power
24, 29
Table 5
Pad
Not connected
Name
Pin type
Buffer type Signal function/remark
6, 19, 20, NC
27, 28
DNC
-
Do Not Connect
All pins must not be connected externally (must be lef
floating).
1, 4, 5, 8, NC
10, 11, 13,
NCI
-
Not Connected Internally
All pins are not connected internally (can be
connected externally).
14, 15, 16,
18, 30, 31
Note:
The exposed die pad referenced as (C) in Figure 4 must be connected to the common ground reference
(GND) for heat distribution.
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3 Pin description
3.3
Typical schematic
Figure 5 shows the typical schematic for the HSM. The power supply pins should be bypassed to GND with
capacitors located close to the device.
VCC
100nF
VCC
GND
1
x
4
x
5
x
6
x
2
3
7
8
10
11
13
14
15
16
18
19
20
27
28
30
31
Sense-SS (RFU)
SPI-IRQ
RST
x
x
x
x
x
x
x
x
x
x
x
x
x
x
GPIOa
GPIOb
OPTIGA™
Trust Charge
Automotive HSM
VQFN-32-13
x not
connected
SPI Master
21
22
23
26
SCLK
SS
MOSI
MISO
SPI-SCLK
SPI-SS
SPI-MOSI
SPI-MISO
(C)
GND
Backside
GND
GND
Figure 5
Typical schematic
3.4
CAD files
CAD files for design-in of the HSM are available on request.
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4 HSM firmware
4
HSM firmware
The HSM firmware is described in detail in the corresponding chapter of the OPTIGA™ Trust Charge Automotive
databook.
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5 Electrical characteristics
5
Electrical characteristics
This section summarizes certain electrical characteristics of the controller. It provides operational
characteristics as well as electrical DC and AC characteristics and particular interface characteristics.
Note:
Note:
TA as given for the operating temperature range of the controller unless otherwise stated.
All currents flowing into the controller are considered positive.
Note:
VCC is connected to VDDP1 and VDDP2. Throughout this document VDDP1 and VDDP2 will simply be
referred to as VCC.
5.1
Absolute maximum ratings
Table 6
Absolute maximum ratings
Parameter
Symbol
Values
Min. Typ.
Unit Note or test condition
Max.
Operating temperature,
ambient
TA
−40
–
+105
°C
TJ must be kept
Junction temperature
Supply voltage
TJ
–
–
–
–
+110
7.0
°C
V
–
–
VCC
−0.3
−0.3
Input voltage,
VIN_GPIO
7.0
V
signal group GPIO
Input voltage,
VIN_SPI
−0.5
–
7.0
V
–
signal group SPI
ESD robustness HBM
ESD robustness CDM
Latchup immunity
VESD,HBM
VESD,CDM
Ilatch
–
–
–
–
–
–
2000
750
V
V
According to EIA/JESD22-
A114-B
According to ESD Association
Standard STM5.3.1 - 1999
150
mA According to EIA/JESD78
105°C, class II
Note:
Stresses exceeding the values listed under 'Absolute maximum ratings' may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or at any other conditions whose values exceed those indicated in the operational sections of this
document is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability, including NVM data retention and write/erase endurance.
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5 Electrical characteristics
5.2
Operational characteristics
This section specifies the AC and DC characteristics of the controller, along with details relating to the specific
interfaces provided by the controller.
5.2.1
DC electrical characteristics
Table 7
DC characteristics
Parameter
Symbol
Values
Unit
V
Note or test condition
Min.
2.97
1.62
–
Typ.
3.3
Max.
3.63
1.98
–
Supply voltage
Supply current
VCC
Overall functional range
1.8
IVCC_Active
16.0
mA
During startup sporadic
spikes up to 32 mA might
occur
Supply current sleep
IVCCS_Sleep
–
120
200 μA
RST inactive (= VCC),
SPI-IRQ inactive (= GND),
SPI-SS inactive (= VCC),
SPI-MOSI, SPI-MISO and SPI-
SCLK do not care
Note:
Current consumption does not include any currents flowing through resistive loads on output pins!
5.2.2
AC electrical characteristics
Table 8
AC characteristics
Parameter
Symbol
Values
Typ.
–
Unit Note or test condition
Min.
Max.
VCC rampup time
tVCCR
1
–
μs
0 to 100% of VCC target voltage
ramp1)
1)
Please refer to Power-up considerations
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5 Electrical characteristics
5.2.2.1
Power-up considerations
The rampup times given in AC electrical characteristics apply under the assumption of a linear rise in
voltage from 0% to 100% of the target voltage level. However, owing to possible current spike effecꢀs, it is
recommended to follow the voltage characteristics shown in the figure below.
VCC
6
Vcc,max
To avoid chip inrush
current, VCC must rise at a
rate of less than 1 V/µs
+/- 10% VCC range:
1.
5
4
3
3. Fast VCC transients are allowed in this
voltage range during chip operation
5
4,5
4
Node VCC has to decrease
strictly monotonically
Recommendation: An active shutdown
device should discharge this power
node down to the “POWER-OFF
region“.
Node VCC has to increase
2.
3,5
3
strictly monotonically
4.
Vcc,min
2,5
2
2
It is good design practice to connect an external capacitor with a low
equivalent series resistor between pin VCC and pin GND. This low
impedance device combined with a continuous current from the external
power source has to avoid dynamic VCC voltage changes or voltage
plateaus. A strictly monotonic VCC power ramp should be the result.
1,5
1
1
next chip startup
0,5
0
100 mV
“POWER-OFF region“
0
0,5
1
1,5
2
2,5
3
0 V
0
0
1
2
3
4
5
6
VCC must remain in the “POWER-OFF
region“ for an extended period
(recommended time > 100 µs)
5.
Figure 6
Recommended power-up behavior
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5 Electrical characteristics
5.3
Particular interface characteristics
This chapter provides electrical characteristics with respect to operation of particular interfaces of the
controller.
Note:
Unless otherwise stated, all values in this section are measured at the pins of the used package,
i.e., the resistance, capacitance and inductance, for example, of the package and the bond wires are
already included in these values!
5.3.1
GPIO interface characteristics
The electrical characteristics of the GPIOs including restrictions with respect to the maximum sink/source
currents for all GPIOs of the controller are given below.
Table 9
GPIO operation supply and input voltages
Parameter
Symbol
Values
Typ.
–
Unit Note or test condition
Min.
Max.
GPIO pad input voltage VIN_GPIO
−0.3
VCC + 0.3
V
VCC1) is in the operational supply
range.
1)
Table 7
Table 10
GPIO DC electrical characteristics
Parameter
Symbol
Values
Unit Note or test condition
Min.
Typ.
Max.
Input current, pull-up
(weak) enabled
IPUW
−3
–
−20
μA
μA
kΩ
μA
0 V ≤ VIN_GPIO ≤ VCC − 0.5 V
0.5 V ≤ VIN_GPIO ≤ VCC
Input current, pull-down IPDW
(weak) enabled
3
–
–
–
20
5.5
2
Pull-up (strong)
resistance
RPUS
ILI
2.5
−2
0 V ≤ VIN_GPIO ≤ VCC − 0.5 V
Input leakage current
Pull-up/down off, output
stage off;
0 V ≤ VIN_GPIO ≤ VCC
Input low voltage
Input high voltage
Output low voltage
VIL
−0.3
–
–
–
–
–
–
–
0.3 * VCC
V
VIH
VOL
0.7 * VCC
VCC + 0.3
V
–
0.3
0.4
–
V
IOL = 1 mA
–
V
IOL = 4 mA, VCC ≥ 2.7 V
IOH = −1 mA
Output high voltage
Input capacitance
VOH
VCC − 0.3
VCC − 0.4
–
V
–
V
IOH = −4 mA, VCC ≥ 2.7 V
CIN
10
pF
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5 Electrical characteristics
Table 11
GPIO AC electrical characteristics
Parameter
Symbol
Values
Typ.
3.5
Unit Note or test condition
Min.
Max.
Output signal rise time
Output signal fall time
tr
–
15.0
ns
ns
10% VCC to 90% VCC;
CLOAD = 15 pF, pull-up/down
off, no DC load.
tf
–
3.5
15.0
90% VCC to 10% VCC;
CLOAD = 15 pF, pull-up/down
off, no DC load; Slew
Rate Control OFF (default
operation mode).
Output signal fall time
Output signal fall time
tf
30.0
15.0
50.0
25.0
–
–
ns
ns
70% VCC to 30% VCC;
CLOAD = 50 pF, pull-up/down
off, no DC load; slower slew
rate.
tf
70% VCC to 30% VCC;
CLOAD = 50 pF, pull-up/down
off, no DC load; faster slew
rate.
GPIO input path
low-pass filter
fCUTOFF
20
–
–
40
25
MHz 50/50 duty cycle.
1)
GPIO input path
low-pass filter
tCUTOFF
12.5
ns High or low pulse width.
1)
Spikes shorter than min. are filtered, spikes longer than max. are not filtered.
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5 Electrical characteristics
5.3.2
SPI interface characteristics
The HSM operates as SPI Slave. The clock signal is received from an external master and synchronizes the data
transfer. Transmission and reception speeds are not depending on the internal system clock.
The HSM is configured for SPI mode 0 where polarity and phase is set to 0.
The assertion of the slave select signal starts the transfer. The rising clock edge is used to latch the incoming
data bit while the falling clock edge shifs the next data bit onto the serial bus.
The following section describes the electrical characteristics of the SPI slave mode.
Table 12
Serial transfer mode
Polarity Phase
SPI
Description
Mode
0
0
0
Signal transmission through MISO and MOSI pads is activated on assertion
of slave select signal (green arrow in Figure 7). Data is latched by the receiver
on the rising clock edge and is shifed by the transmitter on the falling clock
edge. The idle state of the clock is low.
tSCLK
tSSH
SCLK
SPI Clock (Mode 0)
tSU
MOSI
Data Input
tH
tV
tSSDO
MISO
Data Output
tSSS
tSS
SS
Slave Select
Input Sample
Points
Figure 7
SPI Mode 0
Note:
A detailed timing diagram is shown in Figure 8 and the respective values are given in Table 15.
Table 13
DC characteristics for 3.3 V supply voltage range
Parameter
Symbol
Values
Unit
Note or test condition
Min.
2.70
Typ.
Max.
3.63
Pad supply voltage
Input high voltage
Input low voltage
Output high voltage
VCC
VIH
VIL
–
–
–
–
–
V
V
V
V
V
0.7 * VCC
−0.5
VCC + 0.5
0.3 * VCC
–
VOH
VOL
0.9 * VCC
–
IOH = −100 µA
IOL = 1.5 mA
Output low voltage
0.1 * VCC
(table continues...)
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5 Electrical characteristics
Table 13
(continued) DC characteristics for 3.3 V supply voltage range
Parameter
Symbol
Values
Unit
Note or test condition
Min.
−4
Typ.
Max.
Pad leakage SPI input ISIL
–
–
–
–
4
–
4
–
µA
0 V < VPAD < VCC
pads
−1.5
−4
mA
µA
−0.5 V < VPAD < VCC + 0.5 V
0 V < VPAD < VCC
Pad leakage SPI output ISOL
pads
−3
mA
−0.5 V < VPAD < VCC + 0.5 V
Table 14
DC characteristics for 1.8 V supply voltage range
Parameter
Symbol
Values
Unit
Note or test condition
Min.
1.62
0.7 * VCC
−0.3
0.9 * VCC
–
Typ.
Max.
Pad supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
VCC
VIH
VIL
–
–
–
–
–
–
–
–
–
1.98
V
VCC + 0.3
V
0.3 * VCC
V
VOH
VOL
–
V
IOH = −100 µA
0.1 * VCC
V
IOL = 1.5 mA
Pad leakage SPI input ISIL
pads
−4
4
–
4
–
µA
mA
µA
mA
0 V < VPAD < VCC
−1
−0.3 V < VPAD < VCC + 0.3 V
0 V < VPAD < VCC
Pad leakage SPI
output pads
ISOL
−4
−1
−0.3 V < VPAD < VCC + 0.3 V
Table 15
AC characteristics for 1.8 V and 3.3 V supply voltage range (Mode 0)
Parameter
Symbol
Values
Unit
Note or test condition
Min.
Typ.
Max.
10
SCLK frequency
fSCLK
–
–
–
–
–
MHz
MHz
For 3.3 V supply voltage range
For 1.8 V supply voltage range
10
SCLK clock period
tSCLK_range 1/fSCLK − 5%
1/fSCLK + 5% µs
Measured at input pad voltage
of 0.5 * VCC
SCLK nominal clock
period
tSCLK
tSCLKL
tSCLKH
tSlew
–
1/
fSCLK
–
–
–
4
µs
Measured at input pad voltage
of 0.5 * VCC
SCLK low time
0.45 * tSCLK
0.45 * tSCLK
1
–
–
–
µs
Measured at input pad voltage
of 0.5 * VCC
SCLK high time
µs
Measured at input pad voltage
of 0.5 * VCC
SCLK input slew-rate
V/ns
SCLK input voltage slew-rate
measured between
0.2 * VCC and 0.6 * VCC
(table continues...)
Datasheet
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Datasheet
5 Electrical characteristics
Table 15
(continued) AC characteristics for 1.8 V and 3.3 V supply voltage range (Mode 0)
Parameter
Symbol
Values
Unit
Note or test condition
Min.
30
Typ.
Max.
SS inactive time
SS setup time
tSS
–
–
–
–
–
–
ns
ns
ns
For 3.3 V supply voltage range
For 1.8 V supply voltage range
For 3.3 V supply voltage range:
60
tSSS
30
Setup time SS to SCLK rising
edge.
60
–
–
ns
For 1.8 V supply voltage range:
Setup time SS to SCLK rising
edge.
SS hold time
tSSH
tSU
tH
5
2
3
–
–
–
–
–
–
–
ns
ns
ns
ns
Hold time SCLK falling edge to
SS inactive
MOSI setup time
MOSI hold time
Data setup time to SCLK rising
edge
–
Data hold time from SCLK
rising edge
MISO valid delay time tSSV
from SS active
28
For 3.3 V supply voltage range:
Output valid delay time from
SS active
–
–
–
–
58
21
ns
ns
For 1.8 V supply voltage range:
Output valid delay time from
SS active
MISO valid delay time tV
from SCLK edge
For 1.8 V supply voltage range
Output valid delay time from
SCLK falling edge
SCLK input tslew = 1 V/ns
MISO Cload = 30 pF
–
–
15
ns
For 3.3 V supply voltage range
Output valid delay time from
SCLK falling edge
SCLK input tslew = 1 V/ns
MISO Cload = 30 pF
MISO output disable
time
tSSDO
0
0
–
–
30
60
ns
ns
For 3.3 V supply voltage range:
Output disable time from SS
inactive
For 1.8 V supply voltage range:
Output disable time from SS
inactive
(table continues...)
Datasheet
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Datasheet
5 Electrical characteristics
Table 15
(continued) AC characteristics for 1.8 V and 3.3 V supply voltage range (Mode 0)
Parameter
Symbol
Values
Typ.
–
Unit
Note or test condition
Min.
Max.
MISO hold time
tHO
3.5
–
ns
For 1.8 V supply voltage range
Output hold time to SCLK
falling edge
SCLK input tslew = 4 V/ns
MISO Cload = 10 pF
1.5
–
–
ns
For 3.3 V supply voltage range
Output hold time to SCLK
falling edge
SCLK input tslew = 4 V/ns
MISO Cload = 10 pF
Input capacitance
(package pin)
CIN
–
–
10
30
pF
pF
Output load
capacitance
CLOAD
A bigger load capacitance will
decrease the performance.
Note:
All values and timings in Table 15 are related to pin level.
tSCLK
tSCLKH
tSCLKL
SCLK
0.6 x VCC
0.2 x VCC
Mode 0
MOSI
MISO
SS
tSLEW
tSU
tH
data
valid
data
valid
tSSV
tV
tHO
tSSDO
output valid
output valid
tSSS
tHO
tSSH
tSS
SS active
Input
sample
points
Figure 8
Timing diagram Mode 0
Datasheet
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Datasheet
5 Electrical characteristics
5.4
Thermal resistance
Table 16
Thermal resistance
Parameter
Symbol
Min.
Values
Typ.
10.1
Unit
Note or test condition
Max.
Junction to case
Rth(JC)
Rth(JC)
Rth(JA)
–
–
–
–
–
–
K/W
K/W
K/W
To exposed pad (bottom)1)
To top of package2)
35.4
1) 3)
Junction to ambient
37.2
1)
2)
3)
Not subject to production test, specified by design.
https://www.infineon.com/cms/en/product/packages/PG-VQFN/PG-VQFN-32-13/
According to JEDEC JESD 51-5, JESD 51-7 at free convection and radiation on FR4 2s2p board. Board size 76.2 mm x 114.3 mm
x 1.5 mm, 2 inner copper layers (35 µm), thermal via array under the exposed pad connected to the first inner copper layer. Also
refer to 2)
.
As shown in Table 6, a maximum junction temperature TJ of 110°C must not be exceeded. Thermal simulations
(done using the FEM softare ANSYS®) show that this junction temperature TJ limit is not reached at an ambient
temperature of 105°C when the device is mounted on a PCB according to JEDEC 2s2p (JESD 51-7, JESD 51-5).
If the device is mounted on a PCB compliant to JEDEC 1s0p (JESD 51-3), the simulation shows that due to
self-heating of the device, the maximum junction temperature is exceeded at an ambient temperature of 105°C.
5.5
Storage and transport conditions
Table 17
Storage and transport conditions
Symbol
Parameter
Values
Typ.
Unit
Min.
Max.
Storage conditions
Storage temperature
Storage humidity
Storage time
TStorage
+5
10
–
+40
75
31)
°C
RH
%
Years
Transport conditions
Transport temperature2)
TTransport
-25
–
+85
°C
1)
In reference to date code on BPL (Barcode Product Label).
BPL can be found on the Infineon packing.
Products shall be processed before the end of the maximum storage time defined above. Processing beyond expiring date may
increase the risk of reduced processability, malfunction or non-function. Such recommendations are subject to storage time and
storage conditions. Temperature, relative humidity, packing medium and environmental conditions.
short term ≤ 15 days
2)
5.6
IBIS Model
IBIS model is available on request.
Datasheet
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Datasheet
6 Package description
6
Package description
A detailed description of the package can be found under the following link:
https://www.infineon.com/cms/en/product/packages/PG-VQFN/PG-VQFN-32-13/
6.1
PG-VQFN-32-13
Note:
The drawings below are for information only and not drawn to scale. More detailed information about
package characteristics and assembly instructions is available on request.
6.1.1
Package outline
The package dimensions (in mm) of the controller in PG-VQFN-32-13 packages are given below.
Figure 9
PG-VQFN-32-13 package outline
Datasheet
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Datasheet
6 Package description
6.1.2
Package footprint
Figure 10
PG-VQFN-32-13 package footprint
6.1.3
Tape and reel packing
8
4
0.3
Index Marking
5.25
1.1
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure 11
PG-VQFN-32-13 tape and reel packing
Datasheet
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Datasheet
6 Package description
6.1.4
Production sample marking pattern
Figure 12
PG-VQFN-32-13 sample marking pattern
The black dot indicates pin 01 for the chip. The following table describes the sample marking pattern:
Table 18
Marking table for PG-VQFN-32-13 packages
Indicator
Description
Infineon
(line 1)
Manufacturer
SLS37TC
(line 2)
Abbreviation for sales code SLS37CSAE20TC
OTCXXXA
(line 3)
Short ROM code with xxx as placeholder for differenꢀ short ROM codes
Lot code, defined and inserted during fabrication, issued by the packaging site
XXH☐☐☐
(line 4)
Datasheet
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Datasheet
References
References
The following documents set out or describe specifications and/or standards referenced in the text of this
document.
[1]
[2]
[3]
[4]
GlobalPlatform Technology: APDU Transport over SPI / I2C (Version 1.0), January 2020
GlobalPlatform Technology: Secure Channel Protocol '03' - Amendment D (Version 1.2), April 2020
GlobalPlatform: Card Specification (Version 2.3.1), March 2018
ISO/IEC 7816-4: Identification cards - Integrated circuit cards - Part 4: Organization, security and
commands for interchange (Second edition), 2005-01-15
[5]
[6]
NIST FIPS 186-4: Digital Signature Standard (DSS), July 2013
RFC 2119: Bradner, Scott. "Key words for use in RFCs to Indicate Requirement Levels." RFC2119 (1997)
https://tools.ietf.org/rfc/rfc2119.txt.
[7]
Wireless Power Consortium: Qi Specification – Authentication Protocol ( Version 1.3.1, Working Draf 1),
January 2021
Datasheet
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OPTIGA™ Trust Charge Automotive
Datasheet
Glossary
Glossary
AC
Access condition
AC
Alternating Current
AEC
Automotive Electronics Council
Advanced Encryption Standard
Advanced Encryption Standard - Cipher Block Chaining
Advanced Encryption Standard - Counter with CBC MAC mode
Application Protocol Data Unit
Application Programming Interface
Barcode Product Label
AES
AES-CBC
AES-CCM
APDU
API
BPL
BSI
Bundesamt für Sicherheit in der Informationstechnik
Certificate Authority
CA
CAD
CC
Computer-Aided Design
Common Criteria
CDM
CMAC
CMOS
CPHA
CPOL
CPU
CRC
DC
Charged-Device Model
Cipher-based Message Authentication Code
Complementary Metal–Oxide–Semiconductor
Clock Phase
Clock Polarity
Central Processing Unit
Cyclic Redundancy Check
Direct Current
DNC
EAL
Do Not Connect
Evaluation Assurance Level
Elliptic Curve Cryptography
Elliptic Curve Digital Signature Algorithm
Electrostatic Discharge
ECC
ECDSA
ESD
GND
GP
Ground
GlobalPlatform
GPIO
HBM
HSM
I/O
General Purpose Input Output
Human Body Model
Hardware Security Module
Input/Output
I2C
Inter-Integrated Circuit
IBIS
IC
Input/Output Buffer Information Specification
Integrated Circuit
Datasheet
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Datasheet
Glossary
IEC
International Electrotechnical Commission
IMM
IRQ
Interface Management Module
Interrupt Request
ISO
International Organization for Standardization
Instruction Stream Signature
Message Authentication Code
Memory Encryption Device
Master In Slave Out
ISS
MAC
MED
MISO
MOSI
MPU
NCI
Master Out Slave In
Memory Protection Unit
Not Connected Internally
National Institute of Standards and Technology
Nested Vector Interrupt Control
Non-Volatile Memory
NIST
NVIC
NVM
OEM
PCB
PKI
Original Equipment Manufacturer
Printed Circuit Board
Public Key Infrastructure
Protection Profile
PP
PPAP
PRNG
PWR
RAM
RFC
RFU
RNG
ROM
RST
SCLK
SCP
SCP03
SMD
SPI
Production Part Approval Process
Pseudo Random Number Generator
Power
Random Access Memory
Request For Comments
Reserved for Future Use
Random Number Generator
Read-Only Memory
Reset
Serial Peripheral Interface Clock
Symmetric Co-Processor
Secure Channel Protocol 03
Surface-Mounted Device
Serial Peripheral Interface
Slave Select
SS
TRNG
Tx
True Random Number Generator
Transmit
Typ
Typical
Datasheet
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Datasheet
Glossary
UMSLC
VCC
User Mode Security Life Control
Supply Voltage
VQFN
WDT
Very Thin Quad Flat No Leads
Watchdog Timer
Datasheet
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Datasheet
Revision history
Revision history
Reference
Description
Revision 1.0, 2023-01-20
All
Initial release
Datasheet
36
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Datasheet
RoHS compliance
RoHS compliance
On January 27, 2003 the European Parliament and the council adopted the directives:
•
2002/95/EC on the Restriction of the use of certain Hazardous Substances in electrical and electronic
equipment ("RoHS")
•
2002/96/EC on Waste Electrical and Electrical and Electronic Equipment ("WEEE")
Some of these restricted (lead) or recycling-relevant (brominated flame retardants) substances are currently
found in the terminations (e.g. lead finish, bumps, balls) and substrate materials or mold compounds.
The European Union has finalized the Directives. It is the member states' task to convert these Directives
into national laws. Most national laws are available, some member states have extended timelines for
implementation. The laws arising from these Directives have come into force in 2006 or 2007.
The electro and electronic industry has to eliminate lead and other hazardous materials from their products.
In addition, discussions are on-going with regard to the separate recycling of certain materials, e.g. plastic
containing brominated flame retardants.
Infineon is fully committed to giving its customers maximum support in their efforꢀs to convert to lead-free and
halogen-free1) products. For this reason, Infineon's "Green Products" are ROHS-compliant.
Since all hazardous substances have been removed, Infineon calls its lead-free and halogen-free semiconductor
packages "green." Details on Infineon's definition and upper limits for the restricted materials can be found
here.
The assembly process of our high-technology semiconductor chips is an integral part of our quality strategy.
Accordingly, we will accurately evaluate and test alternative materials in order to replace lead and halogen so
that we end up with the same or higher quality standards for our products.
The use of lead-free solders for board assembly results in higher process temperatures and increased
requirements for the heat resistivity of semiconductor packages. This issue is addressed by Infineon by a new
classification of the Moisture Sensitivity Level (MSL). In a first step the existing products have been classified
according to the new requirements.
1
Any material used by Infineon is PBB and PBDE-free. Plastic containing brominated flame retardants, as mentioned in the WEEE
directive, will be replaced if technically/economically beneficial.
Datasheet
37
Revision 1.0
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Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2023-01-20
Published by
Infineon Technologies AG
81726 Munich, Germany
Important notice
Warnings
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheiꢀsgaranꢀie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
Infineon Technologies in customer’s applications.
The data contained in this document is exclusively
intended for technically trained sꢀaff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to such
application.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury.
a written document signed by
©
2023 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email:
CSSCustomerService@infineon.com
Document reference
IFX-nvm1670304102379
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