PEF3086H [INFINEON]
PCM Transceiver, 1-Func, CMOS, PQFP64, PLASTIC, MQFP-64;
| 型号： | PEF3086H |
| 厂家： | 
Infineon |
| 描述： | PCM Transceiver, 1-Func, CMOS, PQFP64, PLASTIC, MQFP-64 PC 电信 电信集成电路 |
| 文件： | 总266页 (文件大小：2773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, DS 1, August 2000
ISAC-SX
ISDN Subscriber Access
Controller
PEB/PEF 3086 Version 1.3
Transceivers
N e v e r s t o p t h i n k i n g .
Edition 2000-08-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 8/3/00.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, DS 1, August 2000
ISAC-SX
ISDN Subscriber Access
Controller
PEB/PEF 3086 Version 1.3
Transceivers
N e v e r s t o p t h i n k i n g .
PEB/PEF 3086
Revision History:
2000-08-03
DS 1
Previous Version:
Page
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEB 3086
PEF 3086
Table of Contents
Page
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1
1.2
1.3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3
3.1
3.2
Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . 31
Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Multiframe Synchronization (M-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . . 56
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
S/T Interface Delay Compensation (TE/LT-T mode) . . . . . . . . . . . . . . . 63
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . 70
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
State Machine TE and LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . 74
States (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
C/I Codes (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Infos on S/T (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
States (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.1
3.2.1.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.7.1
3.3.8
3.3.9
3.3.10
3.3.11
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2
3.5.2.1
3.5.2.2
Data Sheet
5
2000-08-03
PEB 3086
PEF 3086
Table of Contents
Page
3.5.2.3
3.5.2.4
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
C/I Codes (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Infos on S/T (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
States (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
C/I Codes (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Command/ Indicate Channel Codes (C/I0) - Overview . . . . . . . . . . . . . 89
Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Activation initiated by the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Activation initiated by the Network Termination NT . . . . . . . . . . . . . . . . 92
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Serial Data Strobe Signal and Strobed Data Clock . . . . . . . . . . . . . . 107
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MONITOR Channel Programming as a Master Device . . . . . . . . . . 116
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . 117
Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . 122
S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . 124
S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . 126
D-Channel Control in the Intelligent NT (TIC- and S-Bus) . . . . . . . . 126
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . 130
Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Mode Dependent Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
HDLC Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . 139
Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . 147
Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Access to IOM-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.7
3.7.1
3.7.1.1
3.7.2
3.7.2.1
3.7.2.2
3.7.3
3.7.3.1
3.7.3.2
3.7.3.3
3.7.3.4
3.7.3.5
3.7.3.6
3.7.4
3.7.5
3.7.5.1
3.7.5.2
3.7.5.3
3.7.5.4
3.7.6
3.8
3.8.1
3.9
3.9.1
3.9.2
3.9.2.1
3.9.2.2
3.9.3
3.9.3.1
3.9.3.2
3.9.4
Data Sheet
6
2000-08-03
PEB 3086
PEF 3086
Table of Contents
Page
3.9.5
3.9.6
3.10
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4
4.1
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
D-channel HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . 166
RFIFOD - Receive FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 166
XFIFOD - Transmit FIFO D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 166
ISTAD - Interrupt Status Register D-Channel . . . . . . . . . . . . . . . . . . . 167
MASKD - Mask Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 168
STARD - Status Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 169
CMDRD - Command Register D-channel . . . . . . . . . . . . . . . . . . . . . . 170
MODED - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
EXMD1- Extended Mode Register D-channel 1 . . . . . . . . . . . . . . . . . 172
TIMR1 - Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
RBCLD - Receive Frame Byte Count Low D-Channel . . . . . . . . . . . . 175
RBCHD - Receive Frame Byte Count High D-Channel . . . . . . . . . . . 176
TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
RSTAD - Receive Status Register D-Channel . . . . . . . . . . . . . . . . . . 177
TMD -Test Mode Register D-Channel . . . . . . . . . . . . . . . . . . . . . . . . 179
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . 179
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . 180
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . 181
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . 181
Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
TR_CONF0 - Transceiver Configuration Register 0 . . . . . . . . . . . . . . 182
TR_CONF1 - Transceiver Configuration Register 1 . . . . . . . . . . . . . . 183
TR_CONF2 - Transmitter Configuration Register 2 . . . . . . . . . . . . . . 184
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . 185
TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . 186
SQRR1 - S/Q-Channel Receive Register 1 . . . . . . . . . . . . . . . . . . . . 187
SQXR1- S/Q-Channel TX Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 188
SQRR2 - S/Q-Channel Receive Register 2 . . . . . . . . . . . . . . . . . . . . . 188
SQXR2 - S/Q-Channel TX Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 189
SQRR3 - S/Q-Channel Receive Register 3 . . . . . . . . . . . . . . . . . . . . 189
SQXR3 - S/Q-Channel TX Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . 189
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . 190
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 191
TR_MODE - Transceiver Mode Register 1 . . . . . . . . . . . . . . . . . . . . . 191
Auxiliary Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.19
4.1.20
4.1.21
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
4.3
Data Sheet
7
2000-08-03
PEB 3086
PEF 3086
Table of Contents
Page
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
ACFG1 - Auxiliary Configuration Register 1 . . . . . . . . . . . . . . . . . . . . 192
ACFG2 - Auxiliary Configuration Register 2 . . . . . . . . . . . . . . . . . . . . 192
AOE - Auxiliary Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . 194
ARX - Auxiliary Interface Receive Register . . . . . . . . . . . . . . . . . . . . 195
ATX - Auxiliary Interface Transmit Register . . . . . . . . . . . . . . . . . . . . 195
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . 196
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . 197
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . 198
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) . . . 199
BCH_CR - Control Register B-Channel Controller Data . . . . . . . . . . . 201
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0) 202
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
4.4.16
4.4.17
4.4.18
4.4.19
4.4.20
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.6
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . 204
SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . . 205
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . 206
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 208
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . 209
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . 209
SDS_CONF - Configuration Register for Serial Data Strobes . . . . . . 210
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 211
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . 211
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . 212
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 213
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 214
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . 214
Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
AUXI - Auxiliary Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . 216
AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
TIMR2 - Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
B-Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ISTAB - Interrupt Status Register B-Channel . . . . . . . . . . . . . . . . . . . 223
MASKB - Mask Register B-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 224
STARB - Status Register B-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 224
CMDRB - Command Register B-channel . . . . . . . . . . . . . . . . . . . . . . 226
4.6.1
4.6.2
4.6.3
4.6.4
Data Sheet
8
2000-08-03
PEB 3086
PEF 3086
Table of Contents
Page
4.6.5
4.6.6
4.6.7
4.6.8
MODEB - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
EXMB - Extended Mode Register B-channel . . . . . . . . . . . . . . . . . . . 228
RAH1 - RAH1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
RAH2 - RAH2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
RBCLB - Receive Frame Byte Count Low B-Channel . . . . . . . . . . . . 230
RBCHB - Receive Frame Byte Count High B-Channel . . . . . . . . . . . 230
RAL1 - RAL1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
RAL2 - RAL2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
RSTAB - Receive Status Register B-Channel . . . . . . . . . . . . . . . . . . 232
TMB -Test Mode Register B-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 233
RFIFOB - Receive FIFO B-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 234
XFIFOB - Transmit FIFO B-Channel . . . . . . . . . . . . . . . . . . . . . . . . . 234
4.6.9
4.6.10
4.6.11
4.6.12
4.6.13
4.6.14
4.6.15
4.6.16
5
5.1
5.2
5.3
5.4
5.5
5.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Parallel Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . 244
Multiframe Synchronisation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Recommended Transformer Specification . . . . . . . . . . . . . . . . . . . . . . . 250
5.7
5.7.1
5.7.2
5.8
5.9
5.10
5.11
6
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Data Sheet
9
2000-08-03
PEB 3086
PEF 3086
List of Figures
Page
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Logic Symbol of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Applications of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Configuration of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Block Diagram of the ISAC-SX. . . . . . . . . . . . . . . . . . . . . . 32
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ACL Indication of Activated Layer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 48
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 50
Multiframe Synchronization using the M-Bit. . . . . . . . . . . . . . . . . . . . . 53
Sampling Time in LT-S / NT mode (M-Bit input) . . . . . . . . . . . . . . . . . 54
Frame Relationship in LT-S / NT mode (M-Bit input). . . . . . . . . . . . . . 54
Frame Relationship in TE / LT-T mode (M-Bit output) . . . . . . . . . . . . . 55
Data Delay between IOM-2 and S/T Interface (TE mode only) . . . . . . 56
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels
and Maximum Receive Delay(LT-S/NT mode only). . . . . . . . . . . . . . . 58
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 59
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 60
Connection of Line Transformers and Power Supply to the ISAC-SX . 61
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 63
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
External Loop at the S/T-Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock System of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Phase Relationships of ISAC-SX Clock Signals . . . . . . . . . . . . . . . . . 70
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . 75
State Transition Diagram of Unconditional Transitions (TE, LT-T) . . . 76
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Data Sheet
10
2000-08-03
PEB 3086
PEF 3086
List of Figures
Page
Figure 40
Figure 41
Figure 42
Figure 43
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Example of Activation/Deactivation Initiated by the Terminal . . . . . . . 90
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control . . . . . . . . 91
Example of Activation/Deactivation initiated by the Network
Figure 44
Termination (NT).
Activation/Deactivation completely under Software Control . . . . . . . . 92
IOM -2 Frame Structure in Terminal Mode . . . . . . . . . . . . . . . . . . . . 94
Multiplexed Frame Structure of the IOM-2 Interface
Figure 45
Figure 46
in Non-TE Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Architecture of the IOM Handler (Example Configuration). . . . . . . . . . 97
Data Access via CDAx1 and CDAx2 register pairs . . . . . . . . . . . . . . . 99
Examples for Data Access via CDAxy Registers
Figure 47
Figure 48
Figure 49
a) Looping Data
b) Shifting (Switching) Data
c) Shifting and Looping Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . 101
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . 102
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . 105
Examples for the Synchronous Transfer Interrupt Control with
one enabled STIxy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Strobe Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H 109
Examples of MONITOR Channel Applications in IOM -2 TE Mode . . 110
MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . 112
Monitor Channel, Transmission Abort requested by the Receiver. . . 115
Monitor Channel, Transmission Abort requested by the Transmitter. 115
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . 116
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CIC Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . 122
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . 123
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . 124
D-Channel Access Control on the S-Interface. . . . . . . . . . . . . . . . . . 125
Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . 129
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Data Reception Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Data Sheet
11
2000-08-03
PEB 3086
PEF 3086
List of Figures
Page
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
Figure 94
Figure 95
Receive Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Interrupt Status Registers of the HDLC Controllers. . . . . . . . . . . . . . 154
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Register Mapping of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Oscillator Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 239
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 241
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 242
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Microprocessor Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Non-Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Microprocessor Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Non-Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Sampling Time in LT-S/NT Mode (M-Bit Input) . . . . . . . . . . . . . . . . . 247
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Data Sheet
12
2000-08-03
PEB 3086
PEF 3086
List of Tables
Page
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Comparison of the ISAC-SX with the previous version ISAC-S: . . . . . 15
ISAC-SX Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . 23
Host Interface Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ISAC-SX Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
S/Q-Bit Position Identification and Multiframe Structure . . . . . . . . . . . 51
Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . 105
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Receive Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ISAC-SX Configuration Settings in Intelligent NT Applications . . . . . 127
AUX Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
IOM-2 Channel Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
HDLC Controller Address Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Receive Byte Count with RBC11...0 in the RBCHx/RBCLx registers 140
Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 146
XPR Interrupt (availability of XFIFOx) after XTF, XME Commands. . 148
Data Sheet
13
2000-08-03
PEB 3086
PEF 3086
Overview
1
Overview
The ISDN Subscriber Access Controller ISAC-SX integrates a D-channel HDLC
controller and a four wire S/T interface used to link voice/data terminals to the ISDN. It
is the successor of the ISAC-S PEB 2086 in 3.3 V technology.
It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and one B-
channel protocol controller (HDLC or transparent) with reduced features dedicated for
firmware download via the B-channel.
The system integration is simplified by several configurations of the parallel
microcontroller interface selected via pin strapping. They include multiplexed and
demultiplexed interface selection as well as the optional indirect register access
mechanism which reduces the number of necessary registers in the address space to 2
locations. The ISAC-SX also provides a serial control interface (SCI).
The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable
block size (threshold). Besides TE mode the S-transceiver supports other terminal
relevant operation modes like line termination subscriber side (LT-S), line termination
trunk side (LT-T) and NT applications (NT, Intelligent NT mode).
An auxiliary I/O port has been added with interrupt capabilities on two input lines. These
programmable I/O lines may be used to connect peripheral components to the ISAC-SX
which need software control or have to forward status information to the host.
Three programmable LED outputs can be used to indicate certain status information,
one of them is capable to indicate the activation status of the S-interface automatically.
The ISAC-SX is produced in advanced CMOS technology.
Data Sheet
14
2000-08-03
PEB 3086
PEF 3086
Overview
Table 1
Comparison of the ISAC-SX with the previous version ISAC-S:
ISAC-SX PEB 3086
ISAC-S PEB 2086
Operating modes
Supply voltage
Technology
TE, LT-T, LT-S, NT, Int. NT TE, LT-T, LT-S, NT
3.3V ± 5 %
5V ± 5 %
CMOS
CMOS
Package
P-MQFP-64 / P-TQFP-64
P-MQFP-64 / P-LCC-44
Transceiver
Transformer ratio for the
transmitter
receiver
1:1
1:1
2:1
2:1
Test Functions
- Dig. loop via Layer 2 (TLP) - Dig. loop via Layer 2(TLP)
- Layer 1 disable (DIS_TR) - Layer 1 disable (DIS_TR)
- Analog loop (LP_A- bit
EXLP- bit, ARL)
- Analog loop (ARL)
Microcontroller Interface
Serial interface (SCI)
Not provided
8-bit parallel interface:
Motorola Mux
8-bit parallel interface:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
direct/ indirect Addressing
Siemens/Intel Mux
Siemens/Intel Non-Mux
Command structure of the
register access (SCI)
Header/address/data
Address/data
Crystal
7.68 MHz
Provided
7.68 MHz
Buffered 7.68 MHz output
Not provided
Controller data access to
IOM-2 timeslots
All timeslots;
various possibilities of data B- and IC-channel
access
Restricted access to
Data control and
manipulation
Various possibilities of data B- and IC-channel looping
control and data
manipulation (enable/
disable, shifting, looping,
switching)
Data Sheet
15
2000-08-03
PEB 3086
PEF 3086
Overview
ISAC-SX PEB 3086
ISAC-S PEB 2086
IOM-2
IOM-2 Interface
Double clock (DCL),
bit clock (BCL),
Double clock (DCL),
bit clock (BCL),
serial data strobe 1 (SDS1) serial data strobe (SDS)
serial data strobe 2 (SDS2)
Monitor channel
programming
Provided
(MON0, 1, 2, ..., 7)
Provided
(MON0 or 1)
C/I channels
CI0 (4bit),
CI1 (4/6bit)
CI0 (4bit),
CI1 (6bit)
Layer 1 state machine
With changes for
correspondence with the
actual ITU specification
Layer 1 state machine
in software
Possible
Not possible
Not provided
Support of IDSL (144kBit/s) Provided
(HDLC controller access,
SDS1/2 signals active)
D- and B-channel timeslots; D-channel timeslot;
D-channel HDLC support
D-channel FIFO size
FW download support
non-auto mode,
transparent mode 0-2,
extended transparent mode transparent mode 1-3
auto mode,
non-auto mode,
64 bytes cyclic buffer per
direction with
programmable FIFO
thresholds
2x32 bytes buffer per
direction
One B-channel controller
Not provided
HDLC support (B-channel) D- and B-channel timeslots; Not provided
non-auto mode,
transparent mode 0-2,
extended transparent mode
FIFO size (B-channel)
Reset Signals
128 bytes cyclic buffer per Not provided
direction with
programmable FIFO
thresholds (8 or 16 bytes)
RES input signal
RST input/output signal
RSTO output signal
Data Sheet
16
2000-08-03
PEB 3086
PEF 3086
Overview
ISAC-SX PEB 3086
ISAC-S PEB 2086
Reset Sources
RES Input
RST Input
Watchdog
Watchdog
C/I Code Change
EAW Pin
C/I Code Change
EAW Pin
Software Reset
Interrupt Output Signals
INT
Low active INT
low active (open drain) by
default, reprogrammable to
high active (push-pull)
Data Sheet
17
2000-08-03
ISDN Subscriber Access Controller
ISAC-SX
PEB/PEF 3086
Version 1.3
1.1
Features
• Full duplex 2B + D S/T interface transceiver according
to ITU-T I.430
• Successor of ISAC-S PEB 2086 in 3.3V technology
• 8-bit parallel microcontroller interface,
Motorola and Siemens/Intel bus type
multiplexed or non-multiplexed,
direct-/indirect register addressing
P-MQFP-64
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Various types of protocol support (Non-auto mode,
transparent mode, extended transparent mode)
• One D-channel HDLC controller with 64 byte FIFOs
per direction
• One B-channel HDLC controller with reduced
functionality (e.g. for firmware upgrades)
• IOM-2 interface in TE, LT-T, LT-S and NT mode,
single/double clocks and two strobe signals
• D-channel priority handler on IOM-2 for intelligent NT
applications
P-TQFP-64
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control peripheral devices
• Conversion of the frame structure between the S/T-interface and IOM-2
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic activation from power down
state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
Type
Package
PEB/PEF 3086 H, PSF 3086 H
PEB/PEF 3086 F, PSF 3086 F
P-MQFP-64
P-TQFP-64
Data Sheet
18
2000-08-03
PEB 3086
PEF 3086
Overview
• Auxiliary Interface with general purpose I/O pins and LED drivers
• Two programmable timers
• Watchdog timer
• Software Reset
• Multiframe Synchronization
• Test loops
• Sophisticated power management for restricted power mode
• Power supply 3.3 V
• 3.3 V output drivers, inputs are 5 V safe
• Advanced CMOS technology
Data Sheet
19
2000-08-03
PEB 3086
PEF 3086
Overview
1.2
Logic Symbol
The logic symbol gives an overview of the ISAC-SX functions. It must be noted that not
all functions are available simultaneously, but depend on the selected mode.
Pins which are marked with a “ * “ are multiplexed and not available in all modes.
IOM-2 Interface
+3.3V 0V
0V
2
DU
DD
FSC
DCL BCL/ SDS1/2 VDD VSS TP
SCLK VDDA VSSA
RD / DS
WR / R/W
ALE
C768
XTAL2
XTAL1
7.68 MHz output
7.68 MHz ± 100ppm
A0...7
SR1
SR2
SX1
SX2
AD0...4
AD5 / SCL
AD6 / SDR
AD7 / SDX
CS
S Interface
Host
Interface
MODE0
MODE1 / EAW
AMODE
INT
Mode
Setting
RES
RSTO
AUX0...7 *
INT0/1 *
2
CH0...2 *
AUX6/7* / ACL
MBIT *
3
3
LED Output
General
External
IOM channel
Multiframe
Sync.
purpose I/O Interrupts select
21150_17
Auxiliary Interface
Figure 1
Logic Symbol of the ISAC-SX
Data Sheet
20
2000-08-03
PEB 3086
PEF 3086
Overview
1.3
Typical Applications
The ISAC-SX is designed for the user area of the ISDN basic access, especially for
subscriber terminal equipment and for exchange equipment with S interface.
Figure 2 illustrates the general application fields of the ISAC-SX.
PABX (NT2)
S
TE(1)
TE(8)
TE(1)
CP
T
U
LT-S
LT-S
SN
LT-T
NT1
CP = Central
Processor
R
Line
Card
=
ISAC -S
SN = Switching
Network
X
TE(1)
TE(8)
Direct Subscriber Access
(point-to-point, short and extended
passive Bus)
S
U
NT1
ITS02315
Figure 2
Applications of the ISAC-SX
Data Sheet
21
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
2
Pin Configuration
P-MQFP-64
P-TQFP-64
39
38 37 36 35 34 33
48 47 46 45 44
42 41 40
43
49
50
32
31
AUX2
BCL / SCLK
DU
DD
AUX1
AUX0
51
52
53
54
55
56
30
29
28
27
26
25
FSC
SDS1
SDS2
DCL
VSS
VSS
VDD
C768
A7
ISAC-SX
PEB 3086
A6
MODE0
MODE1 / EAW
ACL
A5
57
58
59
60
61
62
63
64
24
23
22
21
20
19
18
17
A4
A3
AUX7
A2
A1
AUX6
A0
AUX5
AUX4
AUX3
VDD
VSS
1
2
3
4
5
7 8 9 10 11 12 13 14 15 16
6
21550_22.vsd
Figure 3
Pin Configuration of the ISAC-SX
Data Sheet
22
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
Host Interface
19 A0
20 A1
21 A2
22 A3
23 A4
24 A5
25 A6
26 A7
I
I
I
I
I
I
I
I
• Non-Multiplexed Bus Mode:
Address Bus
Address bus transfers addresses from the
microcontroller to the ISAC-SX. For indirect address
mode only A0 is valid (A1-A7 to be connected to
VDD).
• Multiplexed Bus Mode:
Not used in multiplexed bus mode. In this case A0-A7
should directly be connected to VDD.
9
AD0
I/O
I/O
I/O
I/O
I/O
• Multiplexed Bus Mode:
Address/data bus
Transfers addresses from the microcontroller to the
ISAC-SX and data between the microcontroller and
the ISAC-SX.
10 AD1
11 AD2
12 AD3
13 AD4
• Non-Multiplexed Bus Mode:
Data bus
Transfers data between the microcontroller and the
ISAC-SX.
14 AD5
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD5 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D5 if the parallel interface is selected.
SCL
I
SCI - Serial Clock
Clock signal of the SCI interface if a serial interface is
selected.
Data Sheet
23
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
15 AD6
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD6 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D6 if the parallel interface is selected.
SDR
I
SCI - Serial Data Receive
Receive data line of the SCI interface if a serial
interface is selected.
16 AD7
I/O
• Multiplexed Bus Mode:
Address/data bus
Address/data line AD7 if the parallel interface is
selected.
• Non-Multiplexed Bus Mode:
Data bus
Data line D7 if the parallel interface is selected.
SDX
OD
SCI - Serial Data Transmit
Transmit data line of the SCI interface if a serial
interface is selected.
39 RD
DS
I
I
Read
Indicates a read access to the registers (Siemens/
Intel bus mode).
Data Strobe
The rising edge marks the end of a valid read or write
operation (Motorola bus mode).
40 WR
R/W
I
I
Write
Indicates a write access to the registers (Siemens/
Intel bus mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host access as
a write operation (Motorola bus mode).
Data Sheet
24
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
41 ALE
I
Address Latch Enable
A HIGH on this line indicates an address on the
external address/data bus (multiplexed bus type
only).
ALE also selects the microcontroller interface bus
type (multiplexed or non multiplexed).
3
1
CS
I
Chip Select
A low level indicates a microcontroller access to the
ISAC-SX.
INT
OD (O)
Interrupt Request
INT becomes active low (open drain) if the ISAC-SX
requests an interrupt.
The polarity can be reprogrammed to high active with
push-pull characteristic.
5
RES
I
I
Reset
A LOW on this input forces the ISAC-SX into a reset
state.
38 AMODE
Address Mode
Selects between direct (0) and indirect (1) register
access mode.
IOM-2 Interface
52 FSC
I/O
I/O
Frame Sync
8-kHz frame synchronization signal.
53 DCL
Data Clock
IOM-2 interface clock signal (double clock) (e.g 1.536
MHz in TE mode).
Data Sheet
25
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
49 BCL/SCLK O
Bit Clock/S-Clock
TE-Mode:
Bit clock output, identical to IOM-2 data rate (DCL/2).
LT-T Mode:
1.536 MHz output synchronous to S-interface.
NT / LT-S Mode:
Bit clock output derived from the DCL input clock
divided by 2.
51 DD
I/O (OD)
I/O (OD)
O
Data Downstream
IOM-2 data signal in downstream direction.
50 DU
Data Upstream
IOM-2 data signal in upstream direction.
29 SDS1
Serial Data Strobe 1
Programmable strobe signal for time slot and/or D-
channel indication on IOM-2.
28 SDS2
O
Serial Data Strobe 2
Programmable strobe signal for time slot and/or D-
channel indication on IOM-2.
Auxiliary Interface
30 AUX0
31 AUX1
32 AUX2
I/O (OD)
I/O (OD)
I/O (OD)
• TE-Mode:
Auxiliary Port 0 - 2 (input/output)
These pins are individually programmable as general
input/output. The state of the pin can be read from
(input) / written to (output) a register.
• LT-T/LT-S/NT Mode:
CH0-2 - IOM-2 Channel Select (input)
These pins select one of eight channels on the IOM-
2 interface.
64 AUX3
I/O (OD)
Auxiliary Port 3 (input/output)
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
Data Sheet
26
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Function
Pin No. Symbol Input (I)
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
63 AUX4
I/O (OD)
I/O (OD)
I/O (OD)
• Auxiliary Port 4 (input/output)
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
• MBIT (input/output)
If ACFG2.A4SEL is set to ’1’, pin AUX4 is used as M-
bit input (LT-S / NT / Int. NT mode) or as M-bit output
(TE / LT-T mode) for multiframe synchronization.
62 AUX5
• Auxiliary Port 5 (input/output)
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
• FBOUT - FSC/BCL output
If ACFG2.A5SEL is set to ’1’, pin AUX5 outputs either
an FSC signal or a BCL signal selected via
ACFG2.FBS.
61 AUX6
INT0
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
Additionally, as input it can generate a maskable
interrupt to the host, which is either edge or level
triggered. An internal pull up resistor is connected to
this pin (open drain mode only), if push pull
characteristic is selected no pull up is available.
As output an LED can directly be connected to this
pin.
Data Sheet
27
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
60 AUX7
I/O (OD)
INT1
This pin is programmable as general input/output.
The state of the pin can be read from (input) / written
to (output) a register.
Additionally, as input it can generate a maskable
interrupt to the host, which is either edge or level
triggered. An internal pull up resistor is connected to
this pin (open drain mode only), if push pull
characteristic is selected no pull up is available.
As output an LED can directly be connected to this
pin.
SGO
Instead of the above described function, AUX7 can
also be programmed to output the S/G bit signal from
the IOM-2 DD line.
Miscellaneous
43 SX1
44 SX2
O
O
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
47 SR1
48 SR2
I
I
S-Bus Receiver Input
S-Bus Receiver Input
35 XTAL1
I
Crystal 1
Connection for a crystal or used as external clock
input. 7.68 MHz clock or crystal required.
Crystal 2
36 XTAL2
O
Connection for a crystal. Not connected if an external
clock is supplied to XTAL1.
57 MODE0
I
Mode 0 Select
A LOW selects TE-mode and a HIGH selects LT-T /
LT-S mode (see MODE1/EAW).
Data Sheet
28
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Function
Pin No. Symbol Input (I)
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
58
The pin function depends on the setting of MODE0.
If MODE0=1: Mode 1 Select
A LOW selects LT-T mode and a HIGH selects LT-S
mode.
MODE1
EAW
I
I
If MODE0=0: External Awake
If a falling edge on this input is detected, the ISAC-SX
generates an interrupt and, if enabled, a reset pulse.
59 ACL
O
Activation LED
This pin can either function as a programmable
output or it can automatically indicate the activated
state of the S interface by a logic ’0’.
An LED with pre-resistance may directly be
connected to ACL.
27 C768
O
Clock Output
A 7.68 MHz clock is output to support other devices.
This clock is not synchronous to the S interface.
6
4
RSTO
TP
OD
Reset Output
Low active reset output, either from a watchdog
timeout or programmed by the host.
I
I
Test Pin
Must be connected to VSS.
2, 42 n.c.
not connected
Power Supply
8, 18, VDD
33, 56
–
–
Digital Power Supply Voltage
(3.3 V ± 5 %)
46 VDDA
Analog Power Supply Voltage
(3.3 V ± 5 %)
Data Sheet
29
2000-08-03
PEB 3086
PEF 3086
Pin Configuration
Table 2
ISAC-SX Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Function
MQFP-64
TQFP-64
Output (O)
Open Drain
(OD)
7, 17, VSS
34, 37,
–
Digital ground
(0 V)
54, 55
45 VSSA
–
Analog ground
(0 V)
Data Sheet
30
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3
Description of Functional Blocks
3.1
General Functions and Device Architecture
Figure 4 shows the architecture of the ISAC-SX containing the following functions:
• S/T-interface transceiver supporting the modes TE, LT-T, LT-S, NT and Intelligent NT
• Different host interface modes:
- Parallel microcontroller interface
(Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes)
- Serial Control Interface (SCI)
• Optional indirect register address mode reduces number of registers to be accessed
to two locations
• One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable
FIFO block size (threshold) of 4, 8, 16 or 32 byte for receive direction and 16 or 32
byte for transmit direction
• Support of firmware download via one B-channel HDLC-controller and FlFOs with
reduced functionality
• IOM-2 interface for terminal (TE mode), linecard (LT-T or LT-S) or NT applications
• IOM handler with controller data access registers (CDA) allows flexible access to IOM
timeslots for reading/writing, looping and shifting data
• Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots
• Flexible timeslot assignment of HDLC controllers on IOM for IDSL support
• MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange
• C/I-channel handler and TIC bus access controller
• D-channel access mechanism in all modes
• D-channel priority handler on IOM-2 for intelligent NT applications
• Capability to control the start of the multiframe for synchronization from external
signals (M-bit input pin in LT-S/NT mode, M-bit output pin in TE, LT-T mode)
• Auxiliary interface with interrupt and general purpose I/O lines and 2 LED drivers
• LED connected to pin ACL indicates S-interface activation status automatically or can
be controlled by the host
• Level detect circuit on the S interface reduces power consumption in power down
mode
• Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s)
• Clock and timing generation
• Digital PLL to synchronize the transceiver to the S/T interface
• Buffered 7.68 MHz oscillator clock output allows connection of further devices and
saves another crystal on the system board
• Reset generation (watchdog timer)
Data Sheet
31
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Peripheral Devices
IOM-2 Interface
IOM-2 Handler
S Transceiver
B-channel
HDLC
D-channel
HDLC
MON
TIC C/I
Handler
I/O- and
Interrupt
Lines
Auxiliary
Interface
RX/TX
FIFOs
RX/TX
FIFOs
DPLL
Host Interface
OSC
Reset
Interrupt
-generation
8-bit parallel
SCI
3086_18
Host
Figure 4
Functional Block Diagram of the ISAC-SX
Data Sheet
32
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2
Microcontroller Interfaces
The ISAC-SX supports a serial or a parallel microcontroller interface. For applications
where no controller is connected to the ISAC-SX microcontroller interface programming
is done via the IOM-2 MONITOR channel from a master device. In such applications the
ISAC-SX operates in the IOM-2 slave mode (refer to the corresponding chapter of the
IOM-2 MONITOR handler). This mode is suitable for control functions (e.g. programming
registers of the S/T transceiver), but the bandwidth is not sufficient for access to the
HDLC controllers.
The interface selections are all done by pinstrapping (see Table 3). The selection pins
are evaluated when the reset input RES is active. For the pin levels stated in the tables
the following is defined:
’High’, ’Low’: dynamic pin; value must be ’High’ or ’Low’ only during reset
VDD, VSS:
edge:
static pin; pin must statically be strapped to ’High’ or ’Low’ level
dynamic pin; any transition (’High’ to ’Low’, ’Low’ to ’High’) has occured
Table 3
PINS
WR
Host Interface Selection
Serial /Parallel
Interface
PINS
ALE
Interface
Type/Mode
RD
CS
(R/W) (DS)
VDD
VSS
edge
VSS
VSS
Motorola
’High’ ’High’
Parallel
Serial
‘High’
Siemens/Intel Non-Mux
Siemens/Intel Mux
VSS
VSS
’High’
Serial Control Interface(SCI)
No
VSS
IOM-2 MONITOR Channel
(Slave Mode)
Host Interface
Note: For a selected interface mode which doesn’t need all input selection and address
pins the unused pins must be tied to VDD or VSS.
The interfaces contain all circuitry necessary for the access to programmable registers,
status registers and HDLC FIFOs. The mapping of all these registers can be found in
Chapter 4.
The microcontroller interface also provides an interrupt request at pin INT which is low
active by default but can be reprogrammed to high active, a reset input pin RES and a
reset output pin RSTO.
The interrupt request pin INT becomes active if the ISAC-SX requests an interrupt and
this can occur at any time.
Data Sheet
33
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning
of a serial access to the registers. The ISAC-SX latches incoming data at the rising edge
of SCL and shifts out at the falling edge of SCL. Each access must be terminated by a
rising edge of CS. Data is transferred in groups of 8 bits with the MSB first.
Figure 5 shows the timing of a one byte read/write access via the serial control interface.
Write Access
CS
SCL
Header
Address
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDR
SDX
'0'
write
Read Access
CS
SCL
SDR
SDX
Header
Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'1'
read
Data
7 6 5 4 3 2 1 0
21150_19
Figure 5
Serial Control Interface Timing
Data Sheet
34
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.1.1 Programming Sequences
The basic structure of a read/write access to the ISAC-SX registers via the serial control
interface is shown in Figure 6.
write sequence:
write
byte 2
address
byte 3
header
write data
0
SDR
7
0 7
6
0
0
7
7
0
0
read sequence:
read
byte 2
header
address
1
SDR
7
0 7 6
byte 3
SDX
read data
Figure 6
Serial Control Interface Timing
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the ISAC-SX.
The possible sequences for access to the complete address range 00H-7FH are listed in
Table 4 and described after that.
Table 4
Header Byte Code
Sequence
Header
Byte
Sequence Type
40H/44H
48H/4CH
43H/47H
41H/45H
49H/4DH
Alternating Read/Write (non-interleaved)
Alternating Read/Write (interleaved)
Adr-Data-Adr-Data
Adr-Data-Data-Data
Read-only/Write-only (constant address)
Read and following Write-only (non-interleaved)
Read and following Write-only (interleaved)
Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set
to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2
must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH).
Data Sheet
35
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. In this mode SDX and SDR can be connected
together allowing data transmission on one line.
Example for a read/write access with header 40H:
SDR header wradr wrdata rdadr
SDX
rdadr
wradr wrdata
rddata
rdata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. This mode allows a time optimized access to
the registers by interleaving the data on SDX and SDR (SDR and SDX must not be
connected together).
Example for a read/write access with header 48H:
SDR header wradr wrdata rdadr rdadr wradr wrdata
SDX
rddata rddata
Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address)
This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr,
wradr) in the range 00H-1FH and 6AH/7AH gives access to the current FIFO location
selected by an internal pointer which is automatically incremented with every data byte
following the first address byte. The sequence can have any length and is terminated by
the rising edge of CS.
Example for a write access with header 43H:
SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR header rdadr
SDX
rddata rddata rddata rddata rddata rddata rddata
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
Data Sheet
36
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D
read access. This mode is useful for reading status information before writing to the
HDLC XFIFO. The termination condition of the read access is the reception of the wradr.
The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 41H:
SDR header rdadr
SDX
rdadr
wradr wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
rddata
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read
access. This mode is useful for reading status information before writing to the HDLC
XFIFO. The termination condition of the read access is the reception of the wradr. The
sequence can have any length and is terminated by the rising edge of the CS line.
Example for a read/write access with header 49H:
SDR header rdadr rdadr wradr wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
SDX
rddata rddata
Data Sheet
37
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.2
Parallel Microcontroller Interface
The 8-bit parallel microcontroller interface with address decoding on chip allows easy
and fast microcontroller access.
The parallel interface of the ISAC-SX provides three types of µP buses which are
selected via pin ALE. The bus operation modes with corresponding pins are listed in
Table 5.
Table 5
Bus Operation Modes
Bus Mode
Pin ALE
VDD
Control Pins
(1) Motorola
CS, R/W, DS
CS, WR, RD
(2) Siemens/Intel non-multiplexed
(3) Siemens/Intel multiplexed
VSS
Edge
CS, WR, RD, ALE
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: If the multiplexed address/data bus type (3) is selected, the unused address pins
A0-A7 must be tied to VDD.
A read/write access to the ISAC-SX registers can be done in multiplexed or non-
multiplexed mode:
• In non-multiplexed mode the register address must be applied to the address bus (A0-
A7) for the data access via the data bus (AD0-AD7).
• In multiplexed mode the address on the address/data bus (AD0-AD7) is latched in by
ALE before a data read/write access via the same bus is performed.
The ISAC-SX provides two different ways to address the register contents which is
selected with the AMOD pin (’0’ = direct mode, ’1’ = indirect mode). Figure 7 illustrates
both register addressing modes.
Direct address mode (AMOD = ’0’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’1’): Only the LSB of the address is used to select
either the address register (A0 = ’0’) or the data register (A0 = ’1’). The microcontroller
writes the register address to the ADDRESS register before it reads/writes data from/to
the corresponding DATA register.
In indirect address mode the ISAC-SX evaluates no address line except the least
significant address bit. The remaining address lines must not be left open but have to be
tied to logical ’1’.
Data Sheet
38
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Indirect Address Mode
MODE2:AMOD=1
Direct Address Mode
MODE2:AMOD=0
Address
A0
Data
AD0-7
Address
A0-7
Data
AD0-7
8Fh
8Eh
Address
Data
:
:
1h
DATA
01h
00h
0h ADDRESS
21150_11
Figure 7
Direct/Indirect Register Address Mode
Data Sheet
39
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.3
Interrupt Structure
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in Figure 8.
B-channel
MASKB
RME
RPF
ISTAB
RME
RPF
RFO
RFO
XPR
XPR
XDU
XDU
MSTI
STI
ASTI
STOV21
STOV20
STOV11
STOV10
STI21
STOV21
STOV20
STOV11
STOV10
STI21
ACK21
ACK20
ACK11
ACK10
MASK
ICB
ISTA
ICB
STI20
STI20
CIX1
CI1E
CIR0
CIC0
CIC1
STI11
STI11
STI10
STI10
ST
CIC
ST
CIC
AUX
TRAN
MOS
ICD
AUX
TRAN
MOS
ICD
EAW
EAW
LD
LD
WOV
TIN2
TIN1
INT1
INT0
AUXM
WOV
TIN2
TIN1
INT1
INT0
AUXI
RIC
RIC
SQC
RME
RPF
RME
SQC
RPF
RFO
XPR
SQW
SQW
MASKTR
ISTATR
RFO
XPR
Interrupt
XMR
XDU
XMR
XDU
MRE
MDR
MER
MDA
MASKD
ISTAD
MIE
MAB
MOCR
MOSR
3086_16.vsd
D-channel
Figure 8
Interrupt Status and Mask Registers
Data Sheet
40
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
All seven interrupt bits in the ISTA register point at interrupt sources in the D-channel
HDLC Controller (ICD), B-channel HDLC controller (ICB), Monitor- (MOS) and C/I- (CIC)
handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary
interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
Data Sheet
41
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.4
Reset Generation
Figure 9 shows the organization of the reset generation of the device.
.
RSS1
(reserved)
125µs
125µs
125µs
125µs
≤
≤
≤
≤
t
t
t
t
≤
≤
≤
≤
250µs
250µs
250µs
250µs
C/I Code Change
(Exchange Awake)
RSS2,1
'0'
'1'
≥
1
'1x'
'01'
EAW
(Subscriber Awake)
'00'
' 01 '
≥
1
Pin
≥
1
RSTO
RSS2,1
Watchdog
Software Reset
Register (SRES)
D, C/I-channel (00H-2FH)
Transceiver (30H-3FH)
IOM-2 (40H-5BH)
Reset
Functional
Block
MON-channel (5CH-5FH)
General Config (60H-6FH)
B-channel (70H-7FH)
Reset MODE1 Register
Pin
Internal Reset of all Registers
RES
3086_21
Figure 9
Reset Generation
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according Table 6.
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Data Sheet
42
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Table 6
Reset Source Selection
RSS2 RSS1
Bit 1 Bit 0
C/I Code
Change
EAW
Watchdog
Timer
0
0
1
1
0
1
0
1
--
--
--
reserved
x
x
--
x
--
--
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125µs ≤ t ≤ 250µs.
• EAW (Subscriber Awake)
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125µs ≤ t ≤ 250µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
WTC1
WTC2
1.
2.
1
0
0
1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in Chapter 5.9.
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in Chapter 4).
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
Data Sheet
43
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in Figure 9.
3.2.5
Timer Modes
The ISAC-SX provides two timers which can be used for various purposes. Each of them
provides two modes (Table 7), a count down timer interrupt, i.e. an interrupt is generated
only once after expiration of the selected period, and a periodic timer interrupt, which
means an interrupt is generated continuously after every expiration of that period.
Table 7
ISAC-SX Timers
Address Register
Modes
Period
Periodic
64 ... 2048 ms
64 ms ... 14.336 s
1 ... 63 ms
24H
65H
TIMR1
TIMR2
Count Down
Periodic
Count Down
1 ... 63 ms
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI
(TIN1, TIN2) and each of the interrupt sources can be masked in AUXM.
MASK
ICB
ISTA
ICB
AUXI
EAW
WOV
TIN2
TIN1
INT1
INT0
AUXM
EAW
ST
CIC
ST
CIC
WOV
AUX
TRAN
MOS
ICD
AUX
TRAN
MOS
ICD
TIN2
TIN1
INT1
INT0
Interrupt
Figure 10
Timer Interrupt Status Registers
Data Sheet
44
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Timer 1
The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing
register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is
generated continuously if CNT=7 or a single interrupt is generated after timer period T if
CNT<7 (Figure 11).
Retry Counter
0 ... 6 : Count Down Timer
7 : Periodic Timer
T = CNT x 2.048 sec + T1
T = T1
Expiration Period
T1 = (VALUE + 1) x 0.064 sec
7 6 5 4 3 2 1 0
TIMR1
24H
CNT
VALUE
21150_14
Figure 11
Timer 1 Register
Timer 2
The host starts and stops timer 2 in TIMR2.CNT (Figure 12). If TIMR2.TMD=0 the timer
is operating in count down mode, for TIMR2.TMD=1 a periodic interrupt AUXI.TIN2 is
generated. The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR2.CNT).
Timer Mode
0 : Count Down Timer
1 : Periodic Timer
Timer Count
0 : Timer off
1 ... 63 : 1 ... 63 ms
7
6
0
5
4
3
2
1
0
TMD
CNT
TIMR2
65H
21150_14
Figure 12
Timer 2 Register
Data Sheet
45
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.2.6
Activation Indication via Pin ACL
The activated state of the S-interface is directly indicated via pin ACL (Activation LED).
An LED with pre-resistance may directly be connected to this pin and a low level is driven
on ACL as soon as the layer 1 state machine reaches the activated state (see
Figure 13).
Figure 13
ACL Indication of Activated Layer 1
By default (ACFG2.ACL=0) the state of layer 1 is indicated at pin ACL. If the automatic
indication of the activated layer 1 is not required, the state on pin ACL can also be
controlled by the host (see Figure 14).
If ACFG2.ACL=1 the LED on pin ACL can be switched on (ACFG2.LED=1) and off
(ACFG2.LED=0) by the host.
+3.3V
ACFG2:LED
0 : off
1 : on
'1'
'0'
ACL
S Interface
Layer 1
ACFG2:ACL
3086_15
Figure 14
ACL Configuration
Data Sheet
46
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3
S/T-Interface
The layer-1 functions for the S/T interface of the ISAC-SX are:
– line transceiver functions for the S/T interface according to the electrical specifications
of ITU-T I.430;
– conversion of the frame structure between IOM-2 and S/T interface;
– conversion from/to binary to/from pseudo-ternary code;
– level detection
– receive timing recovery for point-to-point, passive bus and extended passive bus
configuration
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– activation/deactivation procedures, triggered by primitives received over the IOM-2
C/I channel or by INFO's received from the line;
– execution of test loops.
The wiring configurations in user premises, in which the ISAC-SX can be used, are
illustrated in Figure 15.
Data Sheet
47
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
≤
≤
1000 m 1)
1000 m 1)
ISAC-SX
TR
TR
TR
TR
ISAC-SX
TE
LT-S
Point-to-Point
ISAC-SX
ISAC-SX
Configurations
LT-T
NT
1) The maximum line attenuation tolerated by the ISAC-SX is 7 dB at 96 kHz.
≤
100 m
Short
Passive Bus
TR
ISAC-SX
TR
≤
10 m
NT / LT-S
....
ISAC-SX
ISAC-SX
TE1
TE8
≤
500 m
≤
25 m
Extended
Passive Bus
TR
TR
ISAC-SX
≤
10 m
NT / LT-S
TR: Terminating Resistor
....
ISAC-SX
ISAC-SX
TE1
TE8
3086_20
Figure 15
Wiring Configurations in User Premises
Data Sheet
48
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.1
S/T-Interface Coding
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are
used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance
information.
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
0 1 1
code violation
Figure 16
S/T -Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 17).
In the direction TE → NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT → TE and TE → NT) with all framing
and maintenance bits.
Data Sheet
49
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Figure 17
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) → identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) → number of binary ZEROs sent
after the last L. bit was odd
– D
– E
D-Channel Data Bit
D-Channel Echo Bit
Signaling data specified by user
E = D → received E-bit is equal to transmitted
D-bit
– FA
– N
Auxiliary Framing Bit
See section 6.3 in ITU I.430
FA
N =
– B1
– B2
– A
B1-Channel Data Bit
B2-Channel Data Bit
Activation Bit
User data
User data
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
– S
– M
S-Channel Data Bit
Multiframing Bit
S1 channel data (see note below)
M = (1b) → Start of new multiframe
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
50
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.2
S/T-Interface Multiframing
According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in
the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel).
The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S channel (S1) out of five possible S-channels can be accessed by the ISAC-SX.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR
channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel
registers (SQRRx, SQXRx).
Table 8 shows the S and Q bit positions within the multiframe.
Table 8
S/Q-Bit Position Identification and Multiframe Structure
Frame Number NT-to-TE
NT-to-TE
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
FA Bit Position M Bit
1
2
3
4
5
ONE
ONE
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
6
7
8
9
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
10
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
Data Sheet
51
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
TE Mode
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE → NT) FA bit position in each 5th S/T frame (see Table 8).
When synchronization is not achieved or lost, each received FA bit is mirrored to the next
transmitted FA bit.
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to FA/N bit and M bit positions. Multiframe synchronization is lost
if bit errors in FA/N bit or M bit positions have been detected in two consecutive
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
NT Mode
The transceiver in NT mode starts multiframing if SQXR1.MFEN is set.
After multiframe synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE → NT) FA bit position by the TE in each 5th S/T frame, the
S data will be inserted at the downstream (NT → TE) S bit position in each S/T frame
(see Table 8).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have
changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
52
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.3
Multiframe Synchronization (M-Bit)
The ISAC-SX offers the capability to control the start of the multiframe from external
signals, so applications which require synchronization between different S-interfaces are
possible. Such an application is the connection of DECT base stations to PBX line cards.
For this purpose a multiplexed function of the AUX4 pin is used. If the ACFG2.A4SEL is
set to “1” the pin is not used as general pupose I/O pin but as M-bit input (NT, LT-S) or
as M-Bit output (TE, LT-T). The direction input/output of the pin MBIT is automatically
selected with the operation mode.
S-Interface
S-transceiver
(TE, LT-T)
S-transceiver
(LT-S, NT)
M-Bit
Output
M-Bit
Input
MBIT
MBIT
21150_27
Figure 18
Multiframe Synchronization using the M-Bit
M-Bit Input (LT-S, NT-Mode)
The MBIT pin can be used to synchronize the multiframe structure between several
S-transceivers. Multiframe generation must be enabled (SQXR1.MFEN=1).
The value of MBIT is sampled at the start of the F-bit of the S-frame.
If the input on MBIT is "1", the multiframe counter is reset to frame no. 20 and as a result,
the bits FA, M and S are transmitted as logic ZERO (line = “1”). If MBIT becomes "0"
again, the multiframe counter counts 20 frames (starting with frame no. 1) and begins
again autonomously.
If MBIT is kept "1", the multiframe counter is permanently reset and the bits FA, M and S
stay at logic ZERO (line = “1”). If MBIT becomes "0" for only one S-frame, the multiframe-
counter reaches frame no. 1 at which a logic ONE (line = “0”) is transmitted in the FA and
M-bit position and the S11 bit is transmitted.
Thus, the M-bit can be used to transfer synchronization pulses of any length between
different S-interfaces.
M-Bit Output (TE, LT-T Mode)
In TE and LT-T mode, the ISAC-SX outputs the value of the M-bit on the MBIT pin.
The value of M should be sampled at the falling edge of FSC.
Data Sheet
53
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Sample Time
FSC
DCL
FSC detected
XTAL
20 XTAL
SX1 / SX2
MBIT
FBIT (40xXTAL)
Counter reset
21150_32
The sample time of the MBIT input is related to the rising edge of FSC at the beginning of an S0 frame
-- min: 20 * 1 / xtal
-- max: 20 * 1 / xtal + 1 / xtal + 1 / dcl
Figure 19
Sampling Time in LT-S / NT mode (M-Bit input)
Frame Relationship
M
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
D
S (NT -> TE)
F
B1
B2
B1
B2
B1
B2
B1
B2
FSC (i)
DD (i)
D
D
D
D
B1 B2
B1 B2
B1 B2
B1 B2
don't care
MBIT (i)
Figure 20
Data Sheet
21150_29
'0' or '1'
'0' or '1'
Frame Relationship in LT-S / NT mode (M-Bit input)
54
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
M
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
B2
D
S (NT -> TE)
FSC
F
B1
B2
B1
B2
B1
B2
B1
DD (o)
B1 B2 D
E
B1 B2 D
M i-1
E
B1 B2 D
M
E
B1 B2 D
E
MBIT (o)
21150_30
Figure 21
Frame Relationship in TE / LT-T mode (M-Bit output)
Data Sheet
55
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.4
Data Transfer and Delay between IOM-2 and S/T
TE mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled, bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 22 shows the data delay between the IOM-2 and the S/T interface and vice
versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (MODED.DIM0=0). If S/G evaluation is enabled
(MODED.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
D
NT -> TE
TE -> NT
FSC
F
B1
B2
B1
D
B2
B1
B2
B1
B2
D
D
D
F
D
D
D
D
F
B1
B2
B1
B2
B1
B2
B1
B2
DU
DD
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
E
E
E
E
line_iom_s.vsd
Figure 22
Data Delay between IOM-2 and S/T Interface (TE mode only)
Data Sheet
56
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
D
NT -> TE
TE -> NT
FSC
F
B1
B2
B1
D
B2
B1
B2
B1
D
B2
D
D
D
F
D
D
D
F
B1
B2
B1
B2
B1
B2
B1
B2
DU
DD
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2
B1 B2
B1 B2
D
D
E
D
E
E
E
Mapping of B-Channel Timeslots
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
1. Possibility
2. Possibility
line_iom_s_dch.vsd
Figure 23
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only)
LT-T mode
In this mode the frame relation between S/T interface and IOM-2 is flexible.
LT-S/NT mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
Note: In intelligent NT the D-channel access can be blocked by the IOM-2 D-channel
handler.
Data Sheet
57
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
D
NT -> TE
TE -> NT
FSC
F
B1
B2
B1
D
B2
B1
B2
B1
D
B2
D
D
D
F
D
D
D
F
B1
B2
B1
B2
B1
B2
B1
B2
DD
D
B1 B2
D
D
D
D
D
B1 B2
B1 B2
B1 B2
B1 B2
B1 B2
B1 B2
DU
D
D
B1 B2
line_iom_s4nt.vsd
Figure 24
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only)
E
D
E
D
E
D
E
D
F
E
D
E
D
E
D
E
D
NT -> TE
TE -> NT
F
B1
B2
B1
B2
B1
B2
B1
B2
D
D
D
D
F
D
D
D
D
F
B1
F
B2
B1
B2
B1
D
B2
B1
B2
D
D
D
D
D
D
D
TE -> NT (42µs)
FSC
B1
B2
B1
B2
F
B1
B2
B1
B2
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2
D
DD
B1 B2 D
B1 B2 D
E
E
E
E
line_iom_s4nt_dly.vsd
Figure 25
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels and
Maximum Receive Delay(LT-S/NT mode only)
Data Sheet
58
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.5
Transmitter Characteristics
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.0V;
Imax = 26 mA). The equivalent circuit of the transmitter is shown in Figure 26.
The nominal pulse amplitude on the S-interface 750 mV (zero-peak) is adjusted with
external resistors ( see Chapter 3.3.7.1).
'+0'
VCM+0.525V
VCM
'1'
+
'-0'
V=1
SX1
VCM-0.525V
-
'+0' '1' '-0'
Level
TR_CONF2.DIS_TX
VCM
-
'+0'
V=1
VCM-0.525V
VCM
VCM+0.525V
SX2
'1'
+
'-0'
21150_28
Figure 26
Equivalent Internal Circuit of the Transmitter Stage
Data Sheet
59
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.6
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in Figure 27.
100 kOhm
Figure 27
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 kΩ resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 µs to reach the peak value while storing
the peak level for at least 250 µs (RC > 1 ms).
The additional level detector for power up/down control works with a fixed thresholds
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
60
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.7
S/T Interface Circuitry
For both, receive and transmit direction a 1:1 transformer is used to connect the ISAC-
SX transceiver to the 4 wire S/T interface. Typical transformer characteristics can be
found in the chapter on electrical characteristics. The connections of the line
transformers is shown in Figure 28.
1:1
3.3 V
10 µF
GND
SX1
SX2
VDD
Protection
Circuit
Transmit
Pair
1:1
SR1
SR2
Protection
Circuit
Receive
Pair
VSS
21150_05
Figure 28
Connection of Line Transformers and Power Supply to the ISAC-SX
For the transmit direction an external transformer is required to provide isolation and
pulse shape according to the ITU-T recommendations.
3.3.7.1 External Protection Circuitry
The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results
in a conflict with respect to external S-protection circuitry requirements:
– To avoid destruction or malfunction of the S-device it is desirable to drain off even
small overvoltages reliably.
– To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs
only, ITU-T I.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be
dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer
ratio are not affected.
This requirement results from the fact that this test is also to be performed with no supply
voltage being connected to the TE. Therefore the second reference point for
overvoltages V , is tied to GND. Then, if the amplitude of the 96 kHz test signal is
DD
greater than the combined forward voltages of the diodes, a current exceeding the
specified one may pass the protection circuit.
The following recommendations aim at achieving the highest possible device protection
against overvoltages while still fulfilling the 96 kHz impedance tests.
Data Sheet
61
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Protection Circuit for Transmitter
5 ...10
Ohm
1:1
SX1
S Bus
Vdd
5 ... 10
Ohm
SX2
21150_23
Figure 29
External Circuitry for Transmitter
Figure 29 illustrates the secondary protection circuit recommended for the transmitter.
The external resistors (5 ... 10 Ω) are required in order to adjust the output voltage to the
pulse mask on the one hand and in order to meet the output impedance of minimum 20 Ω
(transmission of a binary zero according to ITU-T I.430) on the other hand.
Two mutually reversed diode paths protect the device against positive or negative
overvoltages on both lines.
An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to V
DD
+ 0.4 V. With the circuit In Figure 29 the pin voltage range is increased from – 1.4 V to
V
+ 0.7 V. The resulting forward voltage of 1.4 V will prevent the protection circuit from
DD
becoming active if the 96 kHz test signal is applied while no supply voltage is present.
Data Sheet
62
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Protection Circuit for Receiver
Figure 30 illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
1:1
Note: up to 10 pF capacitors are optional for noise reduction
Figure 30
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 kΩ=resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the ISAC-SX may need additional circuitry.
3.3.8
S/T Interface Delay Compensation (TE/LT-T mode)
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
Data Sheet
63
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.9
Level Detection Power Down
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.10
Transceiver Enable/Disable
The layer-1 part of the ISAC-SX can be enabled/disabled by configuration (see
Figure 31) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX.
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the ISAC-SX does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The HDLC controller can still operate via IOM-2. The
DCL and FSC pins become input.
TR_CONF0.DIS_TR
TR_CONF2.DIS_TX
’1’
’0’
Figure 31
Disabling of S/T Transmitter
Data Sheet
64
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.3.11
Test Functions
The ISAC-SX provides test and diagnostic functions for the S/T interface:
– The internal local loop (internal Loop A) is activated by a C/I command ARL or by
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
is disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 input B- and D-channels are looped back to the output B- and D-
channels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
affected.
Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
– The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the TR_CONF0 register has
to be programmed and the loop has to be closed externally as described in Figure 32.
The S/T interface level detector is disabled.
This allows complete system diagnostics.
– In remote line loop (RLP) received data is looped back to the S/T interface. The D-
channel information received from the line card is transparently forwarded to the
output IOM-2 D-channel. The output B-channel information on IOM-2 is fixed to ‘FF’H
while this test loop is active. The remote line loop is programmable in
TR_CONF2.RLP.
SX1
100
Ω
SX2
SR1
100
Ω
SR2
Figure 32
External Loop at the S/T-Interface
Data Sheet
65
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
– transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register (see Chapter 3.5.4)
Two kinds of test signals may be transmitted by the ISAC-SX:
– The single pulses are of alternating polarity. One pulse is transmitted in each frame
resulting in a frequency of the fundamental mode of 2 kHz. The corresponding C/I
command is SSP (Send Single Pulses).
– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I command is SCP (Send Continuous Pulses).
Data Sheet
66
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.4
Clock Generation
Figure 33 shows the clock system of the ISAC-SX. The oscillator is used to generate a
7.68 MHz clock signal (fXTAL). In TE mode the DPLL generates the IOM-2 clocks FSC
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
An internal clock divider provides an FSC (ACFG2.FBS=0) or BCL (ACFG2.FBS=1)
output on pin AUX5/FBOUT derived from the DCL clock. The output can be enabled via
ACFG2.A5SEL=1.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see Figure 3.2.4).
FSC (TE mode)
XTAL
f
XTAL
7.68 MHz
DCL (TE mode)
BCL (TE mode)
SCLK (LT-T mode)
OSC
DPLL
Reset
Generation
125 µs
125 µs
125 µs
125 µs
≤
≤
≤
≤
t
t
t
t
≤
≤
≤
≤
250 µs
250 µs
250 µs
250 µs
SW Reset
C/I
EAW
Watchdog
ACFG2.FBS
ACFG2.A5SEL
FBOUT (FSC/BCL output)
21150_06
Figure 33
Clock System of the ISAC-SX
Data Sheet
67
2000-08-03
Table 9
Clock Modes
TE
LT-T
LT-S
NT
Int. NT
Selected via
pin: MODE0=0
pin:MODE1=0
MODE0=1
pin:MODE1=1
MODE0=1
bit:MODE2=0
MODE1=1
MODE0=0
bit:MODE2=1
MODE1=1
MODE0=1 or
MODE0=0 *1)
FSC
o:8 kHz
i:8 kHz
i:8 kHz
i:8 kHz
i:8 kHz
(DIS_TR=0)
i:8 kHz
(DIS_TR=1) *2)
DCL
o:1536 kHz
(DIS_TR=0)
i:1536/768 kHz
(DIS_TR=1) *2)
i:1536 kHz
i:512 kHz or
1536 kHz or
4096 kHz
i:512 kHz or
1536 kHz or
4096 kHz
i:1536 kHz
(from SCLK)
or 4096 kHz
(from ext. PLL)
BCL/SCLK
o:768 kHz
(BCL)
o:1536 kHz
(SCLK) *5)
o:256 kHz or
768 kHz or
2048 kHz
o:256 kHz or
768 kHz or
2048 kHz
o:768 kHz
(derived from
DCL/2)
(derived from
DCL/2)
(derived from
DCL/2)
DU *6)
DD
i
i
o
i
o
i
o
i
o
o
AUX5/FBOUT o:FSC (FBS=0) or o:FSC (FBS=0) or o:FSC (FBS=0) or o:FSC (FBS=0) or o:FSC (FBS=0) or
(A5SEL=1) *3) BCL (FBS=1)
BCL (FBS=1)
BCL (FBS=1)
BCL (FBS=1)
BCL (FBS=1)
AUX0-2
general purpose
I/O pins
CH0-2:
CH0-2:
CH0-2:
general purpose
strap pins for IOM strap pins for IOM strap pins for IOM I/O pins
channel select *4) channel select *4) channel select *4)
PEB 3086
PEF 3086
Description of Functional Blocks
Note: i = input; o = output;
For all input clocks typical values are given although other clock frequencies may
be used, too.
1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins
MODE1 and MODE0. The mode can be reprogrammed in TR_MODE.MODE2-0
where NT and Intelligent NT can be selected additionally. In Int. NT mode MODE0
selects between NT state machine (0) and LT-S state machine (1).
2) In TE mode the S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the
IOM clocks become inputs and with IOM_CR.CLKM the DCL input can be
selected to double clock (0) or single bit clock (1).
3) ACFG2.A5SEL=1 selects the FBOUT function (derived from IOM clocks) which
provides an FSC/BCL output clock if clocks are present on IOM.
4) The number of IOM channels depends on the DCL clock, e.g. with DCL=1536
kHz 3 IOM channels and with DCL=4096 kHz 8 channels are available.
5) In LT-T mode the 1536 kHz output clock on SCLK is synchronous to the S
interface and can be used as input for the DCL clock.<
6) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
Data Sheet
69
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.4.1
Description of the Receive PLL (DPLL)
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
The phase relationships of the clocks are shown in Chapter 34.
F-bit
1536 kHz *
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
768 kHz
ITD09664
FSC
Figure 34
3.4.2
Phase Relationships of ISAC-SX Clock Signals
Jitter
The timing extraction jitter of the ISAC-SX conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
70
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.4.3
Oscillator Clock Output C768
The ISAC-SX derives its system clocks from an external clock connected to XTAL1
(while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and
XTAL2.
At pin C768 a buffered 7.68 MHz output clock is provided to drive further devices, which
is suitable in multiline applications for example (see Figure 35). This clock is not
synchronized to the S-interface.
In power down mode the C768 output is disabled (low signal).
7.68
MHz
n.c.
n.c.
n.c.
n.c.
XTAL1
XTAL2
C768
XTAL1
XTAL2
C768
XTAL1
XTAL2
C768
3086_12
Figure 35
Buffered Oscillator Clock Output
Data Sheet
71
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5
Control of Layer-1
The layer-1 activation/ deactivation can be controlled by an internal state machine via
the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the
default state the internal layer-1 state machine of the ISAC-SX is used. By setting the
L1SW bit in the TR_CONF0 register the internal state machine can be disabled and the
layer-1 commands, which are normally generated by the internal state machine are
written directly in the TR_CMD register or indications read from the TR_STA register
respectively.The ISAC-SX layer-1 control flow is shown in Figure 36.
Figure 36
Layer-1 Control
In the following sections the layer-1 control by the ISAC-SX state machine will be
described. For the description of the IOM-2 C/I0 channel see also Chapter 3.7.4.
The layer-1 functions are controlled by commands issued via the CIX0 register. These
commands, sent over the IOM-2 C/I channel 0 to layer 1, trigger certain procedures,
such as activation/deactivation, switching of test loops and transmission of special pulse
patterns. These procedures are governed by layer-1 state diagrams. Responses from
layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
The state diagrams of the ISAC-SX are shown in Figure 38 and Figure 39. The
activation/deactivation implemented by the ISAC-SX agrees with the requirements set
forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU I.430.
Data Sheet
72
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
State machines are the key to understanding the transceiver part of the ISAC-SX. They
include all information relevant to the user and enable him to understand and predict the
behaviour of the ISAC-SX. The state diagram notation is given in Figure 37. The
informations contained in the state diagrams are:
– state name (based on ITU I.430)
– S/T signal transmitted (INFO)
– C/I code received
– C/I code transmitted
– transition criteria
The coding of the C/I commands and indications are described in detail in Chapter 3.5.4.
ISAC-SX
IPAC
OUT
IPAC
IN
Unconditional
Transition
IOM-2 Interface
Ind.
Cmd.
i r
C /
Ι
State
S / T Interface
INFO
i x
Figure 37
State Diagram Notation
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 deactivated”.
The state may be entered:
– from the unconditional states (ARL, RES, TM)
– from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5
unsynchronized” after the C/I command “DI” has been received.
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
C/I message “DC” is issued on the IOM-2 interface.
The state may be left by either of the following methods:
– Leave for the state “F3 power up” in case C/I = “TIM” code is received.
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
Data Sheet
73
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
– Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/T-
interface.
– Leave for the state “F7 activated” after INFO 4 has been recognized on the S/T-
interface.
– Leave for any unconditional state if any unconditional C/I command is received.
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “ ” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
3.5.1
State Machine TE and LT-T Mode
3.5.1.1 State Transition Diagram (TE, LT-T)
Figure 38 shows the state transition diagram of the ISAC-SX state machine. Figure 39
shows this for the unconditional transitions (Reset, Loop, Test Mode i).
Data Sheet
74
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
DI
DC
i4
TIM
F3
Deactivated
i0
i0
AR i2
DI
DI
AR2)
TIM
PU
PU
AR
F4
Pending Act.
F3
Power Up
TIM
i1
i0
i0
i0
i2
i0
i4
X
RSY
TIM
DI
X
i4
F5
Unsynchronized
DI
TIM
Uncond. State
i0
ix
i2
AR
X
X4)
F6
Synchronized
i0*TO1
ix
i3
i2
DI
i4
X
RSY
F8
Lost Framing
i0
i2
i4
TIM
i0*TO1
i2
i2
i0
DI*TO2
ix
AR2)
X
AI3)
F7
Activated
i3 i4
DR1)
i4
TIM*TO2
F3
Pending Deact.
i0*TO1
i0 i0
TO1:
TO2:
16 ms
0.5 ms
1) DR for transition from F7 or F8
DR6 for transition from F6
2)
AR stands for AR8 or AR10
AI stands for AI8 or AI10
X stands for commands initiating unconditional
transitions (RES, ARL, SSP or SCP)
3)
4)
statem_te_s.vsd
Figure 38
State Transition Diagram (TE, LT-T)
Data Sheet
75
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
SSP
SCP
ARL
RST
SSP
RES
TMA
ARL
RES
i0
ARL
Loop A Closed
i3
SCP
TIM
DI
TIM
DI
TIM
DI
Test Mode i
Reset
iti
*
*
*
i3
i3
RES
AIL
RSY
Any
State
ARL
TIM
DI
Loop A Activated
i3
*
statem_te_aloop_s.vsd
Figure 39
State Transition Diagram of Unconditional Transitions (TE, LT-T)
3.5.1.2 States (TE, LT-T)
F3 Pending Deactivation
State after deactivation from the S/T interface by info 0. Note that no activation from the
terminal side is possible starting from this state. A ’DI’ command has to be issued to enter
the state ’Deactivated State’.
F3 Deactivated State
The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiving info 0 if the CFS bit of the ISAC-SX Configuration Register is set to
“0“. Activation is possible from the S/T interface and from the IOM-2 interface. The bit
TR_CMD.PD is set and the analog part is powered down.
F3 Power Up
The S/T interface is deactivated (info 0 on the line) and the clocks are running.
Data Sheet
76
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
F4 Pending Activation
The ISAC-SX transmits info 1 towards the network, waiting for info 2.
F5 Unsynchronized
Any signal except info 2 or 4 detected on the S/T interface.
F6 Synchronized
The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize
the NT.
F7 Activated
The receiver has synchronized and detects info 4. All user channels are now conveyed
transparently to the IOM-2 interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued and TR_STA.FSYN must be “1” (signal from remote side must
be synchronous).
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external)
The ISAC-SX loops back the transmitter to the receiver and activates by transmission of
info 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external)
The receiver has synchronized to info 3. Data may be sent. The indication “AIL” is output
to indicate the activated state. If the loop is closed internally and the S/T line awake
detector detects any signal on the S/T interface, this is indicated by “RSY”.
Test Mode - SSP
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode - SCP
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Data Sheet
77
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.1.3 C/I Codes (TE, LT-T)
Command
Activation Request with AR8 1000 Activation requested by the ISAC-SX, D-
priority class 8 channel priority set to 8 (see note)
Activation Request with AR10 1001 Activation requested by the ISAC-SX, D-
priority class 10 channel priority set to 10 (see note)
Abbr. Code Remark
Activation Request Loop ARL 1010 Activation requested for the internal or
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
Deactivation Indication
DI
1111 Deactivation Indication
Reset
RES 0001 Reset of the layer-1 statemachine
Timing
TIM
0000 Layer-2 device requires clocks to be
activated
Test mode SSP
Test mode SCP
SSP 0010 One AMI-coded pulse transmitted in each
frame, resulting in a frequency of the
fundamental mode of 2 kHz
SCP 0011 AMI-coded pulses transmitted continuously,
resulting in a frequency of the fundamental
mode of 96 kHz
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
Indication
Abbr. Code Remark
Deactivation Request DR
0000 Deactivation request via S/T-interface if left
from F7/F8
Reset
RES 0001 Reset acknowledge
Test Mode
TMA 0010 Acknowledge for both SSP and SCP
Acknowledge
Slip Detected
SLD 0011
Resynchronization
during level detect
RSY 0100 Signal received, receiver not synchronous
Data Sheet
78
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Indication
Abbr. Code Remark
Deactivation Request DR6 0101 Deactivation Request from state F6
from F6
Power up
PU
AR
0111 IOM-2 interface clocking is provided
1000 Info 2 received
Activation request
Activation request loop ARL 1010 Internal or external loop A closed
Illegal Code Violation CVR 1011 Illegal code violation received. This function
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
Activation indication
loop
AIL
1110 Internal or external loop A activated
Activation indication
with priority class 8
AI8
1100 Info 4 received,
D-channel priority is 8 or 9.
Activation indication
with priority class 10
AI10 1101 Info 4 received,
D-channel priority is 10 or 11.
DC 1111 Clocks are disabled if CFS bit of register
Deactivation
confirmation
MODE1 is set to ’1’, quiescent state
Data Sheet
79
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.1.4 Infos on S/T (TE, LT-T)
Receive Infos on S/T (Downstream)
Name
info 0
info 2
Abbr. Description
i0
i2
No signal on S/T
4 kHz frame
A=’0’
info 4
info X
i4
ix
4 kHz frame
A=’1’
Any signal except info 2 or info 4
Transmit Infos on S/T (Upstream)
Name
Abbr. Description
info 0
i0
i1
i3
it1
it2
No signal on S/T
info 1
Continuous bit sequence of the form ’00111111’
4 kHz frame
info 3
Test info 1
Test info 2
SSP - Send Single Pulses
SCP - Send Continuous Pulses
Data Sheet
80
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.2
State Machine LT-S Mode
3.5.2.1 State Transition Diagram (LT-S)
RST
SSP
TIM
RES
DR
G4 Pend. Deact.
TIM
i0
TIM
SCP
DR
DR
Reset
Test Mode i
ARD1)
*
i0
i0
it
*
DC
RES
DC
SSP
SCP
(i0*16ms)+32ms
DR
Any
State
Any
State
DI
ARD1)
G4 Wait for DR
i0
*
DC
DI
DR
DC
TIM 2)
G1 Deactivated
i0
i0
(i0*8ms)+ARD1)
DC
ARD
DR
AR
G2 Pend. Act.
i2
i3
i3
i3
DC
ARD
DC
ARD
RSY
AI
i3
DR
G2 Lost
Framing S/T
G3 Activated
i4 i3
i2
i3
DR
1) ARD = AR or ARL
2) DI if i0
TIM if i0
s tatem_lts _s.v s d
Figure 40
State Transition Diagram (LT-S)
Data Sheet
81
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.2.2 States (LT-S)
G1 deactivated
The transceiver is not transmitting. There is no signal detected on the S/T-interface, and
no activation command is received in the C/I channel. The clocks are deactivated if
MODE1-CFS is set to 1. Activation is possible from the S/T interface and from the IOM-
2 interface.
G2 pending activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 lost framing
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G4 pending deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 wait for DR.”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Data Sheet
82
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Unconditional States
Test mode - SSP
Single alternating pulses are sent on the S/T-interface.
Test mode - SCP
Continuous alternating pulses are sent on the S/T-interface.
3.5.2.3 C/I Codes (LT-S)
Command
Abbr. Code Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a
complete deactivation from the exchange
side by transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES
is an unconditional command.
Send Single Pulses SSP
0010
0011
Send Single Pulses.
Send Continuous
Pulses
SCP
Send Continuous Pulses.
Activation Request AR
1000
1010
Activation Request. This command is
used to start an exchange initiated
activation.
Activation Request ARL
Loop
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
ActivationIndication AIL
Loop
1110
1111
Activation Indication Loop
Deactivation
Confirmation
DC
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in
which it can be activated from a terminal
(detection of INFO 0 enabled).
Data Sheet
83
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Indication
Abbr. Code Remark
Timing
TIM
0000
Interim indication during activation
procedure in G1.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES
is an unconditional command.
Receiver not
Synchronous
RSY
0100
1000
1011
Receiver is not synchronous
Activation Request AR
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Ciolation
CVR
Illegal code violation received. This
function has to be enabled in
TR_CONF0.EN_ICV.
Activation Indication AI
1100
1111
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
DI
Timer (32 ms) expired or INFO 0 received
for a duration of 16 ms after deactivation
request
3.5.2.4 Infos on S/T (LT-S)
Receive Infos on S/T (Downstream)
I0
I0
I3
I3
INFO 0 detected
Level detected (signal different to I0)
INFO 3 detected
Any INFO other than INFO 3
Transmit Infos on S/T (Upstream)
I0
I2
I4
It
INFO 0
INFO 2
INFO 4
Send Single Pulses (SSP).
Send Continuous Pulses (SCP).
Data Sheet
84
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.3
State Machine NT Mode
3.5.3.1 State Transition Diagram (NT)
RST
SSP
TIM
RES
DR
G4 Pend. Deact.
TIM
i0
TIM
SCP
DR
DR
Reset
Test Mode i
ARD1)
*
i0
i0
it
*
(i0*16ms)+32ms
DC
RES
DC
SSP
SCP
DR
Any
State
DI
Any
State
ARD1)
G4 Wait for DR
i0
*
DC
DR
DI
DC
TIM 3)
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
AR DC
DR
G1 i0 Detected
i0
*
ARD1)
AR ARD
DR
DR
G2 Pend. Act
i2
i3
i3
i3*ARD
AID
RSY
AI ARD
ARD
i3*ARD1)
i3*AID2)
G2 Lost
Framing S/T
G2 Wait for AID
RSY
i2
i3
i2
i3
1) ARD = AR or ARL
2) AID =AI or AIL
3) DI if i0
AID2)
RSY
DR
ARD1)
AID2)
ARD1)
TIM if i0
i3*AID2)
RSY
AID
RSY
AI
DR
G3 Lost
Framing U
G3 Activated
i4 i3
RSY
i2
*
s tatem_nt_s.v sd
Figure 41
State Transition Diagram (NT)
Data Sheet
85
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.3.2 States (NT)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T-interface, and
no activation command is received in the C/I channel. The clocks are deactivated if the
bit MODE1.CFS to 1. Activation is possible from the S/T interface and from the IOM-2
interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream (usually a two-wire U interface) is
synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the transceiver waits for
a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the two-wire U interface, the transceiver transmits INFO 2.
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms
Data Sheet
86
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test Mode SSP
Send Single Pulses
Test Mode SCP
Send Continuous Pulses
3.5.3.3 C/I Codes (NT)
Command
Abbr. Code Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a
complete deactivation from the exchange
side by transmitting INFO 0.
Unconditional command.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES
is an unconditional command.
Send Single Pulses SSP
0010
0011
Send Single Pulses.
Send Continuous
Pulses
SCP
Send Continuous Pulses.
Receiver not
Synchronous
RSY
0100
1000
Receiver is not synchronous
Activation Request AR
Activation Request. This command is
used to start an exchange initiated
activation.
Activation Request ARL
Loop
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Data Sheet
87
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Command
Abbr. Code Remark
Activation Indication AI
1100
1110
1111
Synchronous receiver, i.e. activation
completed.
ActivationIndication AIL
Loop
Activation Indication Loop
Deactivation
Confirmation
DC
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in
which it can be activated from a terminal
(detection of INFO 0 enabled).
Indication
Abbr. Code Remark
Timing
TIM
0000 Interim indication during deactivation
procedure
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES
is an unconditional command.
Receiver not
Synchronous
RSY
0100
1000
1011
Receiver is not synchronous
Activation Request AR
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Ciolation
CVR
Illegal code violation received. This
function has to be enabled in
TR_CONF0.EN_ICV.
Activation Indication AI
1100
1111
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
DI
Timer (32 ms) expired or INFO 0 received
for a duration of 16 ms after deactivation
request
Data Sheet
88
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.5.4
Command/ Indicate Channel Codes (C/I0) - Overview
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the previous sections for commands and
indications applicable in various states.
TE/LT-T
Cmd
LT-S
Cmd
NT
Ind
Ind
Cmd
Ind
Code
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIM
RES
SSP
SCP
–
DR
DR
RES
SSP
SCP
–
TIM
RES
–
DR
RES
SSP
SCP
RSY
–
TIM
RES
–
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RES
TMA
SLD
RSY
DR6
–
–
–
RSY
–
RSY
–
–
–
–
–
–
–
–
–
PU
–
–
–
–
AR8
AR10
ARL
–
AR
AR
–
AR
–
AR
–
AR
–
–
ARL
CVR
AI8
AI10
AIL
DC
ARL
–
–
ARL
–
–
CVR
AI
–
CVR
AI
–
–
–
AI
–
–
–
–
–
–
AIL
DC
–
DI
DC
DI
DI
Data Sheet
89
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.6
Control Procedures
3.6.1
Example of Activation/Deactivation
An example of an activation/deactivation of the S/T interface initiated by the terminal with
the time relationships mentioned in the previous chapters is shown in Figure 42.
A_DEACT.DRW
Figure 42
Example of Activation/Deactivation Initiated by the Terminal
Data Sheet
90
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.6.2
Activation initiated by the Terminal
INFO 1 has to be transmitted as long as INFO 0 is received.
INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is
received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
INFO 0
NT
TDDIS='1', XINF='010'
RINF='01'
INFO 1
INFO 2
T1TE
XINF='000'
RINF='10'
INFO 0
XINF='011'
INFO 3
INFO 4
T2TE
RINF='11'
TDDIS='0'
INFO 0
T3TE
RINF='00'
XINF='000'
INFO 0
INFO 0
TDDIS='1',
T1TE: 2 to 6 frames (0.5 ms to 1.5 ms)
T2TE
T3TE
:
:
2
4
frames (0.5 ms)
frames (1 ms)
act_deac_te-ext_s.vsd
Figure 43
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of register TR_STA.
Data Sheet
91
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.6.3
Activation initiated by the Network Termination NT
INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
INFO 2
RINF='01'
T1TE
RINF='10'
TDDIS='1', XINF='011'
INFO 3
INFO 4
T2TE
RINF='11'
TDDIS='0'
INFO 0
T3TE
RINF='00'
TDDIS='1', XINF='000'
INFO 0
INFO 0
T1TE: 2 to 6 S/T frames (0.5 ms to 1.5 ms)
T2TE
T3TE
:
:
2
4
S/T frames (0.5 ms)
S/T frames (1 ms)
act_deac_lt_ext_s.vsd
Figure 44
Example of Activation/Deactivation initiated by the Network
Termination (NT).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of register TR_STA.
Data Sheet
92
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7
IOM-2 Interface
The ISAC-SX supports the IOM-2 interface in linecard mode and in terminal mode with
single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD
and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the
BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL
is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the
rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
TE Mode
A DCL signal and BCL signal (pin BCL/SCLK) output is provided and the FSC signal is
generated by the receive DPLL which synchronizes it to the received S/T frame.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface. If the
transceiver is disabled (TR_CON.DIS_TR) the DCL and FSC pins become input and the
HDLC part can still work via IOM-2. In this case the clock mode bit (IOM_CR.CLKM)
selects between a double clock and a single clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU:
FSC (o):
DCL (o):
BCL (o):
768 kbit/s
8 kHz
1536 kHz (double clock rate)
768 kHz (single clock rate)
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i):
DCL (i):
8 kHz
1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
LT-S, LT-T, NT Modes
The IOM-2 clock signals FSC and BCL are input.
In LT-T mode a 1536 kHz output clock synchronous to S is provided at pin SCLK which
can directly be connected to the DCL input. Internal clock dividers provide for generation
of an FSC or BCL output clock at pin FBOUT derived from DCL (see Chapter 3.4).
DD, DU:
FSC (i):
DCL (i):
SCLK (o):
data rate = DCL/2 kbit/s (LT-T mode)
8 kHz
512 ... 4096 kHz, in steps of 512 kHz (double clock rate)
1536 kHz (LT-T mode), BCL derived via DCL/2 (LT-S/NT mode)
Note: In all modes the direction of the data lines DU and DD is not fix but depending on
the timeslot which can be seen in the figures below.
Data Sheet
93
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
IOM-2 Frame Structure (TE Mode)
The frame structure on the IOM-2 data ports (DU,DD) of a master device in IOM-2
terminal mode is shown in Figure 45.
Figure 45
IOM -2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other IOM-
2 devices.
• Channel 2 is used for the TlC-bus access. Only the command/indicate bits are
specified in this channel.
Data Sheet
94
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
IOM-2 Frame Structure (LT-S, LT-T Modes)
This mode is used in LT-S and LT-T applications. The frame is a multiplex of up to eight
IOM-2 channels (DCL = 4096 kHz, Figure 46), each of which has the structure
described above.
The reset value for assignment to one of the eight channels (0 to 7) is done via pin
strapping (CH0-2), however the host can reprogram the selected timeslot in
DCH_TSDP.TSS.
125
s
µ
FSC
DCL
DD
R
IOM CH0
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH5
CH5
CH6
CH6
CH7
CH7
CH0
CH0
R
IOM
CH0
DU
MM
R X
B1
B2
MONITOR
D
C/I
ITD09635
Figure 46
Multiplexed Frame Structure of the IOM-2 Interface
in Non-TE Timing Mode
IOM-2 Frame Structure (NT Mode)
In NT mode one IOM-2 channel is used (DCL=512 kHz). The channel structure is the
same as described above.
Data Sheet
95
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.1
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the ISAC-SX and voice/data devices connected to the IOM-
2 interface. Additionally it provides a microcontroller access to all timeslots of the IOM-2
interface via the four controller data access registers (CDA). Figure 47 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in Chapter 4.4.
The PCM data of the functional units
• Transceiver (TR) and the
• Controller data access (CDA)
• B-channel HDLC controller
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 32 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the data control registers (xxx_CR) the access to
the data of the functional units can be controlled by setting the corresponding control bits
(EN, SWAP).
The IOM-2 handler also provides access to the
• MONITOR channel (MON)
• C/I channels (C/I0,C/I1)
• TIC bus (TIC) and
• HDLC control
The access to these channels is controlled by the registers MON_CR, DCI_CR and
BCH_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the ISAC-SX IOM-2 handler corresponds to the defined frame
structure and data ports of a master device in IOM-2 terminal mode (see Figure 45).
Data Sheet
96
2000-08-03
IOM_CR
SDS1/2_CR
SDS1/2_CR
IOM-2 Interface
EN_BCL, CLKM, DIS_OD, DIS_IOM,
DIOM_INV, DIOM_SDS
( ENS_TSS, ENS_TSS+1,
ENS_TSS+3, TSS, SDSx_BCL
IOM-2 Handler
Controller Data Access (CDA)
CDA Registers
CDA Control
( DPS, TSS,
EN_TBM, SWAP,
EN_I1/0, EN_O1/0,
MCDAxy, STIxy,
STOVxy, ACKxy )
CDA10
CDA11
CDA20
CDA21
Control C/I Data
Control HDLC Data
Control
Monitor Data
(DPS, CS2-0,
EN_MON)
TIC Bus
Disable
(TIC_DIS)
Control
Transceiver
Data Access
(DPS, TSS,
CS2-0, EN_D,
EN_B1R,
EN_B1X,
EN_B2R,
EN_B2X )
Transceiver
Data TR
C/I0
(CS2-0)
C/I1
(DPS_CI1,
EN_CI1)
D-channel B-channel
(CS2-0,
D_EN_D,
(DPS, TSS,
DPS_D,
D_EN_B1, EN_D,
D_EN_B2) EN_BC1,
EN_BC2,
D-channel RX/TX
B1-channel RX
B1-channel TX
B2-channel RX
B2-channel TX
CDA_TSDPxy
CDAx_CRx
MCDA
MON_CR
IOM_CR
CS2-0)
STI
MSTI
ASTI
BCH_TSDP_
B1/2,
BCH_CR
TR_TSDP_BC1
TR_TSDP_BC2
TRC_CR
DCIC_CR
DCI_CR
TIC
C/I0
Data
C/I1
D-ch
B1-ch
MON Handler
FIFOs
3086_07
Note: The registers shown above are used to control
the corresponding functional block (e.g. programming
of timeslot, data port, enabling/disabling, etc.)
Microcontroller Interface
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.1.1 Controller Data Access (CDA)
With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the
ISAC-SX IOM-2 handler provides a very flexible solution for the host access to up to 32
IOM-2 time slots.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting of two independent PCM channels to another two independent PCM channels
on both data ports (DU, DD). Between reading and writing the data can be
manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM timeslot
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in Figure 48. Each of the index variables x,y used in the following
description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
• If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and
output of the CDAxy register is defined by its own TSDPxy register.
• If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for timeslot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in
upstream direction the HDLC controller writes data onto IOM and the transceiver reads
data from IOM). For monitoring data in such cases a CDA register is programmed as
Data Sheet
98
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
described below under “Monitoring Data”. Besides that none of the IOM timeslots must
be assigned more than one input and output of any functional unit.
.
TSa
TSb
DU
Control
Register
CDA_CRx
0
0
1
1
Enable
Enable
Input
Swap
(SWAP)
input *
(EN_I1)
output
(EN_O1)
output
input *
(EN_O0) (EN_I0)
CDAx1
1
CDAx0
1
1
1
1
1
1
0
0
1
DD
TSa
TSb
IOM_HAND.FM4
x = 1 or 2; a,b = 0...11
*) In the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and
EN_I1, respectively. If SWAP=1 EN_I0 controls the input of CDAx1 and EN_I1 controls the
input of CDAx0. The output control (EN_O0 and EN_O1) is not affected by SWAP.
Figure 48
Data Access via CDAx1 and CDAx2 register pairs
Looping and Shifting Data
Figure 49 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= 1)
c) switching data from TSa to TSb and looping from DU to DD or TSc to TSd and looping
from DD to DU respectively
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
It should also be noted that the input control of CDA registers is swapped if SWAP=1
while the output control is not affected (e.g. for CDA11 in example a: EN_I1=1 and
EN_O1=1, whereas for CDA11 in example b: EN_I0=1 and EN_O1=1).
Data Sheet
99
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
a) Looping Data
TSa
TSb
TSc
TSd
DU
CDA10 CDA11
CDA20 CDA21
DD
DU
.TSS: TSa
.DPS
.SWAP
TSb
’0’
TSc
’1’
TSd
’1’
’0’
’0’
’0’
b) Shifting Data
TSa
TSb
TSd
TSc
CDA10 CDA11
CDA20 CDA21
DD
DU
.TSS: TSa
TSb
’1’
TSc
’0’
TSd
’1’
.DPS
’0’
.SWAP
’1’
’1’
c) Switching Data
TSa
TSb
TSd
TSc
CDA10 CDA11
CDA20 CDA21
DD
.TSS: TSa
TSb
’0’
TSc
’1’
TSd
’1’
.DPS
’0’
.SWAP
’1’
’1’
Figure 49
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Shifting and Looping Data
Data Sheet
100
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Figure 50 shows the timing of looping TSa from DU to DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
CDAxy
µC *)
DD
TSa
TSa
*) if access by the µC is required
Figure 50
Data Access when Looping TSa from DU to DD
Figure 51 shows the timing of shifting data from TSa to TSb on DU (DD). In Figure 51a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...9 and b ≥ꢀa+2. In Figure 51b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
101
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
a) Shifting TSa → TSb within one frame
(a,b: 0...11 and b ≥ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
CDAxy
µC *)
b) Shifting TSa → TSb in the next frame
(a,b: 0...11 and (b = a+1 or b <a)
FSC
DU
TSa
TSb
TSaTSb
(DD)
CDAxy
ACK
µC *)
*) if access by the µC is required
Figure 51
Data Access when Shifting TSa to TSb on DU (DD)
Data Sheet
102
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Monitoring Data
Figure 52 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots..
.
a) Monitoring Data
EN_O:
EN_I:
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
’1’
CDA_CR1.
’0’
TS(2n+1)
DU
CDA10
CDA20
CDA11
CDA21
DD
TS(2n)
TSS:
TS(2n+1)
DPS: ’1’
’1’
’1’
’0’
CDA_CR2.
’1’
’0’
EN_I:
EN_O:
Figure 52
Example for Monitoring Data
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. In this special case the TSDPx0 must be set to 08h for
monitoring from DU or 88h for monitoring from DD respectively. By this it is possible to
monitor the TIC bus (TS11) and the odd numbered D-channel (TS3) simultaneously on
DU and DD.
Data Sheet
103
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy0 and xy1 are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not
acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 10 gives some examples for that. It is assumed that an STOV interrupt is only
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is
disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is
generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is
enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0.
In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only
generated due to STIxy0 and STOVxy1 is only generated due to STIxy1.
Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is
not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0.
Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is
generated additionally for both STIxy0 and STIxy1.
Data Sheet
104
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Table 10
Examples for Synchronous Transfer Interrupts
Enabled Interrupts
(Register MSTI)
Generated Interrupts
(Register STI)
STI
xy0
STOV
STI
xy0
-
STOV
-
-
Example 1
Example 2
Example 3
Example 4
Example 5
-
xy0
-
xy0
xy1
xy0
xy0
xy1
xy0
xy0 ; xy1
xy0 ; xy1
xy0 ; xy1
xy0 ; xy1
xy0
xy1
xy0
xy1
xy0 ; xy1
xy0 ; xy1
xy1
xy0
xy1
-
Example 6
Example 7
xy1
xy0 ; xy1 ; xy2
xy0
xy1
xy0 ; xy2
xy1 ; xy2
An STOV interrupt is not generated if all stimulating STI interrupts are acknowledged.
An STIxy must be acknowledged by setting the ACKxy bit in the ASTI register until two
BCL clocks (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the time slot which is
selected for the appropriate STIxy.
The interrupt structure of the synchronous transfer is shown in Figure 53.
.
MASK
ICB
ASTI
ISTA
ICB
STI
STOV21
STOV20
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
ST
ST
CIC
STOV11
STOV10
STI21
CIC
WOV
TRAN
MOS
ICD
ACK21
ACK20
ACK11
ACK10
WOV
TRAN
MOS
ICD
STI20
STI20
STI11
STI10
STI11
STI10
Interrupt
Figure 53
Interrupt Structure of the Synchronous Data Transfer
Data Sheet
105
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Figure 54 shows some examples based on the timeslot structure. Figure a) shows at
which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure
b) is identical to example 3 above, figure c) corresponds to example 5 and figure d)
shows example 4.
.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'1'
'1'
'1'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "intermediate CDA
access"; MSTI.STI10 and MSTI.STOV21 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'1'
'1'
'1'
'0'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 5, MSTI.STI10, MSTI.STOV10,
MSTI.STI21 and MSTI.STOV21 enabled
xy:
10
11
21
TS5
'0'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'1'
'1'
'0'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV21 interrupt used as flag for "intermiediate CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV21 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'1'
'1'
'0'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 54
Examples for the Synchronous Transfer Interrupt Control with one
enabled STIxy
Data Sheet
106
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.2
Serial Data Strobe Signal and Strobed Data Clock
For time slot oriented standard devices connected to the IOM-2 interface the ISAC-SX
provides two independent data strobe signals SDS1 and SDS2. Instead of a data strobe
signal a strobed IOM-2 bit clock can be provided on pin SDS1 and SDS2.
3.7.2.1 Serial Data Strobe Signal
The two strobe signals can be generated with every 8-kHz frame and are controlled by
the registers SDS1/2_CR. By programming the TSS bits and three enable bits
(ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2
time slots TS, TS+1 and TS+3 and any combination of them.
The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
Figure 55 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOM-2 whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which can be
used e.g. for an IDSL (144kbit/s) transmission.
Data Sheet
107
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
FSC
M M
R X
M M
R X
DD,DU
D CI0
CI1
B1
B2 MON0
IC1
IC2 MON1
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS1
SDS1,2
(Example1)
SDS1,2
(Example2)
SDS1,2
(Example3)
Example 1: TSS
ENS_TSS
= '0H'
= '0'
ENS_TSS+1 = '1'
ENS_TSS+3 = '0'
Example 2: TSS
ENS_TSS
= '5H'
= '1'
ENS_TSS+1 = '1'
ENS_TSS+3 = '0'
Example 3: TSS
ENS_TSS
= '0H'
= '1'
ENS_TSS+1 = '1'
ENS_TSS+3 = '1'
strobe.vsd
For all examples SDS_CONF.SDS1/2_BCL must be set to “0”.
Figure 55
Data Strobe Signal
Data Sheet
108
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.2.2 Strobed IOM-2 Bit Clock
The strobed IOM-2 bit clock is active during the programmed window. Outside the
programmed window a ’0’ is driven. Two examples are shown in Figure 56.
FSC
M M
R X
M M
R X
DD,DU
D CI0
CI1
B1
B2 MON0
TS1 TS2
IC1
IC2 MON1
TS0
TS3 TS4 TS5 TS6 TS7 TS8
TS9 TS10 TS11 TS0 TS1
SDS1
(Example1)
SDS1
(Example2)
Setting of SDS1_CR:
Example 1: TSS
ENS_TSS
= '0H'
= '0'
ENS_TSS+1 = '0'
ENS_TSS+3 = '1'
Example 2: TSS
ENS_TSS
= '5H'
= '1'
ENS_TSS+1 = '1'
ENS_TSS+3 = '0'
bcl_strobed.vsd
For all examples SDS_CONF.SDS1_BCL must be set to “1”.
Figure 56
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H
The strobed bit clock can be enabled in SDS_CONF.SDS1/2_BCL.
Data Sheet
109
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.3
IOM-2 Monitor Channel
The IOM-2 MONITOR channel (see Figure 57) is utilized for information exchange in the
MONITOR channel between a master mode device and a slave mode device.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the IOM-2
channels (3 IOM-2 channels in TE mode, 8 channels in non TE mode) can be selected
by setting the MONITOR channel selection bits (MCS) in the MONITOR control register
(MON_CR).
The DPS bit in the same register selects between an output on DU or DD respectively
and with EN_MON the MONITOR data can be enabled/disabled. The default value is
MONITOR channel 0 (MON0) enabled and transmission on DD.
IOM-2 MONITOR Channel
IOM-2 MONITOR Channel
V/D Module
(e.g. ARCOFI-BA)
V/D Module
(e.g. ISAR34)
MONITOR Handler
Layer 1
MONITOR Handler
Layer 1
Master
Device
Slave
Device
µC
µC
IOM-2 MONITOR Channel
V/D Module
(e.g. ISAR34)
MONITOR Handler
Layer 1
µC
µC
Data Exchange between
two µC Systems
3086_08
Figure 57
Examples of MONITOR Channel Applications in IOM -2 TE Mode
The MONITOR channel of the ISAC-SX can be used in following applications which are
illustrated in Figure 57:
• As a master device the ISAC-SX can program and control other devices attached to
the IOM-2 which do not need a parallel microcontroller interface e.g. ARCOFI-BA PSB
2161. This facilitates redesigning existing terminal designs in which e.g. an interface
of an expansion slot is realized with IOM-2 interface and monitor programming.
Data Sheet
110
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PEB 3086
PEF 3086
Description of Functional Blocks
• As a slave device the transceiver part of the ISAC-SX is programmed and controlled
from a master device on IOM-2 (e.g. ISAR34 PSB 7115). This is used in applications
where no microcontroller is connected directly to the ISAC-SX in order to simplify host
interface connection. The HDLC controlling is processed by the master device
therefore the HDLC data is transferred via IOM-2 interface directly to the master
device.
• For data exchange between two microcontroller systems attached to two different
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
3.7.3.1 Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described in the following section and Figure 58
illustrates this. The relevant control and status bits for transmission and reception are
listed in Table 11 and Table 12.
Table 11
Transmit Direction
Control/
Register
Bit
Function
Status Bit
Control
Status
MOCR
MXC
MIE
MX Bit Control
Transmit Interrupt Enable
Data Acknowledged
Data Abort
MOSR
MSTA
MDA
MAB
MAC
Transmission Active
Table 12
Receive Direction
Control/
Register
Bit
Function
Status Bit
Control
Status
MOCR
MRC
MRE
MDR
MER
MR Bit Control
Receive Interrupt Enable
Data Received
MOSR
End of Reception
Data Sheet
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PEF 3086
Description of Functional Blocks
µ
µ
P
P
Transmitter
MON
Receiver
MR
MX
FF
1
1
0
1
1
1
MIE = 1
MOX = ADR
MXC = 1
125
µ
s
FF
ADR
MDR Int.
MAC = 1
RD MOR (=ADR)
MRC = 1
ADR
0
1
0
0
0
0
MDA Int.
MOX = DATA1
DATA1
DATA1
MDR Int.
RD MOR (=DATA1)
DATA1
DATA1
0
0
1
0
MDA Int.
MOX = DATA2
DATA2
DATA2
1
0
0
0
MDR Int.
RD MOR (=DATA2)
DATA2
DATA2
0
0
1
0
MDA Int.
MXC = 0
FF
FF
1
1
0
0
MER Int.
MRC = 0
FF
FF
1
1
1
1
MAC = 0
ITD10032
Figure 58
MONITOR Channel Protocol (IOM-2)
Data Sheet
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2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates an MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microprocessor in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microprocessor has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate an MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the
MONITOR channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
The MONITOR transfer protocol rules are summarized in the following section:
Data Sheet
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PEF 3086
Description of Functional Blocks
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX,MR control indicates or acknowledges a new byte in the MON slot by
toggling MX,MR from the active to the inactive state for one frame.
• Two frames with the MX-bit in the inactive state indicate the end of transmission.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the ISAC-SX to send back the response before the
transmission from the controller is completed (the ISAC-SX does not wait for EOM
from controller).
3.7.3.2 Error Treatment
In case the ISAC-SX does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the ISAC-SX will wait until two identical
bytes are received in succession.
A transmission is aborted of the ISAC-SX if
• an error in the MR handshaking occurs
• a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
Data Sheet
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PEF 3086
Description of Functional Blocks
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 59 shows an example for an abort requested by the receiver, Figure 60 shows
an example for an abort requested by the transmitter and Figure 61 shows an example
for a successful transmission.
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MX (DU)
EOM
0
1
MR (DD)
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 59
Monitor Channel, Transmission Abort requested by the Receiver
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MR (DU)
EOM
0
1
MX (DD)
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 60
Monitor Channel, Transmission Abort requested by the Transmitter
Data Sheet
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PEF 3086
Description of Functional Blocks
IOM -2 Frame No.
1
2
3
4
5
6
7
8
1
MR (DU)
EOM
0
1
MX (DD)
0
mon_norm.vsd
Figure 61
Monitor Channel, Normal End of Transmission
3.7.3.3 MONITOR Channel Programming as a Master Device
As a master device the ISAC-SX can program and control other devices attached to the
IOM-2 interface. The master mode is selected by default if one of the possible
microcontroller interfaces are selected. The monitor data is written by the
microprocessor in the MOX register and transmitted via IOM-2 DD (DU) line to the
programmed/controlled device e.g. ARCOFI-BA PSB 2161 or IEC-Q TE PSB 21911.
The transfer of the commands in the MON channel is regulated by the handshake
protocol mechanism with MX, MR which is described in the previous chapter
Chapter 3.7.3.1.
If the transmitted command was a read command the slave device responds by sending
the requested data.
The data structure of the transmitted monitor message depends on the device which is
programmed. Therefore the first byte of the message is a specific address code which
contains in the higher nibble a MONITOR channel address to identify different devices.
The length of the messages depends on the accessed device and the type of MONITOR
command.
Data Sheet
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PEF 3086
Description of Functional Blocks
3.7.3.4 MONITOR Channel Programming as a Slave Device
In applications without direct host controller connection the ISAC-SX must operate in the
MONITOR slave mode which can be selected by pinstrapping the microcontroller
interface pins according Table 3 respectively in Chapter 3.2. As a slave device the
transceiver part of the ISAC-SX is programmed and controlled by a master device at the
IOM-2 interface. All programming data required by the ISAC-SX is received in the
MONITOR time slot on the IOM-2 and is transferred in the MOR register. The transfer of
the commands in the MON channel is regulated by the handshake protocol mechanism
with MX, MR which is described in the previous Chapter 3.7.3.1.
The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1010’ for the ISAC-SX. The lower nibble distinguishes
between a programming command or an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the ISAC-SX
by software, the following identification command is used:
DD 1st byte value
DD 2nd byte value
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
The ISAC-SX responds to this DD identification sequence by sending a DU identification
sequence:
DU 1st byte value
DU 2nd byte value
1
0
0
1
1
0
0
0
0
0
DESIGN
<IDENT>
DESIGN:six bit code, specific for each device in order to identify differences in operation
e.g. 000001: ISAC-SX PEB/PEF 3086 Version 1.3
This identification sequence is usually done once, when the terminal is connected for the
first time. This function is used so that the software can distinguish between different
possible hardware configurations. However this sequence is not compulsory.
Data Sheet
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PEF 3086
Description of Functional Blocks
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte and the principle of a read/
write access to a register is similar to the structure of the serial control interface
described in Chapter 3.2.1.1. For write access the header 43H/47H can be used and for
read access the header 40H/44H.
DD 1st byte value
DD 2nd byte value
DD 3rd byte value
DD 4th byte value
DD (nth + 3) byte value
1
0
1
0
0
0
0
1
Header Byte
R/W
Register Address
Data 1
Data n
All registers can be read back when setting the R/W bit in the byte for the command/
register address. The ISAC-SX responds by sending its IOM-2 specific address byte
(A1h) followed by the requested data.
3.7.3.5 Monitor Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device. After 5 ms without reply the timer expires and the transmission
will be aborted with a EOM (End of Message) command by setting the MX bit to ’1’ for
two consecutive IOM-2 frames.
Data Sheet
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PEF 3086
Description of Functional Blocks
3.7.3.6 MONITOR Interrupt Logic
Figure 62 shows the MONITOR interrupt structure of the ISAC-SX. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
MASK
ICB
ISTA
ICB
ST
ST
CIC
CIC
WOV
TRAN
MOS
ICD
MRE
WOV
TRAN
MOS
ICD
MDR
MER
MIE
MDA
MAB
MOCR
MOSR
Interrupt
Figure 62
MONITOR Interrupt Structure
Data Sheet
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PEF 3086
Description of Functional Blocks
3.7.4
C/I Channel Handling
The Command/Indication channel carries real-time status information between the
ISAC-SX and another device connected to the IOM-2 interface.
1) One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the layer-2 parts of the ISAC-SX. It can be accessed by an external layer-2
device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration is
done in IOM-2 channel 2 (see Figure 45).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in Chapter 3.5.4.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated anytime a change occurs (ISTA.CIC). A new code must be found in two
consecutive IOM-2 frames to be considered valid and to trigger a C/I code change
interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) can be used to convey real time status information
between the ISAC-SX and various non-layer-1 peripheral devices e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can
be changed from 4bit to 6bit by setting bit CIX1.CICW.
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
CIC Interrupt Logic
Figure 63 shows the CIC interrupt structure.
A CIC interrupt may originate
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC 1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
Data Sheet
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PEF 3086
Description of Functional Blocks
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
MASK
ICB
ISTA
ICB
ST
ST
CIC
CIC0
CIC1
CIR0
CIC
CI1E
CIX1
WOV
TRAN
MOS
ICD
WOV
TRAN
MOS
ICD
Interrupt
Figure 63
CIC Interrupt Structure
Data Sheet
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PEF 3086
Description of Functional Blocks
3.7.5
D-Channel Access Control
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
multipoint configuration (NT → TE1 … TE8).
Both arbitration mechanisms are implemented in the ISAC-SX and will be described in
the following two chapters.
3.7.5.1 TIC Bus D-Channel Access Control
The TIC bus is imlemented to organize the access to the layer-1 functions provided in
the ISAC-SX (C/I-channel) and to the D-channel from up to 7 external communication
controllers (see Figure 64).
To this effect the outputs of the D-channel controllers (e.g. ICC - ISDN Communication
Controller PEB 2070) are wired-or (negative logic, i.e. a “0” wins) and connected to pin
DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/
DD are required. The arbitration mechanism must be activated by setting MODED.DIM2-
0=00x.
ICC (7)
.
.
.
TIC-Bus
on IOM-2
ICC (2)
ICC (1)
S-Interface
U-Interface
D-channel
control
S-
NT
transceiver
3086_09
Figure 64
Applications of TIC Bus in IOM-2 Bus Configuration
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (see Figure 65). An access request to the TIC bus may either be
Data Sheet
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PEF 3086
Description of Functional Blocks
generated by software (µP access to the C/I channel) or by the ISAC-SX itself
(transmission of an HDLC frame in the D-channel). A software access request to the bus
is effected by setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the ISAC-SX checks the Bus Accessed-bit BAC (bit 5
of last octet of CH2 on DU, see Figure 65) for the status "bus free“, which is indicated
by a logical ’1’. If the bus is free, the ISAC-SX transmits its individual TIC bus address
TAD programmed in the CIX0 register (CIX0.TBA2-0). The ISAC-SX sends its TIC bus
address TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read
back as ’0’ because of the access of another D-channel source with a lower TAD, the
ISAC-SX withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not
transmitted. The TIC bus is occupied by the device which sends its address error-free.
If more than one device attempt to seize the bus simultaneously, the one with the lowest
address values wins. This one will set BAC=0 on TIC bus and starts D-channel
transmission in the same frame.
DU
Figure 65
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the ISAC-SX, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the ISAC-SX is automatically set into a lower
priority class, that is, a new bus access cannot be performed until the status "bus free"
is indicated in two successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the µP when access to the C/I channels
is no more requested, to grant other devices access to the D and C/I channels.
Data Sheet
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PEF 3086
Description of Functional Blocks
3.7.5.2 S-Bus Priority Mechanism for D-Channel
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus (see Figure 67).
To implement collision detection the D (channel) and E (echo) bits are used. The D-
channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e. the
availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD
last octet of Ch2 channel (Figure 66).
S/G = 1 : stop
S/G = 0 : go
MR
MX
MR
MX
S/G
A/B
DD
B1
B2
MON0 D CI0
IC1
IC2
MON1 CI1
S/G A/B
ITD09693
E
E
Stop/Go
Available/Blocked
Figure 66
Structure of Last Octet of Ch2 on DD
The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to
determine if they can access the S/T bus D channel.
The access to the D-channel is controlled by a priority mechanism which ensures that all
competing TEs are given a fair access chance. This priority mechanism discriminates
among the kind of information exchanged and information exchange history: Layer-2
frames are transmitted in such a way that signalling information is given priority (priority
class 1) over all other types of information exchange (priority class 2). Furthermore, once
a TE having successfully completed the transmission of a frame, it is assigned a lower
level of priority of that class. The TE is given back its normal level within a priority class
when all TEs have had an opportunity to transmit information at the normal level of that
priority class.
The priority mechanism is based on a rather simple method: A TE not transmitting layer-
2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by flags
consisting of the binary pattern “01111110” and zero bit insertion is used to prevent flag
imitation, the D-channel may be considered idle if more than seven consecutive 1s are
detected on the D-channel. Hence by monitoring the D echo channel, the TE may
determine if the D-channel is currently used by another TE or not.
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PEF 3086
Description of Functional Blocks
A TE may start transmission of a layer-2 frame first when a certain number of
consecutive 1s has been received on the echo channel. This number is fixed to 8 in
priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower
level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and
11 for class 2.
A TE, when in the active condition, is monitoring the D echo channel, counting the
number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the
number of consecutive binary 1s. If the required number of 1s according to the actual
level of priority has been detected, the TE may start transmission of an HDLC frame. If
a collision occurs, the TE immediately shall cease transmission, return to the D-channel
monitoring state, and send 1s over the D-channel.
S-Interface
U-Interface
D-Bits
E-Bits
D-channel
control
S-
NT
transceiver
TE 1
D-channel
control
S-
transceiver
TE 2
.
.
.
D-channel
control
S-
transceiver
TE 8
3086_10
Figure 67
D-Channel Access Control on the S-Interface
S-Bus D-channel Access Control in the ISAC-SX
The above described priority mechanism is fully implemented in the ISAC-SX. For this
purpose the D-channel collission detection according to ITU I.430 must be enabled by
setting MODED.DIM2-0 to ’0x1’. In this case the transceiver continuously compares the
received E-echo bits with its own transmitted D data bits.
Depending on the priority class selected, 8 or 10 consecutive ONEs (high priority level,
Data Sheet
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PEF 3086
Description of Functional Blocks
priority 8) need to be detected before the transceiver sends valid D-channel data on the
upstream D-bits on S. In low priority level (priority 10) 10 or 11 consecutive ONEs are
required.
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly
by the choice of the activation command. If the S-interface is activated from the NT, an
activation command selecting the desired priority class should be programmed at the TE
on reception of the activation indication (AI8 or AI10). In the activated state the priority
class may be changed whenever required by simply programming the desired activation
request command (AR8 or AR10).
3.7.5.3 S-Bus D-Channel Control in LT-T
If the TE frame structure on the IOM-2 interface is selected, the same D-channel access
procedures as described in Chapter 3.7.5.2 are used in LT-T mode.
For other frame structures used in LT-T mode, D-channel access on S is handled
similarly, with the difference that the S/G bit is not available on IOM-2 but only on the
S/G bit output pin (SGO).
3.7.5.4 D-Channel Control in the Intelligent NT (TIC- and S-Bus)
In intelligent NT applications (selected via register TR_MODE.MODE2-0) the ISAC-SX
has to share the upstream D-channel with one or more D-channel controllers on the
IOM-2 interface and with all connected TEs on the S interface.
The transceiver incorporates an elaborate statemachine for D-channel priority handling
on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S
interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on
IOM-2. Due to this an equal and fair access is guaranteed for all D-channel sources on
both the S interface and the IOM-2 interface.
This arbitration mechanism is only available in IOM-2 TE mode (12 PCM timeslots) per
frame with enabled TIC bus. The access to the upstream D-channel is handled via the
S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are
inverted to block the terminals on S). Furthermore, if more than one HDLC source is
requesting D-channel access on IOM-2 the TIC bus mechanism is used.
The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the
necessary number of “1s” is counted and an HDLC controller on IOM-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or
10 (TR_CMD.DPRIO).
Data Sheet
126
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/
G bit is not evaluated in this mode.
The configuration settings of the ISAC-SX in intelligent NT applications are summarized
in Table 13.
Table 13
ISAC-SX Configuration Settings in Intelligent NT Applications
Functional Configuration
Configuration Setting
Block
Description
Layer 1
Select Intelligent
NT mode
Transceiver Mode Register:
TR_MODE.MODE0 = 0 (NT state machine)
or
TR_MODE.MODE0 = 1 (LT-S state machine)
TR_MODE.MODE1 = 1
TR_MODE.MODE2 = 1
Layer 2
Enable S/G bit
evaluation
D-channel Mode Register:
MODED.DIM2-0 = 001
Note: For mode selection in the TR_MODE register the MODE2/1 bits are used to select
intelligent NT mode, MODE0 selects NT or LT-S state machine.
With the configuration settings shown above the ISAC-SX in intelligent NT applications
provides for equal access to the D-channel for terminals connected to the S-interface
and for D-channel sources on IOM-2.
For a detailed understanding the following sections provide a complete description on
the procedures used by the D-channel priority handler on IOM-2, although it may not be
necessary to study that in order to use this mode.
Data Sheet
127
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
1. NT D-Channel Controller Transmits Upstream
In the initial state (’Ready’ state) neither the local D-channel sources nor any of the
terminals connected to the S-bus transmit in the D-channel.
The ISAC-SX S-transceiver thus receives BAC = “1” (IOM-2 DU line) and transmits
S/G = “1” (IOM-2 DD line). The access will then be established according to the following
procedure:
• Local D-channel source verifies that BAC bit is set to ONE (currently no bus access).
• Local D-channel source issues TIC bus address and verifies that no controller with
higher priority requests transmission (TIC bus access must always be performed even
if no other D-channel sources are connected to IOM-2).
• Local D-channel source issues BAC = “0” to block other sources on IOM-2 and to
announce D-channel access.
• ISAC-SX S-transceiver pulls S/G bit to ZERO (’Idle’ state) as soon as n D-bits = ’1’ are
counted on IOM-2 (see note) to allow for further D-channel access.
• ISAC-SX S-transceiver transmits inverted echo channel (E bits) on the S-bus to block
all connected S-bus terminals (E = D).
• Local D-channel source commences with D data transmission on IOM-2 as long as it
receives S/G = “0”.
• After D-channel data transmission is completed the controller sets the BAC bit to
ONE.
• ISAC-SX S-transceiver transmits non-inverted echo (E = D).
• ISAC-SX S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel
controller on IOM-2.
Note: Right after transmission the S/G bit is pulled to ’1’ until n successive D-bits = ’1’
occur on the IOM-2 interface. As soon as n D-bits = ’1’ are seen, the S/G bit is set
to ’0’ and the ISAC-SX D-channel controller may start transmission again (if TIC
bus is occupied). This allows an equal access for D-channel sources on IOM-2
and on the S interface.
The number n depends on configuration settings (selected priority 8 or 10) and the
condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10,
respectively) or if the last transmission was successful (n = 9 or 11, respectively).
Figure 68 illustrates the signal flow in an intelligent NT and the algorithm of the D-
channel priority handler on IOM-2 implemented in the ISAC-SX.
Data Sheet
128
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• ISAC-SX S-transceiver (in intelligent NT) recognizes that the D-channel on the S-bus
is active.
• ISAC-SX S-transceiver transfers S-bus D-channel data transparently through to the
upstream IOM-2 bus (IOM-2 channel 0).
For both cases described above the exchange indicates via the A/B bit (controlled by
layer 1) that D-channel transmission on this line is permitted (A/B = “1”). Data
transmission could temporarily be prohibited by the exchange when only a single
D-channel controller handles more lines (A/B = “0”, ELIC-concept).
In case the exchange prohibits D data transmission on this line the A/B bit is set to “0”
(block). For UPN applications with S extension this forces the intelligent NT ISAC-SX S-
transceiver to transmit an inverted echo channel on the S-bus, thus disabling all terminal
requests, and switches S/G to A/B, which blocks the D-channel controller in the
intelligent NT.
Note: Although the ISAC-SX S-transceiver operates in LT-S mode and is pinstrapped to
IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position.
D-channel controller
e.g. ICC PEB 2070
TE
DS
BAC
D-channel
E-channel
DIOM
DU
DD
U
TE
Layer 1
Exchange
transceiver
D
S/G
A/B
S/G
D
DD BAC TBA
IOM-2
Masterdevice,
e.g. IEC-Q TE
D-channel
controller
(TE mode timing)
TE
3086_03
Figure 68
Data Flow for Collision Resolution Procedure in Intelligent NT
Data Sheet
129
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.7.6
Activation/Deactivation of IOM-2 Interface
The IOM-2 interface can be switched off in the inactive state, reducing power
consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and
the data lines are ’1’.
The IOM-2 interface can be kept active while the S interface is deactivated by setting the
CFS bit to "0" (MODE1 register). This is the case after a hardware reset. If the IOM-2
interface should be switched off while the S interface is deactivated, the CFS bit should
be set to ’1’. In this case the internal oscillator is disabled when no signal (info 0) is
present on the S bus and the C/I command is ’1111’ = DIU. If the TE wants to activate
the line, it has first to activate the IOM-2 interface either by using the "Software Power
Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again.
The deactivation procedure is shown in Figure 69. After detecting the code DIU
(Deactivate Indication Upstream) the layer 1 of the ISAC-SX responds by transmitting
DID (Deactivate Indication Downstream) during subsequent frames and stops the timing
signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth frame.
IOM -2
FSC
IOM -2
Deactivated
DI
DI
DI
DI
DI
DI
DI
DI
DI
DU
DD
DR
DR
DR
DR
DR
DC
DC
DC
DC
B1
B2
D
CIO
D
CIO
DCL
ITD09655_s.vsd
Figure 69
Deactivation of the IOM-2 Interface
The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the
IOM_CR register), i.e. the C/I command TIM = "0000" is received by layer 1, or when a
non-zero level on the S-line interface is detected (if TR_CONF0.LDD=0). The clocks are
turned on after approximately 0.2 to 4 ms depending on the oscillator.
Data Sheet
130
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit IOM_CR =’0’ and the C/I code written to CIX0 before (e.g. TIM or
AR8) is output on DU.
The ISAC-SX supplies IOM-2 timing signals as long as there is no DIU command in the
C/I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
CIC : CIXO = TIM
SPU = 1
Int.
SPU = 0
FSC
DU
TIM
PU
TIM
PU
TIM
PU
PU
PU
DD
FSC
DU
IOM R -CH1
IOM R -CH1
IOM R -CH2
IOM R -CH2
B1
B1
0.2 to 4 ms
DD
MR MX
DCL
ITD09656
132 x DCL
Note: The value “132 x DCL” is only valid for
IOM configurations with 3 IOM channels.
Figure 70
Activation of the IOM-2 interface
Data Sheet
131
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Asynchronous Awake (LT-S, NT, Int. NT mode)
The transceiver is in power down mode (deactivated state) and MODE1.CFS=1
(TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect
circuit will asynchronously pull the DU line on IOM-2 to “0” which is deactivated again
after 2 ms if the oscillator is fully operational. If the oscillator is just starting up in
operational mode, the 2 ms duration is extended correspondingly.
Data Sheet
132
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.8
Auxiliary Interface
3.8.1
Mode Dependent Functions
The AUX interface provides various functions, which depend on the operation mode (TE,
LT-T, LT-S, NT or Intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see
Table 14). After reset the pins are switched as inputs until further configuration is done
by the host.
Table 14
Pin
AUX Pin Functions
TE, Int. NT mode
AUX0 (i/o)
LT-T, LT-S, NT mode
CH0 (i)
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
AUX6
AUX7
AUX1 (i/o)
CH1 (i)
AUX2 (i/o)
CH2 (i)
AUX3 (i/o)
AUX3 (i/o)
AUX4 (i/o) / MBIT
AUX5 (i/o) / FBOUT (o)
INT0 (i/o)
AUX4 (i/o) / MBIT
AUX5 (i/o) / FBOUT (o)
INT0 (i/o)
INT1 (i/o) / SGO (o)
INT1 (i/o) / SGO (o)
AUX0-5 (TE, Int. NT mode), AUX3-5 (LT-T, LT-S, NT mode)
These pins can be used as programmable I/O lines.
As inputs (AOE.OEx=1) the state at the pin is latched in when the host performes read
operation to register ARX.
As outputs (AOE.OEx=0) the value in register ATX is driven on the pins with a minimum
delay after the write operation to this register is performed. They can be configured as
open drain (ACFG1.ODx=0) or push/pull outputs (ACFG1.ODx=1). The status (’1’ or ’0’)
at output pins can be read back from register ARX, which may be different from the ATX
value, e.g. if another device drives a different level.
FBOUT
AUX5 is multiplexed with the selectable FSC/BCL output FBOUT, i.e. the host can select
either standard I/O characteristic (ACFG2.A5SEL=0, default) or FBOUT functionality
(ACFG2.A5SEL=1). FBOUT provides either an FSC (ACFG2.FBS=0, default) or BCL
signal (ACFG2.FBS=1) which are derived from the DCL clock (also see Chapter 3.4).
Data Sheet
133
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
INT0, INT1
In all modes two pins can be used as programmable I/O with optional interrupt input
capability (default after reset, i.e. both interrupts masked).
The INT0/1 pins are general input or output pins like AUX0-5 (see description above).
In addition to that, as inputs they can generate an interrupt to the host (AUXI.INT0/1)
which is maskable in AUXM.INT0/1. The interrupt input is either edge or level triggered
(ACFG2.EL0/1).
As outputs both pins can directly be connected to an LED with preresistor.
For both pins AUX6/7 internal pull-up resistors are provided if the pin is configured as
input or as output with open drain chracteristic. The internal pull-ups are disabled if
output mode with push/pull characteristic is selected.
SGO
AUX7 provides the additional capability to output the S/G bit from the IOM-2 interface by
setting ACFG2.A7SEL=1.
MBIT
If ACFG2.A4SEL is set to “1” the pin AUX4 is used for Multiframe Synchronizstion (see
Chapter 3.3.3) and all configuration as general purpose I/O pin is don’t care. In TE and
LT-T modes it is used as M-Bit output and in LT-S, NT and Int. NT mode it is used as M-
Bit input.
Data Sheet
134
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
CH0, CH1, CH2
In linecard mode one FSC frame is a multiplex of up to eight IOM-2 channels, each of
them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits.
So in LT-T and LT-S mode one of eight channels on the IOM-2 interface is selected by
CH0-2. These pins must be strapped to VDD or VSS according to Table 15.
Table 15
IOM-2 Channel Selection
CH2 CH1 CH0 Channel on IOM-2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
For DCL = 1.536 MHz one of the IOM-2 channels 0 - 2 can be selected, for DCL = 4.096
MHz any of the eight IOM-2 channels can be selected.
The channel select pins have direct effect on the timeslot selection of the following
registers:
• TR_TSDP_BC1
• TR_TSDP_BC2
• TR_CR, TRC_CR
• DCI_CR, DCIC_CR
• MON_CR
Data Sheet
135
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9
HDLC Controllers
The ISAC-SX contains two HDLC controllers. The first one is used for the layer-2
functions of the D- channel protocol (LAPD), the second one provides B-channel access
with reduced FIFO thresholds which can be used for firmware upgrade via the line for
example. By setting the Enable HDLC channel bits (EN_D, EN_B1H) in the DCI_CR/
BCH_CR registers each of the HDLC controllers can access the D or B-channels on
IOM-2.
They perform the framing functions used in HDLC based communication: flag
generation/recognition, bit stuffing, CRC check and address recognition.
The FIFO has a size of 64 byte per direction for the D-channel and 128 byte per direction
for the B-channel. They are implemented as cyclic buffers. The transceiver reads and
writes data sequentially with constant data rate whereas the data transfer between FIFO
and microcontroller uses a block oriented protocol with variable block sizes.
The configuration, control and status bits related to the HDLC controllers are all assigned
to the following address ranges:
Table 16
HDLC Controller Address Range
FIFO
Config/Ctrl/Status
Address
Registers
20H-29H
70H-79H
D-channel
B-channel
00H-1FH
7AH
Note: For B-channel data access a single address location is used to read from and write
to the FIFO. For D-channel access the address range 00H-1FH is used (similar as
in ISAC-S PEB 2086), however a single address from this range is sufficient to
access the FIFO as the internal FIFO pointer is incremented automatically
independent from the external address.
The mechanisms for access to the FIFOs are identical for D- and B-channels, therefore
the following description applies to both of them and for simplification specific references
like registers are indicated by an “x” (stands for “D” and “B”) to indicate it is relevant for
D- and B-channel (e.g. ISTAx means ISTAD/ISTAB).
Data Sheet
136
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.1
Message Transfer Modes
The HDLC controllers can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a D-channel two-byte address (LAPD) is shown below:
High Address Byte
SAPI1, 2, SAPG
Low Address Byte
TEI 1, 2, TEIG
C/R 0
EA
For address recognition on the D-channel the ISAC-SX contains four programmable
registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values
for the “group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
The structure of a B-channel two-byte address is as follows:
High Address Byte
Low Address Byte
RAH1, 2, Group Address C/R 0
RAL1, 2, Group Address
For address recognition on the B-channel the ISAC-SX contains four programmable
registers for individual Receive Address High and Low values (RAH1, 2 and RAL1, 2),
plus two fixed values for the High Address Byte (Group Address = ’FE’ or ’FC’) and one
fixed value for the Low Address Byte (Group Address = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
Operating Modes
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEx registers:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
All frames with valid addresses are accepted and the bytes following the address are
transferred to the=µP via RFIFOx. Additional information is available in RSTAx.
Data Sheet
137
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Transparent mode 0 (MDS2-0 = ’110’).
Characteristics: no address recognition
Every received frame is stored in RFIFOx (first byte after opening flag to CRC field).
Additional information can be read from RSTAx.
Transparent mode 1 (MDS2-0 = ’111’).
Characteristics:
SAPI recognition (D-channel)
High byte address recognition (B-channel)
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FEH/FCH) for D-channel, and with RAH1, RAH2 and group address (FEH/
FCH) for B-channel. In the case of a match, all the following bytes are stored in RFIFOx.
Additional information can be read from RSTAx.
Transparent mode 2 (MDS2-0 = ’101’).
Characteristics:
TEI recognition (D-channel)
Low byte address recognistion (B-channel)
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FFH) for D-channel, and with RAL1 and RAL2 for B-channel. In
case of a match the rest of the frame is stored in the RFIFOx. Additional information is
available in RSTAx.
Extended transparent mode (MDS2-0 = ’100’).
Characteristics:
fully transparent
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to Chapter 3.9.5.
Data Sheet
138
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.2
Data Reception
3.9.2.1 Structure and Control of the Receive FIFO
The cyclic receive FIFO buffers with a length of 64 byte for D-channel and 128 byte for
B-channel have variable FIFO block sizes (thresholds) of
• 4, 8, 16 or 32 bytes for D-channel and
• 8 or 16 bytes for B-channel
which can be selected by setting the corresponding RFBS bits in the EXMx registers.
The variable block size allows an optimized HDLC processing concerning frame length,
I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
microcontroller as master. The control of the data transfer between the CPU and the
ISAC-SX is handled via interrupts (ISAC-SX → Host) and commands (Host → ISAC-
SX).
There are three different interrupt indications in the ISTAx registers concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
(EXMx.RFBS) can be read from RFIFOx. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
– RME (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
• a short message is received
(message length ≤ the defined block size (EXMx.RFBS)) or
• the last part of a long message is received
(message length > the defined block size (EXMx.RFBS))
and is stored in the RFIFOx.
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
be stored in RFIFOx and is therefore lost as the RFIFOx is occupied. This occurs if
the host fails to respond quickly enough to RPF/RME interrupts since previous data
was not read by the host.
There are two control commands that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the ISAC-SX that a data block
has been read from the RFIFOx and the corresponding FIFO space can be released
for new receive data.
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. Pending interrupt indications of the receiver
are not cleared by RRES, but have to be cleared by reading these interrupts.
Note: The significant interrupts and commands are underlined as only these are
commonly used during a normal reception sequence.
Data Sheet
139
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
The following description of the receive FIFO operation is illustrated in Figure 71 for a
RFIFOx block size (threshold) of 16 and 32 bytes.
The RFIFOx requests service from the microcontroller by setting a bit in the ISTAx
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCHx,RBCLx), data from the RFIFOx and then may change the
receive FIFO block size (EXMx.RFBS). A block transfer is completed by the
microcontroller via a receive message complete (CMDRx.RMC) command. This causes
the space of the transferred bytes being released for new data and in case the frame was
complete (RME) the reset of the receive byte counter RBC (RBCHx,RBCLx).
The total length of the frame is contained in the RBCHx and RBCLx registers which
contain a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted.
If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least
significant bits of RBCLx contain the number of valid bytes in the last data block indicated
by RMEx (length of last data block ≤ selected block size). Table 17 shows which RBC
bits contain the number of bytes in the last data block or number of complete data blocks
respectively. If the number of bytes in the last data block is ’0’ the length of the last
received block is equal to the block size.
Table 17
Receive Byte Count with RBC11...0 in the RBCHx/RBCLx registers
EXMD1.RFBS EXMB.RFBS Selected
Number of
bits
(D-channel)
bit
block size
complete
data blocks in
bytes in the last
data block in
(B-channel)
’00’
’01’
’10’
’11’
--
32 byte
16 byte
8 byte
RBC11...5
RBC11...4
RBC11...3
RBC11...2
RBC4...0
RBC3...0
RBC2...0
RBC1...0
’0’
’1’
--
4 byte
The transfer block size (EXMx.RFBS) is 32 bytes for D-channel and 16 bytes for B-
channel by default. If it is necessary to react to an incoming frame within the first few
bytes the microcontroller can set the RFIFOx block size to a smaller value. Each time a
CMDRx.RMC or CMDRx.RRES command is issued, the RFIFOx access controller sets
its block size to the value specified in EXMR.RFBS, so the microcontroller has to write
the new value for RFBS before the RMC command. When setting an initial value for
RFBS before the first HDLC activities, a RRES command must be issued afterwards.
The RFIFOx can hold any number of frames fitting in the 64 bytes (D-channel)/128 bytes
(B-channel). At the end of a frame, the RSTAx byte is always appended.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet
140
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
RAM
RAM
EXMx.RFBS=11
The µP has read
32
16
32
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAx.RPF
is set.
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDRx.RMC command.
Following CMDRx.RMC
the 4 bytes of the
last block are
RFACC
RFACC
RFIFO ACCESS
CONTROLLER
RFIFO ACCESS
CONTROLLER
16
RFBS=11
RFBS=01
deleted.
8
8
4
4
HDLC
Receiver
HDLC
Receiver
EXMx.RFBS=01
RMC
µP
RAM
RAM
HDLC
Receiver
32
32
RSTA
RFACC
RFACC
The HDLC
receiver has
HDLC
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTAx)
is appended.
Meanwhile two
more short frames
have been
Receiver
RFIFO ACCESS
CONTROLLER
RFIFO ACCESS
CONTROLLER
RSTA
RSTA
16
16
RSTA
RFBS=01
RFBS=01
8
8
RSTA
RSTA
received.
RMC
µP
µP
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDRx.RMC.
This causes the space occupied by the 16 bytes being
released.
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
Figure 71
RFIFO Operation
Data Sheet
141
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Possible Error Conditions during Reception of Frames
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow
(RDO) byte in the RSTAx byte will be set. If a complete frame is lost, i.e. if the FIFO is
full when a new frame is received, the receiver will assert a Receive Frame Overflow
(RFO) interrupt.
The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it
reads the same data again and again. On the other hand, if it doesn’t read or doesn’t
want to read all data, they are deleted anyway after the RMC command.
If the microcontroller reads data without a prior RME or RPF interrupt, the content of the
RFIFOx would not be corrupted, but new data is only transferred to the host as long as
new valid data is available in the RFIFOx, otherwise the last data is read again and
again.
The general procedures for a data reception sequence are outlined in the flow diagram
in Figure 72.
Data Sheet
142
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
START
Receive
Message End
RME
Y
?
N
Receive
Pool Full
RPF
N
?
Y
Read Counter
RD_Count := RFBS
or
Read RBC
RD_Count := RBC
RD_Count := RBC
1)
*
Read RD_Count
bytes from RFIFO
Change Block Size
Write EXMR.RFBS
(optional)
x
x
Receive Message
Complete
Write RMC
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
1) In case of RME the last byte in RFIFO contains
the receive status information RSTA
*
HDLC_Rflow.vsd
Figure 72
Data Reception Procedures
Data Sheet
143
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
Figure 73 gives an example of an interrupt controlled reception sequence, supposed
that a long frame (68 byte) followed by two short frames (12 byte each) are received. The
FIFO threshold (block size) is set to 32 byte in this example:
• After 32 byte of frame 1 have been received an RPF interrupt is generated to indicate
that a data block can be read from the RFIFOx.
• The host reads the first data block from RFIFOx and acknowledges the reception by
RMC. Meanwhile the second data block is received and stored in RFIFOx.
• The second 32 byte block is indicated by RPF which is read and acknowledged by the
host as described before.
• The reception of the remaining 4 bytes plus RSTAx are indicated by RME (i.e. the
receive status is always appended to the end of the frame).
• The host gets the number of bytes (COUNT = 5) from RBCLx/RBCHx and reads out
the RFIFOx and optionally the status register RSTA. The frame is acknowledged by
RMC.
• The second frame is received and indicated by RME interrupt.
• The host gets the number of bytes (COUNT = 13) from RBCLx/RBCHx and reads out
the RFIFOx and optionally the status register. The RFIFOx is acknowledged by RMC.
• The third frame is transferred in the same way.
IOM Interface
Receive
Frame
68
Bytes
12
12
Bytes Bytes
32
32
4
12
12
RD
32 Bytes
RD
32 Bytes
RD
RD
RD
RD
RD
RD
Count 5 Bytes
Count 13 Bytes
Count 13 Bytes
1)
*
1)
*
1)
*
RPF
RMC RPF
RMC RME
RMC RME
RMC RME
RMC
CPU Interface
1) The last byte contains the receive status information <RSTA>
*
fifoseq_rec.vsd
Figure 73
Reception Sequence Example
Data Sheet
144
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.2.2 Receive Frame Structure
The management of the received HDLC frames as affected by the different operating
modes (see Chapter 3.9.1) is shown in Figure 74.
FLAG
ADDR
CTRL
I
CRC
FLAG
ADDRESS
CONTROL DATA
RFIFOx
STATUS
*1)
MDS2 MDS1 MDS0
MODE
*4)
RSTAx
0
1
1
Non
Auto/16
SAP1
TEI1
TEI2
TEIG
*2)
SAP2
SAPG
*2)
D-channel
RAH1
RAH2
Gr.Adr. Gr.Adr.
RAL1
RAL2
B-channel
*2)
*2)
*4)
RFIFOx
*1)
RSTAx
0
1
0
Non
Auto/8
TEI1
TEI2
*2)
_
_
D-channel
*3)
*3)
RAL1
RAL2
*2)
B-channel
*4)
*4)
RFIFOx
RFIFOx
*1)
*1)
RSTAx
RSTAx
1
1
1
1
0
1
Transparent 0
Transparent 1
D-channel
SAP1
SAP2
SAPG
*2)
RAH1
RAH2
Gr.Adr.
*2)
B-channel
RFIFOx
*4)
*1)
RSTAx
1
0
1
Transparent 2
D-channel
TEI1
TEI2
TEIG
*2)
RAL1
RAL2
*2)
B-channel
Description of Symbols:
*1) CRC optionally stored in RFIFOx if EXMx:RCRC=1
*2) Address optionally stored in RFIFOx if EXMx:SRA=1
*3) Start of the control field in case of an 8 bit address
Compared with registers
(D- or B-channel)
Stored in FIFO/registers
*4) Content of RSTA register appended at the frameend into RFIFOx
21150_13
Figure 74
Receive Data Flow
Data Sheet
145
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
The ISAC-SX indicates to the host that a new data block can be read from the RFIFOx
by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFOx
and information about the received frame is available in the RBCLx and RBCHx registers
and the RSTAx bytes which are listed in Table 18.
Table 18
Receive Information at RME Interrupt
Register Bit
Information
Mode
Type of frame
(Command/
Response)
RSTAx
C/R
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of SAPI
RSTAD
RSTAB
SA1, 0
HA1, 0
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of TEI
RSTAD
RSTAB
TA
LA
All except
transparent mode 0
Result of CRC check
(correct/incorrect)
RSTAx
CRC
All
Valid Frame
RSTAx
RSTAx
VFR
RAB
All
All
Abort condition detected
(yes/no)
Dataoverflow duringreception RSTAx
of a frame (yes/no)
RDO
All
Number of bytes received in
RFIFO
RBCL
RBC4-0 All
RBC11-0 All
Message length
RBCLx
RBCHx
RFIFO Overflow
RBCHx
OV
All
The RSTAx register is always appended in the RFIFOx as last byte to the end of a frame.
Note: The number of bytes received in RFIFOx depends on the selected receive FIFO
threshold (EXMx.RFBS).
Data Sheet
146
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.3
Data Transmission
3.9.3.1 Structure and Control of the Transmit FIFO
The cyclic transmit FIFO buffers with a length of 64 byte for D-channel and 128 byte for
B-channel have FIFO block sizes (thresholds) of
• 16 or 32 bytes (programmable) for D-channel and
• 32 bytes for B-channels
which can be selected by setting the corresponding XFBS bits in the EXMx registers.
There are three different interrupt indications in the ISTAx registers concerned with the
transmission of data:
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
(D-channel), or 32 byte (B-channel) can be written to the XFIFOx (fixed block size).
An XPR interrupt is generated either
• after an XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
• when a data block from the XFIFOx is transmitted and the corresponding FIFO
space is released to accept further data from the host.
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
current frame has been aborted (seven consecutive ’1’s are transmitted) as the
XFIFOx holds no further transmit data. This occurs if the host fails to respond to an
XPR interrupt quickly enough.
– Only valid for D-channel:
XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFOx does not hold the first data bytes of the frame (collision after the 16th/
32nd byte or after the 32nd byte of the frame, respectively).
The occurence of an XDU or XMR interrupt clears the XFIFOx and an XMR interrupt
is issued together with an XDU or XMR interrupt, respectively. Data cannot be written
to the XFIFOx as long as an XDU/XMR interrupt is pending.
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the ISAC-SX that up to 16 or 32
byte (D-channel) or 32 (B-channel) have been written to the XFIFOx and should be
transmitted. A start flag is generated automatically.
– XME (Transmit Message End) command, telling the ISAC-SX that the last data block
written to the XFIFOx completes the corresponding frame and should be transmitted.
This implies that according to the selected mode a frame end (CRC + closing flag) is
generated and appended to the frame.
Data Sheet
147
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
transmit FIFO of any data. After an XRES command the transmitter always sends an
abort sequence, i.e. this command can be used to abort a transmission. Pending
interrupt indications of the transmitter are not cleared by XRES, but have to be cleared
by reading these interutps.
Optionally two additional status conditions can be read by the host:
– XDOV (Transmit Data Overflow), indicating that the data block size has been
exceeded, i.e. more than 16 or 32 byte (D-channel) or 32 byte (B-channel) were
entered and data was overwritten.
– XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFOx.
This status flag may be polled instead of or in addition to XPR.
Note: The significant interrupts and commands are underlined as only these are usually
used during a normal transmission sequence.
The XFIFO requests service from the microcontroller by setting a bit in the ISTAx
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STARx (XFW, XDOV), write data in the FIFO and it can change the
transmit FIFO block size (EXMD.XFBS, for D-channel only) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in Table 19.
Table 19
XPR Interrupt (availability of XFIFOx) after XTF, XME Commands
CMDRx
Register
Transmit pool ready (XPR) interrupt initiated ...
XTF
as soon as the selected buffer size in the FIFOx is available.
XTF & XME
after the successful transmission of the closing flag.
The transmitter always sends an abort sequence.
XME
as soon as the selected buffer size in the FIFO is available,
two consecutive frames share flags.
When setting XME the transmitter appends the CRC and the endflag at the end of the
frame. When XTF & XME has been set, the XFIFOx is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame whereas after XME or XTF the XPR interrupt is
asserted as soon as there is space for one data block in the XFIFOx.
The transfer block size is 32 bytes for D- and B-channel by default, but sometimes, if the
microcontroller has a high computational load, it is useful to increase the maximum
Data Sheet
148
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
reaction time for an XPR interrupt. However, the threshold can only be changed for D-
channel. The maximum reaction time is:
t
max = (XFIFOx size - XFBS) / data transmission rate
With a selected block size of 16 bytes (D-channel only) an XPR interrupt indicates when
a transmit FIFO space of at least 16 bytes is available to accept further data, i.e. there
are still a maximum of 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes
block size (D- or B-channel) the XPR is initiated when a transmit FIFO space of at least
32 bytes is available to accept further data, i.e. there are still a maximum of 32 bytes (D-
channel: 64 bytes - 32 bytes) or 96 bytes (B-channel: 128 bytes - 32 bytes) to be
transmitted. The maximum reaction time for the smaller block size is 50 % higher with
the trade-off of a doubled interrupt load. With a selected block size an XPR always
indicates the available space in the XFIFOx, so any number of bytes smaller than the
selected XFBS may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF, XME or XRES command. XRES resets the XFIFOx.
The XFIFOx can hold any number of frames fitting in the 64 bytes (D-channel) or 128
bytes (B-channel), respectively.
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller doesn’t react fast enough
to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes for D-channel; 32 byte for B-channel), in this case
an XMR transmit message repeat interrupt is set and the microcontroller has to send the
whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFOx. The XFIFOx is locked while
an XMR or XDU interrupt is pending, i.d. all write actions of the microcontroller will be
ignored as long as the microcontroller hasn’t read the ISTAx register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (block size), then the data in the
XFIFOx will be corrupted and the STARx.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDRx.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in Figure 75.
Data Sheet
149
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
START
Transmit
Pool Ready
XPR
N
?
Y
Write one
data block
to XFIFO
Command
XTF
End of
Message
?
N
Y
Command
XTF+XME
End
21150_25
Figure 75
Data Transmission Procedure
Data Sheet
150
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
The following description gives an example for the transmission of a 76 byte frame with
a selected block size of 32 byte:
• The host writes 32 bytes to the XFIFOx, issues an XTF command and waits for an
XPR interrupt in order to continue with entering data.
• The ISAC-SX immediately issues an XPR interrupt (as remaining XFIFOx space is not
used) and starts transmission.
• Due to the XPR interrupt the host writes the next 32 bytes to the XFIFOx, followed by
the XTF command, and waits for XPR.
• As soon as the last byte of the first block is transmitted, the ISAC-SX releases an XPR
(XFIFOx space of first data block is free again) and continues transmitting the second
block.
• The host writes the remaining 12 bytes of the frame to the XFIFOx and issues the XTF
command together with XME to indicate that this is the end of frame.
• After the last byte of the frame has been transmitted the ISAC-SX releases an XPR
interrupt and the host may proceed with transmission of a new frame.
IOM Interface
76 Bytes
Transmit
Frame
32
32
12
WR
12 Bytes
WR
32 Bytes
WR
32 Bytes
XTF+XME
XPR
XPR
XTF XPR
XTF
CPU Interface
fifoseq_tran.vsd
Figure 76
Transmission Sequence Example
Data Sheet
151
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.3.2 Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in Figure 77.
For transparent frames, the whole frame including address and control field must be
written to the XFIFOx. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMx.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDCL frames (EXMx.ITF). One option is to send continuous flags (’01111110’), however
if D-channel access handling (collision resolution on the S bus) is required, the signal
must be set to idle (continuous ’1’s are transmitted). Reprogramming of ITF takes effect
only after the transmission of the current frame has been completed or after an XRES
command.
FLAG
ADDR
CTRL
I
CRC
FLAG
ADDRESS
CONTROL DATA
XFIFO
CHECKRAM
1)
*
Transmit Transparent Frame
(XTF)
1)
*
The CRC is generated by default.
fifoflow_tran.vsd
If EXMR.XCRC is set no CRC is appended
Figure 77
3.9.4
Transmit Data Flow
Access to IOM-2 channels
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the DCI_CR register
(D-channel) and in the BCH_CR register (B-channel) the HDLC controller can access
the D, B1 and B2 channels or any combination of them. In all modes (except extended
transparent mode) transmission always works frame aligned, i.e. it starts with the first
selected channel, whereas reception searches for a flag anywhere in the serial data
stream.
Data Sheet
152
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.5
Extended Transparent Mode
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register DCI_CR or BCH_CR in the
IOM-2 Handler) of the next IOM-2 frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled in D-channel (MODE.DIM = ’0x1’) the stop go bit (S/
G) can be used as clear to send indication as in any other mode. If the S/G bit is set to
’1’ (stop) during transmission the transmitter responds always with an XMR (transmit
message repeat) interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
Receiver
The reception is IOM-2 frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of registers
DCI_CR and BCH_CR in the IOM-2 Handler) of the next IOM-2 frame. The FIFO
indications and commands are the same as in others modes.
All incoming data bytes are stored in the RFIFOx and is additionally made available in
RSTAx. If the FIFO is full an RFO interrupt is asserted (EXMx.SRA = ’0’).
Note: In the extended transparent mode the EXMx register has to be set to ’xxx00000’
Data Sheet
153
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.9.6
HDLC Controller Interrupts
The cause of an interrupt related to the HDLC controllers is indicated in the ISTA register
by the ICD bit for D-channel and ICB for B-channel. These bits point to the different
interrupt sources of the HDLC controllers in the ISTAD and ISTAB registers. The
individual interrupt sources of the HDLC controllers during reception and transmission of
data are explained in Chapter 3.9.2.1 or Chapter 3.9.3.1 respectively.
B-channel
MASK
ICB
ISTA
ICB
MASKB
RME
RPF
ISTAB
RME
RPF
ST
CIC
ST
CIC
RFO
RFO
XPR
XPR
AUX
TRAN
MOS
ICD
AUX
TRAN
MOS
ICD
D-channel
XDU
XDU
MASKD
ISTAD
RME
RPF
RME
RPF
RFO
XPR
XMR
XDU
RFO
XPR
XMR
XDU
Interrupt
3086_16.vsd
Figure 78
Interrupt Status Registers of the HDLC Controllers
Each interrupt source in the ISTAD and ISTAB registers can selectively be masked by
setting the corresponding bit in MASKD/MASKB to “1”.
Data Sheet
154
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
3.10
Test Functions
The ISAC-SX provides test and diagnostic functions for the S-interface, the D-channel
and each of the two B-channels:
• Digital loop via TLP (Test Loop, TMD and TMB registers) command bit (Figure 79):
The TX path of layer 2 is internally connected with the RX path of layer 2. The output
from layer 1 (S/T) on DD is ignored. This is used for testing ISAC-SX functionality
excluding layer 1 (loopback between XFIFOx and RFIFOx).
TMx.TLP = ’0’
TMx.TLP = ’1’
Figure 79
Layer 2 Test Loops
• Test of layer-2 functions while disabling all layer-1 functions and pins associated with
them (including clocking) via bit TR_CONF0.DIS_TR. The HDLC controllers can still
operate via IOM-2. DCL and FSC pins become input.
Data Sheet
155
2000-08-03
PEB 3086
PEF 3086
Description of Functional Blocks
• loop at the analog end of the S interface;
TE / LT-T mode
Test loop 3 is activated with the C/I channel command Activate Request Loop
(ARL). An S interface is not required since INFO3 is looped back internally to the
receiver. When the receiver has synchronized itself to this signal, the message "Test
Indication" (or "Awake Test Indication") is delivered in the C/I channel. No signal is
transmitted over the S interface.
In the test loop mode the S interface awake detector is enabled, i.e. if a level is
detected (e.g. Info 2/Info 4) this will be reported by the Resynchronization Indication
(RSY). The loop function is not effected by this condition and the internally
generated 192-kHz line clock does not depend on the signal received at the S
interface.
NT / LT-S mode
Test loop 2 is likewise activated over the IOM-2 interface with Activate Request
Loop (ARL). No S line is required. INFO4 is looped back internally to the receiver
and also sent to the S interface. When the receiver is synchronized, the message
"AIU" is sent in the C/I channel.
• transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register.
Two kinds of test signals may be sent by the ISAC-SX:
– single pulses and
– continuous pulses.
The single pulses are of alternating polarity, one S interface bit period wide, 0.25 ms
apart, with a repetition frequency of 2 kHz. Single pulses can be sent in all
applications. The corresponding C/I command in TE, LT-S and LT-T applications is
TM1.
Continuous pulses are likewise of alternating polarity, one S-interface bit period
wide, but they are sent continuously. The repetition frequency is 96 kHz. Continuous
pulses may be transmitted in all applications. This test mode is entered in LT-S,
LT-T and TE applications with the C/I command TM2.
Data Sheet
156
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4
Detailed Register Description
The register mapping of the ISAC-SX is shown in Figure 80.
FFh
(Not used)
80h
B-channel
70h
Interrupt, General Configuration
60h
IOM-2 and MONITOR Handler
40h
Transceiver, Auxiliary Interface
30h
D- and C/I-channel
00h
3086_04
Figure 80
Register Mapping of the ISAC-SX
The register address range from 00H-2FH is assigned to the D-channel HDLC controller
and the C/I-channel handler.
The register set ranging from 30H-3FH pertains to the transceiver and auxiliary interface
registers.
Data Sheet
157
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
The address range from 40H-5BH is assigned to the IOM handler with the registers for
timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver
data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA),
serial data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt
(STI).
The address range from 5CH-5FH pertains to the MONITOR handler.
General interrupt and configuration registers are contained in the address range
60H-65H.
The address range 70H-7FH is assigned to the B-channel FIFOs and HDLC controller.
The register summaries of the ISAC-SX are shown in the following tables containing the
abbreviation of the register name and the register bits, the register address, the reset
values and the register type (Read/Write). A detailed register description follows these
register summaries.
The register summaries and the description are sorted in ascending order of the register
address.
Data Sheet
158
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
D-channel HDLC, C/I-channel Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
RFIFOD
D-Channel Receive FIFO
00H-
1FH
R
XFIFOD
ISTAD
D-Channel Transmit FIFO
00H-
1FH
W
RME RPF RFO XPR XMR XDU
0
1
0
1
0
20H
20H
21H
R 10H
W FFH
R 40H
W 00H
MASKD RME RPF RFO XPR XMR XDU
STARD XDOV XFW
CMDRD RMC RRES
0
0
0
STI
0
RACI
XTF
0
0
XACI
XME XRES 21H
MODED MDS2 MDS1 MDS0
RAC DIM2 DIM1 DIM0
22H R/WC0H
23H R/W 00H
24H R/W 00H
EXMD1 XFBS
TIMR1
RFBS
CNT
SRA XCRC RCRC
VALUE
0
ITF
SAP1
SAPI1
SAPI2
0
0
MHA
MLA
25H
26H
W FCH
W FCH
R 00H
R 00H
W FFH
W FFH
R 0FH
SAP2
RBCLD RBC7
RBC0 26H
RBC8 27H
RBCHD
TEI1
0
0
0
OV RBC11
TEI1
TEI2
EA1
EA2
TA
27H
28H
28H
TEI2
RSTAD
TMD
VFR RDO CRC RAB SA1 SA0
C/R
0
0
0
0
0
0
0
TLP
29H R/W 00H
2A-2DH
2EH
TBA2 TBA1 TBA0 BAC 2EH
reserved
CIR0
CIX0
CODR0
CODX0
CIC0 CIC1 S/G BAS
R F3H
W FEH
Data Sheet
159
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
CIR1
CIX1
CODR1
CODX1
CICW CI1E
CICW CI1E
2FH
R
FEH
2FH W FEH
Transceiver, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
30H R/W 01H
TR_
CONF0
DIS_ BUS EN_
0
0
L1SW
0
x
0
EXLP LDD
TR
ICV
TR_
CONF1
0
RPLL_ EN_
ADJ SFSC
0
0
0
x
x
31H R/W
TR_
CONF2
DIS_ PDS
TX
0
RLP
SGP SGD
32H R/W 80H
TR_STA
TR_CMD
RINF
XINF
0
ICV
FSYN
0
LD
0
33H
R 00H
DPRIO TDDIS PD LP_A
34H R/W 08H
SQRR1 MSYN MFEN
SQXR1 MFEN
0
0
0
0
SQR11SQR12SQR13SQR14 35H
SQX11SQX12SQX13SQX14 35H
R 40H
W 4FH
R 00H
W 00H
R 00H
W 00H
R 00H
0
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 36H
SQXR2 SQX21SQX22SQX23SQX24SQX31SQX32SQX33SQX34 36H
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 37H
SQXR3 SQX41SQX42SQX43SQX44SQX51SQX52SQX53SQX54 37H
ISTATR
0
1
0
x
1
0
x
1
0
x
1
0
LD
LD
RIC SQC SQW
RIC SQC SQW
38H
MASKTR
39H R/W FFH
TR_
DCH_ MODE MODE MODE 3AH R/W 00H
INH
MODE
2
1
0
reserved
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
3BH
ACFG1
3CH R/W 00H
Data Sheet
160
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
Transceiver, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
3DH R/W 00H
3EH R/W FFH
ACFG2 A7SEL A5SEL FBS A4SEL ACL LED EL1
EL0
AOE
ARX
ATX
OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
3FH
3FH
R
AT7 AT6 AT5 AT4 AT3 AT2 AT1
AT0
W 00H
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
40H R/WFFH
41H R/WFFH
42H R/WFFH
43H R/WFFH
44H R/W 00H
CDA10
CDA11
CDA20
CDA21
Controller Data Access Register (CH10)
Controller Data Access Register (CH11)
Controller Data Access Register (CH20)
Controller Data Access Register (CH21)
CDA_
TSDP10
DPS
DPS
DPS
DPS
DPS
0
0
0
0
0
0
0
0
0
0
TSS
TSS
TSS
TSS
TSS
CDA_
TSDP11
45H R/W 01H
46H R/W 80H
47H R/W 81H
48H R/W 80H
CDA_
TSDP20
CDA_
TSDP21
BCH_
TSDP_
BC1
BCH_
TSDP_
BC2
DPS
0
0
TSS
49H R/W 81H
reserved
4AH
Data Sheet
161
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
reserved
4BH
TR_
TSDP_
BC1
DPS
DPS
0
0
0
0
TSS
TSS
4CH R/W
TR_
4DH R/W
TSDP_
BC2
CDA1_
CR
0
0
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP 4EH R/W 00H
TBM
CDA2_
CR
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP 4FH R/W 00H
TBM
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
50H R/W
TR_CR
EN_ EN_ EN_ EN_ EN_
CS2-0
(CI_CS=0)
D
B2R B1R B2X B1X
TRC_CR
(CI_CS=1)
0
0
0
0
0
0
CS2-0
CS2-0
50H R/W
BCH_
CR
DPS_
D
EN_D EN_ EN_
BC2 BC1
51H R/W 80H
reserved
52H
DCI_CR DPS_ EN_
(CI_CS=0) CI1 CI1 EN_D EN_B2EN_B1
D_
D_
D_
CS2-0
CS2-0
CS2-0
53H R/W
DCIC_CR
(CI_CS=1)
0
0
0
0
0
0
0
0
53H R/W
MON_CR DPS EN_
MON
54H R/W
SDS1_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
55H R/W 00H
Data Sheet
162
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
SDS2_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
56H R/W 00H
IOM_CR SPU DIS_ CI_CS TIC_ EN_ CLKM DIS_ DIS_
57H R/W 08H
AW
DIS BCL
OD
IOM
STI
STOV STOV STOV STOV STI
STI
20
STI
11
STI
10
58H
58H
R 00H
W 00H
21
0
20
0
11
0
10
0
21
ASTI
MSTI
ACK ACK ACK ACK
21
20
11
10
STOV STOV STOV STOV STI
STI
20
STI
11
STI
10
59H R/W FFH
21
0
20
0
11
0
10
0
21
SDS_
CONF
DIOM_DIOM_SDS2_SDS1_ 5AH R/W 00H
INV SDS BCL BCL
MCDA
MOR
MCDA21
MCDA20
MCDA11
MCDA10
5BH
5CH
R FFH
R FFH
MONITOR Receive Data
MONITOR Transmit Data
MOX
5CH W FFH
5DH R 00H
5EH R/W 00H
R 00H
TOUT 5FH W 00H
MOSR
MOCR
MSTA
MCONF
MDR MER MDA MAB
MRE MRC MIE MXC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAC
0
TOUT 5FH
Interrupt, General Configuration Registers
NAME
ISTA
7
6
5
4
3
2
1
0
ADDR R/WRES
ICB
ICB
0
0
1
0
1
ST
ST
CIC AUX TRAN MOS ICD
CIC AUX TRAN MOS ICD
60H
60H
61H
61H
R 00H
W FFH
R 00H
W FFH
MASK
AUXI
EAW WOV TIN2 TIN1 INT1 INT0
EAW WOV TIN2 TIN1 INT1 INT0
AUXM
1
Data Sheet
163
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
MODE1
MODE2
0
0
0
0
0
0
WTC1 WTC2 CFS RSS2 RSS1 62H R/W 00H
0
INT_
POL
0
0
PPSDX 63H R/W 00H
ID
0
0
DESIGN
64H
R 01H
W 00H
SRES
RES_ RES_
0
RES_ RES_ RES_ RES_ RES_ 64H
CI
BCH
MON DCH IOM
CNT
TR RSTO
TIMR2
TMD
0
65H R/W 00H
reserved
66H-
6FH
Data Sheet
164
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
B-channel HDLC Control Registers
Name
ISTAB
7
6
5
4
3
2
1
0
ADDR R/WRES
RME RPF RFO XPR
0
1
XDU
XDU
0
0
1
0
1
0
70H
70H
71H
R 10H
W FFH
R 40H
W 00H
MASKB RME RPF RFO XPR
STARB XDOV XFW
CMDRB RMC RRES
0
0
0
0
0
RACI
XTF
XACI
0
XME XRES 71H
MODEB MDS2 MDS1 MDS0
RAC
0
0
0
0
72H R/WC0H
73H R/WC0H
74H
EXMB
1
1
RFBS SRA XCRC RCRC
ITF
reserved
RAH1
RAH1
RAH2
0
0
MHA
MLA
75H
76H
W 00H
W 00H
R 00H
R 00H
W 00H
W 00H
R 0EH
RAH2
RBCLB RBC7
RBC0 76H
RBC8 77H
77H
RBCHB
RAL1
0
0
0
OV RBC11
RAL1
RAL2
RAL2
78H
RSTAB
TMB
VFR RDO CRC RAB HA1 HA0 C/R
LA
78H
0
0
0
0
0
0
0
TLP
79H R/W 00H
RFIFOB
XFIFOB
B-Channel Receive FIFO
B-Channel Transmit FIFO
reserved
7AH
7AH
R
W
7BH-
7FH
Data Sheet
165
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1
D-channel HDLC Control and C/I Registers
4.1.1
RFIFOD - Receive FIFO D-Channel
7
0
RFIFOD
Receive data
RD (00-1F)
A read access to any address within the range 00h-1Fh gives access to the “current”
FIFO location selected by an internal pointer which is automatically incremented after
each read access. This allows for the use of efficient “move string” type commands by
the microcontroller.
The RFIFOD contains up to 32 bytes of received data.
After an ISTAD.RPF interrupt, a complete data block is available. The block size can be
4, 8, 16 or 32 bytes depending on the EXMD2.RFBS setting.
After an ISTAD.RME interrupt, the number of received bytes can be obtained by reading
the RBCLD register.
4.1.2
XFIFOD - Transmit FIFO D-Channel
7
0
XFIFOD
Transmit data
WR (00-1F)
A write access to any address within the range 00-1FH gives access to the “current” FIFO
location selected by an internal pointer which is automatically incremented after each
write access. This allows the use of efficient “move string” type commands by the
microcontroller.
Depending on EXMD2.XFBS up to 16 or 32 bytes of transmit data can be written to the
XFIFOD following an ISTAD.XPR interrupt.
Data Sheet
166
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.3
ISTAD - Interrupt Status Register D-Channel
Value after reset: 10H
7
0
ISTAD
RME RPF RFO XPR XMR XDU
0
0
RD (20)
RME ... Receive Message End
One complete frame of length less than or equal to the defined block size
(EXMD1.RFBS) or the last part of a frame of length greater than the defined block size
has been received. The contents are available in the RFIFOD. The message length and
additional information may be obtained from RBCHD and RBCLD and the RSTAD
register.
RPF ... Receive Pool Full
A data block of a frame longer than the defined block size (EXMD1.RFBS) has been
received and is available in the RFIFOD. The frame is not yet complete.
RFO ... Receive Frame Overflow
The received data of a frame could not be stored, because the RFIFOD is occupied. The
whole message is lost.
This interrupt can be used for statistical purposes and indicates that the microcontroller
does not respond quickly enough to an RPF or RME interrupt (ISTAD).
XPR ... Transmit Pool Ready
A data block of up to the defined block size 16 or 32 (EXMD1.XFBS) can be written to
the XFIFOD.
An XPR interrupt will be generated in the following cases:
• after an XTF or XME command as soon as the 16 or 32 bytes in the XFIFO are
available and the frame is not yet complete
• after an XTF together with an XME command is issued, when the whole frame has
been transmitted
• after a reset of the transmitter (XRES)
• after a device reset
XMR ... Transmit Message Repeat
The transmission of the last frame has to be repeated because a collision on the S bus
has been detected after the 16th/32nd data byte of a transmit frame.
Data Sheet
167
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
If an XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFOD holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAD register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
4.1.4
MASKD - Mask Register D-Channel
Value after reset: FFH
7
0
MASKD
RME RPF RFO XPR XMR XDU
1
1
WR (20)
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to ’1’. Masked interrupt status bits are not indicated when
ISTAD is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
Data Sheet
168
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.5
STARD - Status Register D-Channel
Value after reset: 40H
7
0
STARD
XDOV XFW
0
0
RACI
0
XACI
0
RD (21)
XDOV ... Transmit Data Overflow
More than 16 or 32 bytes (according to selected block size) have been written to the
XFIFOD, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOD. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI ... Receiver Active Indication
The D-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
XACI ... Transmitter Active Indication
The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The
XACI-bit is active when an XTF-command is issued and the frame has not been
completely transmitted
Data Sheet
169
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.6
CMDRD - Command Register D-channel
Value after reset: 00H
7
0
CMDRD
RMC RRES
0
STI
XTF
0
XME XRES
WR (21)
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOD may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data.
STI ... Start Timer 1
The ISAC-SX timer 1 is started when STI is set to one. The timer is stopped by writing
to the TIMR1 register.
Note: Timer 2 is controlled by the TIMR2 register only.
XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMD1.XFBS) to the XFIFOD, the
microcontroller initiates the transmission of a transparent frame by setting this bit to ’1’.
The opening flag is automatically added to the message by the ISAC-SX (except in the
extended transparent mode where no flags are used).
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOD completes the corresponding frame. The ISAC-SX terminates the transmission
by appending the CRC (if EXMD1.XCRC=0) and the closing flag sequence to the data
(except in the extended transparent mode where no such framing is used).
XRES ... Transmitter Reset
The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOD and the
appropriate Transmit Command (XTF) has to be written to the CMDRD register
again to continue transmission, when the current frame is not yet complete (see
Data Sheet
170
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
also XPR in ISTAD).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
4.1.7
MODED - Mode Register
Value after reset: C0H
7
0
MODED MDS2 MDS1 MDS0
0
RAC DIM2 DIM1 DIM0 RD/WR (22)
MDS2-0 ... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0 Mode
Number of Address Comparison
Address
Bytes
Remark
1.Byte
2.Byte
0
0
0
0
0
1
0Reserved
1Reserved
0Non-Auto
mode
1
2
TEI1,TEI2
–
One-byteaddress
compare.
0
1
1
0
1Non-Auto
mode
SAP1,SAP2,SAPGTEI1,TEI2,TEIGTwo-byteaddress
compare.
0Extended
transparent
mode
1
1
0Transparent–
–
–
No address
mode 0
compare. All
frames accepted.
1
1
1
0
1Transparent> 1
mode 1
SAP1,SAP2,SAPG–
High-byte
address compare.
1Transparent> 1
mode 2
–
TEI1,TEI2,TEIGLow-byteaddress
compare.
Note: SAP1, SAP2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FEH.
TEI1, TEI2: two programmable address values for the second (or the only, in the
Data Sheet
171
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
case of a one-byte address) received address byte; TEIG = fixed value FFH
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA.
RAC ... Receiver Active
The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
DIM2 DIM1 DIM0 Characteristics
0
0
0
0
1
0
1
Transparent D-channel, the collission detection is disabled
Stop/go bit evaluated for D-channel access handling
Last octet of IOM channel 2 used for TIC bus access
TIC bus access is disabled
0
1
x
x
Reserved
4.1.8
EXMD1- Extended Mode Register D-channel 1
Value after reset: 00H
7
0
EXMD1
XFBS
RFBS
SRA XCRC RCRC
0
ITF
RD/WR (23)
XFBS … Transmit FIFO Block Size
0 … Block size for the transmit FIFO data is 32 byte
1 … Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a receiver command (CMDRD.XME,
CMDRD.XRES, CMDRD.XTF) has been written.
Data Sheet
172
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
RFBS … Receive FIFO Block Size
RFBS
Block Size Receive
FIFO
Bit 6
Bit5
0
0
1
1
0
1
0
1
32 byte
16 byte
8 byte
4 byte
Note: A change of RFBS will take effect after a transmitter command (CMDR.RMC,
CMDR.RRES,) has been written
SRA … Store Receive Address
0 … Receive Address isn’t stored in the RFIFOD
1 … Receive Address is stored in the RFIFOD
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC isn’t transmitted
RCRC… Receive CRC
0 … CRC isn’t stored in the RFIFOD
1 … CRC is stored in the RFIFOD
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the S/T-bus cannot be accessed
Data Sheet
173
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.9
TIMR1 - Timer 1 Register
Value after reset: 00H
7
5
4
0
TIMR1
CNT
VALUE
RD/WR (24)
CNT ... Timer Counter
CNT together with VALUE determines the time period T after which a AUXI.TIN1
interrupt will be generated:
CNT=0...6:T = CNT x 2.048 sec + T1
with T1 = ( VALUE+1 ) x 0.064 sec
CNT=7:T = T1 = ( VALUE+1 ) x 0.064 sec (generated periodically)
The timer can be started by setting the STI-bit in CMDRD and will be stopped when a
TIN1 interrupt is generated or the TIMR1 register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of
T1 (i.e. T = T1).
VALUE ... Timer Value
Determines the value of the timer value T1 = ( VALUE + 1 ) x 0.064 sec.
4.1.10
SAP1 - SAPI1 Register
Value after reset: FCH
7
0
SAP1
SAPI1
0
MHA
WR (25)
SAPI1 ... SAPI1 value
Value of the first programmable Service Access Point Identifier (SAPI) according to the
ISDN LAPD protocol.
MHA... Mask High Address
0 … The SAPI address of an incomming frame is compared with SAP1, SAP2, SAPG.
1 … The SAPI address of an incomming frame is compared with SAP1 and SAPG.
SAP1 can be masked with SAP2 thereby bit positions of SAP1 are not compared
if they are set to ’1’ in SAP2.
Data Sheet
174
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.11
SAP2 - SAPI2 Register
Value after reset: FCH
7
0
SAP2
SAPI2
0
MLA
WR (26)
SAPI2 ... SAPI2 value
Value of the second programmable Service Access Point Identifier (SAPI) according to
the ISDN LAPD-protocol.
MLA... Mask Low Address
0 …The TEI address of an incomming frame is compared with TEI1, TEI2 and TEIG.
1 …The TEI address of an incomming frame is compared with TEI1 and TEIG.
TEI1 can be masked with TEI2 thereby bit positions of TEI1 are not compared
if they are set to ’1’ in TEI2.
4.1.12
RBCLD - Receive Frame Byte Count Low D-Channel
Value after reset: 00H
7
0
RBCLD
RBC7
RBC0
RD (26)
RBC7-0 ... Receive Byte Count
Eight least significant bits of the total number of bytes in a received message (see
RBCHD register).
Data Sheet
175
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.13
RBCHD - Receive Frame Byte Count High D-Channel
Value after reset: 00H.
7
0
RBCHD
0
0
0
OV RBC11
RBC8
RD (27)
OV ... Overflow
A ’1’ in this bit position indicates a message longer than (212 - 1) = 4095 bytes .
RBC8-11 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message (see
RBCLD register).
Note: Normally RBCHD and RBCLD should be read by the microcontroller after an
RME-interrupt in order to determine the number of bytes to be read from the
RFIFOD, and the total message length. The contents of the registers are valid only
after an RME or RPF interrupt, and remain so until the frame is acknowledged via
the RMC bit or RRES.
4.1.14
TEI1 - TEI1 Register 1
Value after reset: FFH
7
0
TEI1
TEI1
EA1
WR (27)
TEI1 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI1 is used by the ISAC-SX for address recognition. In the case of
a two-byte address field, it contains the value of the first programmable Terminal
Endpoint Identifier according to the ISDN LAPD-protocol.
In non-automodes with one-byte address field, TEI1 is a command address, according
to X.25 LAPB.
EA1 ... Address field Extension bit
This bit is set to ’1’ according to HDLC/LAPD.
Data Sheet
176
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.15
TEI2 - TEI2 Register
Value after reset: FFH
7
0
TEI2
TEI2
EA2
WR (28)
TEI2 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI2 is used by the ISAC-SX for address recognition. In the case of
a two-byte address field, it contains the value of the second programmable Terminal
Endpoint Identifier according of the ISDN LAPD-protocol.
In non-auto-modes with one-byte address field, TEI2 is a response address, according
to X.25 LAPD.
EA2 ... Address field Extension bit
This bit is to be set to ’1’ according to HDLC/LAPD.
4.1.16
RSTAD - Receive Status Register D-Channel
Value after reset: 0FH
7
0
RSTAD
VFR RDO CRC RAB
SA1
SA0
C/R
TA
RD (28)
For general information please refer to Figure 3.9.
VFR... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFOD. As opposed to the ISTAD.RFO an RDO indicates that the beginning of a frame
has been received but not all bytes could be stored as the RFIFOD was temporarily full.
CRC ... CRC Check
The CRC is correct (1) or incorrect (0).
RAB ... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
SA1-0 ... SAPI Address Identification
TA ... TEI Address Identification
SA1-0 are significant in non-automode with a two-byte address field, as well as in
transparent mode 3. TA is significant in all modes except in transparent modes 0 and 1.
Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value
FCH/FEH), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG
of value FFH), are available for address comparison.
The result of the address comparison is given by SA1-0 and TA, as follows:
Address Match with
SA1
SA0
TA
1st Byte
2nd Byte
Number of
AddressBytesx
x
x
x
0
1
TEI2
TEI1
-
-
= 1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
x
SAP2
SAP2
SAPG
SAPG
SAP1
SAP1
TEIG
TEI2
TEIG
TEI1 or TEI2
TEIG
Number of
address
Bytes=2
0
0
1
1
1
TEI1
reserved
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTAD corresponds to the last received HDLC frame; it is
duplicated into RFIFOD for every frame (last byte of frame)
Data Sheet
178
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.1.17
TMD -Test Mode Register D-Channel
Value after reset: 00H
7
0
TMD
0
0
0
0
0
0
0
TLP
RD/WR (29)
For general information please refer to Chapter 3.3.11.
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
The setting of TLP is only valid if the IOM interface is active.
4.1.18
CIR0 - Command/Indication Receive 0
Value after reset: F3H
7
0
CIR0
CODR0
CIC0 CIC1 S/G
BAS
RD (2E)
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
S/G ... Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel on the S/T interface.
1: Stop
0: Go
BAS ... Bus Access Status
Indicates the state of the TIC-bus:
0: the ISAC-SX itself occupies the D- and C/I-channel
1: another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at
the first and second read of that register, respectively.
4.1.19
CIX0 - Command/Indication Transmit 0
Value after reset: FEH
7
0
CIX0
CODX0
TBA2 TBA1 TBA0 BAC
WR (2E)
CODX0 ... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel 0.
The code is only transmitted if the TIC bus is occupied. If TIC bus is enabled but
occupied by another device, only “1s” are transmitted.
TBA2-0 ... TIC Bus Address
Defines the individual address for the ISAC-SX on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it
should always be given the address value ’7’.
BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODED.DIM2-0).
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
If this bit is set, the ISAC-SX will try to access the TIC-bus to occupy the C/I-channel
even if no D-channel frame has to be transmitted. It should be reset when the access
has been completed to grant a similar access to other devices transmitting in that IOM-
channel.
Note: Access is always granted by default to the ISAC-SX with TIC-Bus Address (TBA2-
0, STCR register) ’7’, which has the lowest priority in a bus configuration.
4.1.20
CIR1 - Command/Indication Receive 1
Value after reset: FEH
7
0
CIR1
CODR1
CICW CI1E
RD (2F)
CODR1 ... C/I-Code 1 Receive
CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable
These two bits contain the read back values from CIX1 register (see below).
4.1.21
CIX1 - Command/Indication Transmit 1
Value after reset: FEH
7
0
CIX1
CODX1
CICW CI1E
WR (2F)
CODX1 ... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1.
CICW... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width.
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher
two bits are ignored for interrupt generation. However in write direction the full CODX1
code is transmitted, i.e. the host must write the higher two bits to “1”.
CI1E ... C/I-Channel 1 Interrupt Enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
Data Sheet
181
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2
Transceiver Registers
4.2.1
TR_CONF0 - Transceiver Configuration Register 0
Value after reset: 01H
7
0
TR_
CONF0
DIS_ BUS EN_
TR ICV
0
L1SW
0
EXLP LDD RD/WR (30)
DIS_TR ... Disable Transceiver
Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver
again, a transceiver reset must be issed (SRES.RES_TR = 1). The transceiver must not
be reenabled by setting DIS_TR from “1” to “0”.
For general information please refer to Chapter 3.3.10.
BUS ... Point-to-Point / Bus Selection (NT, LT-S and Int. NT mode only)
0: Adaptive Timing (Point-t-Point, extended passive bus).
1: Fixed Timing (Short passive bus).
EN_ICV ... Enable Illegal Code Violation
0:normal operation
1:ICV enabled. The receipt of at least one illegal code violation within one multi-frame is
indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
L1SW ... Enable Layer 1 State Machine in Software
0:Layer 1 state machine of the ISAC-SX is used
1:Layer 1 state machine is disabled. The functionality can be realized in software. The
commands can be written to register TR_CMD and the status can be read from TR_STA.
For general information please refer to Chapter 3.5.
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the
TR_CMD register the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Note: The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
Data Sheet
182
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
For general information please refer to Chapter 3.3.11.
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in power down
state
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
set this bit to ’0’ for an activation of the S/T interface.
For general information please refer to Chapter 3.3.9 and Chapter 3.7.6.
4.2.2
TR_CONF1 - Transceiver Configuration Register 1
Value after reset: 0xH
7
0
TR_
CONF1
0
RPLL_ EN_
ADJ SFSC
0
0
x
x
x
RD/WR (31)
RPLL_ADJ ... Receive PLL Adjustment
0: DPLL tracking step is 0.5 XTAL period per S-frame
1: DPLL tracking step is 1 XTAL period per S-frame
EN_SFSC ... Enable Short FSC
0: No short FSC is generated
1: A short FSC is generated once per multi-frame (every 40th IOM frame)
x ... Undefined
The value of these bits depends on the selected mode. It is important to note that these
bits must not be overwritten to a different value when accessing this register.
Data Sheet
183
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.3
TR_CONF2 - Transmitter Configuration Register 2
Value after reset: 80H
7
0
TR_
CONF2
DIS_ PDS
TX
0
RLP
0
0
SGP SGD RD/WR (32)
DIS_TX ... Disable Line Driver
0: Transmitter is enabled
1: Transmitter is disabled
For general information please refer to Chapter 3.3.10.
PDS ... Phase Deviation Select
Defines the phase deviation of the S-transmitter.
0: The phase deviation is 2 S-bits minus 7 oscillator periods plus analog delay plus delay
of the external circuitry.
1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus delay
of the external circuitry.
For general information please refer to Chapter 3.3.8.
RLP ... Remote Line Loop
0: Remote Loop open
1: Remote Loop closed
For general information please refer to Chapter 3.3.11.
SGP ... Stop/Go Bit Polarity
Defines the polarity of the S/G bit output on pin SGO.
0: low active (SGO=0 means “go”; SGO=1 means “stop”)
1: high active (SGO=1 means “go”; SGO=0 means “stop”)
SGD ... Stop/Go Bit Duration
Defines the duration of the S/G bit output on pin SGO.
0: active during the D-channel timeslot
1: active during the whole corresponding IOM frame (starts and ends with the beginning
of the D-channel timeslot)
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
Note: Outside the active window of SGO (defined in SGD) the level on pin SGO remains
in the “stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if
SGP=0) or SGO=0 (if SGP=1) outside the active window.
4.2.4
TR_STA - Transceiver Status Register
Value after reset: 00H
7
0
TR_
STA
RINF
SLIP
ICV
0
FSYN
0
LD
RD (33)
Important: This register is used only if the Layer 1 state machine of the ISAC-SX is
disabled (TR_CONF0.L1SW = 1) and implemented in software! With the IPAC layer 1
state machine enabled, the signals from this register are automatically evaluated.
For general information please refer to Chapter 3.5.
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 1 - 4
10: Received INFO 1 (NT mode) or INFO 2 (TE mode)
11: Received INFO 3 (NT mode) or INFO 4 (TE mode)
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: Illegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
185
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.5
TR_CMD - Transceiver Command Register
Value after reset: 08H
7
0
TR_
XINF
DPRIO TDDIS PD
LP_A
0
RD/WR (34)
CMD
Important: This register is only writable if the Layer 1 state machine of the ISAC-SX is
disabled (TR_CONF0.L1SW = 1)! With the ISAC-SX layer 1 state machine enabled, the
signals from this register are automatically generated, but nevertheless this register can
always be read. DPRIO can also be written in Intelligent NT mode.
XINF ... Transmit INFO
000: Transmit INFO 0
001: reserved
010: Transmit INFO 1 (TE mode) or INFO 2 (NT mode)
011: Transmit INFO 3 (TE mode) or INFO 4 (NT mode)
100: Send continous pulses at 192 kbit/s alternating or 96 kHz rectangular, respectively
(SCP)
101: Send single pulses at 4 kbit/s with alternating polarity corresponding to 2 kHz
fundamental mode (SSP)
11x: reserved
DPRIO ... D-Channel Priority (always writable in Int. NT mode)
0: Priority Class 1for D channel access on IOM (Int. NT) or on S interface (TE/LT-T)
1: Priority Class 2 for D channel access on IOM (Int. NT) or on S interface (TE/LT-T)
TDDIS ... Transmit Data Disabled (TE mode)
0: The B and D channel data are transparently transmitted on the S/T interface if INFO 3
is being transmitted
1: The B and D channel data are set to logical ’1’ on the S/T interface if INFO 3 is being
transmitted
PD ... Power Down
0: The transceiver is set to operational mode
1: The transceiver is set to power down mode
For general information please refer to Chapter 3.5.1.2.
Data Sheet
186
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
LP_A ... Loop Analog
The setting of this bit corresponds to the C/I command ARL.
0: Analog loop is open
1: Analog loop is closed internally or externally according to the EXLP bit in the
TR_CONF0 register
For general information please refer to Chapter 3.3.11.
4.2.6
SQRR1 - S/Q-Channel Receive Register 1
Value after reset: 40H
7
0
SQRR
MSYN MFEN
0
0
SQR1 SQR2 SQR3 SQR4
RD (35)
For general information please refer to Chapter 3.3.2.
MSYN ... Multi-frame Synchronization State
0: The S/T receiver has not synchronized to the received F and M bits
A
1: The S/T receiver has synchronized to the received F and M bits
A
MFEN ... Multiframe Enable
Read-back of the MFEN bit of the SQXR register
SQR11-14 ... Received S Bits
Received S bits in frames 1, 6, 11 and 16 (TE mode)
received Q bits in frames 1, 6, 11 and 16 (NT mode).
Data Sheet
187
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.7
SQXR1- S/Q-Channel TX Register 1
Value after reset: 4FH
7
0
SQXR1
0
MFEN
0
0
SQX1 SQX2 SQX3 SQX4
WR (35)
MFEN ... Multiframe Enable
Used to enable or disable the multiframe structure (see Chapter 3.3.2)
0: S/T multiframe is disabled
1: S/T multiframe is enabled
Readback value in SQRR1.
SQX1-4 ... Transmitted S/Q Bits
Transmitted Q bits (FA bit position) in frames 1, 6, 11 and 16 (TE mode),
transmitted S bits (FA bit position) in frames 1, 6, 11 and 16 (NT mode).
4.2.8
SQRR2 - S/Q-Channel Receive Register 2
Value after reset: 00H
7
0
SQRR2 SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34
RD (36)
SQR21-24, SQR31-34... Received S Bits (TE mode only)
Received S bits in frames 2, 7, 12 and 17 (SQR21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQR31-34, subchannel 3).
Data Sheet
188
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.9
SQXR2 - S/Q-Channel TX Register 2
Value after reset: 00H
7
0
SQXR2 SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34
WR (36)
SQX21-24, SQX31-34... Transmitted S Bits (NT mode only)
Transmitted S bits in frames 2, 7, 12 and 17 (SQX21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQX31-34, subchannel 3).
4.2.10
SQRR3 - S/Q-Channel Receive Register 3
Value after reset: 00H
7
0
SQRR3 SQR41 SQR42 SQR43 SQR44 SQR51 SQR52 SQR53 SQR54
RD (37)
SQR41-44, SQR51-54... Received S Bits (TE mode only)
Received S bits in frames 4, 9, 14 and 19 (SQR41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQR51-54, subchannel 5).
4.2.11
SQXR3 - S/Q-Channel TX Register 3
Value after reset: 00H
7
0
SQXR3 SQX41 SQX42 SQX43 SQX44 SQX51 SQX52 SQX53 SQX54
WR (37)
SQX41-44, SQX51-54... Transmitted S Bits (NT mode only)
Transmitted S bits in frames 4, 9, 14 and 19 (SQX41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQX51-54, subchannel 5).
Data Sheet
189
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.12
ISTATR - Interrupt Status Register Transceiver
Value after reset: 00H
7
0
ISTATR
x
x
x
x
LD
RIC
SQC SQW
RD (38)
For all interrupts in the ISTATR register the following logical states are defined:
0: Interrupt is not acitvated
1: Interrupt is acitvated
x ... Reserved
Bits set to “1” in this bit position must be ignored.
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the register TR_STA.
SQC ... S/Q-Channel Change
A change in the received S-channel (TE) or Q-channel (NT) has been detected. The new
code can be read from the SQRxx bits of registers SQRR1-3 within the next multiframe
(5 ms). This bit is reset by a read access to the corresponding SQRRx register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the next multiframes (5 ms). This bit is reset by writing register SQXRx.
Data Sheet
190
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.2.13
MASKTR - Mask Transceiver Interrupt
Value after reset: FFH
7
0
MASKTR
1
1
1
1
LD
RIC
SQC SQW RD/WR (39)
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.14
TR_MODE - Transceiver Mode Register 1
Value after reset: 000000xxB
7
0
TR_
0
0
0
0
DCH_ MODE MODE MODE RD/WR (3A)
MODE
INH
2
1
0
For general information please refer also to Chapter 3.7.5.4.
DCH_INH ... D-Channel Inhibit
Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the D-
channel on S by inverting the E-bits.
MODE2-0 ... Transceiver Mode
000: TE mode
001: LT-T mode
010: NT mode (without D-channel handler)
011: LT-S mode (without D-channel handler)
110: Intelligent NT mode (with NT state machine and with D-channel handler)
111: Intelligent NT mode (with LT-S state machine and with D-channel handler)
100: reserved
101: reserved
Note: The three modes TE, LT-T and LT-S can be selected by pin strapping (reset
values for bits TR_MODE.MODE0,1 loaded from pins MODE0,1), all other modes
are programmable only.
Data Sheet
191
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.3
Auxiliary Interface Registers
4.3.1
ACFG1 - Auxiliary Configuration Register 1
Value after reset: 00H
7
0
ACFG1
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 RD/WR (3C)
For general information please refer to Chapter 3.8.1.
OD7-0 ... Output Driver Select for AUX7 - AUX0
0: output is open drain
1: output is push/pull
Note: The ODx configuration is only valid if the corresponding output is enabled in the
AOE register.
AUX0-2 are only available in TE and Int. NT mode and not in all other modes (used
as channel select).
AUX7 and AUX6 provide internal pull up resistors which are only available as
inputs and in output/open drain mode, but disabled in output / push/pull mode.
4.3.2
ACFG2 - Auxiliary Configuration Register 2
Value after reset: 00H
7
0
ACFG2 A7SEL A5SEL FBS A4SEL ACL
LED
EL1
EL0 RD/WR (3D)
A7SEL ... AUX7 Function Select
0: pin AUX7 provides normal I/O functionality.
1: pin AUX7 provides the S/G bit output (SGO) from the IOM DD-line. Bit AOE.OE7 is
don’t care, the output characteristic (push pull or open drain) can be selected via
ACFG1.OD7.
Data Sheet
192
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
A5SEL ... AUX5 Function Select
0: pin AUX5 provides normal I/O functionality.
1: pin AUX5 provides an FSC or BCL signal output (FBOUT) which is selected in
ACFG2.FBS. Bit AOE.OE5 is don’t care, the output characteristic (push pull or open
drain) can be selected via ACFG1.OD5.
For general information please refer to Chapter 3.4.
FBS ... FSC/BCL Output Select
0: FSC is output on pin AUX5.
1: BCL (single bit clock) is output on pin AUX5.
Note: This selection has only effect on pin AUX5 if FBOUT is enabled (A5SEL=1).
In LT-T mode pin SCLK provides an 1.536 MHz output clock which can be used
as DCL input. This is necessary for BCL generation.
For general information please refer to Chapter 3.4.
A4SEL ... AUX4 Function Select
0: pin AUX4 provides normal I/O functionality.
1: pin AUX4 supports multiframe synchronization and is used as M-bit input in Int. NT/
NT/LT-S modes or as M-bit output in TE/LT-T modes (input/output is automatically
selected with the mode). Bit AOE.OE4 is don’t care, the output characteristic (push pull
or open drain) can be selected via ACFG1.OD4.
For general information please refer to Chapter 3.3.3.
ACL ... ACL Function Select
0: Pin ACL automatically indicates the S-bus activation status by a LOW level.
1: The output state of ACL is programmable by the host in bit LED.
Note: An LED with preresistance may directly be connected to ACL.
LED ... LED Control
If enabled (ACL=1) the LED with preresistance connected between VDD and ACL is
switched ...
0: Off (high level on pin ACL)
1: On (low level on pin ACL)
EL0, 1 ... Edge/Level Triggered Interrupt Input for INT0, INT1
0: A negative level ...
1: A negative edge ... on INT0/1 (pins AUX6/7) generates an interrupt to the ISAC-SX.
Data Sheet
193
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset.
This configuration is only valid if the corresponding output enable bit in AOE is
disabled.
For general information please refer to Chapter 3.8.1.
4.3.3
AOE - Auxiliary Output Enable Register
Value after reset: FFH
7
0
AOE
OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 RD/WR (3E)
For general information please refer to Chapter 3.8.1.
OE7-0 ... Output Enable for AUX7 - AUX0
0: Pin AUX7-0 is configured as output. The value of the corresponding bit in the ATX
register is driven on AUX7-0.
1: Pin AUX7-0 is configured as input. The value of the corresponding bit can be read from
the ARX register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
If pins AUX7, AUX6 are to be used as interrupt input, OE7, OE6 must be set to 1.
If pins AUX7, AUX5 and AUX4 are not used as I/O pins (see ACFG2), the
corresponding OEx bit cannot be set, but delivers the mode dependent direction
(input/output) in that function upon a read access. If the secondary function is
disabled, the direction of the pin as I/O pin is valid again.
Data Sheet
194
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.3.4
ARX - Auxiliary Interface Receive Register
Value after reset: (not defined)
7
0
ARX
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
RD (3F)
AR7-0 ... Auxiliary Receive
The value of AR7-0 always reflects the level at pin AUX7-0 at the time when ARX is read
by the host even if a pin is configured as output. If the mask bit for AUX7, 6 is set in the
MASKA register, no interrupt is generated to the ISAC-SX, however, the current state at
pin AUX7,6 can be read from AR7,6
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
4.3.5
ATX - Auxiliary Interface Transmit Register
Value after reset: 00H
7
0
ATX
AT7
AT6
AT5
AT4
AT3
AT2
AT1
AT0
WR (3F)
AT7-0 ... Auxiliary Transmit
A ’0’ or ’1’ in AT7-0 will drive a low or a high level at pin AUX7-0 if the corresponding
output is enabled in the AOE register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
Data Sheet
195
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4
IOM-2 and MONITOR Handler
CDAxy - Controller Data Access Register xy
4.4.1
7
0
CDAxy
Controller Data Access Register
RD/WR
(40-43)
Data registers CDAxy which can be accessed from the controller.
Register
CDA10
CDA11
CDA20
CDA21
Register Address
Value after Reset
40H
41H
42H
43H
FFH
FFH
FFH
FFH
Data Sheet
196
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
7
0
XXX_
TSDPxy
DPS
0
0
TSS
RD/WR
(44-4D)
Register
Register
Address
Value after Reset
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
44H
45H
46H
47H
00H ( = output on B1-DD)
01H ( = output on B2-DD)
80H ( = output on B1-DU)
81H ( = output on B2-DU)
80H ( = output on B1-DU)
81H ( = output on B2-DU)
BCH_TSDP_BC1 48H
BCH_TSDP_BC2 49H
TR_TSDP_BC1
TR_TSDP_BC2
4CH
4DH
00H ( = transceiver output on B1-DD), see note
01H ( = transceiver output on B2-DD), see note
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA),
B-channel controller (BCH) and Transceiver (TR).
The B-channel controller (BCH) can access any combination of two 8-bit timeslots and
one 2-bit timeslot (e.g. 16-bit access to B1+B2 or 18-bit IDSL in 2B+D). The position of
the two 8-bit timeslots is programmed in BCH_TSDP_BC1 and BCH_TSDP_BC2. The
position of the 2-bit timeslot is programmed in BCH_CR. In the same registers each of
the three timeslots is enabled/disabled.
The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1
and TR_TSDP_BC2.
Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection
(MODE0/1) and channel selection (CH0-2).
Data Sheet
197
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
DPS ... Data Port Selection
0:The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1:The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in Chapter 3.7.1.1.
TSS ... Timeslot Selection
Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels.
Note: The TSS reset values for TR_TSDP_BC1/2 are determined by the channel select
pins CH2-0 which are mapped to the corresponding bits TSS4-2.
4.4.3
CDAx_CR - Control Register Controller Data Access CH1x
7
0
CDAx_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1 EN_O0 SWAP
TBM
RD/WR
(4E-4F)
Register
Register Address
Value after Reset
CDA1_CR
CDA2_CR
4EH
4FH
00H
00H
For general information please refer to Chapter 3.7.1.1.
EN_TBM ... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
must be set to 08H for monitoring from DU or 88H for monitoring from DD, respectively
(This selection is only valid if IOM_CR.TIC_DIS = 0).
Data Sheet
198
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP ... Swap Inputs
0:The time slot and data port for the input of the CDAxy register is defined by its own
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
1:The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
4.4.4
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0)
Value after reset: F8H
7
0
TR_CR
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
RD/WR (50)
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
EN_D ... Enable Transceiver D-Channel Data
EN_B2R ... Enable Transceiver B2 Receive Data
EN_B1R ... Enable Transceiver B1 Receive Data
EN_B2X ... Enable Transceiver B2 Transmit Data
EN_B1X ... Enable Transceiver B1 Transmit Data
This register is used to individually enable/disable the D-channel (both RX and TX
direction)and the receive/transmit paths for the B-channel of the S-transceiver.
0: The corresponding data path to the transceiver is disabled.
1: The corresponding data path to the transceiver is enabled.
Data Sheet
199
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
Note: Receive data corresponds to downstream direction, and transmit data
corresponds to upstream direction.
CS2-0 ... Channel Select for Transceiver D-channel
This register is used to select one of eight IOM channels to which the transceiver D-
channel data is related to.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0. It should be noted that writing TR_CR.CS2-0 will also write to
TRC_CR.CS2-0 and therefore modify the channel selection for the transceiver
C/I0 data.
4.4.4.1 TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1)
Value after reset: 00H
7
0
TRC_CR
0
0
0
0
0
CS2-0
RD/WR (50)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for the Transceiver C/I0 Channel
This register is used to select one of eight IOM channels to which the transceiver C/I0
channel data is related to. The reset value is determined by the MODE2-bit and the
channel select pins CH2-0 which are mapped to CS2-0.
Data Sheet
200
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.5
BCH_CR - Control Register B-Channel Controller Data
Value after reset:08H
7
0
BCH_CR DPS_D
0
EN_D EN_
BC2
EN_
BC1
CS2-0
RD/WR (51)
The registers BCH_TSDP_BC1/2 (see above) select the IOM-2 timeslots for B-channel
controller access. For the B-channel controller two 8-bit timeslots can be selected
(position and direction).
This register BCH_CR is used to select the position (CS2-0) and direction (DPS_D) of
the 2-bit timeslot for the B-channel controller, and each of the three selected timeslots
(2 x 8-bit and 2-bit) is individually enabled/disabled (EN_BC1, EN_BC2, EN_D).
DPS_D ... Data Port Selection for D-Channel Timeslot access
0: The B-channel controller data is output on DD.
The B-channel controller data is input from DU.
1: The B-channel controller data is output on DU.
The B-channel controller data is input from DD.
EN_D ... Enable D-Channel Timeslot (2-bit) for B-Channel controller access
EN_BC2 ... Enable B2-Channel Timeslot (8-bit) for B-Channel controller access
EN_BC1 ... Enable B1-Channel Timeslot (8-bit) for B-Channel controller access
These bits individually enable/disable the B-channel access to the 2-bit and the two 8-
bit timeslots.
0: B-channel B/A does not access timeslot data B1, B2 or D, respectively.
1: B-channel B/A does access timeslot data B1, B2 or D, respectively.
Note: The terms B1/B2 should not imply that the 8-bit timeslots must be located in the
first/second IOM-2 timeslots, it’s simply a placeholder for the 8-bit timeslot position
selected in the registers BCH_TSDP_BC1/2.
CS2-0 ... Channel Select for D-Channel Timeslot access
This register is used to select one of eight IOM channels. If enabled (EN_D=1), the B-
channel controller is connected to the 2-bit D-channel timeslot of that IOM channel.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0.
Data Sheet
201
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.6
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0)
Value after reset: A0H
7
0
DCI_CR DPS_ EN_
D_
D_
D_
CS2-0
RD/WR (53)
CI1
CI1 EN_D EN_B2 EN_B1
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
DPS_CI1 ... Data Port Selection CI1 Handler Data
0: The CI1 handler data is output on DD and input from DU
1: The CI1 handler data is output on DU and input from DD
EN_CI1 ... Enable CI1 Handler Data
0: CI1 handler data access is disabled
1: CI1 handler data access is enabled
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM
channel 1.
D_EN_D ... Enable D-timeslot for D-channel controller
D_EN_B2 ... Enable B2-timeslot for D-channel controller
D_EN_B1 ... Enable B1-timeslot for D-channel controller
These bits are used to select the timeslot length for the D-channel HDLC controller
access as it is capable to access not only the D-channel timeslot. The host can
individually enable two 8-bit timeslots B1- and B2-channel (D_EN_B1, D_EN_B2) and
one 2-bit timeslot D-channel (D_EN_D) on IOM-2. The position is selected via CS2-0.
0: D-channel controller does not access timeslot data B1, B2 or D, respectively
1: D-channel controller does access timeslot data B1, B2 or D, respectively
CS2-0 ... Channel Select for D-channel controller
This register is used to select one of eight IOM channels. If enabled, the D-channel data
is connected to the corresponding timeslots of that IOM channel.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0. It should be noted that writing DCI_CR.CS2-0 will also write to
DCIC_CR.CS2-0 and therefore modify the channel selection for the data of the
C/I0 handler.
Data Sheet
202
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.6.1 DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1)
Value after reset: 00H
7
0
DCIC_CR
0
0
0
0
0
CS2-0
RD/WR (13)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for C/I0 Handler
This register is used to select one of eight IOM channels. If enabled, the data of the
C/I0 handler is connected to the corresponding C/I0 timeslot of that IOM channel.
The reset value is determined by the channel select pins CH2-0 which are mapped to
CS2-0.
Data Sheet
203
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.7
MON_CR - Control Register Monitor Data
Value after reset: 40H
7
0
MON_CR DPS EN_
MON
0
0
0
CS2-0
RD/WR (54)
For general information please refer to Chapter 3.7.3.
DPS ... Data Port Selection
0: The Monitor data is output on DD and input from DU
1: The Monitor data is output on DU and input from DD
EN_MON ... Enable Output
0: The Monitor data input and output is disabled
1: The Monitor data input and output is enabled
CS2-0 ... MONITOR Channel Selection
000: The MONITOR data is input/output on MON0 (3rd timeslot on IOM-2)
001: The MONITOR data is input/output on MON1 (7th timeslot on IOM-2)
010: The MONITOR data is input/output on MON2 (11th timeslot on IOM-2)
:
111: The MONITOR data is input/output on MON7 (31st timeslot on IOM-2)
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0.
Data Sheet
204
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.8
SDSx_CR - Control Register Serial Data Strobe x
Value after reset: 00H
7
0
SDSx_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
RD/WR
(55-56)
Register
Register Address
Value after Reset
SDS1_CR
SDS2_CR
55H
56H
00H
00H
This register is used to select position and length of the strobe signals. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to Chapter 3.7.2 and Chapter 3.7.2.2.
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active high or provides a strobed BCL clock output (see SDS_CONF.SDS1/
2_BCL). The data strobe signal allows standard data devices to access a programmable
channel.
Data Sheet
205
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.9
IOM_CR - Control Register IOM Data
Value after reset: 08H
7
0
IOM_CR SPU DIS_ CI_CS TIC_ EN_ CLKM DIS_ DIS_ RD/WR (57)
AW
DIS
BCL
OD
IOM
SPU ... Software Power Up
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following
CIC-interrupt.
For general information please refer to Chapter 3.7.6.
DIS_AW ... Disable Asynchronous Awake (NT, LT-S, Int. NT mode only)
Setting this bit to “1” disables the Asynchronous Awake function of the transceiver.
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CH2-0 of register TR_CR (for the transceiver) and DCI_CR (for the D-channel controller
and C/I-channel controller).
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access delivers the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration of the C/I-channel only,
whereas a read access delivers the C/I-channel configuration only.
TIC_DIS ... TIC Bus Disable
0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus (in a frame timing
with 12 timeslots only).
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
Data Sheet
206
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
EN_BCL ... Enable Bit Clock BCL/SCLK
0: The BCL/SCLK clock is disabled
1: The BCL/SCLK clock is enabled.
CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) or in NT, LT-S and Int. NT mode the DCL
from the IOM-2 interface is an input.
0: A double bit clock is connected to DCL
1: A single bit clock is connected to DCL
For general information please refer to Chapter 3.7.
DIS_OD ... Disable Open Drain Drivers
0: DU/DD are open drain drivers
1: DU/DD are push pull drivers
DIS_IOM ... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection between layer 1 and layer 2. However, the ISAC-SX internal operation
between S-transceiver, B-channel and D-channel controller is independent of the
DIS_IOM bit.
0: The IOM interface is enabled
1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance;
clock inputs are active; DU, DD data line inputs are switched off and outputs have high
impedance; except in TE/LT-T mode the DU line is input (’0’-level causes activation), so
the DU pin must be terminated (pull up resistor).
Data Sheet
207
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.10
STI - Synchronous Transfer Interrupt
Value after reset: 00H
7
0
STI
STOV STOV STOV STOV STI
21 20 11 10 21
STI
20
STI
11
STI
10
RD (58)
For all interrupts in the STI register the following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
The interrupts are automatically reset by reading the STI register. For general
information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles.
Data Sheet
208
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.11
ASTI - Acknowledge Synchronous Transfer Interrupt
Value after reset: 00H
7
0
ASTI
0
0
0
0
ACK ACK ACK ACK
21 20 11 10
WR (58)
For general information please refer to Chapter 3.7.1.1.
ACKxy ... Acknowledge Synchronous Transfer Interrupt
After an STIxy interrupt the microcontroller has to acknowledge the interrupt by setting
the corresponding ACKxy bit to “1”.
4.4.12
MSTI - Mask Synchronous Transfer Interrupt
Value after reset: FFH
7
0
MSTI
STOV STOV STOV STOV STI
21 20 11 10 21
STI
20
STI
11
STI
10
RD/WR (59)
For the MSTI register the following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
For general information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow for STIxy
Mask bits for the corresponding STOVxy interrupt bits.
STIxy ... Synchronous Transfer Interrupt xy
Mask bits for the corresponding STIxy interrupt bits.
Data Sheet
209
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.13
SDS_CONF - Configuration Register for Serial Data Strobes
Value after reset: 00H
7
0
SDS_
CONF
0
0
0
0
DIOM_ DIOM_ SDS2_ SDS1_ RD/WR (5A)
INV
SDS BCL
BCL
For general information on SDS1/2_BCL please refer to Chapter 3.7.2.
DIOM_INV ... DU/DD on IOM Timeslot Inverted
0: DU/DD are active during SDS1 HIGH phase and inactive during the LOW phase.
1: DU/DD are active during SDS1 LOW phase and inactive during the HIGH phase.
This bit has only effect if DIOM_SDS is set to ’1’ otherwise DIOM_INV is don’t care.
DIOM_SDS ... DU/DD on IOM Controlled via SDS1
0: The pin SDS1 and its configuration settings are used for serial data strobe only.
The IOM-2 data lines are not affected.
1: The DU/DD lines are deactivated during the during High/Low phase (selected via
DIOM_INV) of the SDS1 signal. The SDS1 timeslot is selected in SDS1_CR.
SDSx_BCL ... Enable IOM Bit Clock for SDSx
0: The serial data strobe is generated in the programmed timeslot.
1: The IOM bit clock is generated in the programmed timeslot.
Data Sheet
210
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.14
MCDA - Monitoring CDA Bits
Value after reset: FFH
7
0
MCDA
MCDA21
Bit7 Bit6
MCDA20
Bit7 Bit6
MCDA11
Bit7 Bit6
MCDA10
Bit7 Bit6
RD (5B)
MCDAxy ... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on
the TIC bus with the same register
4.4.15
MOR - MONITOR Receive Channel
Value after reset: FFH
7
0
MOR
Monitor Receiver Data
RD (5C)
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the
MONITOR channel protocol. The MONITOR channel (0-7) can be selected by setting the
monitor channel select bit MON_CR.MCS.
4.4.16
MOX - MONITOR Transmit Channel
Value after reset: FFH
7
0
MOX
Monitor Transmit Data
WR (5C)
Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according
to the MONITOR channel protocol.The MONITOR channel (0-7) can be selected by
setting the monitor channel select bit MON_CR.MCS
Data Sheet
211
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.17
MOSR - MONITOR Interrupt Status Register
Value after reset: 00H
7
0
MOSR
MDR MER MDA MAB
0
0
0
0
RD (5D)
MDR ... MONITOR channel Data Received
MER ... MONITOR channel End of Reception
MDA ... MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted.
MAB ... MONITOR channel Data Abort
Data Sheet
212
2000-08-03
PEB 3086
PEF 3086
Detailed Register Description
4.4.18
MOCR - MONITOR Control Register
Value after reset: 00H
7
0
MOCR
MRE MRC MIE MXC
0
0
0
0
RD/WR (5E)
MRE ... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC ... MR Bit Control
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
a packet (if MRE = 1).
1: MR is internally controlled by the ISAC-SX according to MONITOR channel protocol.
In addition, the MDR interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE = 1).
MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC ... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled by the ISAC-SX according to MONITOR channel
protocol.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
4.4.19
MSTA - MONITOR Status Register
Value after reset: 00H
MSTA
MAC ... MONITOR Transmit Channel Active
0
0
0
0
0
MAC
0
TOUT
RD (5F)
The data transmisson in the MONITOR channel is in progress.
TOUT ... Time-Out
Read-back value of the TOUT bit.
4.4.20
MCONF - MONITOR Configuration Register
Value after reset: 00H
MCONF
TOUT... Time-Out
0
0
0
0
0
0
0
TOUT
WR (5F)
0: The monitor time-out function is disabled
1: The monitor time-out function is enabled
Data Sheet
214
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PEB 3086
PEF 3086
Detailed Register Description
4.5
Interrupt and General Configuration
ISTA - Interrupt Status Register
4.5.1
Value after reset: 00H
7
0
ISTA
ICB
0
ST
CIC
AUX TRAN MOS ICD
RD (60)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ICB, ICD ... HDLC Interrupt from B-channel or D-channel
An interrupt originated from the HDLC controllers of the B-channel or D-channel has
been recognized.
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow,
timer1, timer2 or from one of the interrupt input pins (INT0, INT1). The source can be
read from the auxiliary interrupt register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
reading the corresponding status register.
Data Sheet
215
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PEB 3086
PEF 3086
Detailed Register Description
4.5.2
MASK - Mask Register
Value after reset: FFH
7
0
MASK
ICB
1
ST
CIC
AUX TRAN MOS ICD
WR (60)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the ISTA register can selectively be masked/disabled by setting
the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is set, but no interrupt is generated.
4.5.3
AUXI - Auxiliary Interrupt Status Register
Value after reset: 00H
7
0
AUXI
0
0
EAW WOV TIN2 TIN1 INT1 INT0
RD (61)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
EAW ... External Awake Interrupt
An interrupt from the EAW pin has been detected.
WOV ... Watchdog Timer Overflow
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the
correct manner. A reset pulse has been generated by the ISAC-SX.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
TIN2, 1 ... Timer Interrupt 1, 2
An interrupt originated from timer 1 or timer 2 is recognized, i.e the timer has expired.
INT1, 0 ... Auxiliary Interrupt from external devices 1, 0
A low level or a negative state transition (programmable in ACFG2.EL1/0) is detected at
pin AUX7 or AUX6, respectively.
4.5.4
AUXM - Auxiliary Mask Register
Value after reset: FFH
7
0
AUXM
1
1
EAW WOV TIN2 TIN1 INT1 INT0
WR (61)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the AUXI register can selectively be masked/disabled by setting
the corresponding bit in AUXM to ’1’. Masked interrupt status bits are not indicated when
AUXI is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
Data Sheet
217
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PEB 3086
PEF 3086
Detailed Register Description
4.5.5
MODE1 - Mode1 Register
Value after reset: 00H
7
0
MODE1
0
0
0
WTC1 WTC2 CFS RSS2 RSS1 RD/WR (62)
WTC1, 2 ... Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ’11’) the watchdog timer is
started. During every time period of 128 ms the microcontroller has to program the
WTC1 and WTC2 bit in the following sequence
WTC1
WTC2
1.
2.
1
0
0
1
to reset and restart the watchdog timer.
If WTC1/2 is not written fast enough in this way, the timer expires and a WOV-interrupt
(AUXI register) together with a reset pulse is generated.
CFS ... Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except for the
indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state
and with C/I command Deactivation Indication (DI) the "Power Down" state is reached
again.
However, it is also possible to activate the S-interface directly with the C/I command
Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(IOM_CR.SPU) or by resetting CFS again.
After that the S-interface can be activated with the C/I command Activate Request (AR
8/10/L). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
Note: After reset the IOM interface is always active. To reach the "Power Down" state
the CFS-bit has to be set.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
For general information please refer to Chapter 3.3.9.
RSS2, RSS1... Reset Source Selection 2,1
The ISAC-SX reset sources for the RSTO output pin can be selected according to the
table below.
RSS
C/I Code
Change
EAW
Watchdog
Timer
Bit 1 Bit 0
0
0
1
1
0
1
0
1
--
--
--
(reserved)
x
x
--
x
--
--
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
generated at RSTO.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs ≤ t≤ 250 µs is
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
125 µs ≤ t ≤ꢀ250µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
After a reset pulse generated by the ISAC-SX and the corresponding interrupt (WOV or
CIC) the actual reset source can be read from the ISTA.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
4.5.6
MODE2 - Mode2 Register
Value after reset: 00H
7
0
MODE2
0
0
0
0
INT_
POL
0
0
PPSDX RD/WR (63)
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
4.5.7
ID - Identification Register
Value after reset: 01H
7
0
ID
0
0
DESIGN
RD (64)
DESIGN ... Design Number
The design number allows to identify different hardware designs of the ISAC-SX by
software.
01H: Version 1.3
(all other codes reserved)
Data Sheet
220
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PEB 3086
PEF 3086
Detailed Register Description
4.5.8
SRES - Software Reset Register
Value after reset: 00H
7
0
SRES
RES_ RES_
CI BCH
RES_ RES_ RES_ RES_ RES_
MON DCH IOM TR RSTO
WR (64)
RES_xx ... Reset Functional Block xx
A reset can be activated on the functional block C/I-handler, B-channel, Monitor channel,
D-channel, IOM handler, S-transceiver and to pin RSTO.
Setting one of these bits to “1” causes the corresponding block to be reset for a duration
of 4 BCL clock cycles, except RES_RSTO which is activated for a duration of
125 ... 250µs. The bits are automatically reset to “0” again.
Data Sheet
221
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PEB 3086
PEF 3086
Detailed Register Description
4.5.9
TIMR2 - Timer 2 Register
Value after reset: 00H
7
0
TIMR2
TMD
0
CNT
RD/WR (65)
TMD ... Timer Mode
Timer 2 can be used in two different modes of operation.
0:Count Down Timer.
An interrupt is generated only once after a time period of 1 ... 63 ms.
1:Periodic Timer.
An interrupt is periodically generated every 1 ... 63 ms (see CNT).
CNT ... Timer Counter
0:Timer off.
1 ... 63:Timer period = 1 ... 63 ms
By writing ’0’ to CNT the timer is immediately stopped. A value different from that
determines the time period after which an interrupt will be generated.
If the timer is already started with a certain CNT value and is written again before an
interrupt has been released, the timer will be reset to the new value and restarted again.
An interrupt is indicated to the host in AUXI.TIN2.
Note: Reading back this value delivers back the current counter value which may differ
from the programmed value if the counter is running.
Data Sheet
222
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PEB 3086
PEF 3086
Detailed Register Description
4.6
B-Channel Registers
4.6.1
ISTAB - Interrupt Status Register B-Channel
Value after reset: 10H
7
0
ISTAB
RME RPF RFO XPR
0
XDU
0
0
RD (70)
For general information please refer to Chapter 3.9.6.
RME ... Receive Message End
One complete frame of length less than or equal to the defined block size (EXMB.RFBS)
or the last part of a frame of length greater than the defined block size has been received.
The contents are available in the RFIFOB. The message length and additional
information may be obtained from RBCHB and RBCLB and the RSTAB register.
RPF ... Receive Pool Full
A data block of a frame longer than the defined block size (EXMB.RFBS) has been
received and is available in the RFIFOB. The frame is not yet complete.
RFO ... Receive Frame Overflow
The received data of a frame could not be stored, because the RFIFOB is occupied. The
whole message is lost.
This interrupt can be used for statistical purposes and indicates that the microcontroller
does not respond quickly enough to an RPF or RME interrupt (ISTAB).
XPR ... Transmit Pool Ready
A data block of up to the block size 32 bytes can be written to the XFIFOB.
An XPR interrupt will be generated in the following cases:
• after an XTF or XME command as soon as the 32 bytes in the XFIFOB are available
and the frame is not yet complete
• after an XTF together with an XME command is issued, when the whole frame has
been transmitted
• after a reset of the transmitter (XRES)
• after a device reset
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFOB holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAB register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
4.6.2
MASKB - Mask Register B-Channel
Value after reset: FFH
7
0
MASKB
RME RPF RFO XPR
1
XDU
1
1
WR (70)
Each interrupt source in the ISTAB register can selectively be masked by setting the
corresponding bit in MASKB to ’1’. Masked interrupt status bits are not indicated when
ISTAB is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
For general information please refer to Chapter 3.9.6.
4.6.3
STARB - Status Register B-Channel
Value after reset: 40H
7
0
STARB
XDOV XFW
0
0
RACI
0
XACI
0
RD (71)
XDOV ... Transmit Data Overflow
More than 32 bytes have been written to the XFIFOB, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOB. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
RACI ... Receiver Active Indication
The B-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
XACI ... Transmitter Active Indication
The B-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The
XACI-bit is active when an XTF-command is issued and the frame has not been
completely transmitted
Data Sheet
225
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PEB 3086
PEF 3086
Detailed Register Description
4.6.4
CMDRB - Command Register B-channel
Value after reset: 00H
7
0
CMDRB
RMC RRES
0
0
XTF
0
XME XRES
WR (71)
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOB may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOB is cleared of any data.
XTF ... Transmit Transparent Frame
After having written up to 32 bytes to the XFIFOB, the microcontroller initiates the
transmission of a transparent frame by setting this bit to ’1’. The opening flag is
automatically added to the message by the ISAC-SX.
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOB completes the corresponding frame. The ISAC-SX terminates the transmission
by appending the CRC and the closing flag sequence to the data.
XRES ... Transmitter Reset
The B-channel HDLC transmitter is reset and the XFIFOB is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOB and the
appropriate Transmit Command (XTF) has to be written to the CMDRB register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAB).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
4.6.5
MODEB - Mode Register
Value after reset: C0H
7
0
MODEB MDS2 MDS1 MDS0
0
RAC
0
0
0
RD/WR
(72)
MDS2-0 ... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0 Mode
Number of Address Comparison
Address
Bytes
Remark
1.Byte
2.Byte
0
0
0
0
0
1
0Reserved
1Reserved
0Non-Auto
mode
1
2
RAL1,RAL2
–
One-byteaddress
compare.
0
1
1
0
1Non-Auto
mode
RAH1,RAH2,
Group Address
RAL1,RAL2,
Group Address compare.
Two-byteaddress
0Extended
transparent
mode
1
1
0Transparent–
–
–
No address
mode 0
compare. All
frames accepted.
1
1
1
0
1Transparent> 1
mode 1
RAH1,RAH2,
Group Address
–
High-byte
address compare.
1Transparent> 1
mode 2
–
RAL1,RAL2,
Group Address compare.
Low-byteaddress
Note: - RAH1, RAH2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
Group Address= fixed value FC / FEH.
- RAL1, RAL2: two programmable address values for the second (or the only, in
the case of a one-byte address) received address byte;
Group Address= fixed value FFH.
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
RAC ... Receiver Active
The B-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
4.6.6
EXMB - Extended Mode Register B-channel
Value after reset: C0H
7
0
EXMB
1
1
RFBS SRA XCRC RCRC
0
ITF
RD/WR
(73)
RFBS … Receive FIFO Block Size
0 … Block size is 16 byte
1 … Block size is 8 byte
Note: A change of RFBS will take effect after a transmitter command (CMDRB.RMC,
CMDRB.RRES,) has been written
The transmit FIFO block size is fixed to 32 byte and cannot be configured.
SRA … Store Receive Address
0 … Receive Address is not stored in the RFIFOB
1 … Receive Address is stored in the RFIFOB
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC is not transmitted
RCRC… Receive CRC
0 … CRC is not stored in the RFIFOB
1 … CRC is stored in the RFIFOB
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Data Sheet
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PEB 3086
PEF 3086
Detailed Register Description
4.6.7
RAH1 - RAH1 Register
Value after reset: 00H
7
0
RAH1
RAH1
0
MHA
WR (75)
RAH1 ... Value of the first individual programmable high address byte
In operating modes that provide high byte address recognition, the high byte of the
received address is compared with the individual programmable values in RAH1, RAH2
or group address FCH/FEH.
MHA ... Mask High Address
0: The RAH1 address of an incoming frame is compared with RAH1, RAH2 and Group
Address.
1: The RAH1 address of an incoming frame is compared with RAH1 and Group
Address. RAH1 can be masked with RAH2 thereby bitpositions of RAH1 are not
compared if they are set to ’1’ in RAH2.
4.6.8
RAH2 - RAH2 Register
Value after reset: 00H
7
0
RAH2
RAH2
0
MLA
WR (76)
RAH2 ... Value of the second individual programmable high address byte
See RAH1 register above. RAH1 and RAH2 are used in non-auto mode when a 2-byte
address field has been selected and in the transparent mode 1.
MLA ... Mask Low Address
0: The address of an incoming frame is compared with RAL1, RAL2 and Group
Address.
1: The address of an incoming frame is compared with RAL1 and Group Address. RAL1
can be masked with RAL2 thereby bitpositions of RAL1 are not compared if they are set
to ’1’ in RAL2.
Data Sheet
229
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PEB 3086
PEF 3086
Detailed Register Description
4.6.9
RBCLB - Receive Frame Byte Count Low B-Channel
Value after reset: 00H
7
0
RBCLB
RBC7
RBC0
RD (76)
RBC7-0 ... Receive Byte Count
Eight least significant bits of the total number of bytes in a received message (see
RBCHB register).
4.6.10
RBCHB - Receive Frame Byte Count High B-Channel
Value after reset: 00H.
7
0
RBCHB
0
0
0
OV RBC11
RBC8
RD (77)
OV ... Overflow
A ’1’ in this bit position indicates a message longer than (212 - 1) = 4095 bytes .
RBC8-11 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message (see
RBCLB register).
Note: Normally RBCHB and RBCLB should be read by the microcontroller after an RME-
interrupt in order to determine the number of bytes to be read from the RFIFOB,
and the total message length. The contents of the registers are valid only after an
RME or RPF interrupt, and remain so until the frame is acknowledged via the RMC
bit or RRES.
Data Sheet
230
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PEB 3086
PEF 3086
Detailed Register Description
4.6.11
RAL1 - RAL1 Register 1
Value after reset: 00H
7
0
RAL1
RAL1
WR (77)
RAL1 ... Receive Address Byte Low Register 1
The general function (READ/WRITE) and the meaning or contents of this register
depends on the selected operating mode:
– Non-auto mode (16-bit address):
RAL1 can be programmed with the value of the first individual low address byte.
– Non-auto mode (8-bit address):
According to X.25 LAPB protocol, the address in RAL1 is recognized as COMMAND
address.
4.6.12
RAL2 - RAL2 Register
Value after reset: 00H
7
0
RAL2
RAL2
WR (78)
RAL2 ... Receive Address Byte Low Register 2
Value of the second individual programmable low address byte. If a one byte address
field is selected, RAL2 is recognized as RESPONSE according to X.25 LAPB protocol.
Data Sheet
231
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PEB 3086
PEF 3086
Detailed Register Description
4.6.13
RSTAB - Receive Status Register B-Channel
Value after reset: 0EH
7
0
RSTAB
VFR RDO CRC RAB HA1
HA0
C/R
LA
RD (78)
VFR... Valid Frame
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO ... Receive Data Overflow
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFOB. As opposed to ISTAB.RFO an RDO indicates that the beginning of a frame has
been received but not all bytes could be stored as the RFIFOB was temporarily full.
CRC ... CRC Check
The CRC is correct (1) or incorrect (0).
RAB ... Receive Message Aborted
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
HA1, HA0 … High Byte Address Compare; significant only in non automode 16
and in transparent mode 1
In operating modes which provide high byte address recognition, the ISAC-SX compares
the high byte of a 2-bytes address with the contents of two individual programmable
registers (RAH1, RAH2) and the fixed values FEH and FCH (group address).
Depending on the result of this comparison, the following bit combinations are possible:
10 … RAH1 has been recognized
00 … RAH2 has been recognized
01 … group address has been recognized
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address, LAPD)
Data Sheet
232
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PEB 3086
PEF 3086
Detailed Register Description
LA … Low Byte Address Compare; significant only in non automodes 8 and 16 and
in transparent mode 2
The low byte address of a 2-byte address field, or the single address byte of a 1-byte
address field is compared with two programmable registers (RAL1, RAL2) and with the
group address (fixed value FFH)
0 … Group address has been recognized
1 … RAL1 or RAL2 has been recognized
Note: RSTAB corresponds to the last received HDLC frame; it is duplicated into RFIFOB
for every frame (last byte of frame).
If several frames are contained in the RFIFOB the corresponding status
information for each frame should be evaluated from the FIFO contents (last byte)
as RSTAB only refers to last frame in the FIFO.
4.6.14
TMB -Test Mode Register B-Channel
Value after reset: 00H
7
0
TMB
0
0
0
0
0
0
0
TLP
RD/WR
(79)
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
Data Sheet
233
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PEB 3086
PEF 3086
Detailed Register Description
4.6.15
RFIFOB - Receive FIFO B-Channel
7
0
RFIFOB
Receive data
RD (7A)
A read access to this register gives access to the “current” FIFO location selected by an
internal pointer which is automatically incremented after each read access.
The RFIFOB contains up to 128 bytes of received data.
After an ISTAB.RPF interrupt, a complete data block is available. The block size can be
8 or 16 bytes depending on the EXMB.RFBS setting.
After an ISTAB.RME interrupt, the number of received bytes can be obtained by reading
the RBCLB register.
4.6.16
XFIFOB - Transmit FIFO B-Channel
7
0
XFIFOB
Transmit data
WR (7A)
A write access to this register gives access to the “current” FIFO location selected by an
internal pointer which is automatically incremented after each write access.
The total XFIFO size is 128 byte and data blocks with up to 32 bytes of transmit data can
be written to the XFIFOB following an ISTAB.XPR interrupt.
Data Sheet
234
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PEB 3086
PEF 3086
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
max.
Unit
min.
Ambient temperature under bias
TA
°C
PEB
PEF
0
-45
+70
+85
Storage temperature
TSTG
VS
– 55
150
°C
Input/output voltage on any pin
with respect to ground
– 0.3
5.25
V
Maximum voltage on any pin
with respect to ground
Vmax
5.5
V
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
The supply voltage must show a monotonic rise.
Data Sheet
235
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.2
DC Characteristics
VDD/VSS = 3.3V=± 5 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ. max.
H-input level
(except pin SR1/2)
VIH
VIL
2.0
5.5
V
V
L-input level
(except pin SR1/2)
– 0.3
2.4
0.8
H-output level
(except pin XTAL2,
SX1/2)
VOH
V
IOH = - 4.5 mA (AD0-7)
OH = - 400 µA
I
(all others)
L-output level
(except pin XTAL2,
SX1/2)
VOL
0.45
V
IOL = 6 mA (DU, DD,
C768)
IOL = 4.5 mA (ACL,
AUX7, AUX6, AD0-7)
IOL = 2 mA (all others)
Input leakage current
Output leakage current ILO
ILI
± 1
± 1
µA 0V< VIN<VDD
µA 0V< VOUT<VDD
(all pins except
SX1/2,SR1/2,XTAL1/2,
AUX7/6)
Input leakage current
Output leakage current ILO
(AUX7/6)
ILI
50
50
200
200
µA 0V< VIN<VDD
µA 0V< VOUT<VDD
(only if AUX7/6 is
input or output/open-
drain; not relevant if
output/push-pull)
Data Sheet
236
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.3
Capacitances
TA = 25 °C, VDD = 3.3V ±=5 % VSSA = 0 V, VSS = 0 V, fc = 1 MHz, unmeasured pins
grounded.
Parameter
Symbol Limit Values Unit Remarks
min. max.
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
All pins except SX1,2 and
XTAL1,2
Output Capacitance
against VSS
COUT
10
pF
pins SX1,2
Data Sheet
237
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.4
Oscillator Specification
Recommended Oscillator Circuits
External
Oscillator
Signal
41
42
41
42
XTAL1
XTAL2
XTAL1
XTAL2
7.68 MHz
N.C.
Crystal Oscillator Mode
Driving from External Source
Figure 81
Oscillator Circuits
Parameter
Symbol
Limit Values
7.680
Unit
MHz
ppm
pF
Frequency
f
Frequency calibration tolerance
Load capacitance
max. 100
max. 40
CL
Oscillator mode
fundamental
Note: It is important to note that the load capacitance depends on the recommendation
of the crystal specification. Typical values are 22 ... 33 pF.
XTAL1 Clock Characteristics (external oscillator input)
Parameter
Limit Values
min. max.
Duty cycle
1:2
2:1
Data Sheet
238
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.5
AC Characteristics
TA = 0 to 70 °C, VDD = 3.3 V ± 5 %
Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in figure 82.
2.4
2.0
0.8
2.0
0.8
Device
Under
Test
Test Points
CLoad = 100 pF
0.45
ITS09660
Figure 82
Input/Output Waveform for AC Tests
Data Sheet
239
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.6
IOM-2 Interface Timing
FSC (O)
t IIS
t FSD
DCL (O)
t
IIH
DU/DD (I)
t IOD
DU/DD (O)
SDS (O)
t SDD
t BCD
t BCD
FSC/BCL (O)
ITD09663
Figure 83
IOM-2 Timing (TE mode)
Data Sheet
240
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
DCL (I)
FSC (I)
t FSW
t FSS
t FSH
t FSS
t FSH
t IIH
t IIS
DU/DD (I)
Bit 0
t IOD
DU/DD (O)
Bit 0
t SDD
SDS (O)
ITT09680
Figure 84
IOM-2 Timing (LT-S, LT-T, NT mode)
Symbol
Parameter
Limit Values
Unit
min.
max.
IOM output data delay
IOM input data setup
IOM input data hold
FSC strobe delay
Strobe signal delay
BCL / FSC delay
tIOD
tIIS
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tIIH
3
tFSD
tSDD
tBCD
tFSS
tFSH
tFSW
-135
15
50
30
Frame sync setup
Frame sync hold
20
30
40
Frame sync width
Note: Min. value in synchronous state, max. value in non-synchronous state.
Data Sheet
241
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
DCL Clock Output Characteristics
2.3 V
Figure 85
Definition of Clock Period and Width
Symbol Limit Values
Unit Test Condition
min.
585
260
260
typ.
651
325
325
max.
717
391
391
tP
ns
ns
ns
osc ± 100 ppm
osc ± 100 ppm
osc ± 100 ppm
tWH
tWL
DCL Clock Input Characteristics
Parameter
Limit Values
Unit
min.
max.
60
Duty cycle
40
%
Data Sheet
242
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.7
Microcontroller Interface Timing
5.7.1
Serial Control Interface (SCI) Timing
t
1
t
t
t
t
5
4
2
3
CS
SCL
SDR
SDX
t
t
7
6
t
9
t
8
Figure 86
SCI Interface
Parameter
Symbol
Limit values
Unit
SCI Interface
Min
Max
SCL cycle time
SCL high time
t1
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2=
t3=
t4=
t5
100
100
2
SCL low time
CS setup time
CS hold time
10
10
6
SDR setup time
SDR hold time
SDX data out delay
CS high to SDX tristate
t6=
t7=
t8=
t9
30
40
Data Sheet
243
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.7.2
Parallel Microcontroller Interface Timing
Siemens/Intel Bus Mode
Figure 87
Microprocessor Read Cycle
Figure 88
Microprocessor Write Cycle
Figure 89
Multiplexed Address Timing
Data Sheet
244
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
WR x CS or
RD X CS
tAS
tAH
A0-A7
Address
ITT09661
Figure 90
Non-Multiplexed Address Timing
Motorola Bus Mode
AD0-7
Figure 91
Microprocessor Read Timing
R / W
t DSD
tRWD
t WW
t WI
CS x DS
t WD
tDW
Data
AD0-7
ITT09679
Figure 92
Microprocessor Write Cycle
Data Sheet
245
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
CS x DS
tAS
tAH
AD0 - AD7
ITT09662
Figure 93
Non-Multiplexed Address Timing
Microprocessor Interface Timing
Parameter
Symbol
Limit Values Unit
min.
20
5
max.
ALE pulse width
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time to ALE
Address hold time from ALE
Address latch setup time to WR, RD
Address setup time
tAL
tLA
3
tALS
tAS
10
10
3
Address hold time
tAH
tAD
tDSD
tRR
tRD
tDF
ALE guard time
15
3
DS delay after R/W setup
RD pulse width
100
Data output delay from RD
Data float from RD
80
25
RD control interval
tRI
70
10
10
2
W pulse width
tWW
tDW
tWD
tWI
Data setup time to W x CS
Data hold time W x CS
W control interval
70
2
R/W hold from CS x DS inactive
tRWD
Data Sheet
246
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.8
Multiframe Synchronisation Timing
FSC
DCL
FSC detected
XTAL
20 XTAL
SX1 / SX2
MBIT
FBIT (40xXTAL)
Counter reset
21150_32
The sample time of the MBIT input is related to the rising edge of FSC at the beginning of an S0 frame
-- min: 20 * 1 / xtal
-- max: 20 * 1 / xtal + 1 / xtal + 1 / dcl
Figure 94
Sampling Time in LT-S/NT Mode (M-Bit Input)
Data Sheet
247
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.9
Reset
Parameter
Symbol Limit Values Unit Test Conditions
min.
Length of active tRES
low state
4
ms
Power On/Power Down
to Power Up (Standby)
2 x DCL
clock cycles
During Power Up
(Standby)
t RES
RES
21150_26
Figure 95
Reset Signal RES
Data Sheet
248
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.10
S-Transceiver
Parameter
Symbol
Limit Values
typ. max.
Unit Test Condition
min.
VDD= 3.3V ± 5 %; VSS= 0V; TA = 0 to 70 °C
Power supply current-
Power Down
Inputs at VSS / VDD
No output loads
- Clocks Off
IPD1
IPD2
300
3
µA
except SX1,2 (50Ω)
- Clocks On
mA
Power supply current
- S operational (96 kHz) IOP1
30
30
25
mA DCL=1536 kHz
mA DCL=4096 kHz
mA DCL=1536 kHz
IOP2
- B1=00H,B2=FFH, D=0 IOP3
Absolute value of output VX
pulse amplitude
| VSX2 – VSX1 |
1.17
26
V
RL = ∞
Transmitter output
current
IX
mA RL = 5.6 Ω
Transmitter output
impedance (SX1,2)
ZX
10
0
kΩ Inactive or during
binary one;
Ω
during binary zero RL =
50 Ω
Receiver Input
ZR
30
kΩ
VDD = 3.3 V
impedance (SR1,2)
Data Sheet
249
2000-08-03
PEB 3086
PEF 3086
Electrical Characteristics
5.11
Recommended Transformer Specification
Parameter
Symbol
Limit Values
typ. max.
1:1
Unit Test Condition
min.
Transformer ratio
Main inductance
L
25
20
mH no DC current,
10 kHz
mH 2.5 mA DC current,
10 kHz
Leakage inductance
LL
C
8
µH 10 kHz
Capacitance between
primary and secondary
side
80
pF
1 kHz
Copper resistance
R
1.7
2.0
2.3
W
Data Sheet
250
2000-08-03
PEB 3086
PEF 3086
Package Outlines
6
Package Outlines
P-MQFP-64-1
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Dimensions in mm
SMD = Surface Mounted Device
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
SMD = Surface Mounted Device
Dimensions in mm
2000-08-03
Data Sheet
251
PEB 3086
PEF 3086
Package Outlines
P-TQFP-64-1
(Plastic Thin Quad Flat Package)
Data Sheet
252
2000-08-03
PEB 3086
PEF 3086
Appendix
7
Appendix
D-channel HDLC, C/I-channel Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
RFIFOD
D-Channel Receive FIFO
00H-
1FH
R
XFIFOD
ISTAD
D-Channel Transmit FIFO
00H-
1FH
W
RME RPF RFO XPR XMR XDU
0
1
0
1
0
20H
20H
21H
R 10H
W FFH
R 40H
W 00H
MASKD RME RPF RFO XPR XMR XDU
STARD XDOV XFW
CMDRD RMC RRES
0
0
0
STI
0
RACI
XTF
0
0
XACI
XME XRES 21H
MODED MDS2 MDS1 MDS0
RAC DIM2 DIM1 DIM0
22H R/WC0H
23H R/W 00H
24H R/W 00H
EXMD1 XFBS
TIMR1
RFBS
CNT
SRA XCRC RCRC
VALUE
0
ITF
SAP1
SAPI1
SAPI2
0
0
MHA
MLA
25H
26H
W FCH
W FCH
R 00H
R 00H
W FFH
W FFH
R 0FH
SAP2
RBCLD RBC7
RBC0 26H
RBC8 27H
RBCHD
TEI1
0
0
0
OV RBC11
TEI1
TEI2
EA1
EA2
TA
27H
28H
28H
TEI2
RSTAD
TMD
VFR RDO CRC RAB SA1 SA0
C/R
0
0
0
0
0
0
0
TLP
29H R/W 00H
2A-2DH
2EH
reserved
CIC0 CIC1 S/G BAS
CIR0
CIX0
CODR0
CODX0
R F3H
TBA2 TBA1 TBA0 BAC 2EH
253
W FEH
Data Sheet
2000-08-03
PEB 3086
PEF 3086
Appendix
CIR1
CIX1
CODR1
CODX1
CICW CI1E
CICW CI1E
2FH
R
FEH
2FH W FEH
Transceiver, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
30H R/W 01H
TR_
CONF0
DIS_ BUS EN_
0
0
L1SW
0
x
0
EXLP LDD
TR
ICV
TR_
CONF1
0
RPLL_ EN_
ADJ SFSC
0
0
0
x
x
31H R/W
TR_
CONF2
DIS_ PDS
TX
0
RLP
SGP SGD
32H R/W 80H
TR_STA
TR_CMD
RINF
XINF
0
ICV
FSYN
0
LD
0
33H
R 00H
DPRIO TDDIS PD LP_A
34H R/W 08H
SQRR1 MSYN MFEN
SQXR1 MFEN
0
0
0
0
SQR11SQR12SQR13SQR14 35H
SQX11SQX12SQX13SQX14 35H
R 40H
W 4FH
R 00H
W 00H
R 00H
W 00H
R 00H
0
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 36H
SQXR2 SQX21SQX22SQX23SQX24SQX31SQX32SQX33SQX34 36H
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 37H
SQXR3 SQX41SQX42SQX43SQX44SQX51SQX52SQX53SQX54 37H
ISTATR
0
1
0
x
1
0
x
1
0
x
1
0
LD
LD
RIC SQC SQW
RIC SQC SQW
38H
MASKTR
39H R/W FFH
TR_
DCH_ MODE MODE MODE 3AH R/W 00H
INH
MODE
2
1
0
reserved
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
3BH
ACFG1
3CH R/W 00H
Data Sheet
254
2000-08-03
PEB 3086
PEF 3086
Appendix
Transceiver, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
3DH R/W 00H
3EH R/W FFH
ACFG2 A7SEL A5SEL FBS A4SEL ACL LED EL1
EL0
AOE
ARX
ATX
OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
3FH
3FH
R
AT7 AT6 AT5 AT4 AT3 AT2 AT1
AT0
W 00H
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
40H R/W FFH
41H R/W FFH
42H R/W FFH
43H R/W FFH
44H R/W 00H
CDA10
CDA11
CDA20
CDA21
Controller Data Access Register (CH10)
Controller Data Access Register (CH11)
Controller Data Access Register (CH20)
Controller Data Access Register (CH21)
CDA_
TSDP10
DPS
DPS
DPS
DPS
DPS
0
0
0
0
0
0
0
0
0
0
TSS
TSS
TSS
TSS
TSS
CDA_
TSDP11
45H R/W 01H
46H R/W 80H
47H R/W 81H
48H R/W 80H
CDA_
TSDP20
CDA_
TSDP21
BCH_
TSDP_
BC1
BCH_
TSDP_
BC2
DPS
0
0
TSS
49H R/W 81H
reserved
4AH
Data Sheet
255
2000-08-03
PEB 3086
PEF 3086
Appendix
reserved
4BH
TR_
TSDP_
BC1
DPS
DPS
0
0
0
0
TSS
TSS
4CH R/W
TR_
TSDP_
BC2
4DH R/W
CDA1_
CR
0
0
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP 4EH R/W 00H
TBM
CDA2_
CR
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP 4FH R/W 00H
TBM
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
50H R/W
TR_CR
EN_ EN_ EN_ EN_ EN_
CS2-0
(CI_CS=0)
D
B2R B1R B2X B1X
TRC_CR
(CI_CS=1)
0
0
0
0
0
0
CS2-0
CS2-0
50H R/W
BCH_
CR
DPS_
D
EN_D EN_ EN_
BC2 BC1
51H R/W 80H
reserved
52H
DCI_CR DPS_ EN_
(CI_CS=0) CI1 CI1 EN_D EN_B2EN_B1
D_
D_
D_
CS2-0
CS2-0
CS2-0
53H R/W
DCIC_CR
(CI_CS=1)
0
0
0
0
0
0
0
0
53H R/W
MON_CR DPS EN_
MON
54H R/W
SDS1_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
55H R/W 00H
Data Sheet
256
2000-08-03
PEB 3086
PEF 3086
Appendix
SDS2_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
56H R/W 00H
IOM_CR SPU DIS_ CI_CS TIC_ EN_ CLKM DIS_ DIS_
57H R/W 08H
AW
DIS BCL
OD
IOM
STI
STOV STOV STOV STOV STI
STI
20
STI
11
STI
10
58H
58H
R 00H
W 00H
21
0
20
0
11
0
10
0
21
ASTI
MSTI
ACK ACK ACK ACK
21
20
11
10
STOV STOV STOV STOV STI
STI
20
STI
11
STI
10
59H R/W FFH
21
0
20
0
11
0
10
0
21
SDS_
CONF
DIOM_DIOM_SDS2_SDS1_ 5AH R/W 00H
INV SDS BCL BCL
MCDA
MOR
MCDA21
MCDA20
MCDA11
MCDA10
5BH
5CH
R FFH
R FFH
MONITOR Receive Data
MONITOR Transmit Data
MOX
5CH W FFH
5DH R 00H
5EH R/W 00H
R 00H
TOUT 5FH W 00H
MOSR
MOCR
MSTA
MCONF
MDR MER MDA MAB
MRE MRC MIE MXC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAC
0
TOUT 5FH
Interrupt, General Configuration Registers
NAME
ISTA
7
6
5
4
3
2
1
0
ADDR R/WRES
ICB
ICB
0
0
1
0
1
ST
ST
CIC AUX TRAN MOS ICD
CIC AUX TRAN MOS ICD
60H
60H
61H
61H
R 00H
W FFH
R 00H
W FFH
MASK
AUXI
EAW WOV TIN2 TIN1 INT1 INT0
EAW WOV TIN2 TIN1 INT1 INT0
AUXM
1
Data Sheet
257
2000-08-03
PEB 3086
PEF 3086
Appendix
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
ADDR R/WRES
MODE1
MODE2
0
0
0
0
0
0
WTC1 WTC2 CFS RSS2 RSS1 62H R/W 00H
0
INT_
POL
0
0
PPSDX 63H R/W 00H
ID
0
0
DESIGN
64H
R 01H
W 00H
SRES
RES_ RES_
0
RES_ RES_ RES_ RES_ RES_ 64H
CI
BCH
MON DCH IOM
CNT
TR RSTO
TIMR2
TMD
0
65H R/W 00H
reserved
66H-
6FH
Data Sheet
258
2000-08-03
PEB 3086
PEF 3086
Appendix
B-channel HDLC Control Registers
Name
ISTAB
7
6
5
4
3
2
1
0
ADDR R/WRES
RME RPF RFO XPR
0
1
XDU
XDU
0
0
1
0
1
0
70H
70H
71H
R 10H
W FFH
R 40H
W 00H
MASKB RME RPF RFO XPR
STARB XDOV XFW
CMDRB RMC RRES
0
0
0
0
0
RACI
XTF
XACI
0
XME XRES 71H
MODEB MDS2 MDS1 MDS0
RAC
0
0
0
0
72H R/WC0H
73H R/WC0H
74H
EXMB
1
1
RFBS SRA XCRC RCRC
ITF
reserved
RAH1
RAH1
RAH2
0
0
MHA
MLA
75H
76H
W 00H
W 00H
R 00H
R 00H
W 00H
W 00H
R 0EH
RAH2
RBCLB RBC7
RBC0 76H
RBC8 77H
77H
RBCHB
RAL1
0
0
0
OV RBC11
RAL1
RAL2
RAL2
78H
RSTAB
TMB
VFR RDO CRC RAB HA1 HA0 C/R
LA
78H
0
0
0
0
0
0
0
TLP
79H R/W 00H
RFIFOB
XFIFOB
B-Channel Receive FIFO
B-Channel Transmit FIFO
reserved
7AH
7AH
R
W
7BH-
7FH
Data Sheet
259
2000-08-03
PEB 3086
PEF 3086
CDA_TSDPxy registers 197
CDAx_CR register 198
CDAxy registers 196
CFS bit 218
CI_CS bit 206
CI1E bit 181
CIC bit 215
CIC1/0 bits 179
CICW bit 181
A
A4SEL bit 192
A5SEL bit 192
A7SEL bit 192
Absolute maximum ratings 235
AC characteristics 239
ACFG1 register 192
ACFG2 register 192
ACKxy bits 209
CIR0 register 179
CIR1 register 181
CIX0 register 180
CIX1 register 181
CLKM bit 206
Clock generation 67
CMDR register 170
CMDRB register 226
CNT bits 174, 222
CODR0 bits 179
CODR1 bits 181
CODX0 bits 180
CODX1 bits 181
Control of layer-1 72
Controller data access 98
CRC bit 177, 232
ACL bit 192
Activation 90
Activation indication - pin ACL 46
Activation LED 46
Activation/deactivation of IOM-2 interface
130
AOE register 194
Appendix 253
Applications 21
AR7-0 bits 195
Architecture 31
ARX register 195
ASTI register 209
Asynchronous awake 132
AT7-0 bits 195
ATX register 195
AUX bit 215
AUXI register 216
Auxiliary interface 133
AUXM register 217
D
D_EN_B2/1 bits 202
D_EN_D bit 202
DC characteristics 236
DCH_INH bit 191
D-channel access control
Intelligent NT 126
B
BAC bit 180
BAS bit 179
S-bus D-channel control in LT-T 126
S-bus priority mechanism 124
TIC bus 122
BCH_CR registers 201
BCH_TSDP_BC1/2 registers 197
BUS bit 182
DCI_CR register 202
Deactivation 90
Bus operation modes 38
Delay between IOM-2 and S 56
DESIGN bits 220
Device architecture 31
DIM2-0 bits 171
C
C/I channel 120
C/R bit 177, 232
Capacitances 237
Direct address mode 38
Data Sheet
260
2000-08-03
PEB 3086
PEF 3086
DIS_AW bit 206
DIS_IOM bit 206
DIS_OD bit 206
DIS_TR bit 182
DIS_TX bit 184
DPRIO bit 186
DPS bit 197, 204
DPS_CI1 bit 202
DPS_D bit 201
H
HA1/0 bits 232
HDLC controllers
Access to IOM channels 152
Data reception 139
Data transmission 147
Extended transparent mode 153
Interrupts 154
Receive frame structure 145
Test functions 155
Transmit frame structure 152
E
EA1 bit 176
EA2 bit 177
EAW bit 216
I
I/O lines 133
ICB bit 215
EL1/0 bits 192
Electrical characteristics 235
EN_B2/1R bits 199
EN_B2/1X bits 199
EN_BC2/1 bits 201
EN_BCL bit 206
EN_CI1 bit 202
EN_D bit 199, 201
EN_I0 bit 198
EN_I1 bit 198
ICD bit 215
ICV bit 185
ID register 220
Indirect address mode 38
INT_POL bit 220
INT1/0 bits 216
Intelligent NT 126
Interrupt input 134
Interrupt structure 40
IOM_CR register 206
IOM-2 93
EN_ICV bit 182
EN_MON bit 204
EN_O0 bit 198
Frame structure (LT) 95
Frame structure (NT) 95
Frame structure (TE) 94
Handler 96
Interface Timing 240
LT-S, LT-T, NT modes 93
Monitor channel 110
TE mode 93
EN_O1 bit 198
EN_SFSC bit 183
EN_TBM bit 198
ENS_TSSx bits 205
Exchange awake 43
EXLP bit 182
EXMB register 228
EXMD1 register 172
Extended transparent mode 153
External reset input 43
ISTA register 215
ISTAB register 223
ISTAD register 167
ISTATR register 190
ITF bit 172, 228
F
FBS bit 192
Features 18
FSYN bit 185
Functional blocks 31
J
Jitter 70
Data Sheet
261
2000-08-03
PEB 3086
PEF 3086
Error treatment 114
Handshake procedure 111
Interrupt logic 119
Master device 116
Slave device 117
L
L1SW bit 182
LA bit 232
LD bit 185, 190
LDD bit 182
Time-out procedure 118
Monitoring data 103
Monitoring TIC bus 103
MOR register 211
MOS bit 215
MOSR register 212
MOX register 211
MRC bit 213
LED bit 192
LED output 46
Level detection 64
Logic symbol 20
Looping data 99
LP_A bit 186
LT-T mode 126
MRE bit 213
M
MSTA register 214
MSTI register 209
MSYN bit 187
Multiframe sync timing 247
Multiframe synchronization 53
Multiframing 51
MAB bit 212
MAC bit 214
MASK register 216
MASKB register 224
MASKD register 168
MASKTR register 191
M-Bit synchronisation 53
MCDA register 211
MCDAxy bits 211
MCONF register 214
MDA bit 212
MXC bit 213
O
OD7-0 bits 192
OE7-0 bits 194
Oscillator 238
Oscillator clock output 71
OV bit 176, 230
Overview 14
MDR bit 212
MDS2-0 bits 171, 227
MER bit 212
MFEN bit 187, 188
MHA bit 174, 229
Microcontroller interface timing 243
Microcontroller interfaces 33
MIE bit 213
MLA bit 175, 229
MOCR register 213
MODE1 register 218
MODE2 register 220
MODE2-0 bits 191
MODEB register 227
MODED register 171
MON_CR register 204
Monitor channel
P
Package Outlines 251
Parallel microcontroller interface 38
PD bit 186
PDS bit 184
Pin configuration 22
PPSDX bit 220
R
RAB bit 177, 232
RAC bit 171, 227
RACI bit 169, 224
RAH1 register 229
Data Sheet
262
2000-08-03
PEB 3086
PEF 3086
RAH2 register 229
RAL1 register 231
RAL2 register 231
RBC11-8 bits 176, 230
RBC7-0 bits 175, 230
RBCHB register 230
RBCHD register 176
RBCLB register 230
RBCLD register 175
RCRC bit 172, 228
RDO bit 177, 232
Receive PLL 70
Register description 157
RES_xxx bits 221
Reset generation 42
Reset source selection 42
Reset timing 248
Transceiver enable/disable 64
Transmitter characteristics 59
SA1/0 bits 177
SAP1 register 174
SAP2 register 175
S-bus priority mechanism 124
SCI - serial control interface 34
SCI interface timing 243
SDS 107
SDS_CONF register 210
SDS2/1_BCL bits 210
SDSx_CR registers 205
Serial data strobe 107
SGD bit 184
SGP bit 184
Shifting data 99
SLIP bit 185
RFBS bits 172, 228
RFIFOB register 234
RFIFOD register 166
RFO bit 167, 223
RIC bit 190
Software reset 43
SPU bit 206
SQC bit 190
SQR1-4 bits 187
SQR21-24 bits 188
SQR31-34 bits 188
SQR41-44 bits 189
SQR51-54 bits 189
SQRR1 register 187
SQRR2 register 188
SQRR3 register 189
SQW bit 190
RINF bits 185
RLP bit 184
RMC bit 170, 226
RME bit 167, 223
RPF bit 167, 223
RPLL_ADJ bit 183
RRES bit 170, 226
RSS2/1 bits 218
SQX1-4 bits 188
RSTAB register 232
RSTAD register 177
SQX21-24 189
SQX31-34 bits 189
SQX41-44 bits 189
SQX51-54 bits 189
SQXR1 register 188
SQXR2 register 189
SQXR3 register 189
SRA bit 172, 228
SRES register 221
ST bit 215
S
S/G bit 128, 179
S/T-Interface 47
Circuitry 61
Coding 49
Delay compensation 63
External protection circuitry 61
Multiframe synchronization 53
Multiframing 51
STARB register 224
STARD register 169
State machine
Receiver characteristics 60
Data Sheet
263
2000-08-03
PEB 3086
PEF 3086
LT-S mode 81
NT mode 85
TE and LT-T mode 74
Transceiver enable/disable 64
Transformer specification 250
TSS bits 197, 205
STI bit 170
Typical applications 21
STI register 208
V
STIxy bits 208, 209
Stop/Go bit 128, 179
STOVxy bits 208, 209
Strobed data clock 107
Subscriber awake 43
SWAP bit 198
VALUE bits 174
VFR bit 177, 232
W
Watchdog timer 43
WOV bit 216
WTC1/2 bits 218
Synchronous transfer 104
T
X
TA bit 177
TBA2-0 bits 180
TDDIS bit 186
XACI bit 169, 224
XCRC bit 172, 228
XDOV bit 169, 224
XDU bit 167, 223
XFBS bit 172, 228
XFIFOB register 234
XFIFOD register 166
XFW bit 169, 224
XINF bits 186
TEI1 register 176
TEI2 register 177
Test functions 65
Test signals 156
TIC bus 122
TIC_DIS bit 206
Timer 44
Timer 1 45
Timer 2 45
XME bit 170, 226
XMR bit 167
TIMR1 register 174
TIMR2 register 222
TIN2/1 bits 216
XPR bit 167, 223
XRES bit 170, 226
XTF bit 170, 226
TLP bit 179, 233
TMB register 233
TMD bit 222
TMD register 179
TOUT bit 214
TR_CMD register 186
TR_CONF0 register 182
TR_CONF1 register 183
TR_CONF2 register 184
TR_CR register 199
TR_MODE register 191
TR_STA register 185
TR_TSDP_BC1/2 registers 197
TRAN bit 215
Data Sheet
264
2000-08-03
Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly
defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
idleness and wastefulness for all of us, more professional
success, more accurate information, a better overview and,
thereby, less frustration and more satisfaction.”
Dr. Ulrich Schumacher
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
相关型号：
PEF3452HV1.3
PCM Transceiver, 1-Func, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, METRIC, PLASTIC, QFP-44
INFINEON
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