PSB21525-H_技术文档

Contents

Page

Introduction ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .}

Quality Assurance . . . . . . . . . . . . . . . . . . . . . . . .

3

4

Package Information . . . . . . . . . . . . . . . . . . . . . 208

Summary of Types

in Alphanumerical Order . . . . . . . . . . . . . . . . . . . . 209

Mobile Communication ICs . . . . . . . . . . . . . . . .

GSM/PCN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF-Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . .

9

11

26

35

Microelectronics Training Center . . . . . . . . . . 215

Information on Literature ^{. . . . . . . . . . . . . . . . . .}219

Semiconductor Group – Addresses ^{. . . . . . . .}232

Digital Terminal ICs . . . . . . . . . . . . . . . . . . . . . . . 55

Digital Exchange System ICs . . . . . . . . . . . . . . 79

Analog Line Cards . . . . . . . . . . . . . . . . . . . . . . . . .

82

Digital Line Cards . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Primary Rate Interface (PRI) ICs . . . . . . . . . . . 125

Switching, Attenuation

and Conferencing Family ICs . . . . . . . . . . . . . . 141

Communication Network ICs ^{. . . . . . . . . . . . . . .}157

Asynchronous Transfer Mode (ATM) ICs ^{. . . . .}171

Development Systems

for Information Technology . . . . . . . . . . . . . . . . 185

IOM^®, IOM^®-1, IOM^®-2, SICOFI^®, SICOFI^®-2, SICOFI^®-4, SICOFI^®-4µC, SLICOFI^®, ARCOFI^®, ARCOFI^®-BA, ARCOFI^®-SP, EPIC^®-1,

EPIC^®-S, ELIC^®, IPAT^®-2, ITAC^®, ISAC^®-S, ISAC^®-S TE, ISAC^®-P, ISAC^®-P TE, IDEC^®, SICAT^®, OCTAT^®-P, QUAT^®-S are registered

trademarks of Siemens AG.

MUSAC^™-A, FALC^™54, IWE^™, SARE^™, UTPT^™, ASM^™, ASP^™, are trademarks of Siemens AG.

Purchase of Siemens I²C components conveys a license under the Philips’ I²C patent to use the components in the I²C-system provided the

system conforms to the I²C specifications defined by Philips. Copyright Philips 1983.

Siemens Aktiengesellschaft

1

Introduction

Siemens is THE allround-supplier of Communication ICs.

Siemens offers ICs for Digital Exchange Systems, Digital

Terminals, Data Transmission Analog and Networks, Mobile

Communications and Analog Telephone Sets.

Siemens is your partner for Communication ICs:

• Innovative complete system solutions

• Highly optimized devices

• Reliable volume production lines and advanced

technology innovation

• Technical support all over the world

• Long term experience and skilled expert teams

• Long term customer relationships

• Excellent quality

• Basic success factors for further innovations

– Experienced R+D team

Communication ICs from Siemens – that means innovative

and wide ranging problem solving. Siemens Semiconductor

Division has integrated system know-how verified by wide

field experience and excellent chip technology.

A short look to the product segment ISDN, demonstrates:

For the development of ISDN equipment from terminals to

PBX and public switching systems Siemens offers the

broadest range of ISDN chips available on the merchant

market. Siemens is the worldwide market leader for ISDN

ICs, due to their high level of functionality resulting in greatly

simplified system design.

– Device macros

– Design tools

– Technology

Due to the fact that Siemens offers a broad range of

Communication ICs the overview of the spectrum is

presented in this brochure.

In addition, the industry standard IOM-2 interface supports

flexible system architecture with compatible devices.

If you have further questions or if you need application

support, please contact your local Siemens office.

Addresses you will find in this brochure.

Siemens represents technology leadership, offers powerful

software and application tools.

Call Siemens – your partner for Communication ICs!

Siemens Aktiengesellschaft

3

Quality Assurance

Figure 1 and 2 show the most important stages of the QA

system. Quality assurance (QA) departments, independent

of production and development, are responsible for the

selected measures, acceptance procedures and information

feedback loops. Operating QA departments have state-of-

the-art test and measuring equipment at their disposal, work

according to approved methods of statistical quality control,

and are provided with facilities for accelerated life and

environmental tests used for both qualification and routine

monitoring tests.

1

Quality Assurance

The high quality and reliability of integrated circuits from

Siemens are the result of carefully managed design and

production which is systematically checked and controlled at

each stage.

The procedures are subject to a quality assurance system;

full details are given in the brochure “Quality Assurance

lntegrated Circuits”.

The latest methods and equipment for preparation and

analysis are employed to achieve continuity of quality and

reliability.

Specifications, Product Plan, Quality Requirements

Design Rules Check

Suitability of Technology

Estimate Reliability

Planning of Qualification

Release of Qualification

Program

Concept Release

Engineering Samples

Design, Optimization, (Redesign)

Specification met, Process frozen, Production Start

Preliminary Documentation

(Fab Instructions)

First Results of

Qualification Tests

Clearance for delivering

limited Quantities

Pre-Series Release

Production Reproducible

Lot Release, Reliability Monitoring

under QA Surveillance

Pre-Series Samples

and-Deliveries

Final Documentation (Data

Sheet, Fab Instruction)

Complete Qualification

Results

Clearance for unlimited

Deliveries

Series Release

Series-Samples

and-Deliveries

Series Production

ITA05872

Figure 1

Siemens Aktiengesellschaft

4

Quality Assurance

Quality Capability Audits

Suppliers

Parts, Materials

(Physical, Electrical)

Incoming

Inspection

SPC

Wafer Fabrication

Electrical/Optical Chip Testing

Testing Process Parameter

Visual Wafer Inspection

Process Audits

Physical Parameters Dim-

ensions, Geometries visual

recognizeable Failures

Wafer Lot

Clearence

SPC

Die Seperation Assembly,

Wire Bonding, Vis. Examination

before Encapsulation

Visual Chip Test

Die Attach

Wire Bond Strength

Process Audits

Visual Inspection

of bonded Chips

Assembly

Lot Clearance

SPC

Sealing/Molding

Cavity Packages; Hermeticity

Test Final Surface of Leads

Product Marking

Plastic Packages;

X-ray Test

Vis. Inspection Lead Surface

Process Audits

Screening (e.g. Burn-IN)

(If Specified)

Failure Analysis

of defective Parts

Final (Outgoing) Product Test

(Electrical/Mechanical)

Packing for Shipment

100% Performed

Sample Tests

Outgoing Inspection

Electrical Function,

Parameters Mechanical Data

Product

Lot Clearance

Performed by Quality

Assurance Department

Surveillance of Process

Steps and Equipment by SPC

Periodical

Reliability Monitoring

Product ready for Shipment

Stock, Shipping

ITA05873

Figure 2

Siemens Aktiengesellschaft

5

3.3 Reliability monitoring

2

Conformance

The general course of IC failure rate versus time is shown by

a so-called “bathtub” curve.The failure rate has its peak

during the first few operating hours (early failure period). After

the early failure period has ended, the “constant” failure rate

period starts during which the failures may occur at an

approximately uniform rate. This period ends with a repeated

rise of the curve during the wear-out failure period. For ICs,

however, the latter period usually lies far beyond the service

life specified for the individual equipment. Reliability tests for

ICs are usually destructive examinations. They are,

therefore, carried out with samples. Most failure mechanisms

can be accelerated by means of higher temperatures. Due to

the temperature dependence of the failure mechanisms, it is

possible to simulate future operational behavior within a short

time by applying high temperatures; this is called life test. The

acceleration factor F for the life test can be obtained from

Arrhenius’s equation

Each integrated circuit is subjected to a final test at the end of

the production process. These tests are carried out by

computer-controlled, automatic test systems as hundreds of

thousands of operating conditions as well as a large number

of static and dynamic parameters have to be considered.

Moreover, the test systems are extremely reliable and

reproducible. The quality assurance department carries out a

final check in the form of a lot-by-lot sampling inspection to

additionally ensure the minimum percent defectives to

ensure statistically that the PDA of released lots is less than

the AQL agreed. Sampling inspection is performed in

accordance with the inspection plans of DIN 40080, as well

as of the identical MIL-STD-105 or IEC 410.

3

Reliabilitiy

E_A

------

k

1

F = exp

----- – -----

T ₁T ₂

3.1 Measures taken during development

The reliability of ICs is already considerably influenced at the

development stage. Siemens has, therefore, fixed certain

design standards for the development of circuits and layout,

e.g. specifying minimum width and spacing of conductive

layers on a chip, dimensions and electrical parameters of

protective circuits for electrostatic charge, etc. An

examination with the aid of carefully arranged programs

operated on large-scale computers guarantees the

immediate identification and elimination of unintentional

violations of these design standards.

where T₂is the temperature at which the life test is

performed, T₁is the assumed operating temperature and

k is Boltzmann’s constant.

Important for factor F is the activation energy E_A. It lies

between 0.3 and 1.3 eV and differs considerably for

individual failure mechanisms.

For all Siemens ICs the reliability data from life tests is

converted to an operating temperature of T_A= 55 °C,

assuming an average activation energy of 0.5 eV. The

acceleration factor for life tests at 125 °C is thus 22,

compared with operational behavior. This method considers

also failure mechanisms with low activation energy, i.e. which

are only slightly accelerated by the temperature effect.

3.2 In-process control during production

The manufacturing of integrated circuits comprises several

hundred production steps. As each step is to be executed

with utmost accuracy, the in-process control is of outstanding

importance. Some processes require more than a hundred

different test measurements. The tests have been arranged

such that the individual process steps can be reproduced

continuously.

Various reliability tests are periodically performed with IC

types that are representative of a certain production line this

is described in the brochure “Quality Assurance Integrated

Circuits”. Such tests are e.g. humidity test at 85 °C and 85 %

relative humidity, pressure cooker test, as well as life tests up

to 1000 hours and more. Test results are available in the form

of summary reports.

The decreasing failure rates reflect the never ending effort in

this direction; in the course of the years they have been

reduced considerably despite an immense increase in IC

complexity.

Siemens Aktiengesellschaft

6

Quality Assurance System

Quality Assurance Manual

Quality principles, organization, responsibility and

competence for quality assurance procedures and measures

during design and production of ICs are summarized in the

Semiconductor Group Quality Assurance System. This

system also covers

ISO 9000/EN 29000 requirements. It is documented in a

Quality Assurance Manual. This manual is a guideline

mandatory for all Semiconductor Group departments.

Suppliers are also tied into the QA system.

CECC certification for the independent test and trials center of Semiconductor Group,

which the Villach Plant also profits from.

The Villach Plant was certified to the internationally recognized standard ISO 9002 in 1991.

Siemens Aktiengesellschaft

7

Mobile Communication ICs

GSM One-Chip Logic Device

GOLD PMB 2705

Siemens Aktiengesellschaft

9

GSM/PCN

Introduction

Siemens Semiconductor has played a leading role in this

GSM and PCN have evolved in the last few years from

pan-european into global standards for digital cellular mobile

radio systems. The radios are small, easy-to-use and very

competitively priced with the older analog systems as the

explosive growth in subscribers clearly testifies.

growth as the first supplier of commercially available

standard GSM/PCN chip sets. Now after production

standard GSM/PCN chip sets. Now, after production

optimizations of the GOLD chip set, Siemens is offering an

evolutionary step forward in intergration level to provide a

evolutionary step forward in integration level to provide a

complate 3-V generation with a 6 chip solution, GOLD plus.

complete 3-V generation with a 6 chip solution, GOLD plus.

Product Overview

Type

Short Title

Description

Applications

Page

GSM Baseband

PMB 2705

PMB 2706

PMB 2707

PMB 2708

GOLD

GSM One-Chip Logic Device

GSM System Controller

GSM Signal Processor

GSM, PCN, PCS-1900

14

16

18

GOLD µC

GOLD-SP

GOLD-SX

GSM Co-Processor for Advanced

Features

PMB 2900

PMB 2905

GBBC

GAIM

GSM Baseband Codec

GSM, PCN, PCS-1900

19

20

GSM Analog Interface Module

GSM RF

PMB 2200

Direct Vector Modulator

Cellular (GSM, PDC, DAMPS, CDMA),

WLAN, QPSK/QAM modulation up to 1 GHz)

37

41

PMB 2205

Cellular (GSM, PCN, PCS, PDC, DAMPS,

CDMA), Cordless (PHS), WCPE, WLL,

WLAN, QPSK/QAM modulation

PMB 2240

PMB 2245

GSM Transmitter, 2.7 V

PCN Transmitter, 2.7 V

Cellular (GSM, PDC); QPSK/QAM modulation 21

0.8 GHz to 1.0 GHz

Cellular (PCN, PCS), Cordless (PHS);

QPSK/QAM modulation 1.65 GHz to

1.85 GHz

21

PMB 2247

PMB 2306

PMB 2401

PMB 2405

PMB 2407

PCS Transmitter, 2.7 V

PLL

Cellular (PCN, PCS), Cordless (PHS);

QPSK/QAM modulation 1.8 GHz to 1.95 GHz

21

All analog and digital systems as RF- and IF- 47

synthesizer up to 220 MHz

Receiver/Demodulator Circuit

GSM Receiver, 2.7 V

PCN/PCS Receiver, 2.7 V

Cellular (GSM, PDC, DAMPS, CDMA),

WLAN, QPSK/QAM modulation up to 0.9 GHz

43

23

Cellular (GSM, PDC, DAMPS), WLAN,

QPSK/QAM modulation up to 2.5 GHz

Cellular (PCN, PCS) WLAN, QPSK/QAM

modulation up to 2.5 GHz

Siemens Aktiengesellschaft

11

Mobile Communication ICs

SAW

1F

900 MHz /

1.8 GHz

GP-DSP

GOLD PMB 2705

GBBC PMB 2900

Baseband

PMB 2401

Ι

Voiceband

D

A

Channel

Decoder

Speech

Decoder

D

Q

A

LO

A

D

Hard"

CGY60 /

BEP420

"

RF Synth.

PMB 2306

LO

IF Synth.

RF VCO + Presc.

RF-PLL

Baseband

D

A

Ι

Voiceband

A

D

BAR63 +

BAR80

Channel

Encoder

Speech

Encoder

GMSK

Q

Out.

Stage

D

A

4144-3015

CGY120 +

CGY92

PMB 2200 / 05

PA Control

1

4

7

2

5

8

0

3

6

9

#

Control

1

4

7

2

5

8

0

3

6

9

D

A

*

System Interface

RF Control

GSM

SAB

80C166

SIM

Card

*

E²PROM

Flash

RAM

ITB05946

Block Diagram of a GSM Handy Phone (1st Gen.)

Siemens Aktiengesellschaft

12

Mobile Communication ICs

GAIM (PMB 2905)

GOLD-SP (PMB 2707)

SAW

1F

900 MHz /

1.8 GHz

PMB 2405/2407

Voiceband

Baseband

Ι

A

Speech &

Channel

Decoder

Soft"

Equa-

lizer

D

A

"

LO

LNA

Q

A

D

RF-PLL

PMB 2307

RF Synth.

LO

Voice Band Filters

Voiceband

BAR63 +

BAR80

Baseband

D

A

RF VCO + Presc.

IF Synth.

Ι

Speech &

Channel

Encoder

4144-3015

A

GMSK

D

Out.

Stage

Q

D

A

1

4

7

2

5

8

0

3

6

9

#

PA Control

CGY120 +

CGY92

*

PMB 2240 / 45

RF Control

D

A

GSM

Control

1

4

7

2

5

8

0

3

6

9

System Interface

SAB 80C166

SIM

*

Card

GOLD-µC (PMB 2706)

2

E PROM

Flash

RAM

ITB05945

Block Diagram of a GSM/PCN Fullrate & Halferate Mobile

Siemens Aktiengesellschaft

13

GSM One-Chip Logic Device (GOLD)

PMB 2705

General Description

Type

Package

P-TQFP-176-1 (SMD)

The GSM One-Chip Logic Device (GOLD) PMB 2705

performs the tasks of bit error protection, ciphering, radio

channel equalization, bit error detection and correction,

synchronization etc., and above all the microcontroller core

controls all the RF- and baseband functions of a GSM-mobile

terminal.

PMB 2705-F

• Four single modes selectable via pins

– Controller test mode

– System interface test mode

– Channel-codec test mode

– Equalizer test mode

• Two sizes of address spaces covered by chip-select

signals selectable via pin:

Features

• Four function modules integrated on one chip

– 16-bit microcontroller

– Channel codec

– Equalizer

– System interface

• One special external-channel-codec mode selectable by

software

• Four operational modes selectable via pins:

– Normal mode

– External-controller mode

– External-channel-codec mode (different from special

mode!)

– 256 Kbyte

– 2 Mbyte

• Programmable power saving modes

• JTAG-boundary scan (acc. to IEEE Std. 11491)

• Single supply voltage (+ 5 V)

• Low power consumption

• Temperature range – 25 °C to 85 °C

– External-equalizer mode

Siemens Aktiengesellschaft

14

GSM One Chip Logic Device (GOLD)

PMB 2705

FCBDET_SP

ADC ADC & TB

4

KB (9:6)

6

FCBDET_EO

KB (5:0)

CSEO

CLKEO

MONON

EOON

SYNDAT

SYNCLK

SYNSTR

AGC 1

AGC 2

APC

Equalizer

RESET

DSP

Interface

EQCLK

EQVAL

WIN

PADAT

PACLK

PASTR

DY1

1

EQDAT 2

SPDO

SPVALD

SPCLK

EOCLK

RXON

RXON 1

OCE

TXON

DYI

CSD

CLKD

Channel

Decoder

CCIN

CCIO

INTEQ

EOON

8

System

Interface

CCLK

SPVALU

SPDU

CCRST

CCVZ

RD

WR

TXMASK

CCVZQ

CLKANA

CSDSP

CLKDSP

MOT

TMSK

YCL

CYI

IDAC

QDAC

TSTR

Channel

Encoder

CSC

CLKC

CODON

DAC (9:0)

CODON

2

RESET

CSE PROM

INTC

RESET

CHC_INT

TM_INT

CSRAM

CSEPROM 1

CSEPROM 2

SELCLK

CHC_INT

TM_INT

0

1

6

5 7

11

15

3

Port 2

P2

P3

RD

WR = P3, T3

WR

Port 3

Port 5

CLK 26 MHz

OSCCTRL

SIN 13 MHz

V_REF

5

16

8

Port 4

P5

EBC 1

Port 1

Port 0

EBC 0

BUSACT

ALE

CLKPR

Embedded

SAB 80C166

RSTOUT

NMI

HW_PWDN

SW_

PWDN

CLK 4 MHz

XTAL 1

XTAL 2

Oscillator

5

16

RESET

WR

RD

P4 P1

D

4

Block Diagram

TMS TCK TDI TDO MODE MUXBUS RESET ITB05947

Siemens Aktiengesellschaft

15

GOLD System Controller (GOLD-

µC)

PMB 2706

General Description

Type

Package

P-TQFP-144-2 (SMD)

The GOLD System Controller (GOLD-µC) is part of a chip

set, which covers all functions of a mobile radio provided for

the Global System for Mobile communications, GSM. A

mobile terminal which contains this chip set will meet all

performance requirements set down in the GSM

PMB 2706-F

Features

• Integrated 16-bit microcontroller (SAB 80C166) with

2-Mbyte linear address space

recommendations for speech and data services.

Complete development tooling available

• System interface with synthesizer, AGC, AFC and PA

control, chip card interfacing, timing signal generation,

clock generation

GOLD-µC contains a 16-bit microcontroller type 80C166 with

an address space being extended from 256 Kbyte to 2 Mbyte

and a system interface block which comprises a series of

GSM-specific interfaces and control functions.

• Bidirectional tristate buffer

GOLD-SP can access to controller memory

• Package P-TQFP-144, 20 × 20 mm, 0.50 mm pitch

• 3-V supply voltage (± 10 %)

RF Components

General

Purpose Ports

Chip

Card

System

Interface

SAB 80C166

Microcontroller

8 Bit

Data

16 Bit

Data

21 Bit Address & 16 Bit Data Bus

Address &

Data Ports

Tristate Buffer

GOLD-SP

ITB06063

Block Diagram

Siemens Aktiengesellschaft

16

GOLD Signal Processor (GOLD-SP)

PMB 2707

General Description

Type

Package

P-TQFP-100-1 (SMD)

The GOLD Signal Processor (GOLD-SP) is part of a chip

set, which covers all functions of a mobile radio provided for

the Global System for Mobile communications, GSM.

A mobile terminal which contains this chip set will meet

all performance requirements set down in the GSM

recommendations speech and data services.

PMB 2707-F

Features

• Two parallel DSP cores type SPC

each with high performance (26 MIPS @ 2.7 V), low

current consumption (< 1 mA/MlPS), all memory

needed for fullrate operation on chip, shared access to

complete controller memory

• GSM functions realized as DSP firmware

– Complex soft-output equalizer

GOLD-SP contains a fullrate speech codec, a channel codec

with soft-decision decoding and a complex Viterbi equalizer,

all as DSP firmware. Moreover all digital filtering needed for

baseband and voiceband processing, and also GMSK

modulation is performed on this chip.

– Frequency correction burst handling

– Full duplex handsfree

– Channel coding

– Soft-decision decoding (bit-by-bit)

– Speech coding and decoding (RPE-LTP)

• Digital baseband filter

Automatic amplitude calculation

Automatic amplitude offset measurement

• Ciphering with A51/A52

• Digital voiceband filters (receive, transmit)

• GMSK modulator

• PLL-based system clock generation

• Package: P-TQFP-100, 14 × 14 mm, 0.50 mm pitch

• 3-V supply voltage (± 10 %)

Ciphering

Base

Band

Voice

Band

Voice

Band

DAC

Channel

Decoder

"Soft"

Base-

Band

ADC

Speech

Decoder

Equalizer

"Soft"

Voice

Band

Voice

Band

ADC

Base-

Band

DAC

Speech

Encoder

Channel

Encoder

Burst B

GMSK

ITB06064

Block Diagram

Siemens Aktiengesellschaft

17

GSM Co-Processor for Advanced Features (GOLD-SX)

PMB 2708

General Description

Type

PMB 2708-F

Package

P-TQFP-64-1 (SMD)

The GOLD-SX is part of a complete chip set which covers all

functions of a mobile radio for the Global System for Mobile

communications, GSM. A mobile terminal which contains this

chip set can meet all performance requirements set down in

the Technical Specifications for GSM, PCN and PCS-1900.

– Comfort noise generation, DRX (GSM 6.22)

– Serial data exchange with Half-Rate Channel Codec

and voiceband unit on GOLD-SP

– Serial data exchange with system simulator interfacing

box

GOLD-SX is used for advanced features. The function of the

GOLD-SX is dependent on its firmware.

The first version of the GOLD-SX performs Half-Rate speech

encoding including Voice Activity Detection (VAD) and

Discontinuous Transmission (DTX), as well as Half-Rate

speech decoding including Discontinuous Reception (DRX,

Comfort Noise).

• Enhanced Full-Rate Codec

– GSM Enhanced Full-Rate Codec

– Voice activity detection, VAD

– Discontinuous transmission, DTX

– Comfort noise generation, DRX

– Serial data exchange with Enhanced Full-Rate Channel

Codec and voiceband unit on GOLD-SP

– Serial data exchange with system simulator interfacing

box

A planned version will perform: Enhanced Full-Rate speech

coding including all the DTX functions as in Half-Rate speech

coding.

Features

Hardware:

Firmware:

• DSP core of type SPCE (Siemens Signal Processor Core

Enhanced) offering high performance

(39 MIPS @ 39 MHz, 2.7 V) and current consumption

(approx. 0.6 mA/MIPS)

• 12 K Program ROM and 0.25 K RAM, 8 K Data ROM

on-chip

• PLL-based clock generation (13-MHz input)

• Package: P-TQFP-64, 10 × 10 mm², 0.50 mm pitch

• 3-V supply voltage (± 10 %)

The GOLD-SX is available in versions with different mask

programmed ROM code:

• Half-Rate Codec

– GSM Half-Rate Speech Codec

(GSM 6.02, 6.06, 6.07, 6.20)

– Voice activity detection, VAD (GSM 6.42)

– Discontinuous transmission, DTX (GSM 6.41)

Prog.

ROM

12 K

Prog.

RAM

0.25 K

Data

ROM

8 K

XRAM

2 K

YRAM

2 K

Program

Data

Signal

Processor

Core

Test

Select

39 MHz

PLL Clock Unit

SIF 1

SIF 2

Bound.

Scan

13 MHz

9.75 MHz

6.5 MHz

to GOLD-SP to DAI Test Box

ITB08488

Block Diagram

Siemens Aktiengesellschaft

18

GSM Baseband Codec (GBBC)

PMB 2900

Preliminary Data

Overview

Type

Package

P-MQFP-64-1 (SMD)

PMB 2900-H

The GSM Baseband Codec (GBBC) performs the analog-to-

digital and the digital-to-analog conversion of the baseband

signals and additionally the digital-to-analog conversion of

the control signal provided for the RF power amplifier.

General Features

• JTAG-boundary scan (acc. to IEEE Std. 1149.1)

• Single supply voltage (+ 5 V)

• Ambient temperature range – 25 °C to 85 °C

GBBC is part of a chip set, which covers the functions of a

mobile radio provided for the Global System for Mobile

communications, GSM. A mobile terminal which contains this

chip set will meet all performance requirements set down in

the GSM recommendations.

CLKANA

WIN

OCE

TMS

TCK

TDI

13 MHz

÷ 6

2.166 MHz

cos

TDO

Prefilter

Ι

16

9

IR

9 Bit

Window

Offset

Counter

ADCSTB

Σ∆

+

-

8

4

Buffer

ADC (3:0)

Analog

Digital

Q

16

9

QR

9 Bit

Window

Offset

Counter

Σ∆

RXON

sin

IDAC

Logic

Latch

TSTR

10 Bit DAC

QDAC

Postfilter (6th ord.)

10

IT

Pup

Logic

10

(SC Technique)

Digital

Postfilter (6th ord.)

DAC (9:0)

TXON

QT

Pup

Logic

10 Bit DAC

(SC Technique)

Latch

CLKANA

Analog

S & H

Clock

PASTR

PACLK

8

Sample

& Hold

8 Bit DAC

(R String)

8 Bit

Register

PAOUT

Latch

PADAT

ITB05948

V

REFEXT

BIAS

V_REF

Block Diagram

Siemens Aktiengesellschaft

19

GSM Analog Interfacing Module (GAIM)

PMB 2905

General Description

Type

Package

P-TQFP-64-1 (SMD)

The GSM Analog Interfacing Module (GAIM) is part of a chip

set, which covers all functions of a mobile radio provided for

the Global System for Mobile communications, GSM. A

mobile terminal which contains this chip set will meet all

performance requirements set down in the GSM

PMB 2905-F

Features

• Baseband receive A-to-D converter

analog antialiasing filter (2nd order Bessel)

2nd order sigma-delta modulators for

baseband receive and battery measurements

• Baseband transmit D-to-A converter

10 bit switched-capacitor-type DAC

analog postfilter (6 th order Bessel)

• Power ramping control D-to-A converter

8-bit resistor-string-type DAC

recommendations for speech and data services.

GAIM is provided for analog-to-digital and digital-to-analog

conversion of baseband and voiceband signals as well.

Moreover digital-to-analog conversion of an RF power

control signal can be performed by this circuit.

• Voiceband receive D-to-A converter

low pass filter following

digital Σ-∆-modulator on GOLD-SP

two programmable earpiece gain stages

• Voiceband transmit A-to-D converter

2nd order sigma-delta modulator analog

antialiasing filter two programmable

microphone gain stages

• Package

P-TQFP-64-1, 10 × 10 mm, 0.5 pitch

• 3-V supply voltage (± 10 %)

RF

Modulator

PA

Module

Micro

Phones

Loud

Speakers

Battery

Switch

Battery

Switch

Demodulator

Ι

Q

Ι

Q

DAC DAC

Latches

DAC

ADC ADC

Latch

ADC

DAC

Baseband

Filters

GMSK

Modulators

PA

Control

Voiceband

Filters

ITB08458

Block Diagram

Siemens Aktiengesellschaft

20

GSM Transmitter

PCN Transmitter

PCS Transmitter

PMB 2240 ^B6HF

PMB 2245^B6HF

PMB 2247^B6HF

General Description

Type

Package

The PMB 2240, 2245, 2247 family are single-chip

transmitters which include a prescaler for the RF-oscillator

signal and a fixed PLL for the IF-oscillator signal. The

transmitter family is designed for use in combination with the

single-chip receiver family PMB 2405, 2407 and the PLL

PMB 2307 for mobile telephones according to the GSM, PCN

and PCS standards and other vector modulated digital

systems. It is fabricated using Siemens B6HF silicon

process:

PMB 2240-F

PMB 2245-F

PMB 2247-F

P-TQFP-48-1 (SMD)

Application

• Vector modulated cellular and cordless systems:

• PMB 2240: GSM, PDC, DAMPS

• PMB 2245: PCN, PCS, PHS

GSM Chipset

PMB 2240

PMB 2405

PMB 2307

PCN Chipset

PMB 2245

PMB 2407

PMB 2307

PCS Chipset

PMB 2247

PMB 2407

PMB 2307

• PMB 2247: PCN, PCS, etc.

• Various modulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK etc.

• Analog systems with FM- and AM modulation

• Space and power saving optimizations of existing discrete

transmitter circuits

TX

RX

PLL

The PMB 2240/45/47 transmitters include the active

Features

structures for the main oscillator circuit. Alternatively the

oscillator signal can be supplied from an external source. The

oscillator signal is buffered for off-chip use.

• Transmitter with I/Q modulator

• Direct I/Q modulation

• Generation of orthogonal carriers with possibility of phase

adjust with external resistors

• 30-dB carrier rejection, 40-dB SSB rejection

• 48-dB rejection of third order products with 500-mVpp

I/Q-drive level

• High output power with appropriate power matching

network at 500-mVpp I/Q-drive level

PMB 2240: – 3 dBm, PMB 2245: – 6 dBm

PMB 2247: – 8 dBm

• Integrated active part of RF oscillator

• Possibility to use external RF-oscillator signal

• The RF-oscillator signal is buffered for off-chip use,

especially for receiver PMB 2405/07

• Prescaler for the RF-oscillator signal

• Possibility to use the IF oscillator integrated on the

PMB 2405/07

There is a prescaler by 64/65 for the RF-oscillator signal on

chip, which can be used to implement the PMB 2307 PLL

circuit.

The on-chip FIX-PLL consists of the system clock divider, the

IF-oscillator signal divider, the phase detector and the charge

pump. The IF-oscillator signal divider is driven by the

oscillator on the PMB 2405/07 or by an external discrete

VCO. The IF-oscillator signal divider ratio of PMB 2240 and

PMB 2245 is fixed. It can be selected either divided by 1 or by

3 using PMB 2247 and PMB 2407 to drive the FIX-PLL with

two IF frequencies (450 MHz or 150 MHz) to avoid spurious

problems for PCS application.

The two oscillator signals (IF and RF) are combined in the

transmit mixer, and the image sideband and other mixing

products are to be suppressed by an external interstage filter.

The filtered signal reenters the chip at the modulator inputs.

The modulator generates two orthogonal carriers which are

mixed with the I- and Q modulation signals by two multipliers.

The phase between the two carriers can be fine-adjusted to

90° (orthogonality) by two external resistors for maximum

SSB suppression. The outputs of the multipliers are added

and amplified by a linear output stage.

• Possibility to use external IF-oscillator signal

• Fixed IF frequency PLL (FIX-PLL) for IF-VCO (PMB 2240,

2245), switchable IF PLL working at 450-MHz or 150-MHz

IF frequency (PMB 2247)

• Supply voltage range 2.7 to 5.5 V

• P-TQFP-48 package

• Temperature range – 30 °C to 85 °C

Siemens Aktiengesellschaft

21

GSM Transmitter

PCN Transmitter

PCS Transmitter

PMB 2240 ^B6HF

PMB 2245 ^B6HF

PMB 2247 ^B6HF

Baseband D/A

880 ... 915 MHz

Q

% 2

x 2

880 ...

915 MHz

% 2

% 492

13 MHz

Phase

Det.

1126 ... 1206 MHz

RF-

System

Clock

% 13

% 64

% 65

V

CO

Ι

PMB 2240

CLK DA EN

PLL

P-TQFP-48

164 MHz

13 MHz

System Clock

PMB 2307

P-TSSOP-16

925 ...

960 MHz

246 MHz

Q

925 ... 960 MHz

Base-

band

A/D

IF-

% 1

% 2

V

CO

492 MHz

3 Wire Bus

Data Register

PMB 2405

Ι

ITB08463

P-TQFP-48

GSM Application PMB 2240 / PMB 2405 / PMB 2307

Siemens Aktiengesellschaft

22

GSM Receiver

PCN/PCS Receiver

PMB 2405 ^B6HF

PMB 2407 ^B6HF

General Description

Type

Package

The PMB 2405, 2407 family are single-chip double-

conversion heterodyne receivers with LO-phase shifting

circuitry for the I/Q-phase demodulation on chip. It also

includes a switchable low noise amplifier, the second local

oscillator with a VCO output buffer, a programmable gain

controlled IF amplifier, two differential operational amplifiers

for base band signal filtering and a power-down circuitry.

PMB 2405-F

PMB 2407-F

P-TQFP-48-1 (SMD)

Applications

• Vector modulated cellular and cordless systems:

PMB 2405: GSM, PDC, DAMPS,

The receiver family is designed for use in combination with

the single chip transmitter family PMB 2240, 2245, 2247 and

the PLL PMB 2307 for mobile telephones according to the

GSM, PCN and PCS standards and other vector modulated

digital systems. It is fabricated using Siemens B6HF silicon

process.

PMB 2407: PCN, PCS (DCS1900), WLAN etc.

• Various demodulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK

• Space and power saving optimizations of existing discrete

demodulator circuits

Features

GSM Chipset

PMB 2405

PMB 2240

PMB 2307

PCN Chipset

PMB 2407

PMB 2245

PMB 2307

PCS Chipset

PMB 2407

PMB 2247

PMB 2307

• Heterodyne receiver with demodulator

• On-chip, low noise amplifier (LNA),

• Demodulation and generation of I/Q components

• Low mixer noise 9 dB (SSB)

• High input intercept point + 2 dB

• Integrated phase shifter

RX

TX

PLL

• IF amplifier with 80 dB programmable gain control (PGC)

in steps of 2 dB

• On-chip second LO oscillator with external tuning circuit or

possibility to use it as amplifier

• Two differential operational amplifiers for use as base

band filter or amplifier

• Low power consumption due to highly flexible power-down

capability

• Wide input frequency range up to 2.5 GHz

• Wide IF range from 40 MHz to 300 MHz

• Supply voltage range 2.7 to 4.5 V

• P-TQFP-48 package

The input signal is amplified by the internal LNA and filtered

by an external filter. The filtered signal and the first local

oscillator signal LO1 are mixed down to an intermediate

frequency (IF). The amplification of the IF signal is performed

by a digitally programmable gain-controlled amplifier.

The second local oscillator signal LO2 is generated either by

an on-chip oscillator or by an external VCO. The internal LO2

signal is fed to a divider (PMB 2405-by 1; 2407-by 1 or 3) and

then to a buffered output and also to a divider, which

generates orthogonal signals at half the VCO frequency. The

filtered IF signal re-enters the chip at the IF input, where it is

amplified and converted to the final output frequency with

each of the orthogonal signals. The resulting in-phase and in-

quadrature signals pass through differential output drivers.

• Temperature range – 30 °C to 85 °C

Two differential operational amplifiers can be used as active

baseband filters. At both outputs the differential offset is

sensed via the sample and hold circuitry. A feedback loop

corrects the remaining offset error below the tolerable input

value of the GAIM PMB 2905 or any other baseband A/D

converter.

Siemens Aktiengesellschaft

23

GSM Receiver

PCN/PCS Receiver

PMB 2405 ^B6HF

PMB 2407 ^B6HF

Baseband D/A

1850 ... 1910 MHz

Q

% 10

x 2

1850 ...

1910 MHz

% 2

% 450

13 MHz

System

Clock

% 150

Phase

Det.

1700 ... 1765 MHz

RF-

% 64

% 65

% 13

V

CO

Ι

PMB 2247

CLK DA EN

P-TQFP-48

13 MHz

System Clock

PLL

RX 450 MHz

TX 150 MHZ

PMB 2307

P-TSSOP-16

1930 ...

1990 MHz

225 MHz

Q

1930 ... 1990 MHz

Base-

band

A/D

IF-

% 1

% 3

% 2

V

CO

450 MHz

3 Wire Bus

Data Register

PMB 2407

Ι

ITB08464

P-TQFP-48

PCS Application PMB 2247 / PMB 2407 / PMB 2307

Siemens Aktiengesellschaft

24

GSM Receiver

PCN/PCS Receiver

PMB 2405 ^B6HF

PMB 2407 ^B6HF

Baseband D/A

1710 ... 1785 MHz

Q

% 1

x 2

1710 ...

1785 MHz

% 2

% 164

13 MHz

Phase

Det.

1546 ... 1634 MHz

RF-

System

Clock

% 64

% 65

% 13

V

CO

Ι

PMB 2245

CLK DA EN

PLL

P-TQFP-48

164 MHz

13 MHz

System Clock

PMB 2307

P-TSSOP-16

1805 ...

1880 MHz

246 MHz

Q

1805 ... 1880 MHz

Base-

band

A/D

IF-

% 3

% 2

V

CO

492 MHz

3 Wire Bus

Data Register

PMB 2407

Ι

ITB08465

P-TQFP-48

PCN Application PMB 2245 / PMB 2407 / PMB 2307

Siemens Aktiengesellschaft

25

DECT (Digital European Cordless Telecommunication)

Introduction

As the first supplier worldwide, Siemens Semiconductor

offers a complete highly integrated DECT system solution

which covers baseband processing as well as the RF front

end. The Siemens’ solution for the DECT mobile station cuts

down component count of first generation design from more

than 500 parts to less than 200 components and saves cost,

board space and power. Besides solutions for DECT home

terminals and handheld systems, solutions are provided for

cordless key systems, cordless PBX and wireless local loop

applications, too.

DECT is the coming Digital European Cordless

Telecommunication standard which has been defined for a

wide range of different applications. It meets the

requirements of cordless equipment users of home

applications, of the office environment (e.g. cordless PBX)

and of public use as wireless local loop.

DECT is the result of teamwork between industry,

administration and service providers from all over Europe. It

will be introduced in all EU countries and has high potential to

be accepted as a standard also outside Europe.

Product Overview

Type

Description

Applications

Page

DECT Baseband

PMB 27201/2 DECT Baseband Controller for Handhelds

PMB 27251/2 DECT Baseband Controller for Basestation

28

29

30

31

32

PMB 2727

PMB 2728

PMB 2920

DECT Burst Mode Controller for PBX

DECT Burst Mode Controller and ADPCM Codec for Keys Systems

DECT Baseband Analog IC

DECT RF

PMB 2220

PMB 2306

DECT Transmitter, 3 V

PLL

Cordless (DECT); FSK modulation

33

All analog and digital systems as RF- and 47

IF synthesizer up to 220 MHz

PMB 2420

DECT Receiver, 3 V

Cordless (DECT), FSK modulation

34

Siemens Aktiengesellschaft

26

DECT (Digital European Cordless Telecommunication)

Keypad

Display

E PROM

PMB 27201 / 2

PMB 2220

2

Gau.

Filter

Burst

Encoding

T

Power Amp

V

CO

f

2

*

µC

Speech

Encoding

A

D

R

V

CO

Ringer

RAM

ROM

Presc.

DSP

ADPCM

PMB

2920

Shunt Diodes

Speech

Decoding

D

A

LCD

Driver

PLL

Loop

PMB 2306

Filter

Burst

Decoding

SAW

Filter

PMB 2420

4144-3015

RSSI

1

4

7

2

5

8

0

3

6

9

#

LNA

Com-

para.

De-

mod.

*

DECT

ITB08459

RF

Baseband

DECT System Solution

Siemens Aktiengesellschaft

27

DECT Digital Circuit for Handhelds

PMB 27201/2

General Description

Type

Package

P-TQFP-128-1 (SMD)

The DECT-Digital Circuit for Handhelds is one of the devices

of the Siemens chip set for the digital cordless telephone

specified by the DECT standard.

PMB 27201/2

Features

The device designed for cordless handhelds is a highly

integrated circuit and realizes most of the system functions

needed in such an equipment.

• 8-bit µC with integrated ROM/RAM

• Integrated LCD controller

• 32-kbit/s ADPCM-transcoder

• Digital filtering and gain stages

• Burst mode controller

• Power-down mode programmable

• Low voltage detection

• Power supply 3.0 … 5.1 V

• Low power consumption

• Advanced low power CMOS technology

• Encryption

• PMB 27201: 64 K ROM, 4 K RAM

• PMB 27202: 48 K ROM, 2 K RAM

The circuit contains a digital signal processor, an 8-bit

80C51-compatible microcontroller and the burst mode

controller. Furthermore the circuit handles the interfacing of

the different components of the DECT chipset and feature

LCD controller.

The device is fabricated using Siemens advanced CMOS

technology and will be available in a 128 pin package.

Further baseband controllers are PMB 27221 (romless

version with 4 K RAM).

Data Port

(32 kbit/s)

Crystal 10.368 MHz

Timers /

RF-Interf.

Synchro-

nization

Clocks

DSP

Input Data RAM

Control RAM

Serial In

CRC

De-

scramble

Interpolation

Decimation

ADPCM

Trans-

coder

Speech Data

(PMB 2920)

Codec

Filter

TDMA Data

1.152 Mbit/s

Output Data RAM Serial Out

Control RAM CRC

Scramble

Burst-Error-Concealment

Tone Generation

Encryption

Decryption

Burst-Mode-Logic

Power

Control

RSSI

Battery

Control

Internal ROM

48 kBytes

Port X

Keypad

Port Y

Keypad

Port 0

Addit.

D

A

Timers

2

8-Bit CPU

LCD-Drivers

Interrupts

I C Bus

Internal RAM

2 kBytes

Watchdog

Microcontroller Unit

ITB08460

Block Diagram PMB 27202

Siemens Aktiengesellschaft

28

DECT Digital Circuit for Basestations

PMB 27251/2

General Description

Type

Package

P-TQFP-128-1 (SMD)

The DECT-Digital Circuit for Basestations is one of the

devices of the Siemens chip set for the digital cordless

telephone specified by the DECT standard.

PMB 27251/2

Features

The device designed for single cordless fixed stations is a

highly integrated circuit and realizes most of the system

functions needed in such an equipment. The circuit contains

a digital signal processor, an 8-bit 80C51-compatible

microcontroller and the burst mode controller. Furthermore

the circuit handles the interfacing of the different components

of the DECT chipset.

• 8-bit µC with integrated ROM/RAM

• 32 bit/s ADPCM-transcoder

• Digital filtering and gain stages

• Echocancellation

• Burst mode controller

• Internal calls possible

• Power supply voltage: 5 V ± 5 %

• Low power consumption

• Advanced low power CMOS technology

• Encryption

The device is fabricated using Siemens advanced CMOS

technology and wilI be available in a 128 pin package.

• PMB 27251: 6 K RAM

• PMB 27252: 64 K ROM, 4 K RAM

Data Port

(32 kbit/s)

Crystal 20.736 MHz

Timers /

RF-Interf.

Synchro-

nization

Clocks

DSP

Input Data RAM

Serial In

CRC

De-

scramble

Control RAM

Interpolation

Decimation

ADPCM

Trans-

coder

Speech Data

(PMB 2920)

Codec

Filter

Internal Switch

TDMA Data

1.152 Mbit/s

Output Data RAM Serial Out

Control RAM CRC

Scramble

Burst-Error-Concealment

Tone Generation

Encryption

Decryption

Burst Mode Logic

Power

Control

Internal ROM

64 KBytes

Port X

Keypad

Port 0

Addit.

D

A

RSSI

2

8-Bit CPU

Timers

Tonedect.

I C Bus

Internal RAM

4 KBytes

Interrupts

Watchdog

Microcontroller Unit

ITB08461

Block Diagram PMB 27252

Siemens Aktiengesellschaft

29

DECT Multichannel Burst Mode Controller

PMB 2727

General Description

Type

Package

P-MQFP-100-2 (SMD)

The DECT Multichannel Burst Mode Controller is one of the

devices of the Siemens chip set designed cordless

applications specified by the DECT standard.

PMB 2727-H

Features

The device can handle up to twelve DECT channels. It

supports most of the Medium Access Control (MAC) layer

and Physical layer (PHL) functions specified in the DECT

standard. An interface to a standard 8-bit microcontroller

(Motorola and Intel compatible) is implemented.

• Power-down mode programmable

• Power supply voltage: 5 V ± 5 %

• Low power consumption: 100 mW (5 V)

• Advanced low power CMOS technology

Furthermore 3 IOM-2 interfaces are integrated e.g. for direct

connection of U transceivers (ISAC-P TE). The on-chip

P0

RF interface allows the control of the DECT-RF circuitry with

a minimum of discrete components.

The circuit can be used in DECT basestations (Radio Fixed

Parts RFPs). The device supports unprotected data

transmission.

The device is fabricated using Siemens advanced CMOS

technology and will be available in a 100 pin package.

Chipselect

Logic

Timer and Clock Unit

Digital LF-

Interface

BMC-Core-Functions

Serial IN

CRC

3 x

RF-

Port

Descramble

Data and

Control

Memory

RAM

RF-Interface

Serial OUT

CRC

®

IOM -2

Interface

Scramble

Channel

Control

Registers

Synchro-

nization

Encryption

Decryption

Headerpre-

processing

RSSI

ADC

Boundary Scan

Wafertest

Address

Decoder

Microcontroller Interface

ITB05954

Microcontroller

RAM / ROM

Block Diagram

Siemens Aktiengesellschaft

30

DECT PBX

PMB 2728

General Description

Type

Package

P-MQFP-100-2 (SMD)

The DECT PBX circuit is one of the devices of the Siemens

chip set designed for cordless basestations specified by the

DECT standard.

PMB 2728-H

Features

The circuit consists of two main functional blocks, these are

the Burst Mode Controller (BMC) and the Digital Signal

Processor (DSP).

• Power supply voltage: 5 V ± 5 %

• Low power consumption

• 100 pin P-MQFP packaging

The BMC can handle up to six DECT channels. It supports

the timecritical functions specified in the DECT standard.

Either 6 internal connections between handheld or 2 internal

and 2 external connections can be handled. An interface to a

standard 8-bit microcontroller (Motorola/Mitsubishi and Intel

compatible) is implemented. The on-chip RF interface allows

the control of the DECT-RF circuitry with a minimum of

discrete components.

• Advanced low power CMOS technology

Furthermore 1 IOM-2 interface is integrated e.r. for

connection of an ISDN interface device (lSAC-S) or of a

high feature codec device (ARCOFI, PSB 2163). For

analog line interfaces two circuits PMB 2920 can be

directly connected to the PMB 2728. Furthermore an

additional PCM interface is implemented for connection

of an answering machine.

The one-chip DSP can handle PCM/ADPCM

– transcording and echosupression due to the DECT

– standard for two channels.

The device is fabricated using Siemens advanced

CMOS technology and will be available in a

100 pin package.

2 x PMB 2920

or ISDN-Interface

PCM-Interface

2 x ADPCM-Codec

Control RAM

Data Memory

ADPCM Burst Coding and

Interface Decoding (6 ch.)

Serial IN

CRC

Interp.

Codec-

Filter

Echocontrol

Descramble

Scramble

ADPCM-

Trancoder

®

4x

Decim. IOM -2

Interface

Interp.

Codec-

Filter

Echocontrol

ADPCM-

Trancoder

Serial OUT

CRC

Decim.

Control RAM

Addition

PCM-Intf.

Synchro-

nization

RF-

Interface

Timer

Clocks

Channel

Control

Registers

Burst

Switch

Control

PLL

Control

Encryption

Decryption

DSP

BMC

Microcontroller Interface

Microcontroller

PMB 2728

ITB05955

Block Diagram

Siemens Aktiengesellschaft

31

DECT Analog Circuit

PMB 2920

General Description

Type

Package

P-SSOP-24-1 (Shrink, SMD)

The DECT-Analog Circuit is one of the devices of the

Siemens chip set for the digital cordless telephone specified

by the DECT standard.

PMB 2920-S

Features

The device designed for cordless handhelds and cordless

fixed stations is a highly integrated circuit and realizes the

analog front end functions needed in such systems. The

circuit contains an A/D- and a D/A converter and adjustable

gain stages. Connection of microphone and earpiece is

possible with a minimum of external components.

• High performance A/D- and D/A conversion

• Adjustable analog amplifiers

• Analog front end for direct connection of a handset mouth

and earpiece

• On-chip microphone supply generation

• Power savings power-down and MUTE functions

• Comparator for preprocessing of the demodulated receive

signal

• Reference voltage generation for on-chip A/D- and

D/A converters and for the DECT-Digital Circuit

• Support of volume control of the tone ringer signal

Furthermore the device generates the reference voltages for

the A/D converter the TXDA output voltage stabilization and

the LCD-display-driver modules integrated in the

DECT-Digital Circuit.

The reference voltages can be used together with external

components and the PMB 27201, 27202, 27221, 27251,

27252 and 2728 for volume control of the ringer.

The device is fabricated using Siemens advanced ACMOS

technology and will be available in a 24 pin package.

RXDI RXREF

+

RXDA

-

Microphone

ADC

Data Out

AMI

AGX

(REF 1 ... 5)

Digital

Audio

Interface

3.4 MHz (Clock)

32 kHz (Frame)

Data In

Ref. Volt.

Generation

MICS

AGR

DAC

Earpiece

RCTI

+

-

Ringer Control

Control

Block

2

I C Bus

ITB08462

Block Diagram

Siemens Aktiengesellschaft

32

DECT Transmitter

PMB 2220

General Description

Type

Package

P-SSOP-24-1 (Shrink, SMD)

The PMB 2220 is a high speed analog bipolar IC and is one

of the Siemens chipset for the Digital European Cordless

Telephone. Combined with PLL (i.e. PMB 2306) and a power

amplifier, the PMB 2220 device performs a complete DECT

transmitter. Additionally the phase locked loop can be

switched to receive mode and be used as a local oscillator for

the receiver mixer of PMB 2420.

PMB 2220-S

Features

• Either single VCO operation (for receive and transmit) or

dual VCO operation (one for receive and one for transmit)

possible

• 64/65-prescaler on chip

• Frequency doubler for receive and transmit mode with

balanced driver outputs

• Supply voltage regulator (with external pnp-transistor)

for the two VCO’s

• Power-down for the inactive VCO

• Current reference output for PLL charge pump to get

constant lock-in time

• Wide power supple range 3.0 … 5.5 V

I

V

I

V

REF

F1

20

GND3 LOB1

18 17

LOE1

16

LOE2

15

LOB2

14

REF

CC3

REG

19

13

12

11

VCO 1

(Rx / Tx)

VCO 2

(Rx)

Voltage

Regulator

Bandgap reference,

PD charge pump

reference, VCO-power

decoder

Processor

1÷ 64/65

90˚

1

2

3

4

PSRUN

5

6

7

8

9

10

MCC

GND1

V

PA

V

GND2 TXON TXLOFF

CC1

CC2

ITB05958

Block Diagram

Siemens Aktiengesellschaft

33

DECT Receiver

PMB 2420

General Description

Type

Package

P-SSOP-28-1 (Shrink, SMD)

The PMB 2420 is a high speed analog bipolar IC and is one

of the Siemens chipset for the Digital European Cordless

Telephone specified by the DECT standard. All control

inputs and the RSSI signal output match with the

PMB 27201/2 and 27221 and 27251/2 and 2728 and 2727

digital circuits.

PMB 2420-S

• Single balanced RF mixer with current-saving open

collector output on chip

• Limiter and RSSI dynamic range: 75 dB for IF between

40 MHz and 115 MHz

The IC operates as a heterodyne receiver using an

intermediate frequency (IF) at 110 MHz. It consists of a mixer

to downconvert the DECT-RF signal from 1.89 GHz to

110 MHz, a limiter amplifier, a field strength measurement

unit (RSSI) with a peak-hold output, a coincidence

demodulator, a sample-and-hold circuit for offset

compensation and two operational amplifiers for basehand

filtering.

• RSSI output independent of supply voltage and

temperature with 3 dB accuracy

• Peak-hold output for the RSSI signal, reset by the

controller via RSSG

• Sample-and-hold control circuit for baseband threshold

acquisition, loop opened and closed via RXDSG, offset

compensation value is stored during standby mode

• Timing for RSSI and sample-and-hold determined by the

controller

• Two operational amplifiers on chip for baseband filtering,

included in sample and hold control loop

• Standby mode with reduced supply current

• Balanced circuitry throughout the RF and IF

• Parts to improve signal isolation

Features

• Wide supply range 3.0 … 5.5 V

• Single conversion solution;

advantages are: low supply current of total RF part

no second IF image frequency and

therefore insensitive to strong

• Maybe applied as part of a complete DECT-chipset

solution

transmitters at FM radiofrequencies

low total component count 1st mixer

included on chip

V_CC

18

DSTP RXDSG RSTP

LO

25

LO RXOFF GND2 RFB

RFE RSSG

20 19

MO

17

MO

16

RSSI

15

28

27

26

24

23

22

21

Standby

Bandgap

V_BG

R_stp

Integrator

& Hold

Interface

Gating

Ref

Sample &

Hold

Discharge

Switch

Gating

-

+

Limiter Amplifier with RSSI Current Sources

Peak-hold

Stage

R_BBL

Buffer

Amp.

+

-

+

-

C _K

1

2

QUA

3

4

5

6

7

8

9

10

11

12

13

IFE

14

IFB

QUA

OA

OP1I OP1Q

IFP

OP2I RXREF RXDI

BBL GND1

ITB05959

Block Diagram

Siemens Aktiengesellschaft

34

RF-Building Blocks

Introduction

The era of the mobile communications has lead to an

explosion in the variety of RF applications. Active for many

years in this field with high performance IC solutions,

Siemens RF ICs have found use in almost all wireless

systems and are generally recognized for their high

performance, functionality and cost-effectiveness.

Building upon the success of the PMB 2200 modulator

family, the PMB 2401 receiver and Siemens PLLs

(TBB 200/TBB 206/PMB 2306), the new B6HF 25 GHz

bipolar technology will allow for a further increase in

performance, 3-V lower current consumption as well as for

higher frequencies. Starting with the new prescalers

PMB 2313/2314, all the standard RF-building blocks will be

gradually moved to B6HF.

Product Overview

Type

Description

Applications

Page

Modulator/Transmitter ICs

PMB 2200 Direct Vector Modulator

Cellular (GSM, PDC, DAMPS, CDMA), WLAN, QPSK/QAM 37

modulation up to 1 GHz

PMB 2201 ^B6HFDirect Vector Modulator + Mixer, 2.7 V Cellular (GSM, PDC, DAMPS, CDMA), WLAN, QPSK/QAM 38

modulation 0.8 GHz to 1.5 GHz

PMB 2202 ^B6HFDirect Vector Modulator + Mixer, 2.7 V Cellular (PCN, PCS, PDC), Cordless (PHS, WCPE) WLL,

WLAN, QPSK/QAM modulation 1.5 GHz to 2.5 GHz

38

PMB 2205

Direct Vector Modulator

Cellular (GSM, PCN, PCS, PDC, DAMPS, CDMA), Cordless 41

(PHS, WCPE) WLL, WLAN, QPSK/QAM modulation

PMB 2207 ^B6HFVector Modulator + Upconverter

Mixer, 2.7 V

Cellular (GSM, PCN, PCS, PDC, DAMPS, CDMA), Cordless 42

(PHS) WCPE, WLL, WLAN, QPSK/QAM modulation

PMB 2220

DECT Transmitter, 3 V

Cordless (DECT), FSK modulation

33

21

PMB 2240 ^B6HFGSM Transmitter, 2.7 V

PMB 2245 ^B6HFPCN Transmitter, 2.7 V

PMB 2247 ^B6HFPCS Transmitter, 2.7 V

Cellular (GSM, PDC), QPSK/QAM modulation 0.8 GHz to

1.0 GHz

Cellular (PCN, PCS), Cordless (PHS), QPSK/QAM

modulation 1.65 GHz to 1.85 GHz

21

Cellular (PCN, PCS), Cordless (PHS), QPSK/QAM

modulation 1.8 GHz to 1.95 GHz

Demodulator/Receiver ICs

PMB 2401

Receiver/Demodulator Circuit

Cellular (GSM, PDC, DAMPS, CDMA), WLAN, QPSK/QAM 43

demodulation up to 0.9 GHz

PMB 2402

Broadband Receiver/Vector

Demodulator

CATV, Satellite (MSAT, VSAT), DS, WLL, WLAN

44

PMB 2405 ^B6HFGSM Receiver, 2.7 V

Cellular (GSM, PDC, DAMPS), WLAN, QPSK/QAM

demodulation up to 2.5 GHz

23

PMB 2407 ^B6HFPCN/PCS Receiver, 2.7 V

Cellular (PCN, PCS), WLAN, QPSK/QAM demodulation up 23

to 2.5 GHz

PMB 2420

DECT Receiver, 3 V

Cordless (DECT), FSK demodulation

34

Siemens Aktiengesellschaft

35

RF-Building Blocks

Product Overview (cont’d)

Type

Description

Applications

Page

Frequency Synthesizer, Prescaler ICs

PMB 2302 ^B6HF1.25 GHz Dual PLL with Prescaler,

2.7 V

PMB 2303 ^B6HF2.5 GHz Dual PLL with Prescaler,

2.7 V

All analog and digital systems as RF-, IF synthesizer up to

1.25 GHz

45

47

49

51

All analog and digital systems as RF-, IF synthesizer up to

2.5 GHz

PMB 2306

PLL Frequency Synthesizer

All analog and digital systems as RF-, IF synthesizer up to

220 MHz

PMB 2307

PLL Frequency Synthesizer, 2.7 V

All analog and digital systems as RF-, IF synthesizer up to

220 MHz

PMB 2308 ^B6HF1.25 GHz PLL with Prescaler, 2.7 V

PMB 2309 ^B6HF2.5 GHz PLL with Prescaler, 2.7 V

All analog and digital systems as RF-, IF synthesizer up to

1.25 GHz

All analog and digital systems as RF-, IF synthesizer up to

2.5 GHz

PMB 2313 ^B6HF1.1 GHz Prescaler :64/65 :128/129;

2.7 V

PMB 2314 ^B6HF2.1 GHz Prescaler :64/65 :128/129;

2.7 V

All analog and digital systems as part of RF- and IF

synthesizer up to 1.1 GHz

All analog and digital systems as part of RF- and IF

synthesizer up to 2.1 GHz

LNA/Mixer, Driver/Mixer, Mixer ICs

PMB 2330

2.0 GHz Mixer

All analog and digital systems as up- and downconversion

mixer up to 2.0 GHz

52

PMB 2331 ^B6HF2.0 GHz Mixer, 2.7 V

All analog and digital systems as up- and downconversion

mixer up to 2.0 GHz

PMB 2332 ^B6HF1.1 GHz LNA + Mixer, 2.7 V

PMB 2333 ^B6HF3 GHz LNA/Driver + Mixer, 2.7 V

All analog and digital systems as frontend-LNA and mixer up 53

to 1.1 GHz

All analog and digital systems as frontend-LNA or

preamplifier-driver and mixer up to 3 GHz

54

Siemens Aktiengesellschaft

36

Direct Vector Modulator

PMB 2200

General Description

Type

Package

The PMB 2200 is a direct quadrature modulator for use in

mobile communication equipment.

PMB 2200-T

PMB 2200-S

P-DSO-20-1 (SMD)

P-SSOP-20-1 (Shrink, SMD)

An external LO signal f₀is fed to the modulator input. This

signal is first doubled and then bandpass filtered at 2f₀. This

frequency is the clock for a 2:1 divider. At the output of the

divider orthogonal carriers are provided which are mixed with

the baseband modulation signals by two multipliers. The

outputs of the multipliers are added and amplified by a linear

output stage.

Features

• Direct modulation vector modulator

• Linear modulating inputs

• Symmetrical circuitry

• Wide LO-frequency range 0.8 GHz to 1.0 GHz

• Generation of orthogonal carriers without external

elements and without trimming

The EN pin allows the modulator to be switched in

power-down mode.

• 35 dB carrier rejection, 42 dB SSB rejection

• 42 dB rejection of third order products

• 0 dBm linear output power

• Modulation frequency range 0 to 400 MHz

• Power-down mode

• P-DSO-20 or P-SSOP-20 package

• Temperature range – 25 °C to 85 °C

Applications

• Vector modulated cellular and cordless systems:

GSM, PDC, DAMPS, CDMA, WLAN, etc.

• Various modulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK etc.

• Analog systems with FM- and AM modulation

• Space and power saving optimizations of existing discrete

transmitter circuits

DC Test Inputs PP

I (t )

LO-Inputs

1 kΩ

I

GSM-RF-Output

800 to 1000 MHz

+

LOI

1 pF

DLO

+

LO

Linear

Qutput

Stage

E

Frequency

Doubler

Filter

1.8 GHz

Divider

2:1

LOQ

+

LO

+

1 pF

1 kΩ

Q

PO

0˚

90˚

Q (t )

GND

PP

Enable

EN

LOI

V

BIAS

V

SI

S

GND

LOQ

ITB01535

Block Diagram

Siemens Aktiengesellschaft

37

Direct Vector Modulator + Mixer

PMB 2201 ^B6HF

PMB 2202 ^B6HF

General Description

Type

Package

The PMB 2201, 2202 family is a direct quadrature modulator

and double balanced mixer. It is fabricated using Siemens

B6HF silicon bipolar process. In a typical application the

wanted mixer output product is bandpass filtered and then

fed to the modulator LO input. The mixer may also be used to

upconvert the modulator output signal to higher frequencies

up to 2.5 GHz.

PMB 2201-R

PMB 2202-R

P-TSSOP-24-1 (SMD)

Features

• Direct modulation vector modulator

• Wide LO-frequency range

PMB 2201: 0.8 GHz to 1.5 GHz

PMB 2201: 1.5 GHz to 2.5 GHz

• Generation of orthogonal carriers without external

elements and without trimming

• 35-dB carrier rejection, 40-dB SSB rejection

• 42-dB rejection of third order products

• 0-dBm modulator output power

• Independent double balanced Gilbert cell mixer

• RF- and IF-frequency range from DC to 2.5 GHz

• Low noise figure, high conversion gain

• Supply voltage range from 2.7 V to 5.5 V

• Low power consumption

The modulator generates two orthogonal carriers which are

mixed with the baseband modulation signals by two

multipliers. The outputs of the multipliers are added and

amplified by a linear output stage. The modulator and the

mixer have separate power supplies and grounds. They can

be powered down independently.

Applications

• Vector modulated cellular and cordless systems:

PMB 2201: GSM, PDC, DAMPS, CDMA, WLAN,

PMB 2202: PCN, PCS, PDC, PHS, WCPE, WLL,

WLAN, etc.

• Various modulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK etc.

• Analog systems with FM- and AM modulation

• Space and power saving optimizations of existing discrete

transmitter circuits

• Power-down mode

• P-TSSOP-24 package

• Temperature range – 30 °C to 85 °C

MO MO

LO LO

B

A

Q

0˚

RF

E

x 2

% 2

90˚

Bias 1

Bias 2

Ι

IF IF

PD 1 TREF PD 2

ITB08466

Block Diagram

Siemens Aktiengesellschaft

38

Direct Vector Modulator + Mixer

PMB 2201 ^B6HF

PMB 2202 ^B6HF

Q

1429 ... 1465 MHz

(940 ... 956 MHz)

178 MHz

(130 MHz)

°

0

x 2

% 2

°

90

V

CO

Ι

PMB 2201

1607 ... 1643 MHz

(810 ... 826 MHz)

TXDATA

:N2

PD2

:R2

PD1

:R1

:N1

1607 ... 1643 MHz

(940 ... 956 MHz)

PMB 2303

REF

130.5 MHz

455 kHz

130 MHz

De-

mod.

RXDATA

RSSI

1477 ... 1513 MHz

(810 ... 826 MHz)

PMB 2331

PMB 2333

ITB08467

PDC Application PMB 2201 / PMB 2303 / PMB 2331 / PMB 2333

Siemens Aktiengesellschaft

39

Direct Vector Modulator + Mixer

PMB 2201 ^B6HF

PMB 2202 ^B6HF

Q

°

0

259.25 MHz

x 2

% 2

°

90

V_CO

Ι

PMB 2202

1635.75 ... 1647.75 MHz

1895 ...

1907 MHz

TXDATA

:N2

PD2

:R2

PD1

:R1

:N1

1646.65 ... 1658.45 MHz

259.15 MHz

10.7 MHz

PMB 2303

REF

248.45 MHz

1895 ...

De-

mod.

1907 MHz

RXDATA

RSSI

PMB 2331

PMB 2333

ITB08468

PHS Application PMB 2202 / PMB 2303 / PMB 2331 / PMB 2333

Siemens Aktiengesellschaft

40

Direct Vector Modulator

PMB 2205

General Description

Type

Package

The PMB 2205 is a direct quadrature modulator for use in

mobile communication equipment.

PMB 2205-T

PMB 2205-S

P-DSO-20-1 (SMD)

P-SSOP-20-1 (Shrink SMD)

An external LO signal f₀is fed to the modulator input. This

signal is first doubled and then bandpass filtered at 2f₀. The

filter may be realized by an external tank circuit. Alternatively,

a local oscillator operating at 2f₀may be connected to the

divider input. This signal is the clock for a 2:1 divider. At the

output of the divider orthogonal carriers are provided which

are mixed with the baseband modulation signals by two

multipliers. The outputs of the multipliers are added and

amplified by a linear output stage.

Features

• Direct modulation vector modulator

• Linear modulating inputs

• Symmetrical circuitry

• Wide LO-frequency range 120 MHz to 800 MHz

• LO operation alternatively at transmit frequency or double

transmit frequency

The EN pin allows the modulator to be switched in

power-down mode.

• Generation of orthogonal carriers within a wide frequency

range

Applications

• 35 dB carrier rejection, 42 dB SSB rejection

• 42 dB rejection of third order products

• 0 dBm linear output power

• Modulation frequency range 0 to 400 MHz

• Power-down mode

• P-DSO-20 or P-SSOP-20 package

• Temperature range – 25 °C to 85 °C

• Vector modulated cellular and cordless systems:

GSM, PCN, PCS, PDC, DAMPS, CDMA, WLAN, etc.

• Various modulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK etc.

• Analog systems with FM- and AM modulation

• Space and power saving optimizations of existing discrete

transmitter circuits

Tank Circuit or

Double Transmit

Frequency Inputs

I (t )

PP

LO-Input

I

RF-Output

120 to 800 MHz

1 pF

+

LOI

DLO

+

LO

Linear

Output

Stage

E

Frequency

Doubler

Divider

2:1

Buffer

LOQ

+

LO

+

1 pF

Q

PO

PP

0˚

90˚

Q (t )

GND

Enable

EN

LOI

V

BIAS

V

SI

S

GND

LOQ

ITB05482

Block Diagram

Siemens Aktiengesellschaft

41

Direct Vector Modulator + Upconverter Mixer

PMB 2207 ^B6HF

General Description

Type

Package

P-TSSOP-24-1 (Shrink, SMD)

The PMB 2207 is a direct quadrature modulator and double

balanced mixer. It is fabricated using Siemens B6HF silicon

bipolar process. In a typical application the modulator output

signal is bandpass filtered and then fed to the mixer input for

upconversion.

PMB 2207-R

Features

• Vector modulator with upconverter mixer

• Wide LO-frequency range from 80 MHz to 800 MHz

• Mixer RF-frequency range up to 2.5 GHz

• Generation of orthogonal carriers without external

elements and without trimming

• 35 dB carrier rejection, 40 dB SSB rejection

• 42 dB rejection of third order products

• 0 dBm modulator output power

An external LO signal is fed to the modulator input. The

modulator generates two orthogonal carriers which are

mixed with the baseband modulation signals by two

multipliers. The outputs of the multipliers are added and

amplified by a linear output stage. The modulator and the

mixer have separate power supplies and grounds. They can

be powered down independently.

• Independent double balanced Gilbert cell mixer

• IF-frequency range from DC to 2.5 GHz

• Low noise figure, high conversion gain

• Supply voltage range from 2.7 V to 5.5 V

• Power-down mode

• P-TSSOP-24 package

• Temperature range – 30 °C to 85 °C

Applications

• Vector modulated cellular and cordless systems:

GSM, PCN, PCS, PDC, DAMPS, CDMA, PHS, WCPE,

WLL, WLAN, etc.

• Various modulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK etc.

• Analog systems with FM- and AM modulation

• Space and power saving optimizations of existing discrete

transmitter circuits

B

A

E

RF RF

Q

°

0

LO

MO

x 2

% 2

°

90

Bias 1

Bias 2

Ι

PD 1 TREF PD 2

IF IF

ITB08469

Block Diagram

Siemens Aktiengesellschaft

42

Receiver/Demodulator Circuit

PMB 2401

Preliminary Data

Type

Package

General Description

PMB 2401-T

PMB 2401-S

P-DSO-28-1 (SMD)

The PMB 2401 is a single-chip double-conversion

heterodyne PM receiver with phase shifting circuitry for the

l/Q-phase demodulation on chip. It also includes the second

local oscillator, a gain controlled 2nd IF amplifier,

2 differential operational amplifiers for audio purposes and

power-down circuitry.

P-SSOP-28-1 (Shrink, SMD)

Features

• Heterodyne receiver with demodulator

• Down mixing from 900-MHz receiver band to the base

band

• Demodulation and generation of l/Q components

• Lower mixer noise to 10 dB (SSB)

• High intercept point + 2 dBm

• Integrated phase shifter for l/Q demodulator

• 82-dB AGC range

• On-chip second LO oscillator with external tuning circuit

• Two differential operational amplifiers

• Low power consumption due to highly flexible

power-down capability

The PMB 2401 is designed for digital mobile telephones

according the GSM standard and other digital systems.

Application

• Digital mobile cellular systems as GSM, PDC, DAMPS

• Various demodulation schemes, such as PM, PSK, FSK,

QAM, QPSK, GMSK

• Space and power saving optimizations of existing discrete

demodulator circuits

• Wide input frequency range up to 1 GHz

• Wide IF range from 35 MHz to 100 MHz

• P-DSO-28 package, P-SSOP-28 (Shrink)

• Temperature range – 25 °C to 85 °C

MO MO IFI IFI

OUTI OUTI

Diff. Op. Amp.

INI

+

-

First

Mixer

Second

Mixer I

Output

Driver

AGC

SI

SOI

°

0

LO-Buffer

Amp.

LO 2B

LO 2E

Divider

by two

Divider

by two

Divider

by two

LO 1

°

90

SOQ

Second

Mixer Q

Output

Driver

Diff. Op. Amp.

INQ

+

-

Standby

RF

Standby

IF

V

GND

PD 1

PD 2

GC LO 2O OUTQ OUTQ

ITB03903

S

Block Diagram

Siemens Aktiengesellschaft

43

Broadband Receiver/Vector Demodulator

PMB 2402

General Description

Type

Package

The PMB 2402 is a single-chip single-conversion heterodyne

receiver with phase shifting circuitry for the l/Q phase local

baseband demodulation on chip. It also includes the second

oscillator, a gain controlled second IF amplifier, two

differential operational amplifiers for baseband fitering

purposes and power-down circuitry.

PMB 2402-S

P-DSO-28-1 (SMD)

Features

• Heterodyne receiver with demodulators

• Down mixing from 900 MHz receiver band to the base

band

• Demodulation and generation of I/Q-baseband

components

The PMB 2402 is designed for digital mobile telephones

according to the GSM standard and other digital systems.

• Low mixer noise 10 dB (SSB)

Applications

• Input high intercept point + 2 dBm

• Integrated 0° and 90° phase shifter

• 82 dB AGC range

• On-chip second LO oscillator with external tuning circuit

• Low power consumption due to highly flexible

power-down capability

• Digital wideband systems as CATV, Satellite, DBS, WLAN

• Various demodulation schemes, such as PM PSK, FSK,

QAM, QPSK, GM

• Space and power saving optimization of existing discrete

demodulator circuit

• Wide input frequency range up to 1 GHz

• Wide IF range from 35 MHz to 100 MHz

• Wide output frequency range up to 13.5 MHz

• Temperature range – 25 °C to 85 °C

MO MO IFI IFI

OUTI OUTI

Diff. Op. Amp.

INI

+

-

First

Mixer

Second

Mixer I

Output

Driver

AGC

SI

SOI

°

0

LO-Buffer

Amp.

LO 2B

LO 2E

Divider

by two

Divider

by two

Divider

by two

LO 1

°

90

SOQ

Second

Mixer Q

Output

Driver

Diff. Op. Amp.

INQ

+

-

Standby

RF

Standby

IF

V

GND

PD 1

PD 2

GC LO 2O OUTQ OUTQ

ITB03903

S

Block Diagram

Siemens Aktiengesellschaft

44

1.25-GHz Dual PLL with Prescaler

2.5-GHz Dual PLL with Prescaler

PMB 2302 ^B6HF

PMB 2303 ^B6HF

General Description

Type

Package

The PMB 2302, PMB 2303 are single chip dual Phase

Locked Loop (PLL) synthesizers with programmable

frequency dividers for use in mobile communication

equipment. It is fabricated using Siemens B6HF silicon

bipolar process.

PMB 2302-R

PMB 2303-R

P-TSSOP-20-1 (Shrink, SMD)

Features

The circuit consists of high speed dual modulus dividers, shift

registers, programmable counters (2 A-, 2 N- and

2 R-counters), phase detectors with charge pump and a

control logic block.

• Integrated prescaler

• Low operating current

• Different power-down modes

• High input sensitivity, high input frequency

• Two fast phase detectors without dead zone

• Linearization of the phase detector output by current

sources

Since one of the high speed dual modulus dividers is able to

handle frequencies of up to 1.25 GHz (2.5 GHz), there is no

need to add a dedicated external prescaler. The second dual

modulus divider handles frequencies up to 500 MHz. The

switching signals for the dividing ratios are generated by the

corresponding A-counters.

• Large dividing ratios for small channel spacing

• PLL1

max. freq.

prescaler:

A1-counter

N1-counter

R1-counter

PMB 2302

1.25 GHz

:32/:33

PMB 2303

2.5 GHz

:64/:65

The A-counter and the N-down-counter are programmable

via the 3-wire bus. They are clocked by the dual modulus

divider output signals. The carry outputs of the N-counters

are connected to the frequency inputs of the corresponding

phase detectors and are controlling the loading of the

programmed A-/N-counter start values.

0 to 31

0 to 63

32 to 2047

3 to 2047

PMB 2302

500 MHz

:16/:17

0 to 15

16 to 1023

3 to 2047

64 to 1023

3 to 2047

PMB 2303

500 MHz

:16/:17

0 to 15

16 to 1023

3 to 2047

• PLL2

max. freq.

prescaler:

A2-counter

N2-counter

R2-counter

The two 11 bit R-counters are also programmable and are

serving as reference frequency dividers. Their carry outputs

are connected to the corresponding reference frequency

inputs of the phase detector and are controlling the loading of

the programmed counter start values.

• Serial control (3-wire bus: data, clock, enable) for fast

programming (f_max= 10 MHz)

• Switchable polarity and phase detector current

programmable

The phase detectors are of PFD-type (phase and frequency

sensitive). They have a linear output characteristic in the 0˚

phase error region.

• 1 port output (TTL push-pull)

• External current setting for phase detector outputs

• Lock detect output with gated pulse (quasi digital lock

detect)

• Operating voltage 2.7 V to 5.5 V

• P-TSSOP-20 package

The control logic handles phase detectors output polarity,

charge pump output currents and software-generated

power-on (all circuit parts except the shift registers and data

latches).

• Temperature range – 30 °C to 85 °C

Applications

All mobile communication analog and digital systems as RF-

and IF synthesizers

Siemens Aktiengesellschaft

45

1.25-GHz Dual PLL with Prescaler

2.5-GHz Dual PLL with Prescaler

PMB 2302 ^B6HF

PMB 2303 ^B6HF

Divider

RF1

CP

CY

CP 11 (10) Bit Latch

N1- Counter

5 (6) Bit

A1-Counter

÷ 32 / 33

CY

RF1

(÷ 64 / 65)

D0 ... D4

LD

D5 ... D15

LD

1 Bit Latch

(Idle)

5 (6) Bit

A 1-Counter

11 (10) Bit Latch

N 1- Counter

CLK

2 Bit

Adress

(17 + 2) Bit Shift Register

DA

EN

3 Bit Latch

Control & Test

3 Bit Latch

Charge Pump 1

11 Bit Latch

R1- Counter

CT0, CT1, P0

CP0 ... CP2

R0 ... R10

LD

CP

CY

11 Bit

R1- Counter

RI

f

REF

f

VCON

V_{CC 1}

GND 1

V_CCP

PON 1

V_{CC 2}

PD1

LD

Phase

Detector 1

I_REF

Control

& Test

Port

PD2

Phase

Detector 2

GND 2

GND 1

f

VCON

f

REF

11 Bit

R 2- Counter

CP

LD

CY

R0 ... R10

CT0, CT1

CP0 ... CP2

3 Bit Latch

Control & Test

3 Bit Latch

Charge Pump 2

11 Bit Latch

R2- Counter

2 Bit

Adress

(17 + 2) Bit Shift Register

1 Bit Latch

(Idle)

4 Bit

A2-Counter

10 Bit Latch

N2-Counter

2 Bit Latch

(Idle)

D0 ... D3

4 Bit

A2-Counter

LD D4 ... D13

LD

Divider

÷ 16 / 17

RF2

CY

CP

10 Bit Latch

N2- Counter

CY

CP

ITB08470

Block Diagram

Siemens Aktiengesellschaft

46

PLL Frequency Synthesizer

PMB 2306

PMB 2307

General Description

Type

Package

The PMB 2306, PMB 2307 PLL are high speed CMOS ICs

are especially designed for use in battery-powered radio

equipment and mobile telephones. The intended application

will be in GSM, PCN, DECT and other digital mobile systems.

The wide range of dividing ratios also allows application in

analog systems.

PMB 2306-T

PMB 2306-R

PMB 2307-R

P-DSO-14-1 (SMD)

P-TSSOP-16-1 (Shrink, SMD)

Adjustment to the “actual” value then takes place with the

usual transient response as for small transfers in channel.

The synchronous transmission ensures that no additional

phase errors arise due to the change of reference

frequencies.

The circuit consists of a reference-, A- and N-counter, a

dual-modulus-control logic, a phase detector with charge

pump and a serial control logic. The setting of the operating

mode and the selection of the counter ratios is done serially

at the ports CLK, DA and EN.

The PMB 2306/2307 has two standby modes (standby1, 2)

to reduce the current consumption.

The operating modes allow the selection of single or dual

operation, asynchronous or synchronous data acquisition,

4 different antibacklash-impulse times, 8 different PD-output

current modes, polarity setting of the PD-output signal,

adjustment of the trigger-edge of the MOD-output signal,

2 standby modes and the control of the multifunction outputs

MFO1 and MFO2.

• Standby1 switches off the whole circuit, the current

consumption is reduced to below 1 µA.

• Standby2 switches off the counters, the charge pump and

the outputs, only the preamplifiers stay active.

The standby modes do not affect the port output signal. For

the influence on the other output signals see standby table.

The reference frequency is applied at the Rl input and scaled

down by the R-counter. Its maximum value is 50 MHz. The

VCO frequency is applied at the Fl input and scaled down by

the N- or N/A-counter according to single or dual-mode

operation. The maximum value at Fl is 220 MHz at single-,

and 65 MHz at dual-mode operation.

Features

• Low operating current consumption

• Low operating voltage

PMB 2306: 3 V to 5.5 V

PMB 2307: 2.7 V to 5.5 V

The phase detector is frequency and phase sensitive. It

produces a phase detector signal with adjustable anti-

backlash impulses in order to prevent a dead zone at very

small phase deviations. Phase differences smaller than

100 ps can therefore be resolved.

• High input sensitivity, high input frequencies (220 MHz)

• Extremely fast phase detector without dead zone

• Linearization of the phase detector output by current

sources

• Synchronous programming of the counters

(N-, N/A-, R-counters) and system parameters

• Fast modulus switchover for 65-MHz operation

• Switchable modulus trigger edge

• Large dividing ratios for small channel spacing

– A-scaler 0 to 127

– N-scaler 3 to 16380

– R-scaler 3 to 65535

• Serial control (3-wire bus: data, clock, enable) for fast

programming (f_max5 MHz)

• Switchable polarity and rate of trimming rise of the phase

detector

• 2 multifunction outputs

• Digital phase detector output signals (e.g. for external

charge pump)

• f_rn, f_ynoutputs of the R- and N-scalers

• Port 1 output (e.g. for standby of the prescaler)

• External current setting for PD output

• Lock detect output with gated antibacklash pulse (quasi

digital lock detect)

Programming of the IC is done by a serial data control. The

contents of the messages are assigned to the functional units

according to the destination address. Single or dual-mode

operation as well as asynchronous or synchronous data

acquisition is set by status 2 and should therefore precede

the programming of the counters.

The PMB 2306/PMB 2307 offer the possibility of

synchronous data acquisition to avoid error signals at the

phase detector due to non-corresponding dividing factors in

the counters produced by asynchronous loading.

Synchronous programming guarantees control during

changes of frequency or channel. That means that the state

of the phase detector or the phase difference is kept

maintained, and in case of “lock in”, the control process starts

with the phase difference “zero”.

Synchronous transmission is particularly advantageous

when large transfers in channel are to be made in a specific

short transient recovery time. For this purpose a larger

reference frequency is switched to in order to achieve rapid-

“rough”-transient response, increasing the bandwidth of the

loop at the time. When reaching the “quasi lock-in” state, the

reference frequency is switched back to its original values.

Siemens Aktiengesellschaft

47

PLL Frequency Synthesizer

PMB 2306

PMB 2307

f

R

Φ

R

RI

16 Bit R-Counter

Data Register

Phase-

Detector

Lock-

Detector

LD

and

Shadow Register

PD

Charge

Pump

Φ

V

f

V

Shift Register

MFO1

I

REF

MFO2

MOD

Modulus-Control

FI

14 Bit N-Counter

7 Bit A-Counter

Data Register

Shadow Register

Shift Register

V

DD1

SS1

V

DD

SS

CLK

DA

EN

Serial Control Logic

ITB04206

Block Diagram

Siemens Aktiengesellschaft

48

1.25-GHz PLL with Prescaler

2.5-GHz PLL with Prescaler

PMB 2308 ^B6HF

PMB 2309 ^B6HF

General Description

Type

Package

The PMB 2308, PMB 2309 are Phase Locked Loop (PLL)

synthesizers with programmable frequency dividers for use

in mobile communication equipment. It is fabricated using

Siemens B6HF silicon bipolar process.

PMB 2308-R

PMB 2309-R

P-TSSOP-16-1 (Shrink, SMD)

Features

The circuit consists of high speed dual modulus divider, shift

register, programmable counter (A-, N- and R-counter),

phase detector with charge pump and a control logic block.

• Integrated prescaler

• Low operating current

• Different power-down modes

• High input sensitivity, high input frequency

• Fast phase detector without dead zone

• Linearization of the phase detector output by current

sources

Since the high speed dual modulus divider is able to handle

frequencies of up to 1.25 (2.5) GHz, there is no need to add

a dedicated external prescaler. The switching signals for the

dividing ratio 16/17 (32/33) is generated by the A-counter.

The A-counter and the N-down-counter are programmable

via the 3-wire bus. They are clocked by the dual modulus

divider output signal. The carry output of the N-counter is

connected to the frequency input of the phase detector and

is controlling the loading of the programmed A-/N-counter

start values.

• Large dividing ratios for small channel spacing

• PLL

max. freq.

prescaler:

A-counter

N-counter

R-counter

PMB 2308

1.25 GHz

:16/:17

0 to 15

16 to 4095

3 to 2047

PMB 2309

2.5 GHz

:32/:33

0 to 31

32 to 2047

3 to 2047

The 11 bit R-counter is also programmable and is serving as

reference frequency divider. Its carry output is connected to

the reference frequency input of the phase detector and is

controlling the loading of the programmed counter start

value.

• Serial control (3-wire bus: data, clock, enable) for fast

programming (f_max= 10 MHz)

• Switchable polarity and phase detector current

programmable

The phase detector is of PFD-type (phase and frequency

sensitive). It has a linear output characteristic in the 0˚ phase

error region.

• 1 port output (TTL push-pull)

• External current setting for phase detector output

• Lock detect output with gated pulse (quasi-digital lock

detect)

• Operating voltage 2.7 V to 5.5 V

• P-TSSOP-16 package

The control logic handles phase detector output polarity,

charge pump output current and software-generated power-

down (all circuit parts except the shift registers and data

latches).

• Temperature range – 30 °C to 85 °C

Applications

All mobile communication analog and digital systems as RF-

and IF synthesizers

Siemens Aktiengesellschaft

49

1.25-GHz PLL with Prescaler

2.5-GHz PLL with Prescaler

PMB 2308

PMB 2309

Divider

÷16 / 17

(÷ 32 / 33)

CP

CY

CP

12 (11) Bit

N- Counter

RF1

4 (5) Bit

A1-Counter

CY

f

VCOA

D0 ... D3

LD

D4 ... D15

LD

1 Bit Latch

(Idle)

4 Bit Latch

A-Counter

12 Bit Latch

MSB

CLK

DA

1 Bit

Adress

(17 + 1) Bit Shift Register

Shifted First

EN

3 Bit Latch

Control & Test

3 Bit Latch

Charge Pump

11 Bit Latch

R- Counter

MSB

R0 ... R10

LD

CP

CY

11 Bit

R- Counter

RI

f

REF

f

VCON

V_{CC 1}

PD

LD

CP0 ... CP2

CT0, CT1, P0

GND 1

V_CC2

Phase

Detector

I

REF

Control

& Test

Port

GND 2

PON

Power Down

ITB08471

Block Diagram

Siemens Aktiengesellschaft

50

1.1-GHz Prescaler

2.1-GHz Prescaler

PMB 2313 ^B6HF

PMB 2314 ^B6HF

General Description

Type

Package

The PMB 2313, PMB 2314 prescaler family is designed for

use in mobile radio communication devices. It is fabricated

using Siemens B6HF silicon bipolar process. Due to its low

power consumption, low supply voltage down to 2.7 V and

low phase noise generation it is suitable for the use in

various battery powered handheld systems.

PMB 2313-T

PMB 2314-T

P-DSO-8-1 (SMD)

Features

• Low operating current

• Power-down mode

• High input sensitivity

The balanced differential inputs of the IC may be connected

either symmetrically or asymmetrically.

• Wide input frequency range

PMB 2313: 0.1 GHz to 1.1 GHz

PMB 2314: 0.1 GHz to 2.1 GHz

• Low noise

Depending on the logic level at SW input the dividing ratio is

fixed to 1:64/65 or 1:128/129. The MOD input determines

whether modulus 1/n or 1/(n+1) (n=64 or n=128, according to

SW level) is active.

• Operating voltage 2.7 V to 5.5 V

• P-DSO-8 package

• Temperature range – 30 °C to 85 °C

The IC can be switched to a low-power standby mode (input

STB). The MOD input is TTL/CMOS compatible. The emitter

follower output is CMOS compatible.

Applications

All analog and digital mobile communication systems as part

of RF- and IF synthesizers.

V

S

2

7

STB

V

REF

8

4

6

I 2

Q

1:64 / 65

1:128 / 129

1

3

I 1

I

SW

MOD

5

GND

ITB08472

Block Diagram

Siemens Aktiengesellschaft

51

2.0-GHz Mixer

PMB 2330

PMB 2331^B6HF

General Description

Type

Package

The PMB 2330, PMB 2331 are low power, double balanced

up-/downconversion Gilbert cell mixers up to 2.0 GHz. The

PMB 2331 is fabricated using Siemens B6HF silicon bipolar

process.

PMB 2330-T

PMB 2331-T

P-DSO-8-1 (SMD)

Features

Differential signals and symmetrical circuits are used

throughout the mixer. The mixer input can be used in

balanced or unbalanced configuration. The mixer outputs are

high impedance open collector outputs. The adjustable mixer

current allows to improve the mixer performance.

• Low operating current

• Low operating voltage:

PMB 2330: 3.0 V to 7.0 V

PMB 2331: 2.7 V to 5.5 V

• Power-down mode

• RF- and IF-frequency range up to 2.0 GHz

• Mixer current adjustable

An internal bias driver generates supply voltage and

temperature compensated reference voltages.

• Low noise figure

• High conversion gain

• Excellent intercept performance

• Good suppression of input signals at output

• High isolation values

Applications

All analog and digital mobile communication systems as up-

/ downconverter mixer.

• Few external components

• P-DSO-8 package

• Temperature range – 30 °C to 85 °C

MO

V

LO

S

1

2

3

4

Bias

8

7

6

5

MI

GND

LO

ITB08473

Block Diagram

Siemens Aktiengesellschaft

52

1.1-GHz LNA + Mixer

PMB 2332 ^B6HF

General Description

Type

Package

P-TSSOP-16-1 (Shrink, SMD)

The PMB 2332 is a low noise amplifier (LNA) up to 1.1 GHz

and double balanced mixer up to 3 GHz for use in mobile

communication equipment. It is fabricated using Siemens

B6HF silicon bipolar process.

PMB 2332-R

Features

• Low operating current

• Power-down mode

The amplified signal is external available for further use at

output AO. The DC level at GC allows to switch the LNA gain

(on/off: 20 dB).

• LNA frequency range up to 1.1 GHz

• Switchable LNA gain

• High LNA gain (typ. 20 dB at 900 MHz)

• Low LNA noise figure (typ. 1.5 dB at 900 MHz)

• Double balanced mixer up to 3 GHz with high gain

• Excellent intercept performance

• High isolation values

• Few external components

• Operating voltage 2.7 V to 5.5 V

• P-TSSOP-16 package

The mixer is a general purpose up- and downconversion

Gilbert cell mixer. Differential signals and symmetrical

circuits are used throughout the mixer. The mixer input can

be used in balanced or unbalanced configuration. The mixer

outputs are high impedance open collector outputs. The

adjustable mixer current allows to improve the mixer

performance.

An internal bias driver generates supply voltage and

temperature compensated reference voltages. The STB pin

allows the mixer and bandgap part of the IC to be switched in

power-down mode.

• Temperature range – 30 °C to 85 °C

Applications

All analog and digital mobile communication systems as

frontend-LNA and up-/ downconverter mixer.

V

GND

CC

LNA

Mixer

GC

LNA

AO

STB

Bias

MI

LO

AREF

AI

GND GND

LNA LNA

MO

V

LO

ITB08474

CC

Block Diagram

Siemens Aktiengesellschaft

53

3-GHz LNA/Driver + Mixer

PMB 2333 ^B6HF

General Description

Type

Package

P-TSSOP-16-1 (Shrink, SMD)

The PMB 2333 is a low power amplifier and double balanced

mixer up to 3 GHz for use in mobile communication

equipment. It is fabricated using Siemens B6HF silicon

bipolar process.

PMB 2333-R

Features

• Low operating current

• Power-down mode

• Amplifier frequency range up to 3 GHz

• LNA:

Variable gain,

High gain (typ. 12 dB at 1.8 GHz),

Low noise figure (typ. 1.7 dB at 1.8 GHz)

• Driver-amplifier:

The amplifier may be used as low noise amplifier (LNA) or as

driver amplifier. The amplified signal is external available for

further use at the open collector output AO. The DC level at

GC allows to adjust the amplifier current and the gain. Low

current is recommended for using the amplifier as LNA,

higher current for using it as driver.

The mixer is a general purpose up- and downconversion

Gilbert cell mixer. Differential signals and symmetrical

circuits are used throughout the mixer. The mixer input can

be used in balanced or unbalanced configuration. The mixer

outputs are high impedance open collector outputs. The

adjustable mixer current allows to improve the mixer

performance.

Variable gain,

High output (typ. +12 dBm at 1.8 GHz)

• Double balanced mixer up to 3 GHz with high gain

• Excellent intercept performance

• High isolation values

• Few external components

• Operating voltage 2.7 V to 5.5 V

• T-SSOP-16 package

An internal bias driver generates supply voltage and

temperature compensated reference voltages. The STB pin

allows the mixer and bandgap part of the IC to be switched in

power-down mode.

• Temperature range – 30 °C to 85 °C

Applications

All analog and digital mobile communication systems as

frontend-LNA or preamplifier-driver and up-/downconverter

mixer.

GND

AMP

Mixer

GC

AO

STB

Bias

MI

LO

AMP

AREF

AI

GND GND

AMP AMP

MO

V

LO

ITB08475

CC

Block Diagram

Siemens Aktiengesellschaft

54

Digital Terminal ICs

Siemens Aktiengesellschaft

55

Digital Terminals ICs

Positioning of the described products in different kinds of applications/segments.

Type

Video

Data

Voice

Page

ISAC^®-S

PEB 2085

PEB 2086

•

61

ISAC^®-S TE

PSB 2186

ISAC^®-P

PEB 20950

ISAC^®-P TE

PSB 2196

•

62

63

64

66

•

SmartLink-P

PSB 2197

ARCOFI^®

PSB 2160

ARCOFI^®-BA

PSB 2161

ARCOFI^®-SP

PSB 2163

•

68

69

•

70

71

PSB 2165

ITAC^®

PSB 2110

•

74

73

75

76

ISAR

PSB 7110

•

HSCX-TE

PSB 21525

JADE

PSB 7280

•

• = Main application

• = Optional

Depending on the application products out of other segments

like ESCC2; IBC; IEC-Q should also be considered.

Siemens Aktiengesellschaft

56

Overview on ICs for Digital Terminals

ISDN Voice Terminals

The adaptation of existing data terminals (DTE) to an ISDN

through a variety of interfaces (X.21, V24, RS232C, …) is a

subject being covered by a number of emerging standards.

With the digitization of the local loops, new ICs are needed to

adapt the voice and data sources.

The ITAC ISDN adapter circuit PSB 2110 brings a flexible

solution to each configuration.

Because of the analog/digital conversion is implemented in

the telephone, Digital Signal Processing techniques (DSP)

are suitably powerful tools for accomplishing this task. The

ARCOFI^®PSB 2160, ARCOFI^®-BA PSB 2161 and

ARCOFI^®-SP PSB 2165 or PSB 2163 make the best use of

this technology to deliver programmable, telephone specific

codec/filter.

A typical subscriber terminal configuration is shown in the

figure 1.

The modular concept allows the support of several interfaces

like U (ISAC^®-P), U (ISAC^®-P TE, SmartLink-P), S

P0

PN

0

(ISAC^®-S, ISAC^®-S TE) and U (IEC-Q, IEC-T). All interface

k0

controllers including layer-1, -2 support the IOM-2 Bus and

are software compatible.

Extendible to Integrated

Voice / Data Terminals

Packet Data

e.g. X.25

Character Data

e.g. V24 or X.21

®

Voice

IOM -2 Bus

768 kbit / s

S / T

Interface

®

ARCOFI

PSB 2160

ARCOFI

ISAC

-S

PEB 2085

®

HSCX

ITAC

®

-BA

-SP

PEB 2086

SAB 82525

PSB 2110

®

PSB 2161

ISAC

-S TE

®

ARCOFI

PSB 2186

®

PSB 2165

PSB 2163

ISAC

-P

PEB 20950

®

ISAC

-P TE

PSB 2196

Smart Link-P

PSB 2197

µC

(optional)

µP

Figure 1

ISDN Voice Terminal (extendible to integrated voice/data applications)

ITA03699

Siemens Aktiengesellschaft

57

Overview on ICs for Digital Terminals

ISDN Data Access

The shown enhanced passive PC-card version (figure 3)

includes the interface controllers and a DSP-based solution.

There is a dedicated ROM-coded DSP-version for supporting

modem (V.32), fax (V.29), data adaption (V.110, USART

framing) and HDLC controlling in development. Please

contact the Siemens sales office for details.

Shorter dial-up times, higher data rates and simultaneous

voice/data transmission comparing to analog transfer via

modem make ISDN very interesting for data access.

Especially ISDN data transfer via PC card is becoming more

and more popular.

Like the ISDN Voice Terminals (figure 1) both PC-card

version are expendible for voice and active PC-card

solutions.

The signs below show 2 solutions of passive PC cards.

The passive low cost version (figure 2) is optimal for

point-to-point data transfer. The modular concept for this

version includes the HDLC controllers and the interface

controllers (optional for U -, U -, S -, U -interfaces

P0

PN

0

k0

→ see ISDN Voice Terminals). The serial controllers HSCX

(8-bit interface) and ESCC2 (16-bit interface) can be used in

many applications in telecom and datacom systems by

offering dual channel HDLC controlling and DMA capability.

®

HSCX (8 Bit)

SAB 82525

ESCC2 (16 Bit)

SAB 82532

IOM

Bus

-2

IOM

-2

®

ISAC

-S TE

ISAC

-S TE

ISAR

PSB 7110

S

0

Bus

0

(PSB 2186)

Local Bus

PC Bus

PC-Interface

ITA06116

ITA06117

Figure 3

Figure 2

Passive Low-Cost

PC-Card Solution

Enhanced Passive PC-Card Solution

Optimized ROM-Coded

DSP-Solution (in development)

Siemens Aktiengesellschaft

58

Overview on ICs for Digital Terminals

ISDN Video Terminals

The 8×8 VCP is a single-chip programmable video

processor, which support the standards H.261, MPEG1,

MPEG2 IPEG.

Together with the video compression IC (VCP) from 8x8,

Siemens offers a system solution for H.320 ISDN-based

video communication. This four chip solution includes the

VCP ARCOFI-SP (PSB 2165) Joint Audio Decoder-Encoder

JADE (PSB 7280)

The Siemens audio compression IC JADE supports the

following standards: G.711, G.722, G.728.

The figure 4 shows the 8×8-Siemens videophone solution.

ISAC-S (PSB 2186).

ISDN

S-Interface

®

ISAC -S

(PSB 2186)

Micro-

phone

®

IOM -2

SRAM

®

Audio

VCP

8x8 3100 Series

JADE

PSB 7280

ARCOFI -SP

PSB 2163

®

IOM -2

DRAM

Video Video

In Out

Speakers

Camera

Host

Video

Capture

PCI I / F

SAB 80C535

PCI / VL Bus

ITA06118

Figure 4

IIT-Siemens Chipset Single Board PC Videophone Block Diagram

Siemens Aktiengesellschaft

59

Digital Terminal ICs

Product Overview

Type

Short Title

ISAC^®-S

ISAC^®-S TE

ISAC^®-P

ISAC^®-P TE

SmartLink-P

ARCOFI^®

ARCOFI^®-BA

ARCOFI^®-SP

ISAR

Description

Page

61

62

63

64

66

68

69

70

71

73

74

75

76

PEB 2085

PEB 2086

PSB 2186

PEB 20950

PSB 2196

PSB 2197

PSB 2160

PSB 2161

PSB 2163

PSB 2165

PSB 7110

PSB 2110

PSB 21525

PSB 7280

ISDN Subscriber Access Controller

Subscriber Access Controller

Audio Ringing Codec Filter

ISDN Subscriber Access

ITAC^®

ISDN Terminal Adapter Circuit

High-Level Serial Communication Controller Extended

Joint Audio Decoder / Encoder

HSCX-TE

JADE

Siemens Aktiengesellschaft

60

ISDN Subscriber Access Controller (ISAC^®-S)

PEB 2085

PEB 2086

General Description

Type

Package

The PEB 2085/86 ISAC-S implements the four-wire S

interface used to link voice/data terminals to an ISDN. The

component switches B- and D-channels between the S and

the ISDN Oriented Modular (IOM) interfaces, the latter being

a standard backplane interface for the ISDN basic access.

The HDLC packets of the ISDN D-channel are handled by the

ISAC-S which interfaces them to the associated

microcontroller.

0

PEB 2085-N

PEB 2085-P

PEB 2086-H

PEB 2086-N

P-LCC-44-1 (SMD)

P-DIP-40-2

0

P-MQFP-64-1 (SMD)

P-LCC-44-1 (SMD)

Features

• Full duplex 2B+D S interface transceiver according to

0

Applications

CCITT I.430

• Conversion of the frame structure between the S/T

interface and IOM

• Receive timing recovery according to selected operating

mode

• D-channel access control; support of LAPD protocol

• FlFO-buffer (2 × 64 bytes) for efficient transfer of

D-channel packets

• 8-bit microprocessor interface, multiplexed or non-

multiplexed

• Voice/Data Terminals

• ISDN PC Cards/Terminal Adapters

• Videophone

• Video PC Cards/Conferencing Systems

• G4 FAX

• Tele Control Systems

• Point-of-Sales Terminal

• Serial interface: IOM-1, SLD, SSI, IOM-2

• Implementation of IOM-1/IOM-2-MONITOR and C/I-

channel protocol to control peripheral devices

• Watchdog timer

®

IOM

S

ISDN

Basic

SSI

B-Channel

Access

Buffer

SSI

®

IOM

Interface

Switching

Layer-1

Functions

SLD

D-Channel

Control

Handling

FIFO

µP Interface

ITB00843

µP

Block Diagram

Siemens Aktiengesellschaft

61

ISDN Subscriber Access Controller for Terminal Applications

(ISAC^®-S TE)

PSB 2186

General Description

Type

Package

The PSB 2186 ISAC-S TE implements the four-wire S

interface used to link voice/data terminals to an ISDN. The

component switches B- and D-channels between the S and

the ISDN Oriented Modular (IOM-2) interfaces, the latter

being a standard backplane interface for the ISDN basic

access. The HDLC packets of the ISDN D-channel are

handled by the ISAC-S TE which interfaces them to the

associated microcontroller.

0

PSB 2186-H

PSB 2186-N

PSB 2186-P

P-MQFP-64-1 (SMD)

P-LCC-44-1 (SMD)

P-DIP-40-2

0

Features

• IOM-2 terminal specific version of the PEB 2086

(downward pin and SW compatibility)

• Full duplex 2B+D S -interface transceiver according to

Applications

0

CCITT I.430

• Voice/Data Terminals

• ISDN PC Cards/Terminal Adapters

• Videophone

• Video PC Cards/Conferencing Systems

• G4 FAX

• Tele Control Systems

• Cash Register Internetworks

• Point-of-sales terminals

• Conversion of the frame structure between the S/T

interface and IOM-2

• D-channel access control; support of LAPD control

• FIFO buffer (2 × 64 bytes) for efficient transfer of

D-channel packets

• 8-bit microprocessor interface, multiplexed or

non-multiplexed

• Serial interface: IOM-2 interface including bit clock and

strobe signal

• Implementation of IOM-2 MONITOR and C/l-channel

protocol to control peripheral devices

®

IOM - 2

S

ISDN-

Basic

B-Channel

Access

Buffer

®

IOM

Switching

Layer-1

Functions

Interface

D-Channel

Handling

Control

FIFO

µP-Interface

µP

Block Diagram

ITB05406

Siemens Aktiengesellschaft

62

ISDN Subscriber Access Controller (ISAC^®-P)

PEB 20950

General Description

Type

Package

The ISAC-P PEB 20950 is a combination of transceiver and

HDLC controller for ISDN terminals in a two-wire PBX

environment. Transceiver functions are performed according

PEB 20950-N

PEB 20950-P

P-LCC-44-1 (SMD)

P-DIP-40-2

to the two-wire PBX industry standard U . This corresponds

P0

to all of the functions available on the IBC PEB 2095.

Similarly the HDLC protocol is processed as described for

the ICC PEB 2070. The ISAC-P represents both the IBC and

ICC on a single IC.

Features

• Half-duplex burst-mode two-wire transceiver

• AMI-line code

• Adaptive line equalization

• High-level support of LAPD protocol

• FlFO-buffer (2 × 64 bytes) for efficient transfer of

D-channel packets

• IOM interface to other ICs

• Switching of test loops

• 8-bit µP interface

• Advanced CMOS technology

• Low power consumption

Code

SSI Port

SLD Port

HDLC

Receiver

HDLC

LAPD

®

Scramble

IOM

Transmitter Controller

Interface

Status

Command

Register

Decode

Descramble

FIFO

X-FIFO

R-FIFO

Controller

f

Buffer

Timing

ADPLL

µP-Interface

ITB01499

Block Diagram

Siemens Aktiengesellschaft

63

ISDN Subscriber Access Controller for U_PN-Interface Terminals (ISAC^®-P TE)

PSB 2196

General Description

Type

Package

The PSB 2196, ISDN Subscriber Access Controller for U

interface ISAC-P TE, implements the subscriber access

PN

PSB 2196-H

PSB 2196-N

P-MQFP-44-2 (SMD)

P-LCC-44-1 (SMD)

functions for a digital terminal to be connected to a two-wire

interface.

U

PN

Features

The PSB 2196 ISAC-P TE is an optimized device for

TE-applications, covering the complete layer-1 and -2

functions.

• Cost/performance-optimized U -interface transceiver,

PN

compatible to PEB 2096 OCTAT-P

• HDLC controller with 2 × 32-byte FIFO per direction

• HDLC-address recognition and control field handling

compatible to PEB 2070

• IOM-2 interface for terminal application compatible to

PEB 2070 ICC

• 8-bit multiplexed microprocessor interface

• 4-wire serial programming interface

• CPU clock and reset outputs

The PSB 2196 ISAC-P TE combines the functions of the U

transceiver with reduced loop length (one channel of the

OCTAT-P PEB 2096) and the ISDN-Communications

Controller (ICC, PEB 2070) onto one chip.

PN

The microcontroller interface of the ISAC-P TE is compatible

to standard multiplexed microcontrollers. In addition it

provides the microcontroller clock signal as well as a supply

voltage control and reset generation.

• Test loops

• Advanced CMOS technology

The terminal repeater function of the ISAC-P TE allows to

cascade two telephones which are controlled by one U

interface from the line card.

PN

The PSB 2196 ISAC-P TE interfaces to voice/data devices

via the IOM-2 interface.

The PSB 2196 ISAC-P TE is a 1 micron CMOS device

offered in a P-LCC-44 and P-MQFP-44 pin package. It

operates from a single 5-V supply.

Note: U in the document refers to a version of the U

PN

P0

standard with a reduced loop length.

Siemens Aktiengesellschaft

64

ISDN Subscriber Access Controller for U_PN-Interface Terminals (ISAC^®-P TE)

PSB 2196

TE-Mode

®

IOM

-2

U

PN

LCD

Contrast

Pulse

Width

Modulator

®

D-Channel

Controller

U

PN

Transceiver

Interface

LCD

FIFO

Matrix

LED

Matrix

Control

Microcontroller Interface / Reset Logic

Microcontroller

ITB05320

Block Diagram of the ISAC^®-P TE TE-Mode

TR-Mode

®

IOM

-2

U

PN

U

PN

TIC

Transceiver

Interface

Reset

ITB05321

®

Block Diagram of the ISAC -P TE TR-Mode

Siemens Aktiengesellschaft

65

Subscriber Access Controller for U_PN-Interface Terminals (SmartLink-P)

PSB 2197

General Description

Type

Package

P-DSO-28-1 (SMD)

The PSB 2197, SmartLink-P, implements the subscriber

PSB 2197-T

access functions for a digital terminal to be connected to a

two-wire U interface.

PN

Features

The PSB 2197 SmartLink-P is an optimized device for

TE applications, covering the complete layer-1 and basic

layer-2 functions for digital terminals.

• Cost/performance-optimized U interface

tranceiver, compatible to PEB 2096 OCTAT-P or

PSB 2196 ISAC-P TE

• HDLC controller with 2 × 4-byte FIFO per direction

• IOM-2 interface for terminal application including bit

clock and strobe signal

• Uplink MUTE function

• Selective B-channel loop back

• Serial control port

PN

The PSB 2197 SmartLink-P combines the functions of the

U

transceiver with reduced loop length (one channel of the

PN

OCTAT-P PEB 2096) and a simple HDLC controller for

signaling data onto one chip.

A pulse width modulator is included to provide an

LCD-contrast control or a ring tone signal.

• Pulse width output LCD-contrast control or ring tone

generation

• CPU clock and reset output

• Watchdog timer

• Test loops

• Advanced CMOS technology

• Low power consumption: active: 100 mW max.

The serial control port of the SmartLink-P is compatible to

most serial interfaces of microcontrollers. In addition it

provides the microcontroller clock signal as well as an

undervoltage detector and reset generation including a

watchdog function.

The Terminal Repeater function of the SmartLink-P allows to

cascade two telephones which are controlled by one U

PN

interface from the line card or to extend the loop length by

using an IEC-Q transceiver.

The SmartLink-P can also be used as a simple HDLC

controller which provides the TlC-bus access procedure. In

this mode, the U transceiver is inactive.

PN

The PSB 2197 SmartLink-P interfaces to voice/data devices

via the IOM-2 interface and provides an additional bit clock

and strobe signal for standard codecs. The upstream

B-channel information may be muted or loop back the

downstream data.

The PSB 2197 SmartLink-P is a 1-micron CMOS device

offered in a P-DSO-28 package. It operates from a single 5-V

supply.

Note: U in the document refers to a version of the U

PN

P0

standard with a reduced loop length.

Siemens Aktiengesellschaft

66

Subscriber Access Controller for U_PN-Interface Terminals (SmartLink-P)

PSB 2197

TE-Mode

®

IOM

-2 / PCM

U

PN

®

IOM

-2

U

PN

D-Channel

Controller

Interface

Transceiver

TIC

Pulse

Width

Modulator

Ring Tone

Generator

FIFO

Serial Control Port

Clock, Reset

Microcontroller

ITB06298

Block Diagram of the SmartLink-P TE-Mode

TR-Mode

®

IOM

-2

U

PN

U

PN

TIC

Transceiver

Interface

Reset

ITB05321

Block Diagram of the SmartLink-P TR-Mode

Siemens Aktiengesellschaft

67

Audio Ringing Codec Filter (ARCOFI^®)

PSB 2160

General Description

Type

Package

The PSB 2160 ARCOFI provides the subscriber with an

optimized audio, ringing, codec, filter processor solution for a

digital telephone. It fulfills all the necessary requirements for

the completion of a low-cost digital telephone.

PSB 2160-N

PSB 2160-P

P-LCC-28-1 (SMD)

P-DIP-24-1

Features

Applications

• Applications in digital terminal equipment including

a voice path

• Digital signal processing (DSP) performs all CODEC

functions

• Voice Terminals and Voice/Data Terminals

• Telephones with PC Interface

• Voice featured PC Cards

• Fully compatible to the G.714/CCITT specifications

• PCM G.711/CCITT A-Law/µ-Law and 16-bit linear data

• IOM-2 or SLD serial interface bus

• Fax Machines and a/b Terminal Adapter

• DTMF, tone and ringing generators

• Separate output for a piezo ringer

• Dual analog inputs for handset and “hands-free”

microphones plus an auxiliary differential analog input

• Two sets of differential outputs for a handset earpiece and

a loudspeaker

• 100 mW (sine wave) loadspeaker driver capability

• Test and maintenance loopbacks in the analog front end

and the digital processor

• Low power CMOS technology

• Power consumption active:

150 mW

standby: 100 mW

AFE

ASP

ADI

13

XINP

AX

14

XINN

10

9

SA

SB

SC

SD

15

16

Digital

Signal

Processor

Peripheral

Control

Interface

MIP

MIN

A

AHM

1

I / MUX

8

D

7

17

FHM

AFHM

19

11

HOP

HON

DD

AHO

ALS

18

Timing

Unit

12

6

SIP /

DU

®

D

SLD-IOM -2

O / MUX

Coefficient

RAM

Interface

A

CLK /

DCLK

PLL

21

20

LSP

LSN

5

FSC

22

GNDA

23

24

GNDD

1

2

3

4

V

SP 2

SP 1

RS

ITB00891

SS

DD

Block Diagram

Siemens Aktiengesellschaft

68

Audio Ringing Codec Filter Basic Function (ARCOFI^®-BA)

PSB 2161

General Description

Type

Package

P-DSO-28-1 (SMD)

The PSB 2161 ARCOFI-BA provides the Design Engineer

PSB 2161

with a cost-optimized audio, ringing, codec, filter processor

solution for simple digital terminals. It offers the minimum

functions necessary to develop a low-cost telephone and

thus with the high flexibility by the DSP technics.

Features

• Programmable Analog Front End (AFE), enables direct

connection of microphones, earpiece and loudspeaker

• Digital signal processing performs all CODEC functions

• Fully compatible to the G. 714 CCITT and ETSI (NET33)

specification

• PCM A-Law/µ-Law (G. 711 CCITT) and 16-bit linear data

• IOM-2 interface (TE- and non-TE-mode), Serial Control

Interface (SCI) and Serial Data Interface (SDI)

• Three analog inputs: two differential, high performance

inputs for microphones plus a single-ended auxiliary input

• Two differential outputs for a handset earpiece (200 Ω)

and a loudspeaker (50 Ω)

Applications

• Low-Cost Voice Terminals and Voice/Data Terminals

• Telephones with PC Interface

• Voice featured PC Cards

• Video Conference Terminals

• Fax Machines and a/b Terminal Adapter

• 100-mW sine wave and 200-mW square wave

loadspeaker driver capability

• Separate digital output for a piezo ringer

• Flexible Peripheral Control Interface (PCI) in IOM-2

TE-mode

• Flexible DTMF, tone and ringing generator

• Single 5-V power supply

• Low power consumption: standby < 1 mW

Configuration & Coefficients

Peripheral

Control

PCI / SCI

&

Serial Control

Interface

Data

®

IOM -2

Analog

Front

End

Digital

Signal

Processor

®

&

Audio

IOM -2 / SDI

Serial Data

Interface

Timing Unit

&

Reset Logic

ITB05593

Block Diagram

Siemens Aktiengesellschaft

69

Audio Ringing Codec Filter (ARCOFI^®-SP)

Featuring Enhanced Speakerphone

PSB 2163

General Description

Type

Package

The PSB 2163 ARCOFI-SP provides the subscriber with an

DSP-based audio, ringing, codec, filter-processor solution for

a digital telephone. It fulfills all the necessary requirements

for the completion of a low-cost digital telephone featuring

digital speakerphone and controlled loudhearing.

PSB 2163-N

PSB 2163-P

PSB 2163-T

P-LCC-28-1 (SMD)

P-DIP-28-1

P-DSO-28-1 (SMD)

Features

Applications

• Programmable Analog Front End (AFE), enables direct

connection of microphones, earpiece and loudspeaker

• 42+3 dB transmit amplification on chip, allows the direct

connection of the speakerphone microphone without

external OpAmp

• Digital signal processing performs all CODEC functions

Fully compatible to the G.714/CCITT and NET33/ETSI

specifications

• Voice Terminals and Voice/Data Terminals

• Telephones with PC Interface

• Voice Featured PC Cards

• Video Conference Terminals

• Fax Machines and a/b Terminal Adapter

• PCM G.711/CCITT A-Law/µ-Law and 16-bit linear data

• IOM-2 TE, IOM-2 (4 MHz) and SCI/SDI serial data

interfaces

• Enhanced digital speakerphone support without any

external devices:

“Stronger-Wins” Algorithm enables mode switching by just

speaking louder

Controlled monitoring (loudhearing) without any external

devices

Automatic Gain-Control (AGC) in transmit and receive

direction

• 200 mW (square) / 100 mW (sine wave) loudspeaker

driver capability

• Flexible DTMF, tone and ringing generator

• Low power consumption (standby < 1 mW)

Configuration & Coefficients

Peripheral

Control

PCI / SCI

&

Serial Control

Interface

Data

®

IOM -2

Analog

Front

End

Digital

Signal

Processor

®

&

Audio

IOM -2 / SDI

Serial Data

Interface

Timing Unit

&

Reset Logic

ITB05593

Block Diagram

Siemens Aktiengesellschaft

70

Audio Ringing Codec Filter (ARCOFI^®-SP)

Featuring Speakerphone Function

PSB 2165

General Description

Type

Package

The PSB 2165 ARCOFI-SP provides the subscriber with an

optimized Audio, Ringing, Codec, Filter processor solution

for a digital telephone. It fulfills all the necessary

requirements for the completion of a low-cost digital

telephone.

PSB 2165-N

PSB 2165-P

P-LCC-28-1 (SMD)

P-DIP-28-1

Features

The ARCOFI-SP performs all coding, decoding and filtering

functions according to the CCITT and AT&T standard.

• Applications in digital terminal equipment featuring

voice functions

• Digital signal processing performs all CODEC functions

• Fully compatible to the G.714 CCITT specifications

• PCM A-Law/µ-Law and 16-bit linear data

• IOM-2 or SLD serial data interface

• Full digital speakerphone support without any external

devices

• Automatic Gain Control (AGC) in transmit direction

• Controlled monitoring (loudhearing) without any external

devices

• Dual analog input for the microphone in the handset and

single-ended input the speakerphone plus an auxiliary

differential analog input

• Two differential outputs for a handset earpiece and a

loudspeaker

• 100-mW (sine wave) loudspeaker driver capability

• Independent gain programmable amplifiers for all analog

inputs and outputs

• Flexible Peripheral Control Interface (PCI)

• Flexible test and maintenance loopbacks in the analog

front end and the digital signal processor

• Flexible DTMF, tone and ringing generator

• Low power consumption (standby < 1 mW)

• Advanced CMOS technology, single 5-V power supply

Hardware and software support by the Siemens ISDN PC

Board SIPB 5000 and ARCOFI-SP coefficient program

ARCOS SP Plus SIPO 2165

Full featured applications are possible without any external

elements. All the necessary hardware and software is

implemented. In addition, the ARCOFI-SP offers a

speakerphone function as well as a controlled monitoring.

These features are fully implemented in the chip. Two

independent receive channels offer a more flexible use of the

tone generator, the digital gain stages, and the frequency

correction.

Two transducer correction filters (one for each direction) can

be programmed to correct the analog transducer frequency

characteristics.

The ARCOFI-SP provides an universal DTMF, tone and

ringing generator. All the generated tone sequences are

switchable to each output. This flexible tone generator

concept fulfills all the current specifications.

The interfacing to a handset mouth and earpiece is facilitated

by a flexible analog front end. A loudspeaker output has also

been integrated on the chip as well as a secondary input for

a speakerphone microphone. Further auxiliary differential

analog input is available. All analog inputs and outputs are

gain programmable through software.

Functional Description

The ARCOFI-SP bridges the gap between the audio world of

microphones, earphones, loudspeakers and the PCM digital

world by providing a full PCM-CODEC with all the necessary

transmit and receive filters as well as a speakerphone and

monitoring function.

The ARCOFI-SP can be subdivided in three main blocks:

• The ARCOFI Analog Front End (AFE)

• The ARCOFI Signal Processor(ASP)

• The ARCOFI Digital Interface (ADI).

Siemens Aktiengesellschaft

71

Audio Ringing Codec Filter (ARCOFI^®-SP)

Featuring Speakerphone Function

PSB 2165

Auxiliary

Speaker-

phone

Handset

Microphone

A

Signal

Processing

Amplifier

A / µ

D

Futher

Terminal

Functions

Tone and

DTMF

Generator

®

Speakerphone

(+ Monitoring)

Side

Tone

Piezo-

Ringer

IOM

SLD

-2

Power

Supply

± 5 V

D

Loud-

speaker

+

Amplifier

Signal

Processing

A

A / µ

+

Earpiece

+

AFE

ASP

ADI

ITA03966

Signal Flow Diagram

Siemens Aktiengesellschaft

72

ISDN Data Access Controller (ISAR)

PSB 7110

General Description

Type

Package

P-TQFP-100-1 (SMD)

The PSB 7110 ISAR has been designed as advanced

solution for passive ISDN PC cards and stand alone terminal

adapter boxes. It is an ISDN-data access controller, which

supports data rate adaption, standard HDLC protocolling and

communication with remote analog fax or modem

applications.

PSB 7110-F

Features

• Two universal formatter supporting async, HDLC and

binary framing of B-channel data

• One HDLC formatter with TIC-bus support for D-channel

applications in terminal mode

• Fax/modem modulation up to 14.4 kbaud (V.32bis, V.17)

including fall back modes

• DTMF generation / reception

• 8 Kbyte on-chip RAM for internal use and HDLC-frame

buffering

• 256-byte FIFO per direction for host interface

communication

• 8 Kbyte external SRAM interface for V.32bis support

Applications

• ISDN PC Card /Standalone Box

• ISDN Data Terminals

• Modem

• Radio in the Loop

• Digital Terminal Manufacturers

• Computer Manufacturers

• Modem Producers

®

IOM -2 / PCM Bus

Time-slot Assign

Pump

Time-slot Assign

TIC Bus

Pump

Trans-

Fax

Data

Trans-

DTM

V.110

Modem Modem

parent Gen / Det

parent

SART

C / I -

Code

Handler

Test

Diagno-

sis

Monitor

Handler

HDLC

ASYNC HDLC

Binär

ASYNC HDLC

Binär

Buffer 1

Buffer 2

Buffer 3

Buffer 0

Mailbox

ITB08608

Host

Block Diagram

Siemens Aktiengesellschaft

73

ISDN Terminal Adaptor Circuit (ITAC^®)

PSB 2110

General Device Overview

Type

Package

The ISDN Terminal Adapter Circuit interfaces standard

terminals and PCs to a circuit switched data network or an

ISDN. It supports both bitstuffing (V.110) and flag-stuffing

(V.120) adaption protocols. The on-chip communication

controllers handle signaling between data equipment and the

network.

PSB 2110-H

PSB 2110-N

PSB 2110-P

P-MQFP-44-1 (SMD)

P-LCC-44-1 (SMD)

P-DIP-40-1

Features

• Support of async and sync interfaces

(X.21, X.21 bis V.24, RS232C, V.35)

• Modem control lines

Applications

• Voice/Data Terminals

• ISDN PC Cards

• ISDN Terminal Adapters

• Programmable baud rates

• Bit rate adaption according to X.30, V.110, ECMA.102

• USART and HDLC controller to support V.120 and DMI

applications

• In-band parameter exchange and signaling support

• Supports SSI- and IOM-2 interface for basic rate

applications

• IOM-2 MONITOR channel controller

• Siemens/Intel multiplexed microprocessor interface

• Power-down (standby) mode

User

Rate

Intermediate

Rate

TxD

RxD

S

Async

Sync

Converter

ASC

Intermediate

Rate

Converter

IRC

Bearer

Rate

Converter

BRC

Synchron-

ous

Network

Interface

SNI

SDX /

DU

DCE

Interface

SDR /

DD

DTR / C

DCD / I

RTS

CTS

DSR

M1

CLK /

DCL

®

IOM

-2

FSC

Handler

Status and

Configuration

Register

Data Path & Clock Multiplexer

M2

DPLL

M3

MO1

MO2

Intermediate

XTAL1

USAR

USAT

HDLCR HDLCT

Clock

Generation

Network

FIFO

9 Byte

Counter

User Rate

XTAL2

10.752 MHz

Microcomputer / DMA Interface

RD

CS

RST

DACKO DACKI

DMIR EODR

AD0 - 7

Block Diagram

WR

ALE

DMOR

ITB02593

Siemens Aktiengesellschaft

74

High-Level Serial Communications Controller for

Terminals (HSCX-TE)

PSB 21525

General Description

Type

Package

The HSCX-TE is an optimized terminal version of the HSCX

(SAB 82525). The HSCX-TE has been designed to

implement high-speed communication links using HDLC

protocols and to reduce the hardware and software overhead

needed for serial synchronous communications.

PSB 21525-H

PSB 21525-N

P-MQFP-44-2 (SMD)

P-LCC-44-2 (SMD)

Features

• Optimized solution of HSCX (SAB ) for terminal equipment

Non-auto mode and transparent mode (no auto-mode)

Clock mode 5 only

Transfer of data blocks from/to system memory by

interrupt request (no DMA mode)

Applications

• ISDN PC Card/Standalone Box

• ISDN Data Terminal

• Two independent full-duplex HDLC channels

• Independent time-slot length (1-256 bit)

• Transparent receive/transmit of data bytes without HDLC

framing

• Various types of protocol support depending on operating

mode

• 64-byte FIFOs per channel and direction

• 8-bit demultiplexed or multiplexed bus interface

Channel A

DDA

DUA

RTSA

SP-REG

Decoder

CTSA

A0- A6

D0- D7

Data

Link

Controller

Transmit

FIFO

BCLA

TSA

FSCA

STBA

Receive

FIFO

RD / IC1

WR / IC0

CS

µP Bus

Interface

ALE / IM0

INT

STBB

FSCB

BCLB

CTSB

RTSB

DUB

RES

IM1

DDB

Channel B

ITB07459

Block Diagram

Siemens Aktiengesellschaft

75

Joint Audio Decoder/Encoder (JADE)

PSB 7280

General Description

Type

Package

P-TQFP-100-1 (SMD)

The PSB 7280 is a device which implements voice

compression algorithms defined in the ITU-TS G.711, G.722

and the G.728 Recommendation. It fits best into every

application where audicompression is needed.

PSB 7280-H

Features

• G.711/G.722/G.728 compression/decompression for one

audio channel

Applications

• Programmable G.711/G.722/G.728 modes with mixed

modes of operation (e.g. G.722 in receive and G.728 in

transmit direction)

• A/µ-Law recognition in G.711 mode (according to G.725

Appendix I)

• Fax modem signal recognition

• Accepts/outputs uncompressed audio in 8-bit PCM

A/µ-Law, or linear 16-bit format

• ISDN videophones

• Video conference systems

• Corporate networks voice concentrators and gateways

• Data-over-voice and voice-over-data terminals

• Networks (e.g. LANs) for packetized voice

• Digital Added Main-Line (DAML) & Digital Circuit

Multiplication (DCME) equipment

• Voice storage e.g. in PC based applications

• Serial H.221 oriented audio protocol for direct connection

to Videocodec (VCP of IIT Inc.)

• Two universal serial HDLC/transparent data controllers

• Programmable on-chip PLL for internal clock generation

from ISDN low frequency clock

• All program and data memory on chip

• Flexible interfaces (e.g. IOM-2, serial audio interface,

parallel 8-bit host interface, external memory interface)

• Supply voltage: 3.0 to 3.6 V

• 0.5-µm CMOS technology

Siemens Aktiengesellschaft

76

Joint Audio Decoder/Encoder (JADE)

PSB 7280

SIO AD(0:7) RD

WR

CS ALE RDY INTR INT

Reset EA

Parallel Host Interface

Audio

Rec 1

Trm 1

Rec 2

Trm 2

SCLK

SR

DD

HDLC 1

Serial

Audio

I / F

DU

®

IOM

/

ST

PCM

DCL

FSC

HDLC 2

Mailbox

256 Bytes

RFS

TFS

2x

Mon, C / I

Control

Config /

Control

Register

16 KW Prog ROM

DSP Core

CM 0,1

CLKO

2 KW Data 1 KW Data

Y-RAM Y-RAM

3 KW Data

X-ROM

1 KW Data

X-RAM

Timers

BRG

Clock

Gen /

PLL

XTAL 1

XTAL 2

V

REF

External Memory Interface

RADJ

CA(0:15) CD(0:15)

CRD CWR CPS CDS TCLK TMS TDI TDO

ITB06115

Block Diagram

Siemens Aktiengesellschaft

77

Digital Exchange System ICs

Subscriber Line Interface Codec Filter SLICOFI^®; PEB 3065

Siemens Aktiengesellschaft

79

Digital Exchange System ICs

Positioning of the described products in different kinds of applications/segments:

Type

Analog

Digital

Primary

Data Over

Network

Trunk Units

Line Card

Added Main Rate

Line (DAML) Interface

(PRI)

Voice (DOV) Termination

Remote

Power

Termination

(NT/RP)

PIC

•

EPIC^®-S

EPIC^®-1

ELIC^®

SICOFl^®

SICOFI^®-2

SICOFI^®-4

SICOFI^®-4µC

ICC

•

IDEC^®

SBC

•

SBCX

QUAT^®-S

IEC-Q

•

IEC-T

Quad IEC DFE-T

Quad IEC AFE

Quad IEC DFE-Q

IBC

OCTAT^®-P

IEPC

ACFA

IPAT^®-2

•

PRISM

•

FALC^™54

ARCOFI^®

ARCOFI^®-SP

ITAC^®

•

IRPC

•

GPPC

••

ISAC^®-S

ISAC^®-P

SLICOFI^®

HV-SLIC

PRACT

HSCX

•

ESCC2

•

ESCC8

• = Main application

• = Optional

Siemens Aktiengesellschaft

80

Digital Exchange System ICs

General Overview on Architecture and Devices

t / r

Subscriber Units

Switching

Systems

Group

Processors

Analog Line Cards

DAML

®

SICOFI

PIC

MTSS

MTSC

MTSL

DAML-RT

DAML-COT

®

t / r

SICOFI -2 EPIC -S

®

SICOFI -4 EPIC

U

TM

®

SLICOFI

SLIC

ELIC

HSCX

MUSAC -A

®

EPIC -S

®

HV-SLIC

EPIC -1

®

ELIC

Digital Line Cards

HSCX

ESCC2 / 8

MUNICH32

DOV

U

(Basic Rate)

t / r

®

SBC

SBCX

EPIC -S

®

EPIC -1

®

QUAT -S ICC

®

ISAC -S

IEC-T

IEC-Q

IBC

IDEC

ELIC

Trunk Units

ACFA

Transmission

Exchange

HSCX

IEPC

S / T

®

Concentrator

Multiplexer

®

OCTAT -P

IPAT -2

HSCX

PRISM

ESCC2

U

ESCC8

TM

(Primary Rate)

FALC

54

®

ACFA

IPAT -2

PRACT

HSCX

ESCC2 / 8

PRISM

FALC

S

TM

54

NT

RPT

PCM

Highway

ITA03688

Siemens Aktiengesellschaft

81

Analog Line Cards

Product Overview

Type

Short Title

Description

Page

89

PEB 2052

PEB 2054

PEB 2055

PIC

PCM Interface Controller

EPIC^®-S

EPIC^®-1

Extended PCM Interface Controller-Small

Extended PCM Interface Controller

High-Level Serial Communication Controller Extended

90

91

SAB 82525

SAB 82526

HSCX

HSCX1

162

PEB 20550

PEB 2060

PEB 2260

PEB 2465

PEB 2466

PEB 3065

PEB 4065

ELIC^®

SICOFl^®

Extended Line Card Interface Controller

Signal Processing Codec Filter

92

94

SICOFI^®-2

SICOFI^®-4

SICOFI^®-4 µC

SLICOFl^®

HV-SLIC

Dual Channel Codec Filter

96

Four Channel Codec Filter

97

Four Channel Codec Filter with µC Interface

Signal Processing with integrated low voltage SLIC Codec Filter

Subscriber Line Interface Circuit (High Voltage Part)

99

100

101

Siemens Aktiengesellschaft

82

General Exchange Architecture

Analog Line Cards

The conventional implementation is also characterized by

the fixed adjustment of line interface conditions although

telephone line conditions vary considerably with national

standards and even with subscriber line installations. Under

adverse conditions telecommunication equipment must

match the subscriber line and termination impedances while

suppressing return echoes in the two to-four-wire hybrid

network. Compensating for line attenuation is just as critical

for balancing the voice signals in the transmission and

reception paths. To improve voice quality, subscriber line

boards have to be matched to different line conditions by

means of interchangeable discrete components. This

approach is very costly regarding line board design and

manufacturing. Furthermore, the reliability of a board filled

with parts, wires and connections will decrease rapidly.

In a digital exchange system the subscriber line boards

provide the link between the subscriber and the switching

network. The basic functions of analog line boards are

known under acronym BORSHT (Battery, Overvoltage,

Ringing, Supervision, Hybrid, Testing). Additional important

tasks are voice frequency band limitation, analog to digital

conversion into time discrete digital equivalents, time-slot

assignment on the PCM highways and handling of

signaling and control information.

The conventional implementation uses two PCM ports

and one µP interface per subscriber line leading to a large

amount of wiring and, thus, problems are as crosstalk and

large board size.

The best solution to eliminate these line card trouble spots is

the design of one standard line card, which can be

customized for various line conditions and postal

specifications through software control. The right choice of

dedicate device allows the optimal line card design for each

application in public switches, PBX systems as well as in all

kinds of multiplexers and concentrators.

Siemens Aktiengesellschaft

83

General Overview on Architecture and Devices

2 Wires

4 Wires

PCM Higway

a

Analog

Network

Codec /

Filter

PCM

Interface

SLIC

b

Z, B, R, X, G

Problem: Fixed hardware adjustment

although line conditions vary

considerably

ITA00217

General Line Board Structure and Functions

General Line Card Function

Component

Function

Realization of the BORSHT function

SLIC

(Subscriber

line interface

circuit)

B

O

R

S

H

T

Battery feed

Overvoltage Protection

Ringing

Supervision

Hybrid

Testing

Analog network Z

Matching of input and line independence

Frequency response correction

Hybrid balancing

R, X

B

G

Gain adjustment

CODEC/Filter

PCM

Coding, A/D and D/A conversion according to A-Law and µ-Law, voice

Band limitation according to CCITT and LSSGR

Time-slot assignment, PCM-data rate

Siemens Aktiengesellschaft

84

Optimized Line Board Architecture

The Siemens Semiconductor concept is characterized by a

centralized PCM interface controller device providing the

variable Time-Slot Assignment (TSA), the communication

with up to 64 subscriber line devices such as a signal

processing codec/filter (SICOFI) or ISDN devices via the SLD

(Subscriber Line Data) or IOM-2 (ISDN Oriented Modular)

interface, and the interface with a microprocessor.

The use of the signal processing codec/filter (SICOFI) avoids

the analog network which has to be matched to different

requirements by interchanging its discrete components.

Based on Digital Signal Processing (DSP) methods the

SICOFI allows the complete control of the line conditions by

software.

The all-over flexibility and programmability of the unique

device concept gives the user the capability for designing a

standard line card which can be optimized for each

application and can be matched to various line conditions.

As a characteristic architectural feature, for test, monitoring,

and control purposes, the device permits efficient switching

of data streams between all these interfaces and, therefore,

ensures transparency between the PCM channels and

control or signaling data. This opens up attractive

possibilities such as common-channel signaling and

microprocessor access to PCM data.

The SLD/IOM-2 architecture leads to a highly modular line

board configuration with low wiring, reduced board area, and,

dependent on the SLIC being used, very few external

discrete components.

Transmit

PCM

DSP

Codec /

Filter

a

b

Circuit Interface

Highway

Interface

SLIC

Receive

Highway

Controller

®

SICOFI

SICOFI -2

SLD

PIC

Any Electronic SLIC

or Transformer

®

SICOFI -2

IOM -2

EPIC -S, EPIC -1, ELIC

®

SICOFI -4

IOM -2

®

HV-SLIC+SLICOFI

IOM -2

ITA00218

Siemens ICs for Analog Subscriber Lines, Configurations and Interfaces

Siemens Aktiengesellschaft

85

SLD/IOM^®-2 Interface

The SLD-bus is used by the PIC (PCM Interface Controller)

to interface with the subscriber line devices. A Serial

Interface Port (SlP) is used for the transfer of all digital voice

and data, feature control and signaling information

between the individual subscriber line devices, the PCM

highways and the control backplane. The SLD approach

provides a common interface for analog or digital per-line

components. Through the PIC, which is the key device in

the SLD-architecture, the PCM data is transparently

switched onto the PCM highways. The PBC (Peripheral

Board Controller) will make analog and digital subscriber line

boards plug-compatible in a line equipment rack.

Channel A and B are 64-kbit/s channels reserved for voice or

data to be routed to and from the PCM highways. In an

application where one SICOFI is connected to a SIP, voice is

received on channel A and transmitted on channel A and B.

For a three-party conference, channel B is the third-party

voice channel. If two SlCOFls are connected to one SIP,

channel A is assigned to one and channel B to the other

SICOFI. Conferencing is not possible in this configuration.

With digital subscriber line devices the two bytes can be used

to carry 64-kbit/s data channels. The third and sixth byte

locations are used to transmit and receive control information

for programming the slave devices. The last byte in each

direction is reserved for signaling data.

There are three wires connecting each subscriber line device

and the PIC: two common clock signals shared among all

devices, and a unique bidirectional data link for each of the

eight SIP lines. The Direction signal (DIR) is an 8-kHz clock

output from the PIC (master) that serves as a frame sync to

the subscriber line devices (slave) as well as a transfer

indicator. The data are transferred at a 512-kHz rate, clocked

by the Subscriber Clock (SCLK). When DIR is high (first half

of the SLD 125 µs frame), four bytes of digital data are

transmitted on the SLD-bus from the PIC to the slave (receive

direction). During the second half of the frame when DIR is

low, four bytes of data are transferred from the slave back to

the PIC (transmit direction).

Siemens Aktiengesellschaft

86

SLD/IOM^®-2 Interface

Subscriber

Subscriber Line Board

Backplan

DIR

SCLK

SIP

PIC

PEB 2052

®

SICOFI

PEB 2060

PEB 2260

®-1

EPIC

PEB 2055

SLD Bus

µP

1 Frame (125 µs)-512 kbit / s

Transmit

(upstream)

Receive

(downstream)

DIR

SCLK

SIP

512 kHz

A

B

FC

S

A

B

FC

S

ITA00538

Frame Structure of the SLD Interface

The lOM^®-Revision-2 (IOM^®-2) standard defines an industry

standard serial bus for interconnecting telecommunication

ICs. The standard covers line card, NT1, and terminal

architectures for ISDN and analog loop applications.

By providing data, control, and status information over a

serial channel, the IOM-2 bus eliminates the need to have a

microprocessor interface on the transceiver or codec. This

reduces pin count and simplifies line-card layout, thus

reducing cost.

The line-card mode of IOM-2 provides a connection path

between line transceivers (ISDN) and codecs (analog), and

the line-card controller; the line card controller provides the

connection to the switch backbone. The IOM-2 bus time

multiplexes data, control, and status information for up to

eight ISDN transceivers or up to 16 codec/filters over a single

full-duplex interface.

Information is multiplexed into frames, which are transmitted

at an 8-kHz rate. The frames are subdivided into from one to

eight subframes, with one subframe being dedicated to each

transceiver or pair of codecs. The subframes provide

channels for data, programming, and status information for a

single transceiver or a codec pair.

Siemens Aktiengesellschaft

87

SLD/IOM^®-2 Interface

The channel structure of the IOM-2 interface is as follows:

• The fourth octet (control channel) contains

– two bits for the 16-kbit/s D-channel

– a four-bit command/indication channel, in ISDN

applications or

a six bit command/indication channel for analog

subscriber applications

– two bits MR and MX for supporting the monitor

channel protocol.

• The first two octets constitute the two 64-bit/s

B-channels.

• The third octet is the monitor channel. It is used for the

exchange of data between devices using the IOM-2

monitor channel protocol.

®

FSC

DCL

DU

®

SICOFI -2

FRAME

EPIC -1

FRAME

CLOCK

D OUT

D IN

PEB 2055

PEB 2260

®

EPIC -S

CLOCK

D OUT

D IN

SICOFI -4

PEB 2465

PEB 2054

®

ELIC

SLICOFI

DD

PEB 20550

PEB 3065

FSC:

DCL:

DU:

Frame Synchronization

Data Clock

Data Upstream

DD:

Data Downstream

125 µs

FSC

8 kHz

DCL

512 or

4096 kHz

DU

IOM CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH0

DD

IOM CH0

B1

CH3

CH6

M

R

M

X

B2

Monitor

C / I

ITS02242

Multiplexed Frame Structure of the IOM^®-2 Interface

Siemens Aktiengesellschaft

88

PCM Interface Controller (PIC)

PEB 2052

General Description

Type

Package

P-LCC-44-1 (SMD)

The PCM Interface Controller (PIC) PEB 2052 is a device

for the control of voice, data and signaling paths of up

to 16 subscribers on peripheral component boards in

digital communication systems. In combination with the

highly flexible Signal Processing Codec Filter (SICOFI)

PEB 2060/2260 it forms an optimized, analog subscriber

line board architecture. Its flexibility enables its operation

as a general-purpose controller for data switching and

MUX/DEMUX applications.

PEB 2052-N

Features

• Board controller for up to 16 subscribers of a digital

switching system

• Suitable for all PCM systems (24/32/48/64 time-slots)

according to European and US standards

• SLD-bus to peripheral circuits, e.g. codec filter devices or

ISDN components

• Time-slot assignment freely programmable for all

connected subscribers

• µP access to all internal data streams including time-slot

oriented data streams

• All functions software-programmable via a standard

µP interface

• TTL-compatible inputs and outputs, including clock input

• Single + 5 V power supply

The PIC controls space and time switching functions

between subscriber line devices and time division multiplex

highways. Furthermore, it controls the flow of information

between the subscriber inferface ports and a line card local

processor.

To meet different requirements the PIC PEB 2052 provides

the following interfaces:

• Eight serial, bidirectional l/O ports for the transfer of voice,

data, control and signaling information between the PBC

and codec filters (e.g. SICOFI PEB 2060/2260), digital

interface circuits or signal processors.

• Double constructed PCM interface for a redundant system

configuration with load sharing operation.

• Advanced low power CMOS technology

Applications

Telecommunication subscriber board interface controller

IC for digital exchange PCM systems performing:

• digital exchange functions

• Bit-parallel interface for the connection of a standard 8-bit

microcomputer such as SAB 8051.

• digital concentrator functions

• signaling and interface control functions

• multiplex functions

1

Voice / Data

0

Highway 0

Highway 1

Subscriber

(SLD Bus)

PCM

Interface

Buffer

Interface

Buffer

5

8 / (16)

2

3

4

Microprocessor Interface

Data Flow within PIC

D0 - D7

ITS00383

Siemens Aktiengesellschaft

89

Extended PCM Interface Controller – Small (EPIC^®-S)

PEB 2054

General Description

Type

Package

Information from subscriber lines needs to be transferred to

time-slots on system internal PCM communication highways.

The EPIC-S concentrates the circuitry necessary to do this

interfacing for a large number of transmission lines on a

single IC. Therefore, it is not necessary to repeat this PCM

interface circuitry for every line. Applications of the EPIC-S

include communications multiplexers, concentrators, central

switches, PBXs, as well as peripheral ISDN and analog line

cards.

PEB 2054-N

PEF 2054-N

P-LCC-44-1 (SMD)

• Two serial interfaces: PCM and configurable

• Programmable for a wide range of data rates (PCM up to

8 Mbit/s, configurable up to 4 Mbit/s)

• Data rates of PCM and configurable interfaces

independent of each other (data rate adaption)

• Change detection (“last look”) logic for C/l or signaling

channels

Features

• 16-byte FIFO for monitor or feature control channels

• Standard µP interface with multiplexed address/data bus

or separate address and data busses

• Advanced low power CMOS technology

• Also available with extended temperature

range – 40 to 85 °C (PEF 2054-N)

• PCM interface controller for up to 16 ISDN or 32 analog

subscribers

• Time-slot assignment freely programmable for all

subscribers

• Non-blocking switch for 64 channels

• Switching of 16-, 32-, 64-kbit/s channels (128 kbit/s via

two consecutive 64-kbit/s channels)

• Pin compatible with PEB 2055

RES

DCL

PDC

PFS

Timing

FSC

RxD 0

TxD 0

DD0

DU0

TSC 0

RxD 1

TxD 1

PCM

TSC 1

Inter-

Configurable

Interface

Data

Memory

RxD 2

TxD 2

face

DD1

DU1

TSC 2

RxD 3

TxD 3

TSC 3

Control

Memory

Layer-1

Controller

Buffer

µP Interface

Block Diagram

ITB05888

AD0-AD7 WR RD CS ALE INT

Siemens Aktiengesellschaft

90

Extended PCM Interface Controller (EPIC^®-1)

PEB 2055

General Description

Type

Package

Information from subscriber lines needs to be transferred to

time-slots on system internal PCM communication highways.

The EPIC-1 concentrates the circuitry necessary to do this

interfacing for a large number of transmission lines on a

single IC. Therefore, it is not necessary to repeat this PCM

interface circuitry for every line. Since the system cost of the

EPIC-1 is divided by the number of lines it controls, powerful

and comfortable functions can be economically performed.

PEB 2055-N

PEF 2055-N

P-LCC-44-1 (SMD)

• Interfacing with four full-duplex PCM highways (up to

8 Mbit/s)

• Data rates of PCM and configurable interfaces

independent of each other

• Change detection (“last look”) logic for C/l or signaling

channels

Features

• 16-byte FIFO for monitor or feature control channels

• Standard µP interface with multiplexed or demultiplexed

address/data bus or separate address and data busses

• Advanced low power CMOS technology

• Also available with extended temperature

range – 40 to 85 °C (PEF 2055-N)

• PCM interface controller for up to 32 ISDN or 64 analog

subscribers

• Time-slot assignment freely programmable for all

subscribers

• Non-blocking switch for 128 channels

• Switching of 16-, 32-, 64-kbit/s channels (128 kbit/s via two

consecutive 64 kbit/s channels)

• Two serial interfaces: PCM and configurable (IOM-2,

IOM-1, SLD, PCM).

RES

DCL / SCLK

FSC / DIR

PDC

PFS

Timing

RxD 0

TxD 0

DD0 / SIP0

DU0 / SIP4

TSC 0

RxD 1

TxD 1

DD1 / SIP1

PCM

Inter-

face

DU1 / SIP5

Configurable

Interface

Data

Memory

TSC 1

RxD 2

TxD 2

DD2 / SIP2

DU2 / SIP6

TSC 2

DD3 / SIP3

DU3 / SIP7

RxD 3

TxD 3

TSC 3

Control

Memory

Layer-1

Controller

Buffer

µP Interface

Block Diagram

ITB00687

AD0-AD7 WR RD CS ALE INT

Siemens Aktiengesellschaft

91

Extended Line Card Controller (ELIC^®)

PEB 20550

General Description

Type

Package

P-MQFP-80-1 (SMD)

The Extended Line Card Controller (ELIC) PEB 20550-H is a

device to allow the control, supervision and processing of

voice, data and signaling information. It also provides access

for the microcontroller to write/read data to/from the IOM and

PCM interfaces and gives control over layer-1 devices.

Revolutionary is the multiplexing concept allowing to use only

one implemented HDLC controller to process the signaling

information for up to 32 digital subscribers.

PEB 20550-H

The SACCO B is a second integrated HDLC controller

behaving like an external device. It is mainly intended for

signaling information between the line card and the group

processor on the main board. This can be done either via a

dedicated signaling highway or via the PCM highway. The

SACCO B can also be used for music on hold, conferencing

access and other features. The HDLC information handling

between SACCO A and SACCO B always has to go via a

microprocessor.

The switching part of the ELIC controls space and times

switching functions between subscriber line devices and time

division multiplex highways. Furthermore it controls the flow

of information between the subscriber interface ports and a

processor.

Features

For processing signaling information two different HDLC

controllers are implemented. The SACCO A is a Serial

Access Communication Controller (HDLC) which allows

extracting D-Channel information transported on the IOM

interface. The data is then passed to the microcontroller. ln

the downstream direction, the SACCO A passes data,

packed in the HDLC protocol, from the microcontroller to the

IOM interface.

• Configurable interface (CFI) programmable for IOM-2,

IOM-1, SLD or PCM

• Switching between configurable interface (e.g. lOM-2) and

PCM ports

• Switching of 64 B-channels (32 digital or 64 analog

subscribers) without blocking (128 × 128 matrix)

• Two HDLC controllers with 64-byte FlFOs implemented

• Arbiter logic to use one of the HDLC-controllers time

multiplexed for a maximum of 32 digital subscribers

• Full-duplex signaling protocols (LAPD or proprietary)

• HDLC broadcast messages

With 4 IOM interfaces, and 8 digital subscribers possible per

interface, former designs needed 32 HDLC controllers (one

for the D-channel of every subscriber). The SACCO A of the

ELIC can serve all 32 channels in a time-multiplexing

manner. This process is controlled by the BUS ARBITER.

This part of the ELIC monitors all D-channels of the IOM

interface and locks the SACCO A onto one D-channel as

soon as the start of a HDLC frame is detected. After the end-

flag of the HDLC frame has been received, the SACCO A is

released again and can lock onto the next D-channel as soon

as a new request is detected. During the assignment of the

HDLC controller to a certain channel the other subscribers

are not allowed to send information on their D-channels. To

assure this a blocking mechanism is implemented which

indicates to corresponding terminals that they may not use

the D-channel. This mechanism works as well for the

• DMA access to HDLC data

• Boundary scan

Application Areas

• PBX:

– analog line cards

– digital line cards

• CO:

– analog line cards (with disabled arbiter)

– digital line cards (with disabled arbiter)

Interfaces

standard ISDN S as for the proprietary U interface, a two

0

P

• 4 configurable interfaces (individually programmable for

IOM, SLD, PCM)

• 4 PCM interfaces (maximum combined data rate

of 8 Mbit/s)

• µP interface (Siemens/lntel and Motorola interface,

multiplexed and demultiplexed address/data bus)

• Boundary scan (for on-board tests)

• DMA interface

wire ISDN capable interface for PBXs. Any ISDN Telephone

can be connected to a PBX because the standard arbitration

mechanism is used for blocking the phones.

This concept saves the space and the costs of up to

32 HDLC controllers. Due to the bursty characteristic of the

signaling data, one HDLC controller is sufficient to process

this data flow. For central office applications the ELIC is not

recommended when the arbiter is used, as PTTs require

transparent D-channels. In this case the SACCO A can be

used as an independent HDLC controller.

If the design needs higher D-channel data rates additional

HDLC controllers (IDEC, PEB 2075) can be connected. This

can either be done on the IOM interface and is than fixed for

a certain subscriber or via the PCM interface which makes

this extra HDLC controller flexibly assignable.

Siemens Aktiengesellschaft

92

Extended Line Card Controller

PEB 20550

PCM

Highway 0

Boundary Scan

Watchdog Timer

PCM

Highway 1

SACCO

Channel B

SACCO

Channel A

PCM

Highway 2

®

EPIC -1

Powerup Reset

Generator

PCM

Highway 3

µP Interface,

Parallel Ports

D-Channel Arbiter

Clock /

Sync.

ITS05905

Block Diagram

Siemens Aktiengesellschaft

93

Signal Processing Codec Filter (SICOFI^®)

PEB 2060

General Description

Type

Package

The Signal Processing Codec Filter (SICOFI) PEB 2060 is a

fully integrated PCM codec (coder-decoder) and transmit/

receive filter produced in advanced CMOS technology for

applications in digital exchange telecommunication systems.

Based on a digital filter concept the PEB 2060 provides

improved transmission performance and high flexibility. It

enables the control of the device’s analog behavior by digital

signal processing, including attractive features such as

programmable trans-hybrid balancing, impedance matching,

level control and frequency response correction. The device

is optimized for working in conjunction with the PCM Interface

Controller PEB 2052/55.

PEB 2060-N

PEB 2060-P

P-LCC-28-1 (SMD)

P-DIP-22-1

(not for new development)

Features

• Single-chip codec and filter

• Band limitation according to CClTT and LSSGR

recommendations

• Digital signal processing techniques

• Digital voice transmission

– PCM encoded (A-Law or µ-Law)

– linear (16-bit 2s complement)

The analog input signal is A/D converted, digitally filtered and

transmitted either PCM-encoded or linear. Antialiasing is

done with a 2^ndorder Sallen-Key Prefilter (PREFI). The A/D

Converter (ADC) is a modified slope adaptive interpolative

coder with a sampling rate of 128 kHz. Digital downsampling

to 8 kHz is done by subsequent decimation filters D1 and D2

together with the PCM bandpass filter (BP).

•

Programmable digital filters for

– impedance matching

– transhybrid balancing

– gain

– frequency-response correction

Configurable 3-pin serial interface

– 512-kHz SLD-Bus (e.g. to PEB 2052/55)

– burst mode with bit rates up to 8 MHz

The digital input signal is received PCM encoded or linear,

digitally filtered and D/A converted to generate the analog

output signal. Digital interpolation up to 128 kHz is done by

the PCM lowpass filter (LP) and the interpolation filters l1 and

l2. The D/A Converter (DAC) output is fed to the 2^ndorder

Sallen-Key Postfilter (POFI).

• Programmable signaling interface with

peripherals (e.g. SLIC)

• High performance A/D and D/A conversion

• Programmable analog gain

• Advanced test capabilities

– three digital loopback modes

– two analog loopback modes

– on-chip sinewave generation

The high flexibility of the SICOFI is based on a variety of user

programmable filter, which are analog gain adjustment AGR

and AGX, digital gain adjustment GR and GX, frequency

response adjustment R and X, impedance matching filter Z

and the trans-hybrid balancing filter B.

• No trimming or adjustment

• No external components

• Variable SICOFI master clock selection

• Signaling expansion possible

The SICOFI bridges the gap between analog and digital

voice signal transmission in modern telecommunication

systems.

High performance oversampling Analog-to-Digital Converter

(ADC) and Digital-to-Analog Converter (DAC) provide the

conversion accuracy required. An analog antialiasing

Prefilter (PREFI) and smoothing Postfilter (POFI) is included.

The dedicated on-chip Digital Signal Processor (DSP)

handles all the algorithms necessary, e.g. PCM bandpass

filtering, sample rate conversion and PCM comparing. The

3-pin serial SLD-Bus interface handles digital voice

transmission and SICOFI feature control. Specific filter

programming is done by downloading coefficients to the

Coefficient RAM (CRAM).

• Prepared for three-party conferencing

• Advanced low power CMOS technology

The 10-pin parallel signaling interface provides for a powerful

per line SLIC control.

Siemens Aktiengesellschaft

94

Signal Processing Codec Filter (SICOFI^®)

PEB 2060

Signaling

SA...SD SI

SO

4

3

S

L

D

DIR

A

VIN

PREFI

D

SCLK

SIP

Interface

B

U

S

DSP

Coeff.

RAM

D

VOUT

POFI

A

ITB00635

Block Diagram

A

+

VIN

AGX

PREFI

D1

D2

GX

BP

X

Comp

D

Transmit

Receive

SIP

DIR

SLD

Interface

Z

+

B

SIN

SCLK

D

A

VOUT

POFI

AGR

I2

I1

GR

LP

R

Exp

ITS00634

Signal Flow

Siemens Aktiengesellschaft

95

Dual Channel Codec Filter (SICOFI^®-2)

PEB 2260

General Description

Type

Package

The Dual Channel Codec Filter PEB 2260 (SICOFI-2) is a

fully integrated PCM codec and filter fabricated in low power

CMOS technology for applications in digital communication

systems. Based on an advanced digital filter concept, the

PEB 2260 provides excellent transmission performance and

high flexibility. The digital signal processing approach

includes attractive programmable features such as

trans-hybrid balancing, impedance matching, gain and

frequency response correction.

PEB 2260-N

PEF 2260-N

P-LCC-28-1 (SMD)

Features

• Dual channel single chip codec and filter

• Band limitation according to CCITT and LSSGR

recommendations

• Digital signal processing techniques

• PCM encoded digital voice

transmission (A-Law or µ-Law)

• Programmable digital filters for

– impedance matching

– transhybrid balancing

– gain

– frequency response correction

• SLD- and lOM-2 interface

• Programmable signaling interface to

peripherals (e.g. SLIC)

• High performance A/D and D/A conversion

• Programmable analog gain

• Advanced test capabilities

– three digital loopback modes

– two analog loopback modes

– two programmable tone generators

• No trimming or adjustments

• No external components

The SICOFI-2 can be programmed to communicate either

with SLD or with IOM-2 compatible PCM-interface controllers

(e.g. PEB 2052/54/55).

The device bridges the gap between analog and digital voice

signal transmission in modern telecommunication systems.

A high performance oversampling Analog-to-Digital

Converter (ADC) and Digital-to-Analog Converter (DAC)

provide the conversion accuracy required. Analog

antialiasing Prefilters (PREFI) and smoothing Postfilters

(POFI) are included. The dedicated on-chip Digital Signal

Processor (DSP) handles all the algorithms necessary, e.g.

PCM bandpass filtering, sample rate conversion and PCM

companding. The SLD/lOM-2 interface handles digital voice

transmission, SICOFI-2 feature control and access to the

SICOFI-2 signaling pins. Specific filter programming is done

by downloading coefficients to the Coefficient RAM (CRAM).

• Advanced low power CMOS technology

• Also available with extended temperature

range – 40 °C to 85 °C (PEF 2260-N)

A

VIN A

PREFI

POFI

SLD /

D

A

®

IOM -2

Interface

Channel A

VOUT A

D

DSP

A

D

VIN B

PREFI

POFI

D

A

Channel B

VOUT B

CRAM

ITB00385

Block Diagram

Siemens Aktiengesellschaft

96

Signal Processing Codec Filter (SICOFI^®-4)

PEB 2465

General Description

Type

Package

P-MQFP-64-1 (SMD)

The Signal Processing Codec Filter (PEB 2465-H), SICOFI-4

is the interface between four analog subscribers and the

digital switch. The chip combines all the circuitry needed for

encoding, decoding and PCM filtering of 4 speech channels

on CMOS chip. An integrated digital signal processor (DSP)

allows the analog line card to be adapted to the widest variety

of national specifications and applications by programming

the individual digital filter functions. A wide variety of SLlCs

(subscriber line interface circuits) can be employed and

simply adapted.

PEB 2465-H

Features

• Codec for four analog subscribers (public switch and

PBX) usable towards the trunk and the subscriber

• Specification according to relevant CCITT, EIA and

LSSGR

• IOM-2 interface

• Usable with transformer and electronic SLlCs

• DSP technology

• Adaption to different country specifications with

following programmable filters

– AC impedance matching (return loss better than 30 dB)

– transhybrid balancing (better than 30 dB)

– frequency response

– gain (steps of 0.05 dB)

• Advanced test capabilities

The SICOFI-4 can be used in both, PBXs and public

switches. The external configuration does not vary – only

decoupling capacitors are needed. Widely differing national

specifications can be met with a single hardware by just

changing the filter coefficients: Signal level, terminating

impedance, equivalent impedance, frequency response

correction and the required coding procedure (A- or µ-Law)

are simple to program. Siemens provides well proven

software for calculating the required coefficients.

• DTMF generator

• Level metering function

• Boundary scan

• Single 5-V power supply

The SICOFI-4, together with standard SLlCs, also fulfills the

new specification for idle channel noise in the out-of band

range, already demanded by Japan and Great Britain.

A flexible test concept operating at component level as well

as at system level is provided to support users in designing

and manufacturing their systems. The following test options

are integrated into the SICOFI-4:

Applications

PBXs:

• 4 analog lines for subscribers and trunks

CO:

• Interface for four analog subscribers

• BIST (built-in self test) in the digital part

• Boundary scan as per IEEE 1149.1

• Functional testing with various test loops

• Simple stimulation by two built-in DTMF (Dual Tone

Multifrequency) tone generators

• Function self test using what is known as the “level

metering function” with which not only the chip but also the

SLIC connected to it can be tested (system test).

Interfaces

• 4 × t/r interface

• IOM-2 interface

• Eight l/O signaling pins per channel

• Boundary scan

The powerful, modular IOM-2 interface implemented

on the allows minimal wiring to be used on the board and

thereby a low-cost design. A suitable controller (e.g. the

ELIC, PEB 20550-H) is used to direct the relevant

coefficients for filter programming and the required control

signals as well as the voice signals to the SICOFI-4. Signals

from the SLIC can be issued by the SICOFI-4 to the IOM-2

interface and read out under interrupt control. This

significantly reduces the load on the microcontroller.

Siemens Aktiengesellschaft

97

Signal Processing Codec Filter (SICOFI^®-4)

PEB 2465

D

A

Analog OUT

A

D

A

Analog IN

D

DSP

D

A

Analog OUT

Analog IN

A

D

A

Analog IN

D

Command

Signaling

Indication

Command

Indication

®

IOM -2

Signaling

Command

Signaling

Indication

Command

Indication

ITS05889

®

IOM -2 Bus

Block Diagram

Siemens Aktiengesellschaft

98

Signal Processing Codec Filter (SICOFI^®-4

µC)

PEB 2466

General Description

Type

Package

P-MQFP-64-1 (SMD)

The PEB 2466 SICOFI-4 µC, is a programmable codec with

filter functions for four channels. Due to an advanced digital

filter concept based on a DSP, analog line cards can be

easily adopted to different country specifications and SLICs.

The device can be directly connected to two PCM highways

at flexible data rates. The coefficients to modify gain,

frequency response, transhybrid loss and impedance

matching are calculated via a specific software (QSICOS)

and send to the codec, for each channel individually, via the

microcontroller interface.

PEB 2466-H

Features

• Four channel single chip codec and filter

• Specifications according to the relevant CCITT, EIA and

LSSGR recommendations

• Programmable digital filters for adapting transmission

behaviour according to different country specifications

– AC impedance matching

– Transhybrid balancing

– Frequency response

Applications

– Gain

• Analog line cards for CO and PBXs

• Fiber to the curb applications

• Access networks and multiplexers

• Set-top-boxes

– a/µ-Law expansion/compression

• Programmable interface to electronic SLICs and

transformer solutions

• Two flexible programmable PCM interfaces (data rate from

128 kbit/s up to 8192 kbit/s)

• Serial microcontroller interface

• PCM4/PCM8 systems

• Intelligent NTs

.

• High analog driver capability (300 Ω, 50 pF)

• Very low power dissipation (typ. 35 mW/channel)

• Two programmable tone generators (DTMF possible)

• Level metering function for testing of analog input signals

• 7 SLIC-signaling interfaces per channel (programmable

debouncing)

• Single power supply of 5 V (allows to get rid of the – 5 V

supply)

• P-MQFP-64 package

4 x Analog I / O

PCM Highway A Transmit

PCM Highway A Receive

®

SICOFI

-4-µC

PCM Highway B Transmit

PCM Highway B Receive

7 x Signaling ch 1

7 x Signaling ch 2

7 x Signaling ch 3

7 x Signaling ch 4

Interrupt Channel 1/2

Interrupt Channel 3/4

µC Interface

ITB08487

Block Diagram

Siemens Aktiengesellschaft

99

Kit (HV-SLIC and SLICOFI^®)

PEB 3065

PEB 4065

PEB 3065 (SLICOFI^®) General Description

Type

Package

The Signal Processing Subscriber Line Interface Codec Filter

SLICOFI is a logic continuation of the well established family

of the Siemens DSP Codec-Filter ICs with the vertical

integration of all DC-feeding, supervision and PL meterpulse

injection features on-chip as well. Fabricated in a standard

1 µm BiCMOS technology the SLICOFI is tailored for very

flexible solutions in digital communication systems. For the

first time the SLICOFI uses the benefits of a DSP not only for

the voice channel but even for line feeding and supervision

which leads to a very high flexibility without the need for

external components.

PEB 3065-N

PEF 3065-N

P-LCC-44-1 (SMD)

PEB 3065 (SLICOFI^®) Features

• Single chip CODEC and FILTER including all LOW

VOLTAGE SLIC functions

• Only few external components required

• No trimming or adjustments required

• Specification according to relevant CCITT, LSSGR and

DBP recommendations

Based on an advanced digital filter concept, the PEB 3065

provides excellent transmission performance. The new filter

concept leads to a maximum of independence between the

different filter blocks. Each filter block can be seen as a one

to one representative of the corresponding network element.

Together with the software package SLICOS, filter optimizing

to different applications can be done in a clear and straight

forward procedure. The AC frequency behaviour is mainly

determined by the digital filters. Using the new oversampling

1-bit Σ∆-AD/DA converter, linearity is only limited by second

order parasitic effects.

• Digital signal processing technique

• Advanced low power 1 µm BiCMOS technology

• PCM encoded digital voice transmission (A-Law or µ-Law)

• Four pin serial IOM-2 interface

• High performance A/D and D/A conversion

• Programmable digital filters for

– impedance matching

– transhybrid balancing

– frequency response

– gain

• Advanced test capabilities

– integrated line and circuit tests

– 6 digital loops

– 5 analog loops

– two programmable tone generators

• Optimized HV-SLIC interface

The new – digital – solution of line feeding offers free

programmability of feeding current and voltage as well as

very fast settling of the DC operating point after transitions. A

0.4-Hz lowpass filter in the DC loop is mainly responsible for

the system stability.

• Fully digital programmable DC characteristic

– programmable constant current from 0 – 70 mA

– programmable resistive values from 0 – 2 × 500 Ω

• Programmable integrated Teletax injection and filtering

during conversation and onhook

– programmable up to 125 mVrms (5 Vrms at a/b wire)

programmable frequency 12/16 kHz

• Polarity reversal (programmable soft or hard)

• Integrated (balanced) ringing generation with zero

crossing injection

Additionally telefax generation and filtering is implemented

as well as free programmable (balanced) ring generation with

zero crossing injection. Offhook detection with

programmable thresholds is possible in all operating modes.

To reduce overall power consumption of the line card, the

SLICOFI provides a special mode called Power Denial where

offhook is done via two high voltage inputs (VLINE) directly

connected to the line since the HV-SLIC is switched off.

– programmable frequency between 16.6 and 70 Hz

– Programmable amplitude up to 2.125 Vrms (85 Vrms at

a/b wire)

• Four operating modes: power-denial, power-down, active

and ringing

• Offhook detection with programmable thresholds for all

operating modes

• Integrated ring trip detection with zero crossing turn off

function

• Ground start and loop start possible

• Integrated checksum calculation for CRAM

• Line card identification

• Also available with extended temperature range – 40 °C to

85 °C (PEF 3065-N)

Siemens Aktiengesellschaft

100

U/T (HV-SLIC and SLICOFI^®)

PEB 3065

PEB 4065

PEB 4065 (HV-SLIC) General Description

Type

Package

The High Voltage Subscriber Line IC PEB 4065 is a rugged

and reliable interface between the telephone line and the

SLICOFI, a low voltage Subscriber Line Interface and Codec

Filter IC. The PEB 4065 is fabricated in a Smart Power

Technology offering a breakthrough voltage of at least 170 V.

PEB 4065-T

PEF 4065-T

P-DSO-20-5 (SMD)

PEB 4065 (HV-SLIC) Features

The PEB 4065 provides battery feeding between – 24 V and

– 80 V and internal ringing injection with a differential ring

voltage up to 85 Vrms. In order to achieve these high

amplitudes an auxiliary positive battery voltage is used

during ringing. This voltage can also be applied in order to

drive very long telephone lines.

• High voltage line feeding

• Internal ring and metering signal injection

• Sensing of transversal and longitudinal line current

• Reliable 170 V Smart Power Technology

• Battery voltage – 24 V…– 80 V

• Boosted battery mode for long telephone Iines and up to

85 Vrms balanced ringing

The HV-SLIC is designed for a voltage feeding current

sensing line interface concept and provides sensing of

transversal and longitudinal current on both wires.

• Polarity reversal

• Small P-DSO-20-5 power package

• Also available with extended temperature range – 40 °C to

85 °C (PEF 4065-T)

There is a power-down mode reducing power consumption

while providing all supervision functions and a power-denial

mode where the device is switched off turning the line outputs

to a high impedance state.

Customer

Line

Central Office

TM

SLICOFI

PEB 3065

Hybrid for

Telefax Filter

HV-SLIC

PEB 4065

®

170 V

± 5 V

LV-SLIC

SICOFI

IOM -2

Hybrid for

External Indication

ITS05982

Block Diagram

Siemens Aktiengesellschaft

101

Digital Line Cards

ISDN Echo Cancellation Circuit

IEC-Q; PEB 2091

Siemens Aktiengesellschaft

103

Digital Line Cards

Product Overview

Type

Short Title

Function

Page

PEB 2026

PEF 2026

IHPC

ISDN High Voltage Power Controller

106

PEB 2070

PEB 2075

PEB 2080

PEB 2081

PEB 2084

PEB 2091

ICC

IDEC^®

ISDN Communications Controller

107

109

110

111

112

113

114

ISDN D-Channel Exchange Controller (4 channel)

S-Bus Interface Circuit

SBC

SBCX

QUAT^®-S

IEC-Q

IEC-T

S/T-Bus Interface Circuit Extended

Quadruple Transceiver for S/T Interfaces

ISDN Echo Cancellation Circuit (2B1Q-line code)

ISDN Echo Cancellation Circuit (4B3T-line code)

PEB 20901

PEB 20902

PEB 24901

Quad IEC DFE-T

Quad IEC AFE

Quad ISDN Echo-Cancellation Digital Front End (4B3T)

Quad ISDN Echo-Cancellation Circuit Analog Front End

116

117

PEB 24902

PEF 24902

PEB 24911

PEF 24911

Quad IEC DFE-Q

Quad ISDN Echo-Cancellation Digital Front End (2B1Q)

ISDN Burst Transceiver Circuit

118

PEB 2095

PEB 2096

PEB 2025

PEB 20560

PEB 2054

PEB 2055

PEB 20550

IBC

OCTAT^®-P

119

120

121

122

90

Octal Transceiver for U interfaces

PN

IEPC

ISDN Exchange Power Controller

DOC

DSP Oriented PBX Controller

EPIC^®-1

EPIC^®-S

ELIC^®

Extended PCM Interface Controller

Extended PCM Interface Controller-Small

Extended Line Card Interface Controller

High-Level Serial Communication Controller Extended

91

92

SAB 82525

SAB 82526

HSCX

HSCX1

162

PEB 2085

PEB 2086

ISAC^®-S

ISDN Subscriber Access Controller

61

Siemens Aktiengesellschaft

104

Digital Exchange Systems

General Overview on Architecture and Devices

t / r

Subscriber Units

Switching

Systems

Group

Processors

Analog Line Cards

DAML

®

SICOFI

PIC

MTSS

MTSC

MTSL

DAML-RT

DAML-COT

®

t / r

SICOFI -2 EPIC -S

®

SICOFI -4 EPIC

U

TM

®

SLICOFI

SLIC

ELIC

HSCX

MUSAC -A

®

EPIC -S

®

HV-SLIC

EPIC -1

®

ELIC

Digital Line Cards

HSCX

ESCC2 / 8

MUNICH32

DOV

U

(Basic Rate)

t / r

®

SBC

SBCX

EPIC -S

®

EPIC -1

®

QUAT -S ICC

®

ISAC -S

IEC-T

IEC-Q

IBC

IDEC

ELIC

Trunk Units

ACFA

Transmission

Exchange

HSCX

IEPC

S / T

®

Concentrator

Multiplexer

®

OCTAT -P

IPAT -2

HSCX

PRISM

ESCC2

U

ESCC8

TM

(Primary Rate)

FALC

54

®

ACFA

IPAT -2

PRACT

HSCX

ESCC2 / 8

PRISM

FALC

S

TM

54

NT

RPT

PCM

Highway

ITA03688

Siemens Aktiengesellschaft

105

ISDN High Voltage Power Controller (IHPC)

PEB 2026

General Description

Type

Package

The IHPC is an integrated power controller especially

designed for feeding two-wire ISDN-transmission lines. One

line can be powered by one IHPC. An external resistor

defines the value of the current-limit for the line. Powering

can be switched on or off by the logic inputs “PFEN” and

“PFENQ”. With a logic low at the “APFI” output the IHPC

signals that current-limiting is active; this signal is low-pass

filtered. An external capacitor defines the corner frequency of

this low-pass filter and the resulting delay time respectively. A

second external capacitor is needed to make sure that

longitudinal disturbance (AC) will not produce a current

limiting effect. Line current-limiting and reducing this limiting

level in case of overtemperature guards the IHPC against

overloads.

PEB 2026T-P

PEB 2026T-S

PEF 2026T-P

PEF 2026T-S

P-DSO-20-10 (SMD)

P-DSO-20-6 (SMD)

P-DSO-20-10 (SMD)

P-DSO-20-6 (SMD)

Features

• Battery voltage up to 130 V

• Supplies power for one transmission line

• Current limiting and chip temperature control

• Limiting current can be programmed by an external

resistor

• Automatically reduced feeding current in case of

overtemperature

• Reliable 170 V Smart Power Technology (SPT 170)

• Small P-DSO-20 package

V

DD

REF

C

HP

TP

CP

CN

REF

GND D

CTP

GND B

I

Bandgap

AC

5 Ω

I-SENS

I

REF

RB

PFEN

I

TH=PROT

T

I

≥1

TH-PROT

PFENQ

APFI

RA

TP

T

I

L

Limit

D

OP

P

4 Ω

4 kΩ

V

BAT

ITB07375

Block Diagram

Siemens Aktiengesellschaft

106

PEB 2070

ISDN Layer-2 Protocol Controllers

ISDN Communications Controller (ICC)

General Description

Type

Package

While the IOM structure supports high flexibility with respect

to layer-1 of data transmission, the ISDN communications

controller can be used in all applications for link access

protocol control. This is of great importance regarding

production volume, software continuity and engineering effort

necessary for the use of the complex circuit. For further

reduction of software, high-level layer-2 support has been a

main target of circuit definition.

PEB 2070-N

PEB 2070-P

PEF 2070-N

P-LCC-28-1 (SMD)

P-DIP-24-1 (not for new designs)

P-LCC-28-1 (SMD)

Features

• High-level support of LAPD-protocol

• FlFO-buffer (64 bytes per direction) for efficient transfer of

D-channel messages

• IOM interface compatible (IOM-1 or IOM-2)

• Standard parallel microprocessor interface

• Support of activation/deactivation procedure

• Variety of operating modes

• µP access to B-channels and IOM-intercommunication

channels

• Control of peripheral devices via IOM Monitor and C/l-

channel protocols

D-channel protocol handling is the main task of the ICC. Its

characteristic features are determined by an on-chip LAPD

controller and a sophisticated FlFO-structure. The LAPD

controller performs multiframe operation largely

autonomously with a window size of 1. All S- and l-frames,

including the address and control fields, are evaluated in the

ICC. Depending on the status of the controller, positive or

negative acknowledgements are generated without

interrupting the CPU. When the procedure is terminated, an

interrupt status is generated to inform the CPU of the status

of the procedure. To enable the ICC device to be used in

complex protocol applications with window size of up to 7, a

transparent mode is implemented. In this mode the layer-2

headers are transferred transparently to the CPU.

• 2-µm CMOS technology and low power consumption:

Standby: 2 mW

Active:

4 mW at 512 kHz

The synchronization of the 16-kbit/s D-channel with the CPU-

bus is performed by buffers with a capacity of 64 bytes per

direction. Sophisticated buffer controllers allow overlapping

input/output operation, which ensures that the maximum

packet length is not limited by the buffer size.

This feature greatly reduces the dynamic load of the

microprocessor system.

Siemens Aktiengesellschaft

107

ISDN Communications Controller (ICC)

PEB 2070

DCL FSC

Timing Unit

SDAR

B-Channel

Switching

SSI

(Serial

Port A)

SDAX / SDS1

®

IDP0

IDP1

IOM

SCA / FSD / SDS2

(Serial

Port B)

SLD

SIP / EAW

HDLC

LAPD

Receiver Transmitter

Controller

Status /

Command

Registers

FIFO

X-FIFO

R-FIFO

Controller

2 x 32 byte

RES

V

SS

µP-Interface

V

DD

AD0 - AD7

(D0 - D7)

(A0 - A5)

RD (DS) WR (R / W)

ALE

ITB00704

Block Diagram

Siemens Aktiengesellschaft

108

ISDN D-Channel Exchange Controller (IDEC^®)

PEB 2075

General Description

Type

Package

With the IOM-2 interface, designers have more flexibility with

respect to handling of D-channel information. Layer-1

transceivers are connected over the IOM-2 interface directly

to either the PEB 2055 (EPIC-1) or the PEB 2054 (EPIC-S).

PEB 2075-N

PEB 2075-P

PEF 2075-N

P-LCC-44-1 (SMD)

P-DIP-28-1 (not for new designs)

P-LCC-44-1 (SMD)

These devices are capable of switching not only the

B-channels but also the D-channel. Thus, the designer can

decide whether he wants to process D-channel signaling

information decentralized, on the line card, or pass it through

to be processed centrally.

Features

• Four independent HDLC channels

• 64-byte FIFO buffering per channel and direction

• Handling of basic HDLC functions

• Single or quad connection to serial transmission lines

• IOM- or PCM interfaces

• Programmable time-slots and channel data rates (up to

4 Mbit/s)

• Collision detection and resolution circuitry for shared

time-slots

• 8-bit parallel µP interface with vector interrupt

• Advanced low power CMOS technology: 50 mW

The IDEC has been optimized for processing the D-channel

signaling information on digital exchange line cards. Four

independent HDLC controllers have been implemented on a

single IC. Thus, one IDEC can handle the D-channels of up to

four subscriber lines.

The IDEC is based on the same core architecture as the

PEB 2070 ICC, but has been optimized for exchange line

cards and then repeated four times.

CDR

SD0X SD0R SD1X SD1R SD2X SD2R SD3X SD3R

Serial Interface Logic

DCL

FSC

Timing

Switching

Collision

Control

Timing

Switching

Collision

Control

Timing

Switching

Collision

Control

Timing

Switching

Collision

Control

TSC

HDLC

Receiver

Transmitter

Receiver

Transmitter

Receiver

Transmitter

Receiver

Transmitter

RFIFO XFIFO

Microcontroller Interface

8

ITB00728

Block Diagram

INT

AD0 - AD7

RD

WR

CS

ALE

RES

Siemens Aktiengesellschaft

109

PEB 2080

ISDN Layer-1 Transceivers

S-Bus Interface Circuit (SBC)

General Description

Type

Package

The four-wire S-interface between subscriber terminals and

network termination has been standardized by CCITT

recommendation I.430. Making use of a passive bus which

provides separate receiver and transmit loops operating at

192-kbit/s, up to eight terminals can be connected to the

network termination. In case more than one terminal want to

access the bus at the same time, a procedure is provided for

resolving the collision problem. Since all layer-1 functions

such as frame structure, data rate, power feeding,

PEB 2080-N

PEB 2080-P

PEF 2080-N

P-LCC-28-1 (SMD)

P-DIP-22-1 (not for new designs)

P-LCC-28-1 (SMD)

Not for new development.

For new development use the SBCX (PEB 2081)

transceiver characteristics, activation/deactivation and

subscriber access procedure are well defined, the S-bus can

be considered an important tool for standardization of data

communication equipment. It supports connections with a

maximum length of 1 km in a point to-point and 150 m in a

point-to-multipoint bus configuration.

Features

• S-bus transceiver according to CCITT I.430

• Recovery of clock and frame signals in different modes of

application.

• Frame alignment for trunk module application

• IOM interface compatible (IOM-1)

• Handling of command/indication information during the

activation/deactivation procedure

• Switching of test loops

• Control of bus access by echo-bit handling

• Wake-up unit for activation from power-down state

• Several operating modes including trunk applications with

frame alignment

• 2-µm CMOS technology and low power consumption:

Standby: 4 mW

The SBC is designed to meet all CClTT requirements, and,

moreover, implements additional features necessary in

specific applications. The device contains the transceiver

function, timing recovery for the different modes of operation,

circuitry for the collision resolution function and a state

control block to handle the activation/deactivation

procedures autonomously without the support of a

microprocessor. A flexible buffer structure performs the

frame-alignment function in PBX-trunk applications, where

the system clock deviates from the central office clock

derived from the line. Matching of the actual line attenuation

is supported by receiver circuitry which contains adaptively

adjustable thresholds.

Active:

max. 60 mW at 512 kHz

R

REF

AMI

BIN

SX1

SX2

Buffer

SDI

D-CH

3

Control

Mode

SDO

AMI

BIN

SY1

SY2

Buffer

4

Special

Purpose

TCLK RCLK

PLL

DCL

FSC

CP

ITB03957

Block Diagram

Siemens Aktiengesellschaft

110

S/T-Bus Interface Circuit Extended (SBCX)

PEB 2081

General Description

Type

Package

P-LCC-28-1 (SMD)

The PEB 2081 S/T-Bus Interface Circuit Extended (SBCX)

implements the four-wire S/T interface used to link voice/data

ISDN terminals, network terminators (NT) and PBX-trunk

lines to a Central Office exchange. The components switches

B- and D-channels between the S/T and the ISDN Oriented

Modular (IOM-2) interfaces, the latter being a standard

backplane interface for the ISDN-basic access. The SBCX

exceeds both the electrical and functional requirements of

the S/T interface in order to provide high flexibility to the user.

PEB 2081-N

Features

• 1-channel S/T transceiver

• Full duplex 2+D S/T transceiver according to CCITT I.430

• Extended loop length up to 2 km

• Activation and deactivation procedures according to

CCITT I.430

• Fully compliant NT2 trunk mode including multipoint

operation

Applications

• Frame alignment with absorption of phase wander in NT2

network side applications

• Receive timing recovery for point-to-point, passive bus

and extended passive bus configuration

• Access to S- and Q-bits of S/T interface (S1-, S2- and

Q-channel)

• Network terminators (NT and NT2)

• S multiplexer cards

0

• S line cards for ISDN-trunk lines

0

• Voice/Data Terminals, ISDN-PC Cards

• D-channel access control also in trunk applications

• Execution of test loops

• Conversion of frame structure between S/T interface and

IOM-2

• Advanced CMOS technology with low power consumption

(standby < 6 mW, active 80 mW)

FSC

DCL

SX 1

SX 2

Transmit

Buffer

IPD 1

IPD 0

®

IOM

Interface Logic

Activation

Control

D-Channel

Control

SR 1

SR 2

E/Q Bit

Handler

Receive

Buffer

DPLL

ITB03958

Block Diagram

Siemens Aktiengesellschaft

111

Quadruple S/T-Transceiver (QUAT^®-S)

PEB 2084

General Description

Type

Package

P-MQFP-44-1 (SMD)

The PEB 2084, QUAT-S, implements 4 × four-wire S/T

interfaces used to link ISDN terminals to PBXs or PBX to

NTs. The component switches B- and D-channels between

the S/T and the ISDN Oriented Modular (IOM-2) interfaces,

the latter being a standard backplane interface for the ISDN-

basic access. Each of the four S/T-channels implemented in

PEB 2084-H

Features

• 4-channel S/T transceiver

• Full duplex 2B+D S/T transceiver according to

CCITT I.430, ETSI 300.012 and ANSI T1.605

• Receive timing recovery according to selected operating

mode

• Conversion of frame structure between S/T interface and

IOM-2

the device can be individually assigned for S - or T interface.

0

Applications

• Digital line cards for ISDN subscribers

• Digital line cards for ISDN-trunk lines

• Multiplexers

• Access to S- and Q-bits of S/T interface

• Execution of test loops

• Set-top-boxes

• Support of star configurations (external common echo bit)

• Support of D-channel collision resolution in trunk mode

• Full support of arbiter concept of the ELIC (PEB 20550)

• Support of synchronization of cordless applications

• Low power consumption (< 100 mW)

• Loop length > 1.5 km

• JTAG-boundary scan test interface

• P-MQFP-44 package

S / T

Transceiver

R 0

CLK 1 / IDS

Clock

Generator

T 0

CLK 2

0

S / T

Transceiver

1

R 1

T 1

FSC

DCL

IDI

®

IOM

-2

Interface

IDO

S / T

Transceiver

2

CEB / SSYNC

DRDY

ICS

R 2

T 2

S / T

Transceiver

3

R 3

T 3

JTAG

ITB08490

Block Diagram

Siemens Aktiengesellschaft

112

ISDN Echo-Cancellation Circuit (IEC-Q)

PEB 2091

General Description

Type

Package

The PEB 2091, IEC-Q, is a single chip full-duplex

PEB 2091-N

PEF 2091-N

P-LCC-44-1 (SMD)

U-transceiver device meeting the latest American- (ANSI)

and European (ETSI) specifications. It is based on a coding

scheme reducing two binary information into a single

quaternary code. This coding requires a reduced

transmission rate of only 80 kbaud on a twisted copper pair,

minimizing signal attenuation and guaranteeing the highest

transmission rate of all defined U-interface standards.

• Recovery of clock and frame signals from

• the data stream

• Handling of command/indication information during

activation/deactivation procedure

• Switching of test loops

• Wake-up unit for activation from power-down state

• Several operating modes including trunk applications with

frame alignment (LT, NT, TE, Repeater)

• Transmission range of 5.5 km (18 kft)

with 0.4 mm (26 AWG) wire

• U-only activation

• Power feeding control

• Repeater mode

• Echo overload compensation to match ETSI and ANSI test

loops

The PEB 2091 was defined to operate in all ISDN (Line

cards, Network Terminators, Terminals, PBXs and

Repeaters) and non-lSDN (DAML) applications.

Features

• Full-duplex two-wire U-transceiver meeting the

following layer-1 specifications:

ANSI T1.601-1991

CNET ST/LAA/ELR/DNP/822

ETSI DTR/TM 3002

Recommendation CCITT, G961

• 144-kbit/s user bit rate (2B+D)

• 160-kbit/s total bit rate including maintenance and

synchronization

• Dynamic phase adaptation

• 1-µm CMOS technology standby: 70 mW

active: 350 mW

• Low transmission frequency of 80 kbaud by using

the 2B1Q-block line code

• IOM interface compatible

• Adaptive echo cancellation and equalization

using digital filtering

AIN

BIN

A

U-Interface

Receive

Formatter

FSC

DCL

DOUT

DIN

Adaptive

Amplifier,

Equatizer

& Echo

D

®

IOM

Interface

Level

Detect

2B + D

Canceller

U-Interface

Receive

Formatter

Timing

Recovery

& Generator

XTAL1

XTAL2

Oscillator

PLL

AOUT

BOUT

D

A

Mode Control

Microprocessor Interface

PMODE

IEC-Q

MPU Interface or Mode Select

ITB03960

Block Diagram

Siemens Aktiengesellschaft

113

ISDN Echo-Cancellation Circuit (IEC-T)

PEB 20901

PEB 20902

General Description

Type

Package

The most challenging requirement in ISDN is full-duplex

transmission at a data rate of 144 kbit/s over the existing

twisted-pair telephone cables (U-interface). Among several

approaches for solving this problem, ping-pong time-

compression multiplexing and echo cancellation have been

proposed as most suitable for VLSI implementation.

Moreover, echo cancellation has proven to be the best

method for public lines which typically reach lengths in the

range of 8 km.

PEB 20901-N

PEB 20901-P

PEF 20902-N

PEB 20902-P

PEF 20901-N

PEF 20902-N

P-LCC-44-1 (SMD)

P-DIP-40-1 (not for new designs)

P-LCC-28-2 (SMD)

P-DIP-24-1 (not for new designs)

P-LCC-28-2 (SMD)

After a careful study of different transmission codes, a 4B3T

block code was chosen for the IEC-T which make use of

ternary coding of the binary information. A particular

Features

• Full-duplex two-wire U-transceiver

• 144-kbit/s user bit rate (2B+D)

advantage of this code is its low frequency, DC-free

performance spectrum with its energy peak at about 40 kHz.

In this context, for a bit rate of 160 kbit/s the required baud

rate is as low as 120 kHz. As a result transmission systems

benefit from, low line attenuation low crosstalk distortion and

high possible signal levels without causing EMI-problems.

• 160-kbit/s total bit rate including maintenance and

synchronization

• Low transmission frequency of 120 kbaud by using the

4B3T-ternary block code

• Adaptive echo cancellation and equalization using digital

filtering (DSP)

• Recovery of clock and frame signals from the data stream

• IOM-1 interface compatible

The IEC-T is offered as a two chip solution consisting of:

• Digital part, called PEB 20901

• Analog part, called PEB 20902

• Transmission range up to 8 km with 0.6-mm wires

• Handling of command/indication information during

activation/deactivation procedure

• Switching of test loops

• Wake-up unit for activation from power-down state

• Several operating modes including trunk applications with

frame alignment

• 2-µm CMOS technology for PEB 20902, 1-µ technology for

PEB 20901

• 320-mW power consumption

• Repeater mode with no external devices

Siemens Aktiengesellschaft

114

ISDN Echo-Cancellation Circuit (IEC-T)

PEB 20901

PEB 20902

B + B + D

Scrambler

144 kbit / s

Pulse / Shaping

D / A

Post Filter

Frame

MUX

Coder

MM 943

M

Barker

Code, Syn

Word Gen.

Awake

Unit

7.5 kHz

SDI

Control

U

k0

SDO

®

Coeff.

Adapter

Echo

Canceller

IOM

Hybrid

Timing

Gen.

Timing

Recovety

Interface

Unit

CLK

TMS

Coeff. Read

M

Coeff.

Adapter

Code

Error

A

Decoder

Descram-

bler

Equalizer

Receiver

Detector

Dig.

AGC

Dig.

Add.

Dig.

BP

DEMUX

D

B + B + D

144 kbit / s

ITB03959

Block Diagram

Siemens Aktiengesellschaft

115

4 Channel ISDN Echo-Cancellation Digital Front

End (Quad IEC DFE-T)

PEB 24901

Advanced Information

General Description

Type

Package

P-MQFP-64-1 (SMD)

PEB 24901

The PEB 24901 4 Channel ISDN Echocancellation Digital

Front End (Quad IEC DFE-T) is the digital part of an

optimized ISDN 4B3T U-interface line card chip set. It

features 4 independent digital signal processors providing, in

conjunction with the PEB 24902 ISDN Quad Analog Front

End (Quad IEC AFE), full duplex data transmission at the

• Clock recovery (frame and bit synchronization)

• Transposition of ternary to binary data and vice versa

(coding, decoding, scrambling, descrambling, phase

adaption)

• Built-in wake-up unit for activation from power-down state

• Acvtivation and deactivation procedure according to

CCITT I.430 and to FTZ Guideline 1 TR 210 of the DBPT

• Optimized for working in conjunction with telecom ICs as

the IDEC (PEB 2075), EPIC (PEB 2055) and ELIC

(PEB 20550) via IOM-2 interface

U -reference point according to FTZ Guideline 1TR 220,

k0

ETSI ETR80 and CCITT I.430 standards. The PEB 24901/

24902 chip set is based on the PEB 20901/20902 IEC-T

ISDN U-transceiver chip set. The PEB 24901 comes in a

P-MQFP-64 package.

• Data speed conversion between the U frames and the

k0

IOM-2 frames. Absorption of received phase-wander of up

to 18 µs peak-to-peak (CCITT Rec. Q.512)

Features

• Handling of commands and indications contained in the

IOM-2 C/I-channel for activation, deactivation, supervision

of power supply unit and equipment for wire testing

• IOM-2 system interface

• Full duplex transmission and reception of the U -interface

k0

signals according to the FTZ Guideline 1 TR 220 of the

Deutsche Bundespost Telekom (DBPT).

– 144-kbit/s user bit rate over standard local telephone

loops

– 1-kbit/s maintenance channel for transmission of data

loop back commands and detected transmission errors

– 4B3T-ternary block code (subscriber line symbol rate

120 kbaud)

• Data availability via the Monitor channel:

– Accumulated RDS-transmission errors for the whole

U

link

k0

– Echo canceller coefficients and status values, which

can be used to indicate the state of the U interface

k0

• Switching of an analog test loop at the U interface for

k0

– Monitoring of transmission errors

– Subscriber loop length without repeater:

up to 4.2 km on 0.4 mm wire

testing (loop in LT)

• Remote control of test loop switching via maintenance

channel

• 4 relay driver pins per port addressable by Monitor

command

• 2 status pin per port reporting to the Monitor channel

• JTAG-boundary scan path

up to 8.0 km on 0.6 mm wire

• Adaptive echo-cancellation

• Adaptive equalization

• Automatic polarity adaption

®

IOM

- 2

JTAG - Boundary Scan

4 U - Interfaces

DOUT

DIN

SDX

SDR

HYBRID

PEB 24901

Quad IEC DFE - T

PEB 24901

Quad IEC AFE

DCL

15.36 MHz

PDM 0 ... 3

FSC

15.36 MHz

ITL08609

Four Channel LT Application

Siemens Aktiengesellschaft

116

Quad ISDN Echo-Cancellation Circuit Analog Front End (Quad IEC AFE)

PEB 24902

Advanced Information

Type

Package

PEB 24902

PEF 24902

P-MQFP-64-1 (SMD)

General Description

The PEB 24902 Quad IEC AFE (Quadruple ISDN

Echocancellation Circuit Analog Front End) is part of a 2B1Q

or 4B3T ISDN U-transceiver chip set. Up to four lines can be

accessed simultaneously by the Quad IEC AFE. The Quad

IEC AFE is optimized to work in conjunction with the

PEB 24901 Quad IEC DFE-T and the PEB 24911 Quad IEC

DFE-Q. An integrated PLL synchronizes the 15.36-MHz

master clock onto the 8-kHz or 2048-kHz PTT clock. This

specification describes the functionallity for 2B1Q and 4B3T

interfaces.

Features

• Digital to analog conversion (transmit pulse)

• Output buffering

• Analog to digital conversion

• Detection of signal on the line

• Master clock generation by PLL

• P-MQFP-64 package

• Compliant to ANSI T1.601 (1992), ETSI ETR 080 (1995)

• JTAG-boundary scan path compliant to IEEE 1149.1

• Extended temperature range – 40 °C to 85 °C available

(PEF 24902)

DFE

Interface

Digital

Interface

D

Buffer

A

Trafo

Hybrid

Analog

IN / Out

A

Level

D

Voltage Reference

Common

PLL

D

Buffer

A

Trafo

Hybrid

Analog

IN / Out

A

Level

D

Voltage Reference

ITB07132

Block Diagram

Siemens Aktiengesellschaft

117

Quad ISDN 2B1Q Echocanceller Digital Front End (Quad IEC DFE-Q)

PEB 24911

Advanced Information

Type

Package

PEB 24911

PEF 24911

P-MQFP-64-1 (SMD)

General Description

The PEB 24911 Quad ISDN 2B1Q Echocanceller Digital

Front End (Quad IEC DFE-Q) is the digital part of an

optimized ISDN 2B1Q U-interface line card chip set. It

features 4 independent digital signal processors providing, in

conjunction with the PEB 24902 ISDN Quad Analog Front

• Meets transmission requirements for loop #1 through #8 of

ETSI’s 8 telephone plant test loops

• Built-in wake-up unit for activation from power-down state

• Adaptive echo-cancellation

End, full duplex data transmission at the U -reference point

k0

according to ANSI T1.601, ETSI ETR80, CCITT G.961 and

CNET ST/LAA/ELR/DNP/822 standards. The PEB 24911/

PEB 24902 chip set is based on the PEB 2091 IEC-Q V4.4

single chip ISDN U-transceiver. The IEC-Q V4.4 is approved

by Bellcore. The PEB 24911 comes in a P-MQFP-64

package.

• Adaptive equalization

• Automatic polarity adaption

• Clock recovery (frame and bit synchronization) in all

applications

• Automatic gain control

• Low power consumption

• Extended temperature range – 40 °C to 85 °C available

(PEF 24911)

• U-interface propagation delay measurement with better

than ± 300-ns resolution

• LT-PBX mode allowing D-channel arbitration and

synchronization of DECT-base stations

• IOM-2 system interface

• 4 relay driver pins per port addressable by Monitor

command

Features

• Full duplex transmission and reception at the U-reference

point compliant to:

ANSI T1.601-1992,

CNET ST/LAA/ELR/DNP/822,

ETSI ETR 080 1993.

• Recommendation CCITT, G.961

• 144-kbit/s user bit rate over a two-wire subsriber loop

• 2B1Q-block code (2 binary, 1 quaternary)

• 80-kHz symbol rate

• Activation and deactivation procedure

• Meets transmission requirements for loop #1 through loop

#15 of ANSI‘s 15 telephone plant test loops

• Meets transmission requirements for loop #1 through #6 of

CNET’s 6 telephone plant test loops

• 2 status pins per port reporting to the Monitor channel

• Activation procedure with the 15 s limit disabled to cope

with regenerators

• JTAG-boundary scan path

®

IOM -2

8 U-Interface

PDM 0 ... 3

HYBRID

PEB 24911

IEC QUAD DFE-Q

PEB 24902

IEC QUAD AFE

DOUT

DIN

DCL

FSC

SDX

SDR

HYBRID

15.36 MHz

HYBRID

JTAG-

Boundary

Scan

15.36 MHz

HYBRID

SDX

SDR

HYBRID

PEB 24911

IEC QUAD DFE-Q

PEB 24902

IEC QUAD AFE

PDM 0 ... 3

HYBRID

ITS06906

8 Channel LT Application

Siemens Aktiengesellschaft

118

ISDN Burst Transceiver Circuit (IBC)

PEB 2095

General Description

Type

Package

In addition to four-wire S-interface terminals, the IOM

architecture also supports two-wire terminals for PBX

applications. A survey of PBX-loop conditions demonstrates

that typically 95% of the subscriber loops show line lengths

below 2 km. Therefore, a more economical solution which is

optimized to these shorter loop lengths is required.

PEB 2095-N

PEB 2095-P

P-LCC-28-2 (SMD)

P-DIP-24-1 (not for new designs)

Features

• Half-duplex burst-mode two-wire transceiver

• 144-bit/s user bit rate (B+B+D)

• 384-kHz line clock rate including maintenance and

synchronization

A time-compression multiplex concept has been chosen

which – for separation of direction – divides the framing into

a transmit and receive section. Taking synchronization bits

and line conditions into account, a clock rate of 384 kbit/s,

twice as high as for the S-bus, has been found to be optimal

with respect to time compression, interference line

attenuation and delay. The transceiver uses AMI coding,

scrambling, automatic gain control and √f-equalizing to

obtain excellent transmission quality.

• U interface, industry standard for

P0

2-wire PBXs (AMI-line code)

• IOM-interface compatible (IOM-1 or IOM-2)

• Adaptive line equalization (SC filter)

• Recovery of clock and frame signals from data stream

• Activation/deactivation procedure according to CClTT

recommendation

• Awake in power-down mode

• Switching of test loops

• Transmission range up to 3.5 km with 0.6-mm wire

• 2-µm CMOS technology

• Low power consumption

Active:

Power-down:

From a system point of view, the lOM-compatible IBC is

compatible with the IEC or SBC/SBCX as well as with the

EPIC/ELIC and the IDEC on digital line card applications.

Similar to the other components, the device is designed in 2-

µm CMOS technology resulting in low power consumption of

less than 80 mW in the active state.

80 mW (typ.)

6 mW (typ.)

DCL

FSC

Equalization

Filter

DPLL

D-Channel

De-

coder

f

B1

B2

Descrambler

SDI

Equalizer

AGC

Buffer

Control

SDO

D-Channel

Scrambler

Coder

B1

B2

®

IOM

/SLD

U

ITB00815

Block Diagram

Siemens Aktiengesellschaft

119

Octal Transceiver for U_PNInterfaces (OCTAT^®-P)

PEB 2096

General Description

Type

Package

P-MQFP-44-1 (SMD)

The PEB 2096, OCAT-P, performs the layer-1 functions of

the ISDN basic access for eight U interfaces at the LT side

PEB 2096

PN

of the PBX.

Features

• Eight full duplex 2B+D U -interface transceivers, each

Applications

PN

equipped with the following functions:

– Conversion from/to binary to/from pseudo-ternary code

– Receive timing recovery

PBXs

8 × U interfaces

PN

– Activation/deactivation procedures, triggered by

primitives received over the IOM interface or by INFO

received from the line (e.g. detection of INFO1)

– Execution of test loops

Interfaces

• IOM-2 interface

• 8 × U interface

PN

• Boundary scan (for on-board tests)

– Analog line transceiver for up to 16-dB line attenuation

– U -interface functions compatible to PEB 2095, IBC,

PN

and PEB 20950, ISAC-P (except for looplength)

– U interface fully compatible to PSB 2196, ISAC-P TE,

PN

and PSB 2197, SmartLink-P

• IOM-2 interface

• Support for JTAG-boundary scan test

• 1-µ CMOS technology with low power consumption

• P-MQFP-44 package

TMS TCK TDI TDO RST

IDS DCL FSC DD DU MODE

XTAL1

XTAL2

CLK1

CLK2

JTAG

Boundary

Scan Interface

XPLL

384 kHz

LI4a

LI0a

LI0b

®

IOM

U

Transceiver No. 4

Transceiver No. 5

Transceiver No. 6

Transceiver No. 7

U

Transceiver No. 0

Transceiver No. 1

Transceiver No. 2

Transceiver No. 3

PN

LI4b

LI5a

LI5b

LI6a

LI6b

LI7a

LI7b

Interface

LI1a

LI1b

LI2a

LI2b

LI3a

LI3b

ITB04458

OCTAT^®-P Device Architecture

Siemens Aktiengesellschaft

120

PEB 2025

Subscriber Line Power Feeding

ISDN Exchange Power Controller (IEPC)

General Description

Type

Package

The PEB 2025 is an integrated power controller especially

designed for ISDN environments and for the use in a digital

exchange. High-voltage CMOS technology 60 V ensures

variety of applications:

PEB 2025-N

PEB 2025-P

P-LCC-28-1 (SMD)

P-DIP-22-1 (not for new designs)

• Two- and four-wire transmission lines

• Point-to-point configurations

• Point-to-multipoint configurations

Features

• Compatible to CCITT recommendations for power feed at

the S-interface

• Supplies power for up to four transmission lines. Each line

is individually powered and controlled

• High-voltage CMOS technology (up to 60 V, shiftable)

• Maximum output current programmable up to 100 mA

• Programmable switch-off characteristic by overcurrent

detection

• Automatic restart after removal of overload conditions

• Status detectors for each line driver

The device is fully compatible with the CCITT

recommendations for power feed at the S-interface.

Each line is individually powered and controlled via a

microprocessor interface. An interrupt output pin signals

any malfunction to the microprocessor.

Programmable output current and thermal shutdown guard

the PEB 2025 against overloads.

• Microprocessor-compatible interface (up to 8-MHz clock

frequency)

• Interrupt output for detection of any malfunction

• Full protection against shorts between transmission lines

V

GND

V

CC

BAT

a0

C

TO

CLC0

CLC1

CLC2

CLC3

Control

&

Logic

aF0

A

aF1

aF2

aF3

RD, WR,CS,

A0, A1, RES, INT

b0

µP-

Interface

µP-

Interface

MUX

D0-D2

R

Ι

RIMAX

ITB03964

Block Diagram

Siemens Aktiengesellschaft

121

DSP Oriented PBX Controller (DOC)

PEB 20560

Advanced Information

General Description

Type

Package

P-MQFP-160-1 (SMD)

PEB 20560

In order to maintain its leading position Siemens is defining a

new IC – the DOC – comprising all necessary functional

blocks like switching, signaling, DTMF/tone handling and

conferencing on a single chip. The transceivers (layer-1 ICs)

are not integrated.

• On-chip user programmable 16-bit Digital Signal

Processor, Siemens OAK, (with 20, 30 or up to 40 MIPS)

with access to 64 time-slots (via one or two internal IOM-2

interfaces) for DTMF/tone generation and recognition,

conferencing, music-on-hold, modem emulation, etc.

– 1 K × 16-bit on-chip data memory (X)

Features

– 512 × 16-bit on-chip data memory (Y)

– DSP proprietary interface to an external memory:

The DOC provides all necessary features for building PBX

(Private Branche eXchange) systems and Line Cards.

Program memory

Data memory

up to 62 K × 16 bit

up to 32 K × 16 bit

• In the PBX mode, the DOC provides:

– On-chip program memory (Boot)

• a-/µ-Law coding and decoding by hardware (on the fly)

• Firmware for DSP load measurement (within every 125-µs

frame)

• µP-DSP communication via a µP-Mail-Box

• On-chip emulation (OCEM) for DSP program debugging

• 8-bit µP interface compatible with Siemens/Intel/Motorola

bus schemes

– 6 fully usable IOM-2 (GCI) interfaces and thus it can

control up to 48 ISDN or 96 analog subscribers.

– 4 PCM highways with 126 time-slots.

• In the Line Card mode, the DOC provides:

– 2 fully usable IOM-2 interfaces with 16 IOM-2

subframes (2 × 8) and

– 2 limited IOM-2 interfaces, as two DSP ports are

connected, and thus it can control 16 to 24 ISDN (or 32

to 48 analog) subscribers.

• Programmable clock generator with built-in logic for

master and slave configurations

• Watch-dog timer

– 4 PCM highways with 256 time-slots.

• Signaling via 8 assignable HDLC controllers, each with a

64-byte data FIFO for transmit and for receive direction.

– 2 HDLC controllers (SACCO-A) assignable of two of up

to 48 ISDN subscribers at a time via two different

D-channel arbiters.

• Reset logic

• UART for V.24 interface

• Multifunctional input/ouput port configurable as a general

I/O port, DMA lines for one SACCO or as additional UART

lines for modem connection

• Integrated interrupt controller with vector generation and

support for DOC cascading

– 4 HDLC controllers (SIDEC) assignable to any

D-/B-channel in data upstream or data downstream

direction on four IOM-2 interfaces.

– 2 HDLC controllers (SACCO-B) assignable to any time-

slot in data upstream or data downstream direction on

four IOM-2 interfaces or to PCM highway.

Optionally, both controllers can be used as stand alone

HDLC controllers with up to 8.192-Mbit/s transfer rate.

They support DMA interface.

• JTAG interface for on board tests

• Interface for HW and SW evaluation (debugging)

• Advanced CMOS 0.6-µm technology

• 3.3 and 5-V power supply

• TTL driving capability, TTL and CMOS compatible inputs

• P-MQFP-160 package

.

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DSP Oriented PBX Controller (DOC)

PEB 20560

Controller of

Layer = 1 ICs:

Switch

PCM

Highways

C/I and Monitor

Handlers

192 x 128 Time-Slots

or 96 x 256 Time-Slots

Interface

®

IOM

-2

Interface

D-Channel Arbiter

and 2 HDLC Controllers

6 x HDLC

Controllers

External

DSP

Memory for

Program

and Data

Internal DSP

Memory

DSP for Tone and

Voice Management

Clock Generator

µP-Mail Box

Interrupt

Contr.

UART

µP Interface

JTAG

µP

ITB08491

Block Diagram

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Primary Rate Interface (PRI) ICs

Primary Rate Interface Signaling and Maintenance Controller

PRISM; PEB 3035

Siemens Aktiengesellschaft

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Primary Rate Interface (PRI)

Product Overview

Type

Short Title

Description

Page

132

134

135

136

139

162

PEB 2035

PEB 2236

PEB 3035

PEB 2254

PEB 22320

ACFA

Advanced CMOS Frame Aligner

IPAT^®-2

PRISM

FALC^™54

ISDN Primary Access Controller

Primary Rate Interface Signaling and Maintenance Controller

Frame and Line Interface Component

Primary Access Clock and Transceiver Component

High-Level Serial Communication Controller Extended

PRACT

SAB 82525

SAB 82526

HSCX

HSCX1

SAB 82532

SAB 82538

ESCC2

ESCC8

Enhanced Serial Communication Controller (2 channels)

Enhanced Serial Communication Controller (8 channels)

163

165

Siemens Aktiengesellschaft

126

Primary Rate Interface (PRI)

t / r

Subscriber Units

Switching

Systems

Group

Processors

Analog Line Cards

DAML

®

SICOFI

PIC

MTSS

MTSC

MTSL

DAML-RT

DAML-COT

®

t / r

SICOFI -2 EPIC -S

®

SICOFI -4 EPIC

U

TM

®

SLICOFI

SLIC

ELIC

HSCX

MUSAC -A

®

EPIC -S

®

HV-SLIC

EPIC -1

®

ELIC

Digital Line Cards

HSCX

ESCC2 / 8

MUNICH32

DOV

U

(Basic Rate)

t / r

®

SBC

SBCX

EPIC -S

®

EPIC -1

®

QUAT -S ICC

®

ISAC -S

IEC-T

IEC-Q

IBC

IDEC

ELIC

Trunk Units

ACFA

Transmission

Exchange

HSCX

IEPC

S / T

®

Concentrator

Multiplexer

®

OCTAT -P

IPAT -2

HSCX

PRISM

ESCC2

U

ESCC8

TM

(Primary Rate)

FALC

54

®

ACFA

IPAT -2

PRACT

HSCX

ESCC2 / 8

PRISM

FALC

S

TM

54

NT

RPT

PCM

Highway

ITA03688

Siemens Aktiengesellschaft

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Overview on Primary Rate Interface (PRI)

Applications for the Primary Rate Interface include trunk lines

between public central office (CO) exchanges, from a PBX

to a CO, interlinking PBXs, the gateway connecting a LAN to

the public network on a PBX, interlinking LANs, interfacing a

large computer or data intensive terminal (e.g. CAD graphics)

with the CO or a PBX etc.

Frame alignment for all commonly used framing and

multiframing formats is performed by the ACFA. The device

synchronizes the transmit and receive signals, interfaces the

data rate from the line to the 2.048 Mbit/s or 4.096 Mbit/s

internal highway and codes/decodes one of three selectable

line codes.

Due to different technical evolutions in Europe and the US

there are two basic interface types for 1^storder transmission

systems, the T1 and the CEPT or E1 standard. The ISDN-

PRI is based on these two different standards. The main

difference between ISDN-PRI and T1/CEPT transmission

systems is the type of signaling used.

For PCM24, this transmission code can be either B8ZS or

AMI-ZCS whereas for PCM30, it is always HDB3. Alarms and

error conditions are reported to the microprocessor via a

maskable interrupt line. The ACFA can also be used for

various signaling schemes. Rather than using the HSCC/

HSCX, signaling information can be handled by a less

intelligent communications controller without programmable

time-slot access. For such devices, the ACFA provides the

required signaling information via special purpose pins.

Additionally, the ACFA has a DMA interface for transferring

signaling information to/from a microprocessor controlled

memory. Finally, signaling data can be accessed directly via

the microprocessor interface.

The T1 standard is based on the PCM24 technique, where

twenty-four 64-kbit/s basic channels and one framing bit are

combined into one 1.544-Mbit/s frame format.

The CEPT standard is based on the PCM30 technique. The

2.048-Mbit/s frame consists of thirty 64-kbit/s basic channels,

one 64 kbit/s signaling channel and 64-kbit/s framing and

maintenance channel.

Siemens new generation of Primary Rate Interface

component, the PEB 2254 FALC54 (Framing And Line

Interface plus signaling Controller), implements the

functionality of a line interface, frame aligner and signaling

controller for both standards E1 and T1 on a single chip.

Siemens Semiconductor Division offers a complete solution

of ICs covering different standards and applications.

The PEB 2236 IPAT^®-2 (ISDN Primary Access Transceiver)

and the PEB 2035 (Advanced CMOS Frame Aligner) fulfill

the T1 and CEPT standards. At the system side the ACFA

provides a synchronous PCM interface for connecting to

other application specific ICs (e.g. MTSx, HSCX).

Applications

In general the following applications can be covered:

• Synchronous/asynchronous multiplexers

• Digital access cross connects

• Central offices switches

• Remote switches, subscribers loop carriers

• LAN, MAN, WAN, Bridges, Routers

• FITL

The IPAT-2, together with the ACFA, implement the layer-1

physical interface.

Both devices are programmed via the µP interface to perform

the different standards, applications and maintenance/

service functions.

The IPAT-2 is a monolithic line driver for primary access lines

of either the PCM24 (T1, N. America/Japan) or PCM30

(CEPT, W. Europe) standards. In the receive direction, the

device recovers the clock and data signals from the line and

forwards them to the ACFA.

• PBX interfaces

The following chapter outlines the application of the Primary

Rate devices ACFA, FALC54 and I PAT-2 and shows the

flexibility of the architecture.

The IPAT-2 is transparent to the received line code. In the

transmit direction, the device takes the signal received from

the ACFA and forms it into transmission pulses according to

CCITT recommendations for the PCM30 or AT&Ts DMI

specifications for PCM24. Correspondingly, input/output jitter

requirements comply with both CCITT and

In the switching application the Primary Rate Interface is

connected to a switching network of a PBX, CO or

concentrator. The switching devices MTSL (Memory Time

Switch Large), MTSC (Memory Time Switch CMOS) and

MTSS (Memory Time Switch Small) perform the switching

and data rate adaption. In addition to the switching function

the MUSAC (Multipoint Switching and Conferencing) can

handle 64-conference channels in any combination.

AT&T specifications.

Siemens Aktiengesellschaft

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Overview on Primary Rate Interface (PRI)

Line Interface

Framing

Synchronous

Interface

Line

CEPT 2.048 Mbit / s

2.048 Mbit / s

4.096 Mbit / s

T1

1.544 Mbit / s

Clock

Data

®

IPAT -2

ACFA

Clock

Data

µP

ITA00219

Block Diagram

Line

Line Interface

Framing

Signaling

Switching

CEPT

T1

2.048 Mbit / s

1.544 Mbit / s

Synchronous

Interface

2.048 Mbit / s

4.096 Mbit / s

Conferenenzing

Data Rate Adaption

Backplane

2.048 Mbit / s

8.192 Mbit / s

Clock

Data

®

IPAT -2

ACFA

MTSX

TM

MUSAC

Clock

Data

HSCX

FALC^TM54

µP

ITA00220

Primary Access Interface with Switch

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Overview on Primary Rate Interface (PRI)

Using the Primary Rate Interface in a MUX (Multiplexer)

application, the EPIC (Extended PCM Interface Controller)

multiplexes the analog or digital Subscriber line into the PCM

highway. The device handles also the control information

for the IOM interface. The HSCX (High level Serial

Communication Controller extended) and the IDEC (ISDN

D-channel Exchange Controller) performs the signaling

function.

Line

Line Interface

2.048 Mbit / s

Framing

Signaling

Multiplexing

Signaling

Line Interface

®

CEPT

T1

Synchronous

Interface

2.048 Mbit / s

4.096 Mbit / s

IOM

-2

U

S

k0

P0

0

1.544 Mbit / s

Interface

Clock

Data

SBCX

IEC

®

IPAT -2

ACFA

EPIC

IBC

Clock

Data

®

HSCX

IDEC

(opt.)

SBCX

IEC

IBC

TM

FALC 54

µP

ITA00221

Multiplexer for Digital Subscriber with Primary Rate Interface

Line

Line Interface

2.048 Mbit / s

Framing

Signaling

Multiplexing

CODEC-Filter

®

CEPT

T1

Synchronous

Interface

IOM

-2

Analog

Line

1.544 Mbit / s

Interface

2.048 Mbit / s

4.096 Mbit / s

Clock

Data

SLIC

®

IPAT -2

ACFA

EPIC

SICOFI -2

Clock

Data

HSCX

SLIC

®

SICOFI -2

TM

FALC 54

µP

ITA00222

Multiplexer for Analog Subscriber with Primary Rate Interface

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Overview on Primary Rate Interface (PRI)

For fast data transmission via the Primary Rate Interface the

HSCX or ITAC (ISDN Terminal Adaptor Circuit) is connected

to the PCM highway. Using the HSCX, X.25 interfaces can be

connected to the PRI or data

transmission from the system memory (e.g. file transfer) of a

PC to another PC or host computer can be performed. The

lPAT handles data from a X.21 into V.24 or V.35 interface

and inserts the information into the PRI.

Line

Line Interface

2.048 Mbit / s

Framing

Signaling

CEPT

T1

Synchronous

Interface

Data Transmission

1.544 Mbit / s

2.048 Mbit / s

4.096 Mbit / s

X.2.1

X.21 to

Clock

Data

®

IPAT

V.24

V.35

®

IPAT -2

ACFA

Clock

Data

HSCX

V.25

TM

FALC 54

µP

ITA00223

Data Terminal/SS No. 7 Terminal with Primary Access Interface

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Advanced CMOS Frame Aligner (ACFA)

PEB 2035

General Information

Type

Package

The Advanced CMOS Frame Aligner (ACFA) PEB 2035 is a

VLSI device used in interface modules with PCM systems.

PEB 2035-N

PEB 2035-P

PEF 2035-N

PEF 2035-P

P-LCC-44-1 (SMD)

P-DIP-40-1

Designed as an universal frame aligner, the ACFA will

implement layer-1 (coding, decoding and synchronizing)

functions for all PCM30 (32 channels) and PCM24 (24

channels) oriented applications. It complies with CCITT/

CEPT recommendations as well as with the AT&T DMI

specifications (CCITT Rec. G 703, 704, 732, 733,

November 1984; DMI specification April 1985).

P-LCC-44-1 (SMD)

P-DIP-40-1

Features

• Frame alignment for 2.048-Mbit/s

and 1.544 Mbit/s PCM system

• Meets CCITT Rec’s (G 703, 704, 732, 733) and

AT&T technical advisories

• Coding/decoding for HDB3, B8ZS and AMI-ZCS (zero

code suppression) line codes

• Clear channel capability for AMI ZCS and CAS-BR

• Unipolar NRZ for interfacing fiber-optic transmission

routes

• Error checking via CRC4 or CRC6

• Interfacing with a system internal 2.048-Mbit/s or

4.096-Mbit/s highway

• Elastic memory for route clock wander and jitter

compensation

• Support for different signaling schemes

• Testing and diagnostics

Switching between the PCM24 and the PCM30 modes is

performed by programming via the microprocessor interface

of the device. The extended features implemented in each of

these two modes will meet most present and future

requirements. A high degree of flexibility allows its use

without addition of specialized hardware.

Besides interfacing to T1/CEPT routes and to an internal

system highway, the ACFA supports the following

interfaces:

– interface with fiber-optic transmission routes

– parallel microprocessor interface

– interface to support different signaling schemes

– testing and diagnostic interface

• Single +5-V power supply

• Advanced CMOS technology

• Low power consumption

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132

Advanced CMOS Frame Aligner (ACFA)

PEB 2035

1)

RFSPQ

RRCLK XRCLK

Timing Control

SYPQ SCLK

1)

ACKNLQ

RSIGM / RREQ

XSIGM / XREQ

Signaling

Support

1)

ROID

PMFB

1)

XMFB

Receive

Link

Interface

Receive

Speech

Memory

RDIP

RDIM

Receiver

RDO

Parity

Check

CH. Loop

Parity Gen.

RCHPY

1)

DFPY

µP Bus

Parity

Check

1)

XOID

XDOP

XDOM

XTOP

XTOM

Transmit

Link

Interface

Transmit

Speech

Memory

Transmitter

XDI

1)

XSIG

XCHPY

Alarm

Interrupt

Control

Register

Status

Register

Signaling

Stacks

Parity Gen.

1)

ITB00548

COS

AINT

A 3 - 0 D 7 - 0 RDQ WRQ CEQ RESQ

Block Diagram

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ISDN Primary Access Transceiver (IPAT^®-2)

PEB 2236

General Information

Type

Package

The ISDN Primary Access Transceiver IPAT-2 (PEB 2236) is

a monolithic CMOS device which implements the analog

receive and transmit line interface functions to primary rate

PCM carriers. It may be programmed or hardwired to operate

in PCM30 (2.048 Mbit/s) and PCM24 (1.544 Mbit/s) carrier

systems.

PEB 2236-N

PEB 2236-P

PEF 2236-N

PEF 2236-P

P-LCC-28-1 (SMD)

P-DIP-28-1

P-LCC-28-1 (SMD)

P-DIP-28-1

The IPAT-2 recovers clock and data using an adaptively

controlled receiver threshold. It is transparent to ternary

codes and shapes the output pulse according to the AT&T

Technical Advisory #34 or CCITT G.703. The jitter tolerance

of the device meets the latest CCITT recommendations

(I.431) and many other specifications by AT&T/Bellcore.

Diagnostic facilities are included.

Features

• ISDN line interface for 1544

and 2048 kbit/s (T1 and CEPT)

• Data and clock recovery

• Transparent to ternary codes

• Low transmitter output impedance for a high

return loss with reasonable protection resistors

(CCITT G.703 requirements for the line input return

loss fulfilled).

Specially designed line interface circuits simplify the tedious

task of protecting the device against overvoltage damage

while still meeting the return loss requirements.

• Adaptively controlled receiver threshold

• Programmable pulse shape for T1 applications

• Jitter specifications of CCITT I.431 and many

AT&T/Bellcore publications met

• Implements local and remote loops for diagnostic

purposes

The IPAT-2 is suitable for use in a wide range of voice and

data applications such as for connections of digital switches

and PBXs to host computers, for implementations of primary

ISDN subscriber loops as well as for terminal applications.

The maximum range is determined by the maximum

allowable attenuation.

• Monolithic line driver for a minimum of external

components

• Low power, reliable advanced CMOS technology

1

2

28

27 100 nF

R

2

Over-

voltage

Protection

100 nF

3

26

25

24

23

22

Receive

Line

4

5

22 pF

6

7

®

IPAT -2

8

21

PEB 2235

100 nF

20

9

R

1

10

11

12

13

14

19

18

17

16

15

Over-

voltage

Protection

1 µF

Transmit

Line

1

Crystal optional

ITS00558

External Wiring of the IPAT

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Primary Rate Interface Signaling and Maintenance Controller (PRISM)

PEB 3035

General Description

Type

Package

The PEB 3035 (Primary Rate Interface Signaling and

Maintenance Controller) is a two channel serial

PEB 3035-N

P-LCC-28-1 (SMD)

P-DIP-28-1

PEB 3035-P

PEF 3035-N

PEF 3035-P

communication controller designed to support signaling and

maintenance functions for T1 Primary Rate Interfaces using

the Extended Superframe format ESF. The device supports

the DL-channel protocol for ESF format according to T1.403-

1989 ANSI specification or according to AT&T specification

TR 54016, September 1989. The 8-bit parallel µP-interface

fits perfectly into every Siemens/lntel 8-bit or 16-bit

microcontroller system. Two serial channels can be

programmed in three different clock modes to function in

time-slot oriented applications, in a strobe mode or as a serial

interface.

P-LCC-28-1 (SMD)

P-DIP-28-1

Features

Serial Interface

• Two independent signaling channels

• Programmable idle code (Flags, all ones)

• Continuous transmission of up to 32 bytes of data

• Data rate up to 4 Mbit/s

Protocol Support

• Support of ESF-DL protocol according to T1.403-1989

or according AT&T TR 54016 specifications

• Support of HDLC protocol

• Transparent mode for totally transparent data

transmission and reception

RxDA

LAP

Controller

SP-REG

Decoder

Alignment

TxDA

CTSA

RTSA

AD0 - AD7

Transmit

FIFO

Data

Link

Controller

RxCLKA

TxCLKA

Clock

Control

Receive

FIFO

TSA

Channel A

µP Bus

Interface

TxCLKB

RxCLKB

RD

WR

CS

RTSB

CTSB

TxDB

ALE

INT

RES

RxDB

Channel B

ITB03617

Block Diagram

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Frame and Line Interface Component (FALC^™54)

PEB 2254

General Information

Type

Package

P-MQFP-80-1 (SMD)

The Frame and Line Interface Component PEB 2254

(FALC54) is a high sophisticated single chip solution for

primary rate PCM carriers. It may be programmed to operate

in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.

The FALC54 provides the complete functionality of a line

interface-, a framing-, clock generation (2 VCOs) and

signaling unit on one chip with greatly increased

functionalities.

PEB 2254-H

1544-kbit/s Applications

• PCM-multiplex equipment according to G.733

• Digital multiplex equipment according to G.734, G.743

• Digital exchange equipment according to G.705, Q.511,

Q.512

• Transmultiplex equipment according to G.793

• Video conferencing according to H.120, H.130

• Transcoder equipment according to G.762

• Digital circuit multiplication equipment according to G.763

• Digital section/line system according to G.951, G.955

• ADPCM-multiplex equipment according to G.724

The FALC54 recovers clock and data using an integrated

digital phase-locked loop. It shapes the output pulse

following the AT&T Technical Advisory #34 or CCITT G.703

and generates a variety of systems clocks. The jitter

tolerance of the device meets the newest CCITT

recommendations and many other specifications by AT&T/

BELLCORE.

Features

The FALC54 features include: selectable multiframe (six

multiframe formats), error checking (CRC4, CRC6), multiple

line codes (HDB3, B8ZS, AMI, CMI, NRZ), alarm reporting,

maintenance and performance monitoring. The circuit

contains a two-frame elastic memory which ensures wander

absorption between the PCM carrier and a synchronous,

system internal highway.

Line Interface

• Data and clock recovery

• Low transmitter output impedance for a high return loss

with reasonable protection resistors (CCITT G.703

requirements for the line input return loss fulfilled)

• Adaptively controlled receiver threshold

• Programmable pulse shape for T1 and CEPT

• Transmit line monitor

• Jitter specifications of CCITT I.431 and

AT&T publications 62411 met

• Maximum line attenuation more than 16 dB (CCITT I.431)

• Wander and jitter attenuation

All signaling types – CCS, CAS and bit robbed signaling in

conjunction with Clear Channel Capability – are controlled by

the integrated LAPD/CAS signaling controller. In addition, the

FALC54 allows flexible access to facility data link and service

channels. All signaling and data link access can be handled

via 64-byte FlFOs.

• Implements local and remote loops for diagnostic

purposes

• Selectable line codes (H DB3, B8ZS, AMI, AMI with ZCS)

• Analog and digital loss of signal indication

• On-chip clock generator for system clocks

• TRISTATE function of transmit line outputs

• Jitter attenuator

The device includes functions which meet newest CCITT,

ETSI and FTZ recommendations for primary rate interfaces

and the AT&T Digital Multiplexed Interface specifications

(DMI). Controlling and monitoring of the device is performed

via a parallel 16-bit data bus interface which is directly

compatible with the most popular 8/16-bit microprocessors

(Intel or Motorola type).

Below a list of equipment as described by the CClTT which

potential FALC54 applications.

2048-kbit/s Applications

• PCM-multiplex equipment according to G.732 G.735,

G.738

• Digital multiplex equipment according to G.736, G.742,

G.745

• External access equipment according to G.737, G.739

• Digital exchange equipment according to G.705, Q.511

Q.512

• Transmultiplex equipment according to G.793

• Video conferencing according to H.120, H.130

• Transcoder equipment according to G.761

• Digital circuit multiplication equipment according to G.763

• Digital section/line system according to G.921, G.952,

G.956

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136

Frame and Line Interface Component (FALC^™54)

PEB 2254

Frame Aligner

Signaling Controller

• Frame alignments/synthesis for 2048 kbit/s (CEPT,

PCM30) and 1544 kbit/s (T1, PCM24)

• Meets newest CCITT Rec’s, ETSI Rec’s, FTZ Rec’s, and

AT&T Technical References

• LAPD controller

• Support DL-channel protocol for ESF format according to

T1-403-1989 ANSI specification or according to

AT&T specification TR54016 september 1989

• Handling of bit-oriented functions

• Programmable maximum packet size checking

• Programmable preamble

• Extended address masking

• Programmable FIFO size (32,16, …)

• CAS controller

• Multiframe synchronization and synthesis

• Alarm detection and generation

• Bit robbing support

• Clear channel capabilities in PCM24 mode

• Transparent Mode

• Programmable formats for

PCM30: Doubleframe, CRC Multiframe

PCM24: 4-Frame Multiframe (F4),12-Frame Multiframe

(F12, D3/4), Extended Superframe (ESF), Remote Switch

Mode (F72, SLC96)

• Selectable conditions for loss of sync

• Fully implementation of the CRC4 Non-CRC4

• Interworking of CCITT G.706

• Error checking via CRC4 or CRC6 procedures

• Error monitoring via E-bit and SA6-bit in CEPT mode

• Performance monitoring

• Insertion and extraction of alarms (AIS, RRA, AUXP…)

• IDLE-code insertion for selectable channels

• System clock frequency different for receive and

transmit

• Selectable 2048/4096-kbit/s system internal highway with

programmable receive/transmit shifts

• Programmable TRISTATE function of 4096 kbit/s output

via RDO

• Two-frame deep elastic receive memory for receive route

clock wander and jitter compensation (can be reduced to

one frame length for PCM30 master-slave

applications)

MP Interface

• 8/16-bit microprocessor bus interface (Intel or Motorola

type)

• All registers directly accessible (byte or word access)

• Extended interrupt capabilities

General

• Boundary scan standard IEEE 1149.1

• Advanced CMOS technology

• P-MQFP-80 package

• Power consumption less than 400 mW

Note: The FALC54’s power consumption is mainly

determined by the line length and type of the cable.

• One frame elastic transmit memory (PCM24 mode only)

for transmit route clock wander and jitter compensation

• Support for different data link schemes

• Flexible transparent modes

• Channel- and line loop back capabilities

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Frame and Line Interface Component (FALC^™54)

PEB 2254

RDO

XDI

RL (T1)

Equalizer

Local Loop

RL1/

RL2/

XOID/

XL1/

XL2/

RDIP

RDIN

CLKDR

XDOP

XDON

ITB06095

DR = Dual Rail RL = Remote Loop XS = Xslicer

Block Diagram

Siemens Aktiengesellschaft

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Primary Access Clock and Transceiver Component (PRACT)

PEB 22320

General Description

Type

Package

P-LCC-44-1 (SMD)

The Primary Rate Access Clock Generator and Transceiver

PEB 22320-N

PRACT (PEB 22320) is a monolithic CMOS device which

implements the analog receive and transmit line interface

functions to primary rate PCM carriers. It may be

programmed or hard-wired to operate in 1.544-Mbit/s (T1) or

2.048-Mbit/s (CEPT) carrier system.

Features

• ISDN-line interface for 1544 and 2048 kbit/s (T1 and

CEPT)

The PRACT recovers clock and data using an adaptively

controlled receiver threshold. It is transparent to ternary

codes and shapes the output pulse following the AT&T

Technical Advisory #34 or CCITT G.703. The jitter tolerance

of the device meets the CCITT (I.431) recommendation and

many other specifications by AT&T/Bellcore. An on-chip

selectable jitter attenuation is available which meets the I.431

recommendation for CEPT – and the PUB 62411 for T1

application. Diagnostic facilities are included.

• Data and clock recovery

• Transparent to ternary codes

• Low transmitter output impedance for a high return loss

with reasonable protection resistors (CCITT G.703

requirements for the line input return loss fulfilled)

• Adaptively controlled receiver threshold

• Programmable pulse shape for T1 applications

• Jitter specifications of CCITT I.431 and many

AT&T/Bellcore publications met

• Wander and jitter attenuation

Specially designed line interface circuits simplify the tedious

task of protecting the device against overvoltage damage

while still meeting the return loss requirements.

• Jitter tolerance of receiver: 0.5 Ul s

• Implements local and remote loops for diagnostic

purposes

• Monolithic line driver for a minimum of external

components

• Low power, reliable CMOS technology

• Loss of signal indication for receiver

• Clock generator for system clocks

The PRACT is suitable for use in a wide range of voice and

data applications such as for connections of digital switches

and PBXs to host computers for implementations of primary

ISDN subscriber loops as well as for terminal applications.

The maximum range is determined by the maximum

allowable attenuations.

In the T1 case the PRACT’s power consumption is mainly

determined by the line length and type of the cable.

LL

XTAL1,2,3,4

XTIP

Transmit

RL1

XTIN

Receive

Receiver

Input

Test Data

RRCLK

Clock &

Data

Recovery

XCLK (T1)

RL2

P

N

System

Clocks

Jitter Attenuator

&

Clock Generator

RCLK

RDOP

RDON

Loss of

Signal

Detection

LOS

Driver

XL1

XDIP

XDIN

Transmit

Output

XL2

Timing &

Pulseshaper

D / A

ROM

XCLK

(CEPT)

Block Diagram

LS0,1,2

RL

ITB04876

Siemens Aktiengesellschaft

139

Switching, Attenuation and Conferencing Family ICs

Multipoint Switching and Conferencing Unit Attenuation

™

MUSAC -A; PEB 2445

Siemens Aktiengesellschaft

141

Switching, Attenuation and Conferencing Family ICs

Product Overview

Type

Short Title

Function

Page

147

150

151

153

154

90

PEB 2045

PEB 2046

PEB 2047

PEB 2047-16

PEB 2445

PEB 2054

PEB 2055

PEB 20550

MTSC

Memory Time Switch CMOS

MTSS

Memory Time Switch Small

MTSL

Memory Time Switch Large

MTSL-16

MUSAC^™-A

EPIC^®-S

EPIC^®-1

ELIC^®

Memory Time Switch Large H-16 MHz

Multipoint Switching and Conferencing Unit with Attenuation

Extended PCM Interface Controller

Extended Line Card Interface Controller

Internetworking & Protocol Controllers

91

92

SAB 82C258

SAB 82C257

ADMA

169

SAB 82525

SAB 82526

HSCX

HSCX1

High-Level Serial Communication Controller Extended

162

SAB 82532

SAB 82538

PEB 20320

ESCC2

Enhanced Serial Communication Controller (2 channels)

Enhanced Serial Communication Controller (8 channels)

Multichannel Network Interface Controller for HDLC

163

165

167

ESCC8

MUNICH32

Siemens Aktiengesellschaft

142

Switching, Attenuation and Conferencing IC-Family

t / r

Subscriber Units

Switching

Systems

Group

Processors

Analog Line Cards

DAML

®

SICOFI

PIC

MTSS

MTSC

MTSL

DAML-RT

DAML-COT

®

t / r

SICOFI -2 EPIC -S

®

SICOFI -4 EPIC

U

TM

®

SLICOFI

SLIC

ELIC

HSCX

MUSAC -A

®

EPIC -S

®

HV-SLIC

EPIC -1

®

ELIC

Digital Line Cards

HSCX

ESCC2 / 8

MUNICH32

DOV

U

(Basic Rate)

t / r

®

SBC

SBCX

EPIC -S

®

EPIC -1

®

QUAT -S ICC

®

ISAC -S

IEC-T

IEC-Q

IBC

IDEC

ELIC

Trunk Units

ACFA

Transmission

Exchange

HSCX

IEPC

S / T

®

Concentrator

Multiplexer

®

OCTAT -P

IPAT -2

HSCX

PRISM

ESCC2

U

ESCC8

TM

(Primary Rate)

FALC

54

®

ACFA

IPAT -2

PRACT

HSCX

ESCC2 / 8

PRISM

FALC

S

TM

54

NT

RPT

PCM

Highway

ITA03688

Siemens Aktiengesellschaft

143

Overview on Switching, Attenuation and Conferencing IC-Family

Supervision and control of the entire system, including

connection set-up, maintenance and testing, is performed

in a powerful central processing unit. Besides this, the

through-switching of PCM channels is done in a switching

network unit, whereas the tasks of a frame alignment unit are

to interface PCM transmission routes with the switching

system.

In a digital switching matrix one distinguishes between two

basic switching principles:

• Time division multiplex

• Space division multiplex

A method that is frequently used involves a combination of

the two principles, this being called space/time division

multiplex. The figure illustrates the different principles.

Digital exchanges put calls through by newly arranging the

speech signals coded with 8-bit words (PCM time-slots). The

code words are transmitted serially on PCM lines. The

sampling frequency of 8 kHz produces PCM frames with a

duration of 125 µs. The transmission rate on the line

determines how many code words (speech channels) can be

accommodated within a sampling period. With a data rate of

2048 kbit/s for example, there are 32 time-slots of 8 bits each.

Four lines with a data rate of 8192 kbit/s have a transmission

capacity of 512 channels.

In time division multiplex only the time-slot is altered during

switching. All signals from a certain input PCM line are

switched to a fixed output line, only the time-slot sequence

may change.

In space division multiplex incoming PCM data are only

rearranged in space. The input time-slot equals the output

time-slot. However, input from one PCM line can be switched

to different output lines.

Time-Division Multiplex

TS0 TS1 TS2 TS3

A1

A2

A3

A4

A3

A4

A1

A2

Input Timing

TS0

Output Timing

ITA00540

TS0

C1

Space-Division Multiplex

A1

B1

C1

Line 1

Line 2

Line 3

1

2

3

A1

B1

Input Timing

TS0 TS1 TS2 TS3

Output Timing

ITA00541

TS0 TS1 TS2 TS3

B4

Space/Time-Division Multiplex

A1

A4

B4

Line 1

1

2

3

A1

C2

Line 2

Line 3

C2

A4

Input Timing

Output Timing

ITA00542

Siemens Aktiengesellschaft

144

Overview on Switching, Attenuation and Conferencing IC-Family

Wideband Switching

or “Fractional” T1. 64 kbit/s time-slots are combined for

An additional future requirement is wideband switching. In

contrast to voice switching, wideband switching is

optimized for data transmission, e.g. for ISDN H-channels

higher data rates. As a precondition all switched time-slots

have to be output in the same frame. For example

6 time-slots could be combined to a 384-kbit/s bundle.

Wideband Switching of 64-kbit / s Time-Slots

384-kbit / s

"Bundle"

192-kbit / s

"Bundle"

Individual

64-kbit / s

Time-Slots

32

1

2

3

4

5

6

7

8

9

10 11 30 31 32

1

2

3

ITT01746

Frame 0

Frame 1

Frame 2

Data "Bundle":

- switched time-slots have to be output in the same frame

Multipoint Switching

information back. In contrast to audio conferences, data

terminals broadcast to the switching matrix which are

or-connected. With multipoint switching an independent

LAN in a PBX system could be realized.

In a multipoint switching configuration data communication

between terminals can be achieved by connecting all

stations to one or more time-slots and transmitting the

ITA03952

Siemens Aktiengesellschaft

145

Overview on Switching, Attenuation and Conferencing IC-Family

MTSC

MTSL/MTSL-16

Siemens Semiconductor offers devices which take into

consideration the needs for efficient realization of these

tasks. One of the switching network circuits offered is the

Memory Time Switch in CMOS (MTSC) PEB 2045, which

has the ability to connect any of 512 incoming PCM

channels to any of 256 outgoing PCM channels on a single

chip. A non-blocking switch for 512 time-slots can be built up

with two devices only. A further expansion can be realized

very easily too. Different kinds of operation modes enable the

use of the MTSC PEB 2045 in 2048 Mbit/s, 4096 Mbit/s and

8192 Mbit/s or mixed PCM systems.

The largest in our family, the Memory Time Switch Large

(MTSL) PEB 2047 is capable of switching up to 1024

time-slots.

The MTSL allows the switching of fractional T1 and data

bundles. The MTSL-16 is a selection for 16-MHz

applications.

MUSAC

Siemens Semiconductor also supplies a solution for

conferencing, the Multipoint Switching And Conferencing

Unit (MUSAC) PEB 2245, which performs the complete

switching functions of the MTSC, and has a signal processor

for handling up to 64 conferencing channels in any

combination. The input and output channels can also be

attenuated individually to achieve best transmission quality.

As an additional feature the MTSC PEB 2045 together with

an Advanced CMOS Frame Aligner (ACFA) PEB 2035 can

realize the system interface of up to four primary multiplex

access lines.

MTSS

MUSAC-A

The Memory Time Switch Small (MTSS) PEB 2046 is a

smaller version of the MTSC PEB 2045 performing time/

space switch functions for a non-blocking switch of 256 PCM

channels.

The MUSAC-A is an upward compatible device to the MTSL

and MUSAC. It offers in addition the attenuation and

amplification of every time-slot.

An overview on the complete switching and conferencing

IC-family is shown in the following table:

Switching, Attenuation and Conferencing IC-Family

MTSC

PEB 2045

MTSS

PEB 2046

MTSL

PEB 2047

MTSL-16

PEB 2047-16

MUSAC-A

PEB 2445

EPIC-1

PEB 2055

EPIC-S

PEB 2054

Switching capacity

(time-slots)

512 × 256

256 × 256

1024 × 512

1024 × 1024

512 × 256

256 × 256

64 × 256

Input/output

lines

‘16/8

‘8/8

2

‘16/8

‘4/4

‘1/2

PCM-data rate

(Mbit/s)

2/4/8 +

mixed mode

2/4/8 +

mixed mode

2/4/8/16 +

mixed mode

2/4/8 +

mixed mode

up to 8

up to 4

Clock rate

(MHz)

4096

8192

4096

8192

4096

8192

4096/8192

16384

4096

8192

up to

8192

2048

8192

Conferencing

64 channels

Attenuation

all channels

– 4 to 12 dB

PRI/T1 mode

yes

Fractional T1

data bundling

yes

128 kbit/s

channel

µC access

read

yes

Multipoint

switching

yes

100

Power (mW) max.

consumption typ.

50

100

170

50

Package

P-DIP-40-1

P-LCC-44-1

P-DIP-40-1

P-LCC-44-1

P DIP-40-1

P-LCC-44-1

P-DIP-40-1

P-LCC-44-1

Siemens Aktiengesellschaft

146

Memory Time Switch CMOS (MTSC)

PEB 2045

General Description

Type

Package

The MTSC PEB 2045 is a monolithic CMOS circuit, which

has the ability to connect any of the 512 PCM channels of

16 incoming PCM lines to any of the 256 PCM channels of

eight output lines.

PEB 2045-N

PEB 2045-P

PEF 2045-N

PEF 2045-P

P-LCC-44-1 (SMD)

P-DIP-40-1 (not for new design)

P-LCC-44-1 (SMD)

The PCM information for a complete frame is stored in the

4-Kbit speech memory SM, i.e. all of the 512 words with 8 bits

are written into a fixed position of the SM. This is controlled

by the input counter every 125 µs. The words are read using

random access with an address that is stored in a connection

memory CM for each of the 256 output channels. The access

to the CM is controlled by the output counter.

P-DIP-40-1 (not for new design)

Features

• Time/space switch for 2.048-, 4.096- and 8.192-kbit/s

PCM systems

• Different kinds of modes (2048, 4096, 8192 kbit/s

or mixed mode)

• Switching of up to 512 incoming PCM channels to up to

256 outgoing PCM channels

• 16 input and eight output PCM lines

• Configurable for primary access and

standard applications

To produce a connection the SM address and the CM

address must be written into the PEB 2045 via a µP interface.

The SM-address contains the time-slots and line numbers of

the incoming PCM words. The CM address consists of the

time-slots and line numbers of the output words.

The PEB 2045 can be connected to 2-Mbit/s, 4-Mbit/s and

8-Mbit/s PCM systems, the device clock may be either

4.096 MHz or 8.192 MHz.

• Programmable clock shift with half clock

step resolution for input and output in primary access

configuration

In a second operational mode the PEB 2045 together with the

PEB 2035 (ACFA, Advanced CMOS Frame Aligner) and the

PEB 2235 (IPAT, ISDN Primary Access Transceiver)

implements the system interface of up to four primary

multiplex access lines. This interface can be configured for

2-Mbit/s, 4-Mbit/s and 8-Mbit/s systems; a clock shift for input

and output lines with half clock step resolution is

• Configurable for a 4096- and 8192-kHz device clock

• Tristate function for further expansion and tandem

operation

• Tristate control signals for external drivers in primary

access configuration

• 2048-kHz clock output in primary access configuration

• Space switch mode

• 8-bit µP interface

programmable. Selection of operating modes and

programming is made by writing to the mode register and, via

the Indirect Access Register (IAR), the Clock Shift Register

(CSR) and the General Configuration Register (GCR).

• Single + 5-V power supply

• Advanced low power CMOS technology

The components PEB 2045 and PEF 2045 are functionally

identical. The difference between the two types lies in the

temperature range. The PEB 2045 operates in the

temperature range 0 to 70 °C, the PEF 2045 in the range

– 40 to 85 °C.

Applications

• All types of switching systems

• Concentrator function

• Frequency transforming interface between 2-Mbit/s,

4-Mbit/s and 8-Mbit/s PCM systems

• 16/16 space switch for 8-Mbit/s PCM systems

• System interface for up to four primary multiplex access

lines in combination with the PEB 2035 (ACFA) and

*PEB 2235 (IPAT)

Siemens Aktiengesellschaft

147

Memory Time Switch CMOS (MTSC)

PEB 2045

IN0

IN15

D7 - D0

MOD

STA

PCM IN

Connection

Memory

CM

µP

Interface

A0

RD

IAR

WR

CS

Speech

Memory

SM

CCS

GCR

CM

Address Gen

Timing Control

PCM OUT

SP

CLK

OUT 0

OUT 7

Block Diagram

ITB00554

Line

Interface

Dual Rail

Interface

Internal

Primary

System

Interface

1.544 Mbit / s

2.048 Mbit / s

Highway

2.048 Mbit / s

2.048 / 4.096 /

8.192 Mbit / s

PEB 2045

MTSC

PEB 2235

IPAT

PEB 2035

ACFA

®

SAB 82525

HSCX

ITB00544

Optimized System Interface for Four Primary Multiplex Access Lines

Siemens Aktiengesellschaft

148

Memory Time Switch CMOS (MTSC)

PEB 2045

8

PEx 2045

PCM IN

2 MHz

16

PCM OUT

2 MHz

ITS00583

Memory time switch 16/16 for a non-blocking 512-channel switch

8

PEx 2045

11

PEx 2045

21

16

PEx 2045

12

PEx 2045

22

PCM IN

2 MHz

PCM OUT

2 MHz

8

PEx 2045

23

PEx 2045

13

8

PEx 2045

24

PEx 2045

14

ITS00584

Memory time switch 32/32 for a non-blocking 1024-channel switch using tristate function

Block Diagram of two PCM Switch Configurations with PEB 2045

Siemens Aktiengesellschaft

149

Memory Time Switch Small (MTSS)

PEB 2046

General Description

Type

Package

The MTSS PEB 2046 is a monolithic CMOS device which

has the ability to connect any of the 256 PCM channels of

eight incoming PCM lines to any of the 256 PCM channels of

eight output lines.

PEB 2046-N

PEB 2046-P

P-LCC-44-1 (SMD)

P-DIP-40-1

The input information of a complete frame is stored in the

speech memory SM. The incoming 256 channels

of 8 bits each are written in sequence into fixed positions in

the SM. This is controlled by the input counter in the timing

control block with an 8-kHz repetition rate.

Features

• Time/space switch for 2.048-kbit/s PCM systems

• Switching of up to 256 incoming PCM channels to up to

256 outgoing PCM channels

• Eight input and eight output PCM lines

• Configurable for a 4096- and 8192-kHz device clock

• Tristate function for further expansion and tandem

operation

• 8-bit µP-interface

• Single +5-V power supply

• Advanced low power CMOS technology

For output, the connection memory (CM) is read in sequence.

Each location in CM points to a location in the speech

memory. The byte in this speech memory location is read into

the current output time-slot. The read access of the CM is

controlled by the output counter which also resides in the

timing control block.

Thus the CM needs to be programmed beforehand for the

desired connection. The CM address corresponds to one

particular output time-slot and line number. The contents of

this CM-address point to a particular input time-slot and line

number (now resident in the SM).

MOD

STA

IAR

DB7-

DB0

Input Buffer

Connection

Memory

CM

µ P

Interface

A0

RD

WR

CS

Speech Memory

SM

CGR

Timing Control

Output Buffer

SP

CLK

ITB00604

Block Diagram

Siemens Aktiengesellschaft

150

Memory Time Switch Large (MTSL)

PEB 2047

Features

Type

Package

P-LCC-44-1 (SMD)

• Time/space switch for 2048-, 4096- or 8192-kbit/s PCM

systems

PEB 2047-N

• Different modes programmable for input and output

separately 2048 kbit/s (4096 kbit/s, 8192 kbit/s or mixed

mode)

• Switching of up to 1024 incoming PCM channels to up to

5124 outgoing PCM channels

• Configurable for a 4096-kHz or 8192-kHz device clock 16

input and 8 output PCM lines

• Constant frame delay for switching of wideband data, e.g.

ISDN H-channels or minimized delay for voice applications

• Tristate function for further expansion and tandem

operation

• µP read access to PCM data

• Programmable clock shift with half clock step resolution for

input and output

• Individual line delay measurement and clock shift

mechanism for 8 PCM inputs

• Built-in selftest

• 8-bit Motorola or Intel type µP interface

• Advanced low power 1 µ-CMOS technology

• Single 5-V-power supply

4

MTSL

CLK

PCM IN

8 MHz

8

PCM OUT

8 MHz

MTSL

CLK

8.192 MHz

ITS05937

Memory Time Switch for a Non-blocking 1024 Channel Switch with 8-MHz Device Clock

Siemens Aktiengesellschaft

151

Memory Time Switch Large (MTSL)

PEB 2047

General Description

microprocessor command. As a result the input countervalue

on the rising edge of the FS signal can be read from an

internal register. Thus delay compensation is easily

managed by programming appropriate clock shift values

and/or a possible software offset.

The MTSL PEB 2047 is a memory time switch device.

Operating with a device clock of 4096 kHz or 8192 kHz it can

connect any of 1024 PCM-input channels to any of 512

output channels.

During operation of the chip, a frame length check, which

controls correct synchronization by the SP pulse and

generates an interrupt in case of lost or achieved

synchronization is also supplied.

The input information of a complete frame is stored

in the on-chip 8-kbit data memory DM. The incoming

1024 channels of 8 bits each are written in sequence into

fixed positions in the DM. This is controlled by the input

counter in the timing control block with an 8-kHz repetition

rate.

The standard 8-bit µP interface can communicate with Intel

multiplexed/demultiplexed microprocessors as well as with

Motorola demultiplexed processors. It gives access to the

internal registers and to the control – and data memory. Five

directly addressable registers are provided. All other

registers and the memories are accessed by a simple three

byte indirect access method (similar to the MTSC PEB 2045).

For outputting, the connection memory (CM) is read in

sequence. Each location in CM points to a location in the data

memory. The byte in this data memory location is transferred

into the current output time-slot. The read access of the CM

is controlled by an output counter.

The switching path of the MTSL including input buffer, data

memory, control memory, output buffer and timing control

can be tested in the system by a built-in selftest. After

activating this mechanism it takes 1.25 ms (8192 kHz) until

the result “selftest ok/selftest not ok” can be read from the

internal status register.

The synchronization of this procedure will be achieved by a

rising edge of the synchronizing pulse SP, which is always

sampled with the falling edge of the device clock.

Different modes of operation are configurable at the PCM-

input interface. Also, 8 PCM-input lines can be synchronized

with individual clock shift values to compensate different line

delays. If more than 8 inputs are used one clock shift value

controls up to two ports at the same time.

After test completion the control-memory is also reset.

In applications where 64-kbit/s channels are combined for

higher data rates (e.g. ISDN H-channels) the MTSL ensures

that all switched time-slots are output in the same frame.

The input lines IN8 to IN15 can be used as additional

frame-synchronization inputs FS. After synchronizing the

device by the SP pulse, the FS inputs can be evaluated on a

per port basis. This evaluation procedure is started by a

In voice applications where a low delay is important, the

MTSL can be programmed for minimized switching delays.

Wideband Switching of 64-kbit / s Time-Slots

384-kbit / s

"Bundle"

192-kbit / s

"Bundle"

Individual

64-kbit / s

Time-Slots

32

1

2

3

4

5

6

7

8

9

10 11 30 31 32

1

2

3

ITT01746

Frame 0

Frame 1

Frame 2

Data "Bundle":

- switched time-slots have to be output in the same frame

MTSL Submultiplexing of 64-kbit/s Time-Slot

Siemens Aktiengesellschaft

152

Memory Time Switch Large H-16 MHz (MTSL-16)

PEB 2047-16

General Description

Type

Package

P-LCC-44-1 (SMD)

The MTSL-16 is an upward compatible device to the MTSL.

The MTSL-16 supports 16-MHz clocking and switching

capability of 1024 × 1024 time-slots.

PEB 2047-16-N

• Tristate function for further expansion and tandem

operation

• µP access to PCM data

Features

• Programmable clock shift with half clock step resolution for

input and output

• Individual line delay measurement and clock shift

mechanism for 8 PCM inputs

• Upward compatible to MTSL

• Time/space switch for 2048-, 4096-, 8192- or 16384-kbit/s

PCM systems

• Different modes programmable for input and output

separately (2048-, 4096-, 8192- or 16384-kbit/s or mixed

mode)

• Switching of up to 1024 incoming PCM channels to up to

1024 outgoing PCM channels

• Built-in selftest

• 8-bit Motorola or Intel type µP interface

• Advanced low power 1-µ CMOS technology

• Single 5-V-power supply

• Configurable for a 8192-kHz or 16384-kHz device clock

• 16 input and 8 output PCM lines

• Constant frame delay for switching of wideband data, e.g.

ISDN H-channels or minimized delay for voice applications

PCM IN

8 MHz

8

PCM OUT

8 MHz

MTSL

CLK

16.384 MHz

4

MTSL

CLK

PCM IN

8 MHz

8

PCM OUT

8 MHz

MTSL

CLK

8.192 MHz

ITS00225

Memory Time Switch for a Non-blocking 1024 Channel Switch with 16-MHz Device Clock

Siemens Aktiengesellschaft

153

™

Multipoint Switching and Conferencing Unit-Attenuation (MUSAC -A)

PEB 2445

General Description

Type

Package

P-LCC-44-1 (SMD)

The MUSAC-A is an upward compatible device to the

components MTSC and MUSAC. Additionally to the standard

MUSAC features switching and conferencing, the MUSAC-A

PEB 2445-N

Conference Mode

supports additional attenuation functions.

• Up to 64 conference channels in any combination

• Up to 21 independent conferences

simultaneously (3 subscribers)

• Programmable attenuation (0/3/6/9 dB) on each input

channel

• Programmable attenuation (0/3 dB) on each output

channel

• Programmable PCM-level adaption (attenuation or

amplification) of up to 64 channels

• Programmable noise suppression (four thresholds)

• Conference overflow handling

Every time-slot is freely programmable in 1-dB step

resolutions to an attenuation range from 0 to 12 dB and

amplified from 0 to 4 dB.

With enlarged attenuation functions to every time-slot the

MUSAC-A fulfills the ability for new requirements. l.e.

different PBX terminals could be adapted to a certain

reference point from the private network to the public

network.

Features

• Tone insertion capability

• A-Law/µ-Law compatible

• Compatible with all kinds of PCM-byte formats

Switching

• Time/space switch for 2048-, 4096- or 8192-kbit/s PCM

systems

• Switching of up to 512 incoming PCM channels to up to

256 outgoing PCM channels

Multipoint Switching

• 16 input and 8 output PCM lines

• Different kinds of modes (2048, 4096, 8192 kbit/s or

mixed mode)

• Configurable for a 4096- and 8192-kHz device clock

• Tristate function for further expansion and tandem

operation

• Multiple independent LAN s within one PBX

• Multiplexing of up to 64 channels

• 64-kbit/s channels

General

• 8-bit µP interface

• Single + 5-V-power supply

• Advanced low power CMOS technology

• TTL compatible inputs/outputs

• Upward compatible to MTSL

Attenuation and Amplification

• Attenuation and amplification of every time-slot

• Attenuation range from 0 to 12 dB

• Amplification range from 0 to 4 dB

Siemens Aktiengesellschaft

154

™

Multipoint Switching and Conferencing Unit-Attenuation (MUSAC -A)

PEB 2445

Timing

PCM

IN

PCM

OUT

Attenuation

Time Switch

Signal

Processor

µP Interface

Address

Data

Control

ITS03806

Block Diagram

Reference Point

Public Network

Private Network

Analog

Line

Card

a / b

Analog

ISDN

Line

Card

2B + D

ISDN

Central

Office

™

MUSAC -A

NT

Prop.

Line

Card

CEPT / T1

ISDN

µC

Loudness Ration

Echo Attenuation

ITA03955

PBX-Example Attenuation for Every Time-Slot

Siemens Aktiengesellschaft

155

Communication Network ICs

Multichannel Network Interface Controller for HDLC

MUNICH32; PEB 20320

Siemens Aktiengesellschaft

157

Communication Network ICs

Product Overview

Type

Short Title

Function

Page

SAB 82525

SAB 82526

HSCX

HSCX1

High-Level Serial Communication Controller Extended

162

SAB 82532

SAB 82538

SAB 82518

PEB 20320

ESCC2

ESCC8

ASCC8

MUNICH32

ADMA

Enhanced Serial Communication Controller (2 channels)

Enhanced Serial Communication Controller (8 channels)

Universal Asynchronous Reciever/Transmitter (UART)

Multichannel Network Interface Controller for HDLC

Advanced DMA Controller for 16-bit Microcomputer Systems

163

165

161

167

169

SAB 82C257

SAB 82C528A

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A World of Applications

Data communication has gained a key role in modern

computer systems. We are on the threshold of an era of total

communication: every (micro)computer unit has to be able to

communicate with other devices – either in synchronous or

asynchronous data transmission mode.

Office Automation and

Wide Area Networks (WAN)

Typical ESCC2 (Enhanced Serial Communication Controller

with 2 channels, SAB 82532) applications are

communication boards for workstations and minicomputers

as well as l/O multiplexers, bridges and gateways (X.24,

PRI). ESCC2 can be used for nearly all applications from

terminal adaptors and fast HDLC links to Primary Rate

Interfaces (T1/S2) or ISDN interfaces (SO); using unique

software.

Let us have a look at this rapidly growing world of many

different applications. There are among others the following

applications: telecom, office automation, traffic control,

medical equipment, and factory automation.

Telecom

If the designer requires multichannel access, he can save a

tremendous amount of board space by using the highly

integrated eight-channel multiprotocol controller SAB 82538

(ESCC8): four ESCC2s (eight serial channels) in one

package.

Todays telephone and telecommunication equipment is

getting more and more digitalized while the older analog units

are being replaced. This means that analog signals are

converted to digital data as soon as possible before being

transferred and processed. Back-conversion is made as late

as possible. Consequently the amount of transferred data in

telecom applications is increasing tremendously. Depending

on the desired data throughput and transmission mode, the

designer always gets the right choice with serial

communication ICs from Siemens. There are a lot of goals to

be met: transfer control by high level transportation protocols,

transmitting and receiving data pockets, time-division

multiplexing in time-slot systems, handling of different data

encoding/decoding schemes, etc.

Fast LANs

If clock recovery up to 4 Mbit/s is needed (e.g. in fiberoptic

transmission systems), the designer can use ESCC2

(Enhanced Serial Communications Controller, SAB 82532).

Basically, the ESCC2 is a faster 16-bit HSCX with a big

bundle of extra functions. HDLC-data transfer can be

implemented up to 10 Mbit/s. ESCC2 is a multiprotocol

controller which enables designers to use synchronous,

bisynchronous as well as asynchronous, fast data transfer

with one chip on one software basis.

All these kinds of data transfer can be managed by

SAB 82525 or SAB 82526. These ICs are called High-Level

Serial Communication Controllers Extended (HSCX,

SAB 82525) and Single-Channel High-Level Serial

Communication Controllers Extended (HSCX1, SAB 82526).

They were especially designed for serial communication

interfaces in telecom networks requiring HDLC based

protocols.

Typical HSCX applications are network communication

boards, central D-channel signaling, DMI boards, data-link

controllers in digital mobile radio networks as well as cordless

telephone sets.

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Product Overview

Performance / Integration

MUNICH32

PEB 20320

32-Bit

ADMA

ESCC8

ASCC8

SAB 82C258

SAB 82538

SAB 82518

16-Bit

ESCC2

SAB 82532

ESCC1

SAB 82531

HSCX

SAB 82525

ICs available

ICs in development

ICs in definition

8-Bit

HSCX1

SAB 82526

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

ITB01818

Siemens’ family of serial communication controllers

ESCC2

comprises a full range of different ICs. While each of them is

designed to enhanced particular features, together they

compose a wide profile of performance. Thus, most likely our

family of complementary devices offers an ideal solution to

many applications in serial data communications.

The Enhanced Serial Communications Controller (ESCC2) is

a multiprotocol controller offering an extraordinary profile of

protocol options at a high-speed transfer rate of up to

10 Mbit/s for each of its two independent channels.

ESCC2 was developed for the different communication

requirements of wide area network, local area network, small

area network and proprietary network applications.

HSCX

The High-Level Serial Communications Controller Extended

(HSCX) supports a number of synchronous standardized

protocols and a greater number of proprietary protocols at a

transfer rate of up to 4 Mbit/s. Each of its two channels works

independent of the other. Its specific fields of application are

proprietary HDLC local area networks (LAN).

The result is a communications controller as a standard for

implementing Open System Interconnection (OSI) layers-1

and -2 in all these applications. This fact noticeably reduces

development and system costs.

The board space, for example, is reduced by on-chip collision

detection and resolution, programmable preamble, clock

recovery, the logic for multiple protocols and multiple

encodings, 16- and 32-bit CRC, time-slot, assignment,

queued interrupt status for all important events like receiver

FIFO full, receiver FIFO overrun and end of frame

transmission.

HSCX 1

The Single-Channel High-Level Serial Communications

Controller Extended (HSCX1) is the single channel version of

HSCX.

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Product Overview

Features

Type

HSCX1

SAB 82526

HSCX

SAB 82525

ESCC2

SAB 82532

ESCC8

SAB 82538

ASCC8

SAB 82518

MUNICH32

PEB 20320

Number of serial channels

Parallel ports

1

2

8

32

no

8-bit

28-bit

no

Serial communication

Supported protocols

SYNC

SYNC/ASYNC SYNC/ASYNC ASYNC

SYNC

HDLC/SDLC

ASYNC/

HDLC/SDLC ASYNC

ASYNC/

HDLC/SDLC

BISYNC

Encoding schemes

NRZ, NRZI

FM0, FM1

Manchester

NRZ/NRZI

FM0, FM1

Manchester

NRZ

Programmable preamble

CRC

no

yes

no

16-bit

4 Mbit/s

–

16-bit

4 Mbit/s

–

16-/32-bit

10 Mbit/s

2 Mbit/s

64/64 bytes

8-/16-bit

16-/32-bit

10 Mbit/s

2 Mbit/s

64/64 bytes

8-/16-bit

–

16-/32-bit

Max baud rate/channel (SYNC)

Max baud rate/channel (ASYNC)

–

4 Mbit/s/128 Kbit/s

2 Mbit/s

no

–

Integrated clock recovery (DPLL) up to 1.2 Mbit/s

1.2 Mbit/s

64/64 bytes

8-bit

no

FIFO size per channel (R × D/T × D) 64/64 bytes

64/64 bytes

8-/16-bit

256/256 bytes

16-/32-bit

Data-bus width

Data bus types

DMA controller on-chip

DMA support

8-bit

Intel/Motorola Intel/Motorola Intel/Motorola Intel/Motorola Intel/Motorola Intel/Motorola

no

yes

–

yes

no

Time-slot assignment

Package

yes

P-LCC-44

P-LCC-68

P-MQFP-160 P-MQFP-160 P-MQFP-160

P-MQFP-44

The reduction of the software size, due to the 16-bit Intel or

Motorola processor interface, the direct register accessibility,

large FlFOs, vectorized interrupts and four channel DMA

support lead to higher performance and decrease CPU time

to an absolute minimum.

32 data channels of a full-duplex PCM highway. It has been

designed for use in fractional T1 interfaces as well as for

applications in switching systems.

ADMA

Less system cost, less development cost, less board

space, less power consumption and high performance in a

proven 1-µm CMOS technology are what you gain by using

this communication genius as a standard for all your

applications.

The Advanced DMA Controller (ADMA) is a four channel l/O

coprocessor that is optimized to handle data transfers in

either 8-, 16- or 32-bit microprocessor systems. It can

transfer up to 40 Mbytes of data per second in a 20-MHz

system. The ADMA transfers data using single cycle, two

cycle and 32-bit fly by operations and can gather or scatter

data with efficient linked list data chaining, making it one of

the most versatile DMA controllers available today. A smaller,

reduced cost version of the ADMA (SAB 82C257) is also

available.

The following ICs are in development or under definition and

will be available in due time to offer new attractive solutions

for serial communication control.

ESCC8

The eight-channel Enhanced Serial Communications

Controller (ESCC8) offers eight independent serial channels.

Basically it consists of four ESCC2 cores. It is a very suitable

solution for multiprotocol and multichannel applications.

ASCC8

The ASCC8 is an eight-channel Universal Asynchronous

Receiver/Transmitter (UART). It is optimized to handle eight

high-speed asynchronous channels at rates of up to 2 Mbit/s

in 16-×-oversampling mode. The ASCC8 is ideally suited for

applications that include card-to-card signaling MODEM

pools, asynchronous routers, and simple high speed

point-to-point communications between processing elements

within a large system.

MUNICH32

The Multichannel Network Interface Controller for HDLC

(MUNIC32) is a protocol controller for handling up to

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High-Level Serial Communications Controller

Extended (HSCX)

SAB 82525

SAB 82526

General Description

Type

Package

The HSCX (SAB 82525) has been designed to implement

high speed communication links using HDLC protocols and

to reduce the hard and software overhead needed for serial

synchronous communications.

SAB 82525-N

SAF 82525-N

SAB 82526-N

SAF 82526-N

SAB 82525-H

P-LCC-44-1 (SMD)

P-MQFP-44-1 (SMD)

Due to its 8-bit demultiplexed adaptive bus interface it fits

perfectly into every INTEL or Motorola 8- and 16-bit

microcomputer system.

The HSCX directly supports the X.25 LAPB, the ISDN LAPD-

and SDLC protocols and is capable of handling a large set of

layer-2 protocol functions independently from the host

processor.

Features SAB 82525 (82526)

• Two (one) independent HDLC/SDLC channels

• High level support of LAPB/LAPD protocols

• Oscillator DPLL and baud rate generator for each channel

• Collision detect and resolution logic

• Data rate up to 4 Mbit/s

• Clock recovery up to 1.2 Mbit/s

• 8 bit parallel multiplexed and demultiplexed system bus

adaption

The time division capability of the SAB 82525 and other

programmable telecom features make it suitable for time-slot

oriented PCM systems designed for packet switching. Due to

its high speed data transfer and high level protocol support it

fits very well in industrial applications e.g. Iaser printers.

The HSCX1 (SAB 82526), the single channel version of the

HSCX, opens another wide application area.

• 64-byte FIFO per channel and direction

• 4 (2) channel DMA interface

• CMOS technology

For an easy access to the wide variety and complexity of

synchronous data transfer Siemens provides a PC based

HSCX evaluation Kit.

The SAB 82525/82526 operates in the temperature range

0 to 70 °C, the SAF 82525/82526 in the range -40 to 85 °C.

Channel A

A0- A6

RxDA

TxDA

RTSA

CTSA /

CxDA

LAP

Controller

Decoder

Collision

Detection

SP-REG

D0- D7

RD / IC1

WR / IC0

DPLL

Data

Link

Controller

Transmit

FIFO

RxCLKA

CS

BRG

TSA

Clock

Control

ALE / IM0

µP Bus

Interface

Receive

FIFO

AxCLKA

TxCLKA

INT

RES

IM1

TxCLKB

AxCLKB

RxCLKB

DRQTA

DRQRA

DACKA

DMA

Interface

CTSB /

CxDB

DRQTB

DRQRB

DACKB

RTSB

TxDB

RxDB

ITB00946

Channel B

Block Diagram

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Enhanced Serial Communication Controller

(ESCC2)

SAB 82532

General Description

Type

Package

Max. Data Rate Time-

The Enhanced Serial Communication Controller ESCC2

(SAB 82532) is a multiprotocol data communication

controller with two symmetrical serial channels. It has been

designed to implement high speed communication links and

to reduce hardware and software overhead needed for serial

synchronous/asynchronous communications.

Clocked

Slot

Mode

ext.

int.

(DPLL)

SAB 82532-N

P-LCC-68-1 2 Mbit/s 2 Mbit/s no

SAB 82532-N-10 P-LCC-68-1 10 Mbit/s 2 Mbit/s yes

The version 82532N-10 of the ESCC2 opens a wide area for

application which use time division multiplex methods (e.g.

time-slot oriented PCM systems, systems designed for

packet switching, ISDN applications).

Protocol Support (HDLC / SDLC)

• Various types of protocol support depending on operating

mode

– Auto-mode (automatic handling of S- and l-frames)

– Non-auto mode

– Transparent mode

General Features

Serial Interface

• Handling of bit oriented functions

• Support of LAPB / LAPD / SDLC / HDLC protocol in auto-

mode (I- and S-frame handling)

• Modulo 8 or modulo 128 operation

• Programmable time-out and retry conditions

• Programmable maximum packet size checking

• Two independent full-duplex serial channels

– On-chip clock generation or external clock source

– On-chip DPLL for clock recovery of each channel

– Two independent baud rate generators

– Independent time-slot assignment for each channel

with programmable time-slot length (1 - 256 bits)

• Async, sync character oriented

(MONOSYNC/BISYNC) or HDLC/SDLC modes (including

SDLC LOOP)

• Transparent receive/transmit of data bytes without framing

• NZR, NRZI, FM and Manchester encoding

• Modem control lines (RTS, CTS, CD)

• CRC support:

– HDLC/SDLC: CRC-CCITT or CRC-32

– (automatic handling for transmit/receive direction)

– BISYNC: CRC-16 or CRC-CClTT

– (support for transmit direction)

• Support of bus configuration by

collision detection and resolution

• Statistical multiplexing

MP Interface and Ports

• 64-byte FlFOs per channel and direction

(byte or word access)

• 8/16-bit microprocessor bus interface

(Intel or Motorola type)

• All registers directly accessible

(byte and work access)

• Efficient transfer of data blocks

from/to system memory via DMA or interrupt request

• Support of Daisy Chaining and Slave Operation

with Interrupt Vector generation

• 8-bit programmable bidirectional universal port

• Continuous transmission of 1 to 32 bytes possible

• Programmable preamble (8 bit) with selectable

repetition rate (HDLC/SDLC and BISYNC)

• Data rate up to 10 Mbit/s

• Master clock mode with data rate up to 4 Mbit/s

Applications

• Universal, multiprotocol communication board for

Workstation- and PC-boards

• Terminal controllers

• Computer peripherals

• Time-slotted packet networks

• Multimaster communication networks

• LANs

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Enhanced Serial Communication Controller

(ESCC2)

SAB 82532

A0 - A6

D0 - D15

Config.

Registers

LAP B / D

Controller

RxDA

Encoder

Decoder

TxDA

RTSA

Collision

Detection

Data

Link

Controller

CTSA / CxDA

CDA

RES

16

ALE

Bus

Timer

- Sync.

Inter-

face

Unit

WR / R / W

RD / DS

BHE / BLE

WIDTH

DTACK

CS

Clock

Control

Transmit

FIFO

64 Byte

- Async.

- Bisync.

DPLL

BRG

Receive

FIFO

64 Byte

Preamble

Generator

TxCLKA

RxCLKA

TSA

Channel A

INT

P0

8 Bit

Parallel

Port

Inter-

rupt

Inter-

face

INTA

IE0

P7

XTAL1

IE1

Oscillator

DRTA

DRRA

DACKA

XTAL2

RxDB

TxDB

RTSB

CTSB / CxDB

CDB

TxCLKB

RxCLKB

ITB01780

DMA

Inter-

face

DRTB

DRRB

DACKB

Channel B

Block Diagram

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Enhanced Serial Communication Controller

(ESCC8)

SAB 82538

General Description

Type

Package

Max. Data Rate Time-

The Enhanced Serial Communication Controller ESCC8

(SAB 82538) is a data communication device with eight serial

channels. It has been designed to implement high speed

communication links and to reduce hardware and software

overhead needed for serial synchronous/asynchronous

communications.

Clocked

Slot

Mode

ext.

int.(DPLL)

SAB 82538-H

P-MQFP-160-1 2 Mbit/s 2 Mbit/s no

SAB82538-H-10 P-MQFP-160-1 10Mbit/s 2 Mbit/s yes

The version 82538 H-10 of the ESCC8 opens a wide area for

application which use time division multiplex methods (e.g.

time-slot oriented PCM systems, systems designed for

packet switching, ISDN applications).

Protocol Support (HDLC / SDLC)

• Various types of protocol support depending on

operating mode

– Auto-mode (automatic handling of S- and I-frames)

– Non-auto mode

General Features

Serial Interface

– Transparent mode

• Handling of bit-oriented functions

• Support of LAPB / LAPD / SDLC / HDLC protocol in auto-

mode (I- and S-frame handling)

• Modulo 8 or modulo 128 operation

• Programmable time-out and retry conditions

• Programmable maximum packet size checking

• Eight independent full-duplex serial channels

• On-chip clock generation or external clock source

• On-chip DPLL for clock recovery of each channel

• Eight independent baud rate generators

• Independent time-slot assignment for each channel with

programmable time-slot length (1 - 256 bits)

• Async., sync. character oriented

MP Interface and Ports

(MONOSYNC BISYNC) or HDLC/SDLC modes

(including SDLC LOOP)

• Transparent receive/transmit of data bytes

without framing

• NZR, NRZI, FM and Manchester encoding

• Modem control lines (RTS, CTS, CD)

• CRC support:

– HDLC/SDLC: CRC-CClTT or CRC-32

(automatic handling for transmit/receive direction)

– BISYNC: CRC-16 or CRC-CClTT

• 64-byte FlFOs per channel

and direction (byte or word access)

• 8/16-bit microprocessor bus

interface (Intel or Motorola type)

• All registers directly accessible (byte and word access)

• Efficient transfer of data blocks from/to

system memory via DMA or interrupt request

• Support of Daisy Chaining and

Slave Operation with Interrupt Vector generation

• 28-bit programmable universal l/Os

(support for transmit direction)

• Support of bus configuration by

collision detection and resolution

• Statistical multiplexing

• Continuous transmission of 1 to 32 bytes possible

• Programmable preamble (8 bit) with

selectable repetition rate (HDLC/SDLC and BISYNC)

• Data rate up to 10 Mbit/s

• Master clock mode with data rate up to 4 Mbit/s

Applications

• Universal, multiprotocol communication board

• Asynchronous and synchronous terminal cluster

controllers

• LAN gateways and bridges

• Multiplexers, cross-connect points, DMI boards

• Time-slotted packet networks

• Packet switches, packet assemblers/disassemblers

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Enhanced Serial Communication Controller

(ESCC8)

SAB 82538

XTAL1 / 2

2

RES

A0 - A8

Osc.

Internal Data Bus

D0 - D15

16

ALE

WR / R / W

RD / DS

BHE / BLE

WIDTH

16

7

6

8

1

DTACK

Serial

Interface 0

CS

Bus

Inter-

face

Unit

FIFO

Timer

SDLC

INT

HDLC

INTA

IE0

BISYNC. ASYNC.

TSA DPLL BRG

IE1

28 - BIT

PARALLEL

PORT

IE2

DMA

ENDEC

Supp.

RxD0

TxD0

RTS0

RxCLK0 DRT0

TxCLK0 DRR0

PA0 - 7 PB0 - 7 PC0 - 7 PD0 - 3

CD0

DACK0

CTS0 / CxD0

ITB05129

Block Diagram

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Multichannel Network Interface Controller for HDLC

(MUNICH32)

PEB 20320

General Description

Type

Package

The Multichannel Network Interface Controller for HDLC

(MUNICH32, PEB 20320) is a multichannel protocol

controller which handles up to 32 data channels of a full-

duplex PCM highway. It performs layer-2 HDLC formatting/

deformatting or transparent modes of the DMI protocol,

passing on data to an external memory shared with one or

more processors.

PEB 20320-H

PEF 20320-H

P-MQFP-160-1 (SMD)

Bit Processor Functions (adjustable for each channel)

• Transparent mode or HDLC protocol selectable

• Automatic flag detection and transmission

• Shared opening and closing flags

• Zero-bit insertion and deletion

• Flag stuffing and flag adjustment for rate adaption

• Detection of interframe-time-fill change

• Channel inversion

The MUNICH32 is compatible with the LAPD ISDN

(Integrated Services Digital Network) protocol specified by

CClTT as well as with HDLC, SDLC, LAPB DMI protocols. It

provides any rate adaptation for time-slot transmission data

rates from 64 kbit/s, 56 kbit/s down to 8 kbit/s as well as the

concatenation of any time-slots to data channels supporting

ISDN superchannels.

• CRC generation and checking (16 or 32 bits)

• Transparent CRC option

• Error detection (abort, long frame, short frame, data under

and overflow) as well as ABORT/IDLE generation and

transmission

• V.110, X.30 80-bit framing,

network data rate up to 38.4 kbit/s

The MUNICH32 can be used in a wide area of

communication applications, e.g. in gateways with fractional

T1 interface, l/O multiplexers, central office switches or for

the connection of a digital PBX to a host computer or as a

central D-channel handler for 32 ISDN basic-access

D-channels. Up to four MUNlCH32s can be connected to one

PCM highway to implement a controller for 128 D-channels.

Processor Interface

The PEB 20320 operates in the temperature range 0 to

70 °C, the PEF 20320 in the range -40 to 85 °C.

• On-chip 64 channel DMA controller with buffer chaining

capability

• Compatible with Motorola 68020 processor family and

Intel 32-bit processor (80386)

Features

• 32-bit data and 32-bit address

buses (4-GByte RAM addressable)

Serial Interface

• Up to 32 independent communication channels

• Serial multiplexed (full-duplex) input/output for

2048-, 4096-,1544- or 1536-kbit/s PCM highways

• Interrupt-circular buffer with variable size

• Maskable interrupts for each channel

• Burst cycles of up to 16 long words

in the generic case are possible

• General on-chip receive and transmit

data buffer; the buffer size is 256 bytes each

• Loop mode, complete loop as well as single channel loop

• JTAG-boundary scan test

Dynamic Programmable Channel Allocation

• Compatible with T1/DS1 24-channel and

CEPT 32-channel PCM byte format

• Concatenation of any, not necessarily consecutive,

time-slot to superchannels independently for receive and

transmit direction

• Support of H0, H11, H12 ISDN channels

• Subchannelling on each time-slot possible

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Multichannel Network Interface Controller for HDLC

(MUNICH32)

PEB 20320

TCLK

TSP TDATA

TEST RESET SCLK

JTEST

CI (4 : 0)

5

RCLK RSP RDATA

4

CD

Serial Interface / Formatter Controller Unit

CSRCM

Configuration and

State RAM

TF

RD

Transmit Formatter

Receive Deformatter

TB

CM

RB

Transmit Buffer

DMA Controller

Receive Buffer

MI

Microprocessor Bus Interface

32

BE

A

D

ADS / DS W / R / READY / HOLD / HLDA BGACK HLDA0 / BERR INT / AR B16 I / M

AS R / W DSACK BR BG BG0 INT

(3 : 0) (31: 2) (31: 0)

ITA03968

Block Diagram

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Advanced DMA Controller

SAB 82C257

for 16-Bit Microcomputer Sytems (ADMA)

SAB 82C258A

General Description

Type

Package

Speed Muxed

Channel

The SAB 82258A is an advanced general-purpose four-

channel DMA controller tailored for efficient high speed data

transfer between peripheral devices and memories. It is

either coupled tightly with a companion CPU (local mode) or

working in stand alone applications using the remote mode.

The SAB 82258A is unique among DMA controllers providing

complete direct interfacing to the SAB 80286 as well as to

SAB 80186/188/86/88 bus.

SAB 82C257-1-N

P-LCC-68-1 (SMD) 10 MHz no

SAB 82C258A-12-N P-LCC-68-1 (SMD) 12 MHz yes

SAB 82C258A-20-N P-LCC-68-1 (SMD) 20 MHz yes

Features

• 16-bit DMA controller for

16-bit family processors

– SAB 80286

– SAB 80186 188

– SAB 8086/88

• 4 independent high-speed DMA channels

• 16 Mbyte addressing range

• 16 Mbyte maximum block length

• Memory based communication with CPU

• “On-the fly” compare, translate and verify operations

• Transfer rates up to 10 Mbyte/s

• 32-bit-fly-by transfers with

up to 20 Mbyte/s (10-MHz system)

• Single cycle and two cycle transfer

• Automatic chaining of command blocks

• Variable chaining of data blocks

• Multiplexer mode operation with up to 32 subchannels

• Local and remote (standalone) mode

• Support of 16-bit and 8-bit data buses

• Multiple programmable control of channel priorities

• Direct and fast CPU/channel communication

Its four superfast DMA channels transfer rate up to 10 Mbytes

per second are possible. If the maximum transfer rate

reaches as much as 20 Mbyte/second. In addition one of the

DMA channels may be configured as multiplexer channel so

that a large number of low speed peripherals can share the

use of the same channel. The interrupt structure belongs to

the fastest and most versatile ones available. Multiple

SAB 82258A DMAs can be integrated very easily by using a

simple local bus arbiter logic.

The SAB 82258A is the only DMA controller that provides

source or destination-oriented data chaining (two chaining

modes) as well as conditional command chaining (jumps

within channel program based on several conditions).

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Advanced DMA Controller

SAB 82C257

for 16-Bit Microcomputer Sytems (ADMA)

SAB 82C258A

Bus Interface

Unit

Address Unit

ALU

Central Control

Internal Channel

Requests

Address

Incrementer

L

a

t

c

h

Priority

Logic

Addr.

Data

Byte Count Unit

Instruction

Pointer

Registers

Pointer

Registers

Burst

Counters

Byte

Counters

Channel

Control

Signals

Internal Data Bus

Temp. Data

Registers

&

ROM

Data Path

Control

Data Handler

Data

Micro-

instruction

Cache

Channel

Command

Registers

Bus

Control

Signals

Bus

Control

Registers

Control

Status

Registers

A

L

U

Instruction

Registers

Match

Registers

Multiplexer

Channel

Registers

CLK

RESET

Timing

Generator

Mask

Registers

Pipeline

Registers

ITS05934

Block Diagram SAB 82C258A

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Asynchronous Transfer Mode (ATM) ICs

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Asynchronous Transfer Mode (ATM) ICs

Product Overview

Type

Short Title

FALC 54

IWE

Function

Page

178

179

180

181

182

183

184

PEB 2254

PXB 4220

PXB 4110

PXB 4230

PXB 4240

PXB 4310

PXB 43201

PXB 43202

Frame and Line Interface Component

Interworking Element

SARE

Segmentation and Reassembly Element

Unshielded Twisted Pair Transceiver

SDH/SONET Transceiver

UTPT

SDHT

ASM

ATM-Switching Matrix

ASP -up

ASP -down

ATM-Switching Preprocessor Chip Set (up)

ATM-Switching Preprocessor Chip Set (down)

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Asynchronous Transfer Mode (ATM) ICs

Introduction

Traditional telecommunication structures are based on Time

Division Multiplexing (TDM), offering fixed-bandwidth time-

slots. ATM however sends data only when required, i.e.

frames are sent asynchronously. By packing the information

in 53-byte cells, including a 5-byte header containing the

destination address, data is guided through the network

along virtual paths and channels. ATM offers bandwidth on

demand with highspeed transmission ranging from kilobytes

up to gigabytes per second.

In the last few years, Asynchronous Transfer Mode (ATM)

has made big leaps towards standardization and

practicability.

Acceptance in the market is high, due to the future need of

highspeed networking and seamless internetworking. This

new technology perfectly suits these market demands. ATM

networks offer bandwidth on demand, thus being capable of

matching the user’s data needs from sporadic high-

bandwidth bursts to isochronous constant-bandwidth. ATM

technology offers high-speed networks with various

bandwidths and works with any type of transmission

infrastructure. The very flexible basic structure allows to build

and interconnect high-speed WANs, corporate WANs/MANs,

backbone LANs, or powerful links to desktop terminals.

Siemens Semiconductor Group addresses the market’s

demand for this kind of network technology by being a driving

force in the standardization activities and providing a

complete ATM chipset to the market. ATM-system designers

are supported by a family of Siemens ATM devices to build all

kind of ATM applications. This ranges from dedicated ICs for

Network or Line Interface Cards to powerful ATM switches

and transmission devices.

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Asynchronous Transfer Mode (ATM) ICs

Building Seamless ATM Networks

ATM technology is capable of providing powerful networks

for various needs. Such an application could be a large

campus network, just as shown in the figure below. In this

example, several backbone switches, located at different

places, are linked together. However, ATM allows this

network to be managed centrally, since all backbone

switches are configured to logically constitute one single

switch. Workgroups are connected to the backbone via ATM

workgroup switches.

The functionality of the Siemens ATM chipset, such as the

cross connect feature of the ATM-Switching Matrix

PXB 4310, allows members of the same workgroups to

communicate effectively with each other without occupying

the backbone. Only two devices of the Siemens ATM chipset

are required to develop ATM-Network Interface Cards for

PCs and WS, providing seamless access to the network.

AWS

Fiber

ATM

Backbone

Switch

ATM

Backbone

Switch

ATM

Backbone

Switch

622 Mbit/s Fiber Ring

155 Mbit/s

ATM

Fiber

Backbone

Switch

NIC-Board

TM

UTP cat 3/5

SARE

TM

UTPT

TM

UTPT

Laser

µP

PC/WS

TM

UTPT

TM

UTPT

TM

SDHT

TM

ASM

TM

ASP

AWS-Board

ATM Workgroup Switch

Network Interface Card

ITB08483

ATM-Workgroup Switch Network Interface Card

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Asynchronous Transfer Mode (ATM) ICs

ATM-Application Examples

ATM-Workgroup Switch

Instead of using a hub to connect a small number of

computers (workgroup), an ATM-work group switch can be

applied. Data transmission to the computers is handled by

transceiver devices, such as the PXB 4230 for unshielded

twisted pair lines, or PXB 4240 for SDH/SONET lines. The

actual switching function is performed by the ATM-Switching

Matrix (ASM) PXB 4310.

This cell switch features 32 inputs and 16 outputs with cross

connect functionality. The ASM chip is designed to a special

cell format, in order to reduce the pin count and power

dissipation. Up-stream and down-stream conversion from the

standard 53-byte ATM-cell format to this Siemens proprietary

format SLIF (Switch Link Interface) is performed by the ASP

chipset PXB 43201 and PXB 43202.

10 x

UTOPIA

TM

UTPT

TM

UTPT

SLIF

TM

to PCs

ASP

TM

UTPT

1

2

TM

to Edge

Node

Switch

UTPT

TM

ASM

2 x

12

UTOPIA

TM

to Server

SDHT

ASP

ITB08484

ATM Workgroup Switch

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Asynchronous Transfer Mode (ATM) ICs

Network Interface Card (NIC)

A Network Interface Card can be designed with a Siemens

ATM two-chip solution. It consists of the PXB 4110, which

converts data (or video) frames to ATM cells, and a

transceiver device. For twisted pair lines, the PXB 4230

(Unshielded Twisted Pair Transceiver) is used, whereas for

optical transmission the PXB 4240 (SDH/SONET

Transceiver) is required.

Network Interface Card

Control

UTOPIA

ATM Layer

and AAL 3/4,

5 Functions

Transmission

Line

TM

UTPT

or SDHT

SARE

Line Termination

Function

PCI-Interf.

ITB08485

Network Interface Card

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Asynchronous Transfer Mode (ATM) ICs

Evaluation/Demonstration Tools

The EASY ATM Demonstration, Evaluation & Development

System provides designers of ATM systems with a H/W-and

S/W tool kit. The Network Interface Card Evaluation System

allows the designer to evaluate and test the following

members of the Siemens ATM IC family: The Segmentation

and Reassembly Element PXB 4110, the Unshielded

Twisted Pair Transceiver PXB 4230 and the SDH

Transceiver PXB 4240.

The demonstration system shows the functionality and

performance of the Siemens ATM chipset by demonstrating

high speed and/or time critical data transfer in multimedia or

videoconferencing applications.

Easy ATM NIC Board

PC / PCI Board with SARE

TM

and SDHT or UTPT

PXB 4230

STS-1

TM

(UTPT

)

UTOPIA

Opt.

Transc.

PXB 4240

(SDHT)

STM-1 / STS-3c

PXB 4110

TM

(SARE

)

CPU

RAM

PCI Interface

PCI Bus

ITB08486

EASY ATM NIC Board

PC / PCI Board with SARE and SDHT or UTPT

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Frame and Line Interface Component (FALC 54)

PEB 2254

General Description

Type

Package

P-MQFP-80-1 (SMD)

The Frame and Line Interface Component PEB 2254

(FALC54) is a high sophisticated single-chip solution for

primary rate PCM carriers., It may be programmed to operate

in either 1.544 Mbit/s (T1) or 2.048 Mbit/s (CEPT) carrier

systems. The FALC54 provides the complete functionality of

a line interface, a framer, clock generation (2 VCOs) and

signaling unit on one chip with greatly increased

functionalities. The FALC functions include selectable

multiframe, error checking, multiple line codes, alarm

reporting, maintenance and performance monitoring. All

signaling types are controlled by either the integrated CAS-

signaling controller or the integrated HDLC controller.

Furthermore, the FALC54 allows flexible access to facility

data link and service channels. Controlling and monitoring of

the devices is performed via a Siemens/Intel/Motorola

compatible 8/16-bit data bus.

PEB 2254-H

Features

• Covers both standards E1 and T1

• On-Chip Line Interface including Data & Clock Recovery

• On-Chip CAS-CC/CAS-BR Signaling Controller

• On-Chip HDLC Controller (LAPD, F/DL, Sa-bit data)

• On-Chip System Clock Generation Unit

• Meets CCITT, ETSI and AT&T Requirements for use in

systems that are compliant with:

AT&T CB119, TR-NWT-499, ANSI T1.406, CCITT G.703,

G.704, G.706, G.732, G.735-9, G.775, G.823-4, I.431,

ETS 300233, V5.1 Interface, V5.2 Interface

• 8-/16-bit microprocessor interface, Siemens/Intel/Motorola

compatible

• Performance Monitoring support (16-bit error counters,

1 second timer)

• JTAG-boundary scan interface

• P-MQFP-80 package

Sync.

8

X

8

Clock Generation

1T2B

HDLC

CAS-CC

CAS-BR

System

Highway

Line

Interface

Framer

G.821

G.706 app. B

TM

FALC 54 PEB 2254-H

ITB08476

Block Diagram

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Interworking Element (IWE )

PXB 4220

General Description

Type

Package

P-MQFP-256-1 (SMD)

The Interworking Element functions as a gateway between

Asynchronous Transfer Mode networks and time-slot based

networks. The device supports both the mapping and

demapping of ATM cells into/from PDH frame (T1/E1)

according to G.804 and the packetizing and depacketizing of

n x 64-bit time-slots into/from ATM cells according to AAL1 or

AAL0. Target end products are Network and Line Interface

Cards supporting the low bit rate UNI according I.432. The

IWE can be directly connected to the Siemens ASP chipset

via its UTOPIA level 1 interface at the ATM layer. At the

physical layer several devices of the Siemens Frame and

Line Interface Component PEB 2254 (E1/T1 framer) can be

connected to the IWE’s serial interface.

PXB 4220

Features

• Single chip full duplex ATM packetizer / depacketizer for

several T1/E1 highways

• All T1/E1 channels are independently configurable

• Structured and unstructured mode

• ATM-cell mapping according to G.804

• AAL1 and optional AAL0 functionality

• VPI / VCI assignment

• Support for partially filled cells

• UTOPIA level 1 interface

• 16-bit microprocessor interface

• Built-in data path loops fortest

• JTAG-boundary scan test support

• 0.5 µm 3.3-V CMOS technology

• P-MQFP-256 package

TM

IWE

PXB 4220

2 x 8

T 1 / E 1

AAL 0

AAL 1

UTOPIA

Interface

S / P

P / S

Processor

Interface

JTAG

4

T 1 / E 1

ITB08477

Block Diagram

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Segmentation and Reassembly Element (SARE )

PXB 4110

General Description

Type

Package

P-MQFP-208-1 (SMD)

The SARE is specifically developed to build up ATM

applications such as Network Interface Cards and ATM

switches/hubs. This Segmentation And Reasssembly

Element converts data (or video) frames to ATM cells. The

flexible architecture enables it not only to handle the ATM-

adaption layers AAL3/4 or AAL5, but also cell FIFO mode to

support CBR. The interface for the ATM-physical layer is

implemented as industry standard UTOPIA level 1. The

device operates this UTOPIA interface in either slave mode,

as required by switch/hub applications, or in master mode to

be used in NIC (Network Interface Card) products. On the

AAL side SARE features a PCl-bus interface. A 0.5-µ

technology with 3.3-V supply ensures a highly integrated and

cost effective system design. The SARE enables the

implementation of glueless, truly cost optimized solutions for

AAL-terminating equipment in ATM networks.

PXB 4110

Features

• AAL 3/4 and 5 segmentation/reassembly

• Transparent mode to support constant bit rate

• On-chip support of 32 virtual connections

• Built-in FIFO (2+10 cell receive and 4 cell transmit)

• Full duplex transfer rate 155.52 Mbit/s

• VC level OAM-cell detection and CRC-10 calculation

• Cell rate shaping in transmit direction with up to 8 (dual)

leaky buckets

• Bus master DMA with linked list structure and

programmable buffer length

• Integrated MMU with packet scatter/gather capability

• Built-in data path loops for self-test purpose

• JTAG-(IEEE 1149.1) boundary scan

• 0.5 µ 3.3-V CMOS technology

• Optional ext. RAM supports up to 64 K virtual connections

• 32-bit PCI-bus interface

• UTOPIA level 1 interface

• P-MQFP-208 package

TM

SARE

PXB 4110

32

2 x 8

UTOPIA

Interface

SAR

Unit

PCI

Interface

Context

RAM

Interface

JTAG

4

DMA

32

ITB08478

Block Diagram

Siemens Aktiengesellschaft

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Unshielded Twisted Pair Transceiver (UTPT )

PXB 4230

General Description

Type

Package

P-MQFP-160-1 (SMD)

The UTPT is a full duplex ATM transceiver for two pairs of

twisted pair lines, one for each direction.

PXB 4230

It supports both the ATT and IBM mode. In AT&T mode

provides automatic bit rate adaption depending on the quality

of the transmission line. The UTPT communicates with other

devices on the ATM side via the industry standard universal

multiport UTOPIA interface being compatible with UTOPIA

level 1 and level 2.

Features

• Single chip full duplex ATM transceiver for unshielded

twisted pair cat 3/5 cables

• Programmable to AT&T and IBM mode

• AT&T mode: STS-1 framing, CAP-n coding 51.84-Mbit/s,

25.92-Mbit/s and 12.96-Mbit/s automatic rate adaption

according to cable and B.E.R.

• IBM mode: 4b/5b coding, NRZI, 25.6 Mbit/s

• Serial, differential in/outputs with direct connection to line

transformers

As additional feature, the device is able to transmit 2B+1D

ISDN channels when operating in AT&T mode. It also

provides an ISDN IOM-2 inter-device interface and as such

can be directly connected to Siemens ISDN chips. The UTPT

is perfectly suited to be integrated into Network and Line

Interface Cards.

• Built-in clock recovery

• ATM-layer functions: HEC evaluation, payload

descrambling, cell delineation and cell rate decoupling

according to ITU-T I.423

• Universal multiport UTOPIA interface compatible to level 1

and level 2

• Complete overhead handling including bit error

measurement

• 16-bit microprocessor interface

• Built-in data path loops for test

• Support of JTAG-boundary scan test

• 0.5 µm 3.3-V CMOS technology

• P-MQFP-160 package

TM

UTPT

PXB 4230

2 x 8

Sonet /

25.6

PMD

Sonet /

25.6

TC Funct.

UTOPIA

Interface

Funct.

®

Clock

Recovery

Processor

Interface

IOM

Interface

JTAG

Interface

16

4

ITB08479

Block Diagram

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SDH/SONET Transceiver (SDHT)

PXB 4240

General Description

Type

Package

P-MQFP-160-2 (SMD)

The SDHT is a complete Synchronous Optical Network

Synchronous Digital Hierarchy framer for 155-Mbit/s ATM

implementations. It includes Transmission Convergence

(TC) Sublayer processing for ATM payloads and performs

the framing of data for transmission and receipt from an SHD

or SONET-based Physical Layer medium.

PXB 4240

Features

• Single chip full duplex ATM transceiver for STS-3c/STM-1

optical transmission lines

• Transfer rate 155.52 Mbit/s

• Serial, differential in/outputs with LVDS levels according to

IEEE 1596.3

• Output of serial, differential data stream with 155.52 Mbit/s

• ATM-layer functions: HEC evaluation, payload

descrambling, cell delineation and cell rate decoupling

according to ITU-T I.423

• UTOPIA interface level 1

• Complete overhead handling (incl. alarms, error

measurement, DCC, orderwire)

The flexible architecture allows the chip to operate in two

different modes. In ATM mode for use in transmission path

equipment, and in VC-4 mode to be used in multiplexer

section transmission equipment.

The SDHT-chip interfaces with the ATM layer via a standard

UTOPIA interface. Communication with the Physical Medium

Sublayer is handled via its LVDS-level interface. To control

the SDHT, a µP can be directly connected to the 16-bit

microprocessor I/F.

• Error counting with built-in 1 second timer

• 16-bit microprocessor interface

• Automatic laser shutdown

• Built-in data path loops for test

• Support of JTAG-boundary scan test

• 0.5 µm 3.3-V CMOS technology

• P-MQFP-160 package, pin compatible with UTPT

SDHT

PXB 4240

SDH

STM-1 /

SONET

STS-3c

UTOPIA

Interface

2 x 8

e.g.: Siemens

Processor

Interface

Single Mode Fiber

or Multimode

Fiber OC 3 ATM

Transceiver

Clk

JTAG

4

16

ITB08480

Block Diagram

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ATM-Switching Matrix (ASM )

PXB 4310

Advanced Information

General Description

Type

Package

PXB 4310

P-BGA-352

The ATM-Switching Matrix is a cell switch with a maximum

total throughput of 2.5 Gbit/s. The switch has a maximum

transport capacity of one STM-1 per output. Furthermore the

ASM has the capability of bundling lines to form ports up to

2.5 Gbit/s.

Features

• Self-routing switching matrix with multicast capability

• High performance: 10E-11 cell loss probability (at 95 %

Bernoulli type traffic)

• Central buffer architecture provides minimum cell delay

variation at high data throughput with up to 2.5 Gbit/s

• Routing header provides 48-bit routing address

• Scalable architecture from 16 x 16 to 256 x 256

• Configuration as multiplexer/concentrator

• I/O aggregation of lines to form 622-Mbit/s and 2.5-Gbit/s

ports

• Switch Link Interface interconnects (208 Mbit/s serial,

differential data link lines)

• Switch Link Interface uses LVDS levels for low crosstalk,

less interference and low power consumption

• Individual phase adaption per input; no separate clock

required

The ASM supports both self-routing and multicast. The

device can be used as either standalone or in a networked

configuration to build switching networks of arbitrary size. In

order to achieve a lower pin count and lower power

dissipation, the inputs and outputs are realized as serial,

differential transmission lines. This Siemens proprietary

interface is defined as SLIF (Switch Link Interface) and its

electrical characteristics are according to the LVDS standard.

Internally the ASM works with 64-byte ATM cells, each cell

containing the 53-byte ATM cell extended by routing and

housekeeping information. Conversion from 53-byte cell

format to SLIF format is done by the Siemens ASP (ATM -

Switching Preprocessor) chipset PXB 43201/2.

• 0.5 µm 3.3-V CMOS technology

• P-BGA-352 package

TM

ASM

PXB 4310

Shared

Buffer

SL

In

SL

Out

Intf.

SLIF

Queue

Control +

Routing

SLIF

Intf.

Processor

Interface

Clk

16

ITB08481

Block Diagram

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ATM-Switching Preprocessor Chip Set (ASP -up, ASP -down)

PXB 43201

PXB 43202

Advanced Information

Type

Package

PXB 43201

P-BGA-342

General Description

PXB 43202

The ATM-Switching Preprocessor (ASP) chipset PXB 43201

and PXB 43202 is used to adapt the 53-byte standard ATM

Features

cell format to the 64-byte Siemens proprietary format. This

cell format, also known as Switch Link Interface (SLIF), is

used by the Siemens ATM-Switching Matrix to achieve a

lower pin count and reduced power dissipation. At the

physical layer side the ASP supports via its UTOPIA interface

up to 4 physical layer devices with a total throughput of up to

150 Mbit/s. For example the following number of Siemens

devices can be connected with the ASP: Up to 4 Interworking

Elements (IWE) or Unshielded Twisted Pair Transceivers

(UTPT) or 1 SDH Transceiver (SDHT). The ASP devices are

designed to perform header translation and OAM functions

according to ITU-T I.610 and Bellcore 1248.

• Interfaces directly to ATM-switching networks built with

ASM chips

• Header translation

• Throughput 150 Mbit/s

• OAM functions according to ITU-T I.610 and bellcore

1248:

– Alarms: generation of AIS/RDI cells for all connections

(F4 and F5)

– Continuity check: automatic for all connections

– Loopback: automatic loop of LB cells

– Performance Monitoring: complete HW support for up to

64 connections

• Double switch plane support for redundant fail safe

switching systems

• System Control Information Flow via SLIF Datalink

supported

• Use external SDRAMs for storage of connection related

data

• 16-bit general purpose microprocessor interface

• JTAG-boundary scan

• P-BGA-342 ball grid array package

ATM Switching Network

SLIF

UTOPIA

SLIF

Receive Intf.

TM

ASP

-up

ASM

TM

ASP

-down

UTOPIA

Transmit Intf.

208 MHz

ITB08482

Block Diagram

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Development Systems for Information Technology

Siemens Aktiengesellschaft

185

Development Systems for Information Technology System Designs

1

Tools for Analog Line Card Design

Product Overview

Introduction

1.1

PCM Codec Filter for Analog Line Cards

in Digital Communication Systems

Todays highly complex system development projects make it

necessary to have a powerful development environment

available additionally to the components themselves.

The Siemens PCM Codec Filter are fully integrated PCM

CODEC and Filter in advanced low power CMOS technology

for applications in digital communication systems.

Some of the necessary tools are supplied by the chip

manufacturer himself.

Based on a digital signal processing technique

programmable digital filters adapt the transmission behaviour

especially for AC impedance matching transhybrid balancing

frequency response and gain.

The tools consist of either component evaluation boards or

sometimes even almost ready to copy system designs. Also

software chip drivers are often supplied to ease the

integration of components into a customer’s software design.

In some cases software skeleton solutions or even ready to

use software is supplied to speed up the whole system

design.

For analog line card designs in digital communication

systems a family of Siemens Codec-Filter ICs can be

offered:

Besides the tools supplied by the silicon vendor a lot of third

party tools are available on the market which can efficiently

be used. The support tools supplied by Siemens are typically

designed to be used in conjunction with a PC and third party

software tools giving a very powerful environment.

Codec

Channel

per Chip

Part

Number

Best

Application

SICOFI

1

2

4

1

PEB 2060

PEB 2260

PEB 2465

PEB 2466

PEB 3065

PEB 4065

PBX and CO

PBX

SICOFI -2

SICOFI -4

SICOFI -4 µC

SLICOFI

The application oriented guide describes the different

support tools supplied by Siemens in an application oriented

way and it gives hints to set up a development environment

by adding third party equipment whenever meaningful.

PBX

CO

This is an application oriented guide meant to provide a fast

way into the typical development environments customers

need. Such a general approach does of course not

necessarily describe the customers specific environment

exactly. However it describes the most common ones.

HV-SLIC

CO

As shown in the table above the best application for our

codec filter ICs may be in a Private Branch Exchange (PBX)

and/or in a Central Office (CO). The SICOFI, SICOFI-2 and

SICOFI-4 Codec-Filter ICs may also be used in TRUNK

applications.

The four channel codec filters PEB 2465 and PEB 2466 are

the logic continuation of a well established family of Siemens

Codec-Filter ICs.

The SLICOFI PEB 3065 is a single codec and filter with an

optimized high voltage. SLIC interface including all low

voltage SLIC functions. The DC-characteristic is fully digitally

programmable. Together with the HV-SLIC circuitry

PEB 4065, Siemens offers a complete system solution for

central office applications.

Based on an advanced digital filter concept the PEB 2465 as

well as the PEB 3065 provide excellent transmission

performance and high flexibility. They fulfill all specifications

to relevant CCITT, EIA and LSSGR recommendations. The

new filter concept (second generation) leads to a maximum

of independence between the different filter blocks.

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Development Systems for Information Technology

1.2

Software to Calculate Digital Filter Coefficients

1.3

Hardware Support for Analog Line Cards

Different software tools are available to get optimized sets of

filter coefficients for the Siemens Codec-Filter lCs easily and

quickly.

For development different hardware environments are

offered for the analog line card design. For additional detailed

information please refer also to the description of the Tools

for PCM Control and Switching System Designs.

Software

Codec

Part

To build a typical development environment for an analog

subscriber line card one of the following set-ups may be

used:

Number

SICOFI

SICOFI Coefficients

Program for PEB 2060

and PEB 2260

STS 2060

STS 2465

STS 3065

Codec

Codec Board

Additional

Hardware

QSICOS

SLICOS

Quad SICOFI

Coefficients Software

for PEB 2465/PEB 2466

SICOFI

SICOFI Test Board

STUT 2060

none

SICOFI -2

SICOFI Test Board

STUT 2060

none

SLICOFI Coefficients

Software for PEB 3065

SICOFI -2 Board

SIPB 5135

1) or 2)

SICOFI -4

SICOFI -4 Board

STUT 2465

1) or 2)

none

SICOFI -4 µC Kit STSI 2466

(SICOFI -4 µC Board

STUT 2466

EVC50X µC Board)

SLICOFI

SLICOFI Board

STUT 3065

1) or 2)

Additional Hardware

1. Board configuration:

SIPB 5000 + SIPB 5121 + SIPB 5311

2. PERCOFI Board STUT 2000

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187

Development Systems for Information Technology

1.3.1

Using the SIPB 5000 PC-Userboard System

in Conjunction with a Line Card Module

Instead of using the SICOFI-4 Board STUT 2465 also the

SICOFI-2 Board SIPB 5135 or the SLICOFI Board

STUT 3065 may be connected via IOM interface to the Line

Card Module SIPB 5121.

The next figure shows a set-up that is used to measure the

SICOFI and SLIC transfer characteristic using a PCM4 by

Wandel & Goltermann. In this configuration the PC

mainboard SIPB 5000, the Line Card module SIPB 5121, the

PCM4 adaptor SIPB 5311 and the SICOFI-4 Board

STUT 2465 are used.

If the STUT 2466 and the SICOFI-4 µC are used together, the

SIPB 5000 and SIPB 5121 are not required. Instead the

microcontroller board EVC50X (Part of STSI 2466 kit) is used

to program the SICOFI-4 µC.

SIPB 5121

Line-Card Module

Mainboard SIPB 5000

Power Supply

PCM 4

Adaptor

PCM Frame

PCM Input

Signal PFS

SLIC 1

SLIC 2

SLIC 4

SLIC 3

7

4

1

0

8

5

2

.

9

6

3

-

®

SICOFI -4

Board

STUT 2465

CLK

OUT

Analog

IN

Analog

OUT

PCM

IN

PCM

OUT

ITB05748

Set-Up to Measure Transfer Characteristics

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Development Systems for Information Technology

1.3.2

Using the PERCOFI Board STUT 2000

programmed via the RS232 interface by using the same

trackfiles that are used with the Mainboard SIPB 5000 and

the Line Card Module SIPB 5121 to program the codec

devices.

The PERCOFI Board is an universally usable board to

measure the SlCOFl-2 SICOFI-4 or SLICOFI. The PERCOFI

Board is not only to replace the SICOFI testboard

STUT 2060, but also to allow critical performance

measurements.

Instead of using the SICOFI-2 Board SIPB 5135 also the

SICOFI-4 Board STUT 2465 or the SLICOFI Board

STUT 3065 may be connected to the PERCOFI Board

STUT 2000 via IOM interface.

The following configuration shows a typical line card

application using the STUT 2000 PERCOFI Board and the

SICOFI-2 Board SIPB 5135. The PERCOFI Board is

7

4

1

0

8

5

2

.

9

6

3

-

PCM 4

RS 232

XXXXX

Power Supply

PERCOFI Board

STUT 2000

®

SICOFI -2

SIPB 5135

SLIC

ITB05749

Configuration with PERCOFI Board STUT 2000

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Development Systems for Information Technology

1.3.3

Using the SICOFI Test Board STUT 2060

1.3.4

SLIC Boards to be used with the SICOFI Family

The SICOFI test board STUT 2060 is a stand-alone board

which offers the possibility of connecting any external

customer specific SLlCs with the SICOFI PEB 2060/2260 for

evaluation of customer specific combinations of SLIC and

SICOFI. The next figure shows a set-up that allows

measurements and tests covering the transfer functions of

the complete subscriber line module.

A collection of SLIC babyboards has been designed to be

used with the SICOFI PEB 2060, SICOFI-2 PEB 2260 or

SICOFI-4 PEB 2465.

Codec

Available SLIC Module

Part

Number

PEB 2060/

2260

Transformer SLIC

Board

STUS 1001

STUS 3030

STUS 3090

STUS 3736

The board is programmable via an RS232 interface by a

terminal or PC. The registers of the PBC or PIC and SICOFI

can be accessed and therefore the SLIC can be controlled.

PEB 2060/

2260

STM L3000 + L3030 SLIC

STM L3000 + L3090 SLIC

Ericsson PBL 3736 SLIC

With the SICOFI testboard the SICOFI PEB 2060 and

SICOFI-2 PEB 2260 codec filter devices can be tested. The

PCM interface of the board can be connected directly to a

PCM4 Wandel & Goltermann test equipment. This set-up

allows to test the SLIC hardware and to verify the

programmed coefficients, which are calculated with the

SICOFI coefficients program.

PEB 2060/

2260

PEB 2060/

2260

PEB 2465

PEB 2060/

2260

PEB 2465

Ericsson PBL 3762/64

SLIC

STUS 3762

STUS 5502

STUS 5509

Different customer specific SLlCs or ready designed SLIC

boards available from Siemens Semiconductor may be

connected to the SICOFI test board STUT 2060 via a 64-pin

connector.

PEB 2060/

2260

PEB 2465

Harris SLIC HC5502

Harris SLIC HC5509

PEB 2060/

2260

PEB 2465

PCM Frame Signal PFS

7

4

1

0

8

5

2

.

9

6

3

-

PCM 4

XXXXX

CLK OUT Analog Analog

PCM OUT IN OUT

PCM IN

Power Supply

RS 232

SICOFI Board

STUT 2060

SLIC 1

SLIC 2

ITB06113

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2

Tools for ISDN Basis Rate Line Card Designs

U Transceiver Development Tool (2B1Q)

The IEC-Q Reference Board interfaces ISDN transmission

lines and terminal areas providing echo cancellation and

message recovery using digital techniques. Hence the main

use of the IEC-Q Reference Board is to accomplish

performance measurements i.e. bit error rate (BER)

measurements on the ETSI and ANSI defined loops.

2.1

Together with the SIPB 5121 Line Card Module the IEC-Q

Reference Board SIPB 2091 constitutes the layer-1

functionally needed for the evaluation of various digital line

card architectures using 2B1Q technique for interfacing with

the U-reference point.

The optimized layout of the Reference Board allows for

performance measurements in all operation modes available

with the IEC-Q. The so called hybrid was developed to reach

optimum loop lengths and to cover all 15 ANSI loops as well

as the 8 ETSI defined loops. The figure below shows a typical

configuration with LT and NT 1 where the interconnection

between the two U-transceiver devices is established with

means of a dual lead copper wire (U).

2.2

Introduction to the IEC-Q Reference Board

SIPB 2091, SIPB 2092 and SIPB 2092-H

The IEC-Q Reference Board was developed to demonstrate

the performance of the Siemens IEC-Q (PEB 2091)

U-interface transceiver IC. The IEC-Q (ISDN Echo

Cancellation Circuit) uses 2B1Q code for transmission on U.

A single board can be configured by the user to suit multiple

operation modes such as LT and NT modes. Test points

allow for comfortable monitoring of relevant signals. This

enables the developer to quickly comprehend both the

IC- and U-interface-related signals.

The SIPB 2092 additionally supports the stand-alone

(IOM-2) mode and the µP-interface mode. SIPB 2092-H is

identical to SIPB 2092 except that a P-TQFP-64 package

socket instead of a P-LCC-44 socket is provided. For stand-

alone operation of the IEC-Q, both SIPB 2091 and SIPB 2092

are equally suited.

Exchange

NT1

®

IOM

U

LT

NT

PC

ITS05942

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Development Systems for Information Technology

2.3

Bit-Error-Rate Measurement

with SIPB 5000 Main Board

The configuration below describes the use of standard LT/NT

applications for the purpose of BER measurements when

supplemented with two BEAM modules. The figure shows

the complete SIPB system set-up for a BER measurement in

LT-NT direction.

For bit-error-rate (BER) measurements on U the following

add-on modules are required on the LT side in addition to the

LT IEC-Q Reference Board:

ISDN Terminal Adaptor Module (ITAC ) SIPB 5140

LAYER-2 Module SIPB 5120-2

Comments:

For the bit-error-rate measurement the LT is configured in the

LT-512-kHz mode since the BEAM module only supports a

512-kHz-DCL clock rate.

Bit Error Adaptor Module (BEAM) SIPB 5312

The following modules are required for BER measurement

on the NT side in addition to the NT IEC-Q Reference Board:

With means of the two BEAM modules the BER test

equipment can be synchronized to the IOM clock rate as well

as insert and extract B1/B2 channel data via IOM. BER

measurement is then accomplished by comparing the

inserted with the extracted data. A line simulator is used for

emulating lines and loops including NEXT noise impairments

in order to run performance tests according to the relevant

specifications (ETSI/ANSI).

LAYER-2 Module SIPB 5120-2

Bit-Error-Adaptor Module (BEAM) SIPB 5312

TX

TX - CL

Bit Error

Measurement Device

Ext. Clock

RX

RX - CL

Data Clock

IN

Data OUT

BEAM

®

BEAM

ITAC

Layer 2

Mainboard SIPB 5000

DCL = 512 kHz

FSC= 8 kHz

DIN

FSC= 8 kHz

DIN

Next Noise

DOUT

B1 + B2

Testpattern

SIPB 2091/2

LT

Line

Simulator

SIPB 2091/2

NT

B1 + B2

ITS05943

Set-Up for Bit-Error-Rate Measurements Using SIPB 5000 System

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Development Systems for Information Technology

2.4

Bit-Error-Rate Measurements

with Bellcore Board (BELL 2091)

In conjunction with two IEC-Q Reference Boards, the so

called Bellcore Boards provide the most comfortable method

to evaluate the PEB 2091 and perform BER measurements.

No PC is needed for simulating 2B1Q U-transmission

configuration.

TX

TX - CL

Bit Error

Measurement Device

RX

Ext. Clock

RX - CL

DCL = 512 kHz

FSC= 8 kHz

DIN

DCL = 512 kHz

FSC= 8 kHz

DIN

Bellcore

LT - Simulator

Bellcore

LT - Simulator

DOUT

SIPB 2091/2

LT

Line

Simulator

SIPB 2091/2

NT

B1 + B2 Testpattern

B1 + B2 Loop-Back

ITS05944

Set-Up for Bit-Error-Rate Measurements Using Bellcore Board (BELL 2091)

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Development Systems for Information Technology

3

Tools for PCM Control

and Switching System Designs

The basic module needed to build a line card is either

SIPB 5121 or SIPB 5122. Depending on the requirements for

layer-1 interface (for digital line cards) and/or CODEC filter

(analog line cards) additional modules have to be connected.

The following modules may be combined with the line card

module:

3.1

Development Environment

3.1.1

A Typical Development Environment

for Subscriber Line Cards

When using the SIPB 5000 ISDN PC-Userboard system in

conjunction with a line card module, an engineer is capable of

designing his own digital or analog line card board.

Interface

Required Module

Part Number

Connection

Analog

SICOFI -2 Module

SLIC

SIPB 5135

e.g. STUS 5502

External

Analog

SICOFI -4 Board

SLIC

STUT 2465/2466

e.g. STUS 5502

External

Analog

SLICOFI Board (SLICOFI + HV-SLIC)

S-Access Module (ISAC -S)

SBCX Layer-1 Module

STUT 3065

SIPB 5100-0

SIPB 5116

External

S interface

SIPB 5000

External

QUAT -S Board

SIPB 5117-S

SIPB 2091/2

SIPB 2490/1

SIPB 5104

U

U -Layer-1 Module (IEC-Q)

SIPB 5000

External

k0

P0

k0

QUAT U Board (AFE + DFE-Q / DFE-T)

k0

U

-Access Module (ISAC -P)

SIPB 5000

External

P0

OCTAT -P Board

Layer1-Module (IBC)

SIPB 5117-P

SIPB 5113

U

SIPB 5000

P0

e.g. S-Interface

U-Interface...

Layer-1

Module

SIP 5121 / 5122

Line-Card Board

PCM

AMC 3

AMC 2

AMC 1

Mainboard

SIPB 5000

80C188 CPU

System

PC

Interface

ITB05750

Realization of a Digital Line Card

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Development Systems for Information Technology

SIP 5121 / 5122

Line-Card Board

®

IOM -2

AMC 3

AMC 2

AMC 1

Mainboard

SIPB 5000

80C188 CPU

System

PC

Interface

®

SICOFI -2

SIPB 5135

SLIC

STUS 5502

a / b

SLIC

STUS 5502

Example for an Analog Line Card Using External Modules

ITB05751

3.1.2

A Typical Development Environment

for a Switching System

The SIPB 7600 Memory Time Switching Board is a

PC/XT/AT based development tool that helps engineers to

get familiar with switching and conferencing ICs.

working with continuous data streams additional modules

(layer-1 modules) have to be connected via a 9-pin-flat cable

to the IOM-2 interface.

Test patterns may be generated on board and put as an input

to the switching and conferencing circuits. When

The figure below shows an example how to connect analog

as well as digital subscribers to the SIPB 7600:

®

SICOFI -2

SLIC Board

Module

U

Board

U

Board

k0

P0

STUS

5502

SIPB

5135

SIPB

5113

SIPB

2091/2092

80C188 CPU

System

MTSX Userboard

SIPB 7600

®

IOM -2

PC

Interface

ITB05752

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Development Systems for Information Technology

3.2

The Different Steps in Development

Designing the Hardware

The ISDN Telephone Development Board SIPB 8051 is a

more or less ready to copy environment to demonstrate the

terminal system in silicon using the ARCOFI-SP (PSB 2163),

the ISAC-S TE (PSB 2186) and the one-chip controller

SAB 80515 with the ISDN protocol software. An ITAC

(PSB 2110) for the rate adaption as well as an ISAC-P TE

3.2.1

The SIPB 5000 system can be used as a platform for all

development steps. In a later stage it is of course necessary

to make a cost optimized design. For this a subset of the

board design can be used. All the wiring diagrams are

shipped with the board to speed up this process.

(PSB 2196) for the U interface is also onboard.

PN

To set up a development environment for serious

developments it is best to use both an SlPB 7011A kit as a

network terminator being able to simulate the public ISDN

and secondly an SIPB 8051 system as the real development

platform. Both systems should be connected and of course a

PC should be connected to the SIPB 8051 to run a

C-Compiler and to download and debug code.

3.2.2

Developing the Software

In a premature stage of a development it is very useful to

verify the design by running program sequences on a similar

hardware platform. To manage this task Siemens offers a

very comfortable menu-driven testing and debugging

software. The package delivered with the userboard allows a

direct access to the chip registers by symbolic names.

Subsequent accesses may be written to a file and run as a

trackfile.

The Keil C51 professional package (in USA Franklin C51

package) as well as the development package of the

Swedish company lAR Systems (in USA Archimedes) have

been used with the SIPB 8051. Their high level language

debuggers can be used very efficiently with the SlPB 8051.

Example trackfiles for different configurations are delivered in

the package and will be a great help to the user in getting

started and to speed up his software development.

Both systems should be connected and an 8051 type

C-Compiler and high level language debugger should be

available. Additionally the IOS software should be used as a

very efficient software platform if a public protocol is required.

This software is a very compact software solution. It fits on a

one chip controller without needing additional memory. For

rapid prototyping or PTT approval an E²PROM version of the

80C515A is also available.

4

Tools for ISDN Basic Rate Terminal Designs

4.1

A Typical Development Environment

for an ISDN Phone or TA

The Siemens ISDN PC Board Kit SIPB 7011A is based on a

very modular tool environment. This allows to configure every

existing application just by replacing some modules. The

system can be configured as either a terminal itself or as a

network simulator. It can be used to program and evaluate

the chips but it can also be used to run real software (see

IOS).

®

IOM -2 TE Mode

SIPB 5130

SIPB 5100

4 3 2 1

ON

AMC 3

AMC 2

AMC 1

Mainboard SIPB 5000

®

IOM -2 Mode

SIPB 5132-SP

ITB05753

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Development Systems for Information Technology

4.2

The Different Steps in Development

Designing the Hardware

4.2.3

Figuring out the ARCOFI -SP Coefficients

for Speakerphone

4.2.1

Siemens Semiconductor Group offers two dedicated,

DSP-based speakerphone realizations ARCOFI-SP

PSB 2165 and PSB 2163.

The SIPB 8051 can be used as a platform for all development

steps. In a later stage it is of course necessary to do a cost

optimized design. For this a subset of the SIPB 8051 design

can be used. All the wiring diagrams are shipped with the

board to speed this process up.

The first digital speakerphone support was implemented in

the ARCOFI-SP PSB 2165, which already exists since 1991.

A substantial feature of the ARCOFl-SP is to provide means

for minimizing feedback in electrical loops and to

compensate for acoustical couplings. Therefore ARCOFI-SP

offers 23 parameters which are set by software

4.2.2

Developing the Protocol Software

A major task in the design work is the development of the

public ISDN protocol software. To ease this work Siemens

provides the IOS as an almost ready to copy protocol

software kernel. IOS has been designed in C and it can be

ported in nearly all CPU environments. For the development

of ISDN phones or TAs IOS has been ported onto an

80C515. Still it might be necessary to do some modifications

or more likely add some features. The board can immediately

load code but the use of a high level debugger like the Keil

(FRANKLIN) TS51 or the IAR (ARCHIMEDES) C-SPY is

recommended. After loading the target system Monitor down

to the board the debuggers work perfectly. An emulator is

really not required.

programming. No further external components or trimming

are required. This half-duplex mode is based on a two point

speech detection, which controls the mode switching within

125 µs.

The speakerphone support of the new ARCOFI-SP

PSB 2163 is based on a “Stronger-Wins” algorithm. Two

speech comparators, one at the acoustic (AE) and one at the

line side (LE), mainly control the switching from one active

mode to another one. They compare permanently the signal

levels of both signal paths and control the influences caused

by the echoes at the acoustic side and at the line side. Once,

a speech detector has detected speech activity, the

comparator switches immediately to the direction where the

speech signal is louder than the other one plus the returned

echo.

This offers the advantage of a completely separate

programming of the sensitivity and of the echo control. The

sensitivity is adjusted by the speech detectors and the

speech comparators control the different feedback paths at

the acoustic side and at the line side.

PSB

(2165)

2163

SAB

80C535

PSB

2110

2120

SIEMENS IOS

PSB

2186

PSB

2196

SIPB 8051-SP

(optional)

ITB05754

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Development Systems for Information Technology

The ARCOFI -SP allows the control of electrical

feedbacks. It is recommended, however, to have the

majority of the acoustic couplings minimized before, by

an optimum design of the telephone case.

Hardware Development

GOLDplus Evaluation System

The Siemens GOLDplus evaluation system comprises all

parts of a GSM full rate and half rate handset. It consists

mainly of the GOLDplusX GSM baseband board and the

GOLDplus GSM RF board as shown in figure 1.

For both ARCOFI-SPs there is very comfortable coefficient

software called ARCOS-SP PLUS which eases and reduces

any optimizations to just a simple task at the PC.

Thanks to the DSP realization, the main operational functions

are all parameterized. This technique offers a high level of

flexibility and reproducibility. An enormous advantage is the

reduction of the optimization time. With a special adaptor¹⁾it

is possible to optimize the speakerphone system using just

one link. The iterated procedure of “Building-up a line →

Testing → Deactivating the link → Opening the telephone

case → Resoldering some RC elements → Closing the case”

is reduced to a comfortable computer session focusing on the

real work: the optimization of the switching behaviour. The

speakerphone maintenance/test function of the ARCOFI-SP

supports the transparency of these modes which are

mentioned above (refer to Application Hints for ARCOFI-SP

Users).

On the GOLDplusX baseband board all Siemens GOLDplus

baseband devices are located including the system controller

GOLD-µC (PMB 2706), the signal processor GOLD-SP

(PMB 2707), the digital-to-analog conversion device GAIM

(PMB 2905) and optionally the half-rate coprocessor

GOLD-SX (PMB 2708). All required memory devices like

FLASH memory and RAM are also found on this board.

Suitable periphery like LCD display and keypad complete the

system to a fully functional handset. The connector to the RF

board carries all baseband I- and Q-signals in both receive

and transmit direction and all RF-control signals from

GOLD-µC.

On the GOLDplus GSM RF board all the Siemens GSM RF

devices are located including the transmitter PMB 2240, the

receiver PMB 2405, the PLL PMB 2307 and the power

amplifier consisting of CGY 92 and CGY 120.

¹⁾Refer to the application Note “Adaptor to program

ARCOS-SP in customer hardware with Siemens ISDN

PC User Board and ARCOS-SP PLUS”

The GOLDplus demo system permits evaluation of all

features of the GOLDplus chip set, both for the baseband as

well as the RF part. By adding the PMB 2708 half-rate

coprocessor the baseband may be upgraded optionally to

half-rate operation. Critical parameters like power

consumption or equalizer performance can be measured.

Cost estimations for a customer handset can be based upon

the bill of materials of the board.

5

Tools for GSM Telephone Designs

5.1

A Typical GOLDplus Development Environment

The development of a GSM handset splits up into

development of GSM hardware and GSM software. Up to a

certain stage development will run in parallel converging

more and more prior to GSM type approval. Hardware

development splits up into development of the baseband part

and the RF part with the RF part requiring considerable

experience and know-how.

GOLDplusX Baseband Board

Software Development Platform

GOLDplusX board permits the customer getting started

immediately with his GSM software development without

having to wait for his own board prototypes. It provides an

optimum debugging platform not only for the GOLD-µC C166

system controller but also for the DSP cores if customer

specific features have to be implemented in DSP firmware.

Siemens along with its partners offers support for all stages

of both hardware and software development permitting even

newcomers to the GSM arena to get started quickly. For

application of the GOLDplus chip set Siemens offers local as

well as central support from headquarters in Munich. UK

based Symbionics offers development of a complete GSM

hardware according to customer requirements. For

development of the RF hardware they build upon their

profound RF experience. Munich based OPTIMAY offers

mature GSM software with an easily customizable MMI.

Besides getting quickly acquainted with the baseband

functionality the board permits easy and complete control of

the RF-chip set using the GOLD-µC controller functions. This

is especially useful for evaluation and fine tuning of the

RF-board functionality.

The development of a GSM handset requires both optimum

hardware and software development tools to meet time

scales in a rapidly moving market.

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Development Systems for Information Technology

SIEMENS

RX

PMB 2405

TX

PMB 2240

SIEMENS

PMB 2706

GOLD µC

SIEMENS

PMB 2707

GOLD SP

RAM

PLL

PA

PMB 2307

CGY 92

CGY 120

SIEMENS

PMB 2905

GAIM

SIEMENS

PMB 2708

GOLD SX

FLASH

GOLDplusX GSM Rf Board

GOLDplusX GSM Baseband Board

LCD

SIM

1

4

7

2

5

8

0

3

6

9

#

*

ITS08202

Figure 1

GOLDplus Evaluation System

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Development Systems for Information Technology

6

Tools for DECT-Cordless Telephone Designs

6.2

Development Steps

6.1

A typical Development Environment

for a DECT-Home System

6.2.1

Designing the Hardware

In order to speed up this process, all the wiring diagrams are

shipped with the boards. Major parts of the hardware shipped

can of course be used for the final design. This is especially

true for the SWUD 1300 RF board. The SWUD 3020E or

SWUD 3025 board respectively has of course to be replaced

by the PMB 2720X or PMB 2725X chip along with the

E²PROM and the PMB 2920 chips. However, their

interconnection can be taken from of the shipped wiring

diagrams of the SWUD board.

For DECT-home system development projects, there is a

complete hardware and software solution available, which

was designed to provide a first prototype to the customer. It

actually covers all the necessary functional blocks and is fully

operational, when connected to an analog telephone

network.

The effort was made in order to speed up the development of

a DECT-home system and to provide a system hardware for

immediate software development. Besides the tremendous

know how, especially on the RF part, which is necessary for

designing DECT phones, it is now the first time that a

european standard protocol has to be matched. The DECT

standard actually defines a very complex layered protocol.

To implement that standard, a tremendous software

development effort has to be made. This part of a DECT

project is considered to be done in parallel to the final

hardware design. The DECT-user board system provides a

hardware development platform today which allows

The SWUD 1100 board will typically need to be customized

because it is very likely that one wants to use a different

keyboard layout or a customized display etc.

The major parts of the SWUD 1200 board can again be used

to design a real base station telephone line interface.

6.2.2

Developing the Software

A major task in the design work is the development of the

DECT-protocol software. The effort is considered to be

several man years. The SWUD 3500 setup is designed to

support software development projects. The memory layout

has been designed in close cooperation with Compiler and

Debugger suppliers, with the result that C51 Debuggers can

run in this environment.

customer’s software group to start working immediately.

Handheld

Base Station

SWUD 1300

PMB 2220

PMB 2420

PMB 2306

PMB 2220

PMB 2420

PMB 2306

Handset

PMB

27201

27251

PSB

4500

PMB

2920

PMB

2920

Tip / Ring

SWUD 3020E

SWUD 3025

SWUD 1200

SWUD 1100

ITS08203

Figure 2

A Typical Development Environment for a DECT-Home-System

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Development Systems for Information Technology

The board can immediately load software, but the use of a

high-level language debugger like the Keil (Franklin) TS51 is

recommended. The monitor program of this third party

software package is already shipped with the board to get

user started more quickly. For most of the software

debugging, an emulator is not really required. But in addition

to the described software monitoring by a software debugger,

there is also a hardware emulator available from Kleinhenz

Electronic. It seems to be a good approach to use the

software debugger for most of the daily work, but to have one

emulator available for tricky real-time debugging and for final

target system software implementations.

7

Tools for Universal RF Circuit Designs

For the various RF circuits there are test boards available for

evaluation. For distinct applications like the DECT-system-

oriented family of user boards a complete RF application has

been put together to complete the baseband tool set as a

system solution.

Besides hardware, there is also code available to support the

development. There is a low level device driver software

available which controls the chips.

In addition to that, the source code package PRODECT adds

a complete software implementation for a typical home

system. This includes all the layers and saves the above-

mentioned several man years. PRODECT is marketed as a

one time buy out license. It implements the complete DECT

standard, and by using PRODECT the customer’s software

effort is decreased to about 10% for customized

modifications.

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8

Tools for ISDN Primary Rate System Designs

The base board comprises an 80188 microcontroller,

128 Kbyte local RAM and a DP RAM-based interface to the

PC. The PRACT Evaluation Board itself can be used in all

applications using E1 or T1 transmission systems. It reflects

the features of the Siemens components for a typical

application like Primary Access TE, especially the new

PRACT device, which contains in addition to the line

transceiver a powerful clock generator with PLL. Signaling

procedures like CAS or CCS as well as bit-robbed signaling

can also be performed.

The Evaluation System for Primary Rate Interface SIPB 7520

comprises a modular hardware and software architecture. It

contains a typical Primary Rate Interface system application

based on the Siemens devices HSCX (SAB 82525), ACFA

(PEB 2035) and the new PRACT (PEB 22320).

8.1

SIPB 7520 Hardware

The SIPB 7520 hardware consists of a PC base board

equipped with an 80188 coprocessor system and an

extender board, the new PRACT Evaluation Board, as shown

in the following figure.

8.2

SIPB 7520 Software

The SIPB 7520 software comprises the PC Evaluation

Software, which realizes the general user access to the

Primary Rate Interface system and the Device Driver

Software for the Siemens Communication ICs, which can be

downloaded onto the SIPB 7520 PC Board. The Device

Driver Software contains in addition to a standard HDLC

Device Driver Module for the HSCX two new Device Driver

Modules for the ACFA V4.1 and PRACT supporting E1

(CRC4) and T1 (ESF, CRC6) systems.

SIPB 75xx

SIPB 7520

Base Board

Extender Board

SAB 80188

Primary Rate Interface

Coprocessor System

with PRACT, ACFA and HSCX

ITB06119

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Development Systems for Information Technology

8.3

Primary Rate Extender Board

The most important devices of the SIPB 7520 PRACT

Evaluation Board are the Advanced CMOS Frame Aligner

(ACFA), the ISDN Primary Access Clock Generator and

Transceiver (PRACT) and the High level Serial

The block diagram of the Primary Rate Extender Board of

figure above shows the main parts of the SlPB 7520 PRACT

User Board:

Communications Controller eXtended (HSCX).

• ISDN Primary Access Clock Generator and Transceiver

(PRACT) PEB 22320

• Advanced CMOS Frame Aligner (ACFA) PEB 2035

• High-level Serial Communications Controller eXtended

(HSCX) SAB 82525

• Microprocessor System based on SAB 80188

• Configuration field for E1/T1 applications

• Service Access Connector to physical line and for external

measurements

The ACFA contains the main parts of the layer-1 functions of

the Primary Rate Interface and performs frame alignment to

the incoming data stream. Its activity is supported by the

PRACT linking the dual rail interface of the ACFA to E1 or T1

transmission lines which may be accessed via the Service

Access Connector (SAC). A dedicated overvoltage

protection circuitry is included and screens against voltage

surges on the physical line.

The HSCX supports optimized high speed data transmission

on DMA or interrupt request using HDLC protocols. It is

employed as signaling controller as well as controller for data

transmission in time-slot oriented transmission systems.

Both channels A and B of the HSCX can be used either for

signaling or for data transmission.

• Extender Board Connector

• PC Interface Connector

All clocks required by the ACFA and the HSCX are generated

by the integrated clock PLL of the PRACT.

Configuration

Field E1 / T1

Service

Access

Connector

HSCX

ACFA

PRACT

SAB 82525

PEB 2035

PEB 22320

Overvoltage

Protection

Base Board

SAB 80188

CPU System

ITB06120

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Development Systems for Information Technology

9

Tools for Communication Networks System

Designs

• The Device Driver Software contains optimized Device

Driver Modules especially written for the Communication

IC ESCC2 from Siemens. These modules demonstrate the

features, power and flexibility of the Siemens

Communication ICs. The Device Driver Modules are

completely written in C. They support the different protocol

modes of the ESCC2, e.g. ASYNC, BISYNC, HDLC/

SDLC.

• An Application Program Interface (API) for the

C language helps writing individual application software

for the PC, communicating via a standard interface (C/l

Mailbox Interface) with Device Driver Software on the

coprocessor board. The program EXAMPLE gives a first

idea of how to apply the C/I Mailbox API in a simple

PC-application program.

• The EASY532 tool comprises Downland, Debugging and

Single Step test features, as well as Sequential Test

capabilities. Its main purpose is to simplify the control and

verification of Device Driver Software developed on the

PC. This driver software can directly be downloaded on the

coprocessor board for real-time applications. Furthermore

the window driven Register Access Editor presents the

Siemens Communication IC ESCC2 in a user-friendly

manner. The time, that has to be spent for learning how the

chip architecture looks like and how the chip works in

principle is reduced to a minimum.

9.1

Datacom Application Board EASY532

The Evaluation & Development System EASY532

provides a hardware and software development tool for

communication system applications with the serial

communication controller SAB 82532 (ESCC2) using the PC

as interface to the user. The relevant features of the

SAB 82532 (ESCC2) are supported.

Due to its original concept the Datacom ESCC2-Userboard

EASY532 assists an engineer in developing his own

applications. It reduces greatly the time spent for hardware

and software development in offering not only a ready-to-use

circuitry but also a plain and reliable software for operating,

modifying, and testing the hardware according to one’s own

pretensions and requirements. Thus using the Datacom

ESCC2-Userboard EASY 532 in a short time leads to a

stable hardware development; it provides level-1 and level-2

software support while creating and testing own application

software.

The hardware is designed such as to fit into an expansion slot

any PC/XT/AT or compatible. Thus after some simple

configuring procedures (e.g. selecting l/O address by means

of switches) and insertion of the board into the PC the circuit

is just ready for use.

• Application specific software can be developed by the user

using so called “application modules” (→ apm.c,

apm.h). This modules are linked to the Device Driver

Software and downloaded on the Datacom Board, thus

providing a high performance real time data

This Datacom Application System comprises an SDA 80186

coprocessor system, a PC Interface with 2-Kbyte Dual Port

RAM and the Communication IC ESCC2 from Siemens.

communication system.

Software for EASY 532

• Line drivers like RS232-, RS422-, RS485-drivers, or even

optical modules can be connected to the EASY 532 board.

Using such drivers or modules different system

configurations can be supported, e.g. Master Slave,

Multi-Master, Point To Point.

The main features of this powerful integrated Evaluation and

Development Software System are:

• The Device Driver Software consists of a Device Driver

System, including the start-up sode and a run-time library

for the EASY 532 80186-coprocessor system. Over 95%

of the Device Driver Software is written in C and available

in source code.

RS232

RS422

RS485

SAB

80C186

EPROM

RAM

ESCC2

Serial I / O

PC Interface

Opt.

Channel A

Module

Channel B

ITB06121

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Development Systems for Information Technology

9.2

EASY320 Evaluation System for MUNICH32

The device driver software is available in C source code. With

a standard C cross development package for the 32-bit CPU

it is possible to generate executable code which can be

downloaded onto the communication subsystem with the

EASY320 download utility.

General Overview

The Evaluation System for the MUNICH32 comprises

modular hardware and software components especially

optimized to demonstrate the excellent performance of the

MUNICH32 device in a real communication subsystem.

For a quick start using the MUNICH32 device in such a

minimum reference system a sophisticated Windows user

interface is built into the EASY320 PC-Evaluation Software

especially designed for the MUNICH32 shared memory data

structures. This user interface simplifies the direct access to

the MUNICH32 device by mapping the MUNICH32 data

structures to corresponding window structures on the PC.

The hardware is divided into a 32-bit CPU base board and an

appropriate extender board, which contains an individual

system application with the MUNICH32 (e.g. Primary Rate

Interface).

The associated software structure for use with this

hardware architecture consists of dedicated device driver

software running on the communication subsystem and the

corresponding Evaluation Software EASY320 on the PC host

system.

Applications

• Intuitive learning by doing “How the MUNICH32 behaves

in a real system”

• Realization of individual system applications

• Development and test of individual MUNICH32 device

driver software

MUNICH32 Extender Board

MC 68040

Communication

Processor

Base Board

ITB06122

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Development Systems for Information Technology

PC Evaluation Software EASY320

The PC Evaluation Software EASY320 is a single

MS-Windows application program containing mainly the

following functional modules:

• Download of communications software onto the

EASY320 communication subsystem

• Single Step Test of downloaded communications software

via the exchange of C/l Messages

• Direct Chip Level Access to MUNICH32 shared memory

data structures

The initial screen view is illustrated in the following figure.

EASY32 Evaluation Software for MUNICH32 - EASY32 Log

View Window Help

File Edit

Chip Level Test

Options

T

C

L

MUNICH32 Shared Memory

Action Specification

Interrupt Specification

Interrupt

Circular

Queue

Timeslot Assignment

(Channel 0 ... 31)

Receive

Descriptor

Channel 0

Receive

Descriptor

Channel 0

Channel Specification

(Channel 0 ... 31)

Receive

DATA

Channel 0

Receive

DATA

Channel 0

Current Rc Descr. Addr.

(Channel 0 ... 31)

Transmit

Descriptor

Channel 0

Transmit

Descriptor

Channel 0

Current Tx Descr. Addr.

(Channel 0 ... 31)

Transmit

DATA

Channel 0

Transmit

DATA

Channel 0

Action Request

EASY32 Log

;

17.03.1994 16:12 - Download of file: F:\ EASY320\ 940302.MBF

-> AR-ACK-V2.1, 3, 0, 0

Message: AR_ACK_V2.1

Description:

ld: 1

Source: 3

Destination: 0

Entity: 0

Data Length: 0

Msg-Type: Indication

Program running

NUM

ITA06123

EASY320 Initial Screen View

Siemens Aktiengesellschaft

206

Package Information

Package Outlines of the desribed Products are shown in our

Databook “Package Information”

Siemens Aktiengesellschaft

207

Package Information

Datenbuch „Gehäuse Information“

Databook “Package Information”

Der Bereich Halbleiter stellt dem interessierten Leser,

praktischen Anwender und Kunden seine

Gehäusevielfalt vor und gibt zusätzlich Informationen

zu den Themen, die im Gesamtzusammenhang mit

Gehäusen stehen.

The Siemens Semiconductor Group wishes to

introduce interested readers, practical users, and its

customers to its numerous packages, and to present

information on the subjects directly associated with

packages.

Die Gehäusethematik gewinnt nicht nur für den

Halbleiterhersteller als Folge größer werdender

Chips sowie steigender Arbeitsfrequenz immer mehr

an Bedeutung, sondern gerade auch für den

Verarbeiter und Kunden, der mit einer ständig

wachsenden Vielfalt an Gehäusen hinsichtlich

Pinzahl, Anschlußraster und Gehäuseabmessungen

konfrontiert wird. Aus diesem Grunde sollte die

Auswahl der Produkte nicht nur auf den Chip,

sondern auch auf die Gehäuse und damit auf die

spätere Verarbeitung bezogen werden, um die

Machbarkeit und Wirtschaftlichkeit sicherzustellen.

Packaging is becoming increasingly important as a

consequence of larger chips and higher operating

frequencies, not only for the semiconductor

manufacturer but specifically for processors and

customers confronted with a steadily growing variety

of packages with regard to pin count, pin raster and

package sizes. For this reason, product selection

should involve not just the chip but also the packages

and, consequently, subsequent processing in order

to ensure feasibility and economy

Das Einführungskapitel behandelt die weltweite

Gehäusestruktur und deren Trend für die Zukunft und

die sich aus der zunehmenden Diversifizierung an

Gehäusen ergebende Problematik für den

Verarbeiter.

The opening section deals with the worldwide pattern

of packages and their future trend, while special

mention is made of the problems facing processors

as a result of increasing package diversification.

Die Kapitel 2 bis 4 behandeln detailliert

Abmessungen, Kenngrößen und Beschriftungen der

typischen Gehäuse des Bereichs Halbleiter

Sections 2 to 4 present a detailed discussion of

dimensions, characteristics, and markings of typical

packages from the Semiconductor Group.

Der Verpackung haben wir wegen ihrer steigenden

Bedeutung als Bindeglied zwischen

Halbleiterhersteller und Verarbeiter ein eigenes

Kapitel (5) gewidmet.

In view of its rising importance as a link between the

manufacturer of semiconductors and their processors

a whole chapter (5) has been devoted to packing.

Nützliche Hinweise zur Verarbeitung von

Bauelementen enthält Kapitel 6. Die einzelnen

Prozeßschritte werden beschrieben und die Vor- und

Nachteile der unterschiedlichen Verfahren diskutiert.

Auf die Verarbeitung feuchteempfindlicher ICs sowie

auf elektrostatisch gefährdeter Bauelemente ESD

wird gesondert eingegangen .

Useful advice on processing devices is contained in

Section 6. The different process stages are

described, and the pros and cons of the different

methods are discussed. Special mention is made of

processing humidity-sensitive ICs and anti-ESD

measures.

Ein Gehäuseverzeichnis rundet das Gehäuse-

Datenbuch ab

A list of packages, completes the Package Data

Book.

Bestell-Nr.: B192-H6636-G1-X-7400

Ordering No.: B192-H6636-G1-X-7400

(Siehe auch Abschnitt „Literaturhinweise“)

(see refer section “Information on Literature”)

Siemens Aktiengesellschaft

208

Summary of Types

Siemens Aktiengesellschaft

209

Summary of Types in Alphanumerical Order

Type

Short Title

lEPC

Function

Page

121

106

167

132

147

150

153

151

89

PEB 2025-N

PEB 2025-P

PEB 2026T-P

PEB 2026T-S

PEB 20320-H

PEB 2035-N

PEB 2035-P

PEB 2045-N

PEB 2045-P

PEB 2046-N

PEB 2046-P

PEB 2047-16-N

PEB 2047-N

PEB 2052-N

PEB 2054-N

PEB 2055-N

PEB 20550-H

PEB 20560

ISDN Exchange Power Controller (SMD)

ISDN Exchange Power Controller

ISDN High Voltage Power Controller (SMD)

Multichannel Network lnterface Controller for HDLC (SMD)

Advanced CMOS Frame Aligner (SMD)

Advanced CMOS Frame Aligner

lEPC

IHPC

MUNlCH32

ACFA

MTSC

MTSS

MTSL-16

MTSL

Memory Time Switch CMOS (SMD)

Memory Time Switch CMOS

Memory Time Switch Small (SMD)

Memory Time Switch Small

Memory Time Switch Large (SMD)

PCM Interface Controller (SMD)

PIC

EPIC -S

EPlC -1

ELIC

Extended PCM Interface Controller-Small (SMD)

Extended PCM Interface Controller (SMD)

Extended Line Card Controller (SMD)

DSP Oriented PBX Controller (SMD)

Signal Processing Codec Filter (SMD)

Signal Processing Codec Filter

90

91

92

DOC

122

94

PEB 2060-N

PEB 2060-P

PEB 2070-N

PEB 2070-P

PEB 2075-N

PEB 2075-P

PEB 2080-N

PEB 2080-P

PEB 2081-N

PEB 2084-H

PEB 2085-N

PEB 2085-P

PEB 2086-H

PEB 2086-N

PEB 20901-N

PEB 20901-P

PEB 20902-N

PEB 20902-P

PEB 2091-N

PEB 2095-N

PEB 2095-P

PEB 20950-N

PEB 20950-P

PEB 2096

SICOFI

lCC

94

ISDN Communications Controller (SMD)

ISDN Communications Controller

107

109

110

111

112

61

lCC

IDEC

ISDN D-Channel Exchange Controller (SMD)

ISDN D-Channel Exchange Controller

S-Bus Interface Circuit (SMD)

IDEC

SBC

S-Bus Interface Circuit

SBCX

QUAT -S

ISAC -S

IEC-T

S/T-Bus Interface Circuit Extended (SMD)

Quadruple S/T-Transceiver (SMD)

ISDN Subscriber Access Controller (SMD)

ISDN Subscriber Access Controller

ISDN Subscriber Access Controller (SMD)

ISDN Echo Cancellation Circuit (SMD)

ISDN Echo Cancellation Circuit

61

114

113

119

63

IEC-T

ISDN Echo Cancellation Circuit (SMD)

ISDN Echo Cancellation Circuit

IEC-T

IEC-Q

IBC

ISDN Echo Cancellation Circuit (SMD)

ISDN Burst Transceiver Circuit (SMD)

ISDN Burst Transceiver Circuit

IBC

ISAC -P

OCTAT -P

PRACT

IPAT -2

ISDN Subscriber Access Controller (SMD)

ISDN Subscriber Access Controller

63

Octal Transceiver for U Interfaces (SMD)

120

139

134

PN

PEB 22320-N

PEB 2236-N

PEB 2236-P

Primary Access Clock and Transceiver Component (SMD)

ISDN Primary Access Transceiver (SMD)

ISDN Primary Access Transceiver

Siemens Aktiengesellschaft

210

Summary of Types in Alphanumerical Order

Type

Short Title

FALC 54

Function

Page

136/178

96

PEB 2254-H

PEB 2260-N

PEB 2445-N

PEB 2465-H

PEB 2466-H

PEB 24901

PEB 24902

PEB 24911

PEB 3035-N

PEB 3035-P

PEB 3065-N

PEB 4065-T

PEF 2026T-P

PEF 2026T-S

PEF 20320-H

PEF 2035-N

PEF 2035-P

PEF 2045-N

PEF 2045-P

PEF 2054-N

PEF 2055-N

PEF 2070-N

PEF 2075-N

PEF 2080-N

PEF 20901-N

PEF 20902-N

PEF 2091-N

PEF 2236-N

PEF 2236-P

PEF 2260-N

PEF 24902

PEF 24911

PEF 3035-N

PEF 3035-P

PEF 3065-N

PEF 4065-T

PMB 2200-S

PMB 2200-T

PMB 2201-R

PMB 2202-R

PMB 2205-S

PMB 2205-T

PMB 2207-R

PMB 2220-S

PMB 2240-F

Frame And Line Interface Component (SMD)

Dual Channel Codec Filter (SMD)

SICOFI -2

MUSAC -A

SICOFI -4

SICOFI -4 µC

Multipoint Switching and Conferencing Unit Attenuation (SMD)

Signal Processing Codec Filter (SMD)

154

97

99

Quad IEC DFE-T 4 Channel ISDN Echo-Cancellation Digital Front End (SMD)

Quad IEC AFE Quad ISDN Echo-Cancellation Circuit Analog Front End (SMD)

Quad IEC DFE-Q Quad ISDN 2B1Q Echocanceller Digital Front End (SMD)

116

117

118

135

100

101

106

167

132

147

90

PRISM

SLICOFI

HV-SLIC

IHPC

Primary Rate Interface Signaling and Maintenance Controller (SMD)

Primary Rate Interface Signaling and Maintenance Controller

Signal Processing Subscriber Line Interface Codec Filter (SMD)

High Voltage Subscriber Line (SMD)

ISDN High Voltage Controller (SMD)

IHPC

ISDN High Voltage Controller (SMD)

MUNICH32

ACFA

Multichannel Network Interface Controller for HDLC (SMD)

Advanced CMOS Frame Aligner (SMD)

Advanced CMOS Frame Aligner

ACFA

MTSC

Memory Time Switch CMOS (SMD)

MTSC

Memory Time Switch CMOS

EPlC -S

EPIC -1

ICC

Extended PCM Interface Controller-Small (SMD)

Extended PCM Interface Controller (SMD)

ISDN Communication Controller (SMD)

ISDN D-Channel Exchange Controller (SMD)

S-Bus Interface Circuit (SMD)

91

107

109

110

114

113

134

94

lDEC

SBC

IEC-T

ISDN Echo Cancellation Circuit (SMD)

IEC-T

ISDN Echo Cancellation Circuit (SMD)

IEC-Q

ISDN Echo Cancellation Circuit (SMD)

IPAT -2

lPAT -2

SICOFI -2

Quad IEC AFE

ISDN Primary Access Transceiver (SMD)

ISDN Primary Access Transceiver

Dual Channel Codec Filter (SMD)

Quad ISDN Echo-Cancellation Circuit Analog Front End (SMD)

117

118

135

100

101

37

Quad IEC DFE-Q Quad ISDN 2B1Q Echocanceller Digital Front End (SMD)

PRISM

Primary Rate Interface Signaling and Maintenance Controller (SMD)

Primary Rate Interface Signaling and Maintenance Controller

Signal Processing Subscriber Line Interface Codec Filter (SMD)

High Voltage Subscriber Line (SMD)

PRISM

SLICOFI

HV-SLIC

Direct Vector Modulator (SMD) (Shrink)

Direct Vector Modulator (SMD)

37

Direct Vector Modulator + Mixer (SMD)

38

Direct Vector Modulator + Mixer (SMD)

38

Direct Vector Modulator (SMD) (Shrink)

41

Direct Vector Modulator (SMD)

41

Direct Vector Modulator + Upconverter Mixer (SMD) (Shrink)

DECT Transmitter (SMD) (Shrink)

42

33

GSM Transmitter (SMD)

21

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211

Summary of Types in Alphanumerical Order

Type

Short Title

Function

Page

21

45

47

49

51

52

53

54

43

44

23

34

14

16

18

28

29

30

31

19

20

32

74

75

68

69

70

PMB 2245-F

PMB 2247-F

PMB 2302-R

PMB 2303-R

PMB 2306-R

PMB 2306-T

PMB 2307-R

PMB 2308-R

PMB 2309-R

PMB 2313-T

PMB 2314-T

PMB 2330-T

PMB 2331-T

PMB 2332-R

PMB 2333-R

PMB 2401-S

PMB 2401-T

PMB 2402-S

PMB 2405-F

PMB 2407-F

PMB 2420-S

PMB 2705-F

PMB 2706-F

PMB 2707-F

PMB 2708-F

PMB 27201

PMB 27202

PMB 27251

PMB 27252

PMB 2727-H

PMB 2728-H

PMB 2900-H

PMB 2905-F

PMB 2920-S

PSB 2110-H

PSB 2110-N

PSB 2110-P

PSB 21525-H

PSB 21525-N

PSB 2160-N

PSB 2160-P

PSB 2161

PCN Transmitter (SMD)

PCS Transmitter (SMD)

1.25-GHz Dual PLL with Prescaler (SMD) (Shrink)

2.5-GHz Dual PLL with Prescaler (SMD) (Shrink)

PLL Frequency Synthesizer (SMD) (Shrink)

PLL Frequency Synthesizer (SDM)

PLL Frequency Synthesizer (SMD) (Shrink)

1.25-GHz PLL with Prescaler (SMD) (Shrink)

2.5-GHz PLL with Prescaler (SMD) (Shrink)

1.1-GHz Prescaler (SMD)

2.1-GHz Prescaler (SMD)

2.0-GHz Mixer (SMD)

1.1-GHz LNA + Mixer (SMD) (Shrink)

3-GHz LNA/Driver + Mixer (SMD) (Shrink)

Receiver/Demodulator Circuit (SMD) (Shrink)

Receiver/Demodulator Circuit (SMD)

Broadband Receiver/Vector Demodulator (SMD)

GSM Receiver (SMD)

PCN/PCS Receiver (SMD)

DECT Receiver (SMD) (Shrink)

GOLD

GSM One-Chip Logic Device (SMD)

GOLD System Controller (SMD)

GOLD-µC

GOLD-SP

GOLD-SX

GOLD Signal Processor (SMD)

GSM Co-Processor for Advanced Features (SMD)

DECT Digital Circuit for Handhelds (SMD)

DECT Digital Circuit for Basestations (SMD)

DECT Multichannel Burst Mode Controller (SMD)

DECT PBX (SMD)

GBBC

GAIM

GSM Baseboard Codec (SMD)

GSM Analog Infterfacing Module (SMD)

DECT Analog Circuit (SMD) (Shrink)

ISDN Terminal Adaptor Circuit (SMD)

ISDN Terminal Adapter Circuit (SMD)

ISDN Terminal Adaptor Circuit

lTAC

ITAC

HSCX-TE

ARCOFI

High-Level Serial Communications Controller for Terminals (SMD)

Audio Ringing Codec Filter (SMD)

Audio Ringing Codec Filter

ARCOFI

ARCOFl -BA

ARCOFl -SP

ARCOFI -SP

Audio Ringing Codec Filter Basic Function (SMD)

Audio Ringing Codec Filter (SMD)

Audio Ringing Codec Filter

PSB 2163-N

PSB 2163-P

PSB 2163-T

Audio Ringing Codec Filter (SMD)

Siemens Aktiengesellschaft

212

Summary of Types in Alphanumerical Order

Type

Short Title

ARCOFI -SP

ISAC -S TE

ISAC -P TE

SmartLink-P

ISAR

Function

Page

71

PSB 2165-N

PSB 2165-P

PSB 2186-H

PSB 2186-N

PSB 2186-P

PSB 2196-H

PSB 2196-N

PSB 2197-T

PSB 7110-F

PSB 7280-H

PXB 4110

Audio Ringing Codec Filter (SMD)

Audio Ringing Codec Filter

71

ISDN Subscriber Access Controller for Terminals (SDM)

ISDN Subscriber Access Controller for Terminals (SMD)

ISDN Subscriber Access Controller for Terminals

62

Subscriber Access Controller for U -Interface Terminals (SMD)

64

PN

ISDN Subscriber Access Controller for U -lnterface Terminals (SMD)

64

PN

Subscriber Access Controller for U -Interface Terminals (SMD)

66

PN

ISDN Data Access Controller (SMD)

73

JADE

Joint Audio Decoder/Encoder (SMD)

76

SARE

Segmentation and Reassembly Element (SMD)

Interworking Element (SMD)

180

179

181

182

183

184

162

163

165

169

162

PXB 4220

IWE

PXB 4230

UTPT

Unshielded Twisted Pair Transceiver (SMD)

PXB 4240

SDHT

SDH/SONET Transceiver (SMD)

PXB 4310

ASM

ATM-Switching Matrix

PXB 43201

PXB 43202

SAB 82525-H

SAB 82525-N

SAB 82526-N

SAB 82532-N

SAB 82532-N-10

SAB 82538-H

SAB 82538-H-10

SAB 82C257-1-N

ASP -up

ASP -down

HSCX

ATM-Switching Preprocessor Chip Set

High-Level Serial Communication Controller Extended (SMD)

Enhanced Serial Communication Controller (SMD)

Advanced DMA Controller for 16-Bit Microcomputer Systems (SMD)

High-Level Serial Communication Controller Extended (SMD)

HSCX

ESCC2

ESCC8

ADMA

SAB 82C258A-12-N ADMA

SAB 82C258A-20-N ADMA

SAF 82525-N

SAF 82526-N

HSCX

Siemens Aktiengesellschaft

213

Microelectronics Training Center

Siemens Aktiengesellschaft

215

Schule für Mikroelektronik

Microelectronics Training

Center

Gehen Sie auf Erfolgskurs!

Hit the Road to Success!

Programm SS 1996 der Schule für

Mikroelektronik

SS 1996 Program of the Microelectronics

Training Center

Das Angebot: ca. 130 Kurse von April bis Ende

September 1996 zu aktuellen Themen der

Mikroelektronik. Praxisorientierte Ausrichtung,

modernste Ausstattung, pädagogisch aufbereitetes

Kursmaterial und die intensive Betreuung durch

Fachdozenten garantieren den Lernerfolg.

What is offered: e.g. 130 courses from April through to

the end of September 1996 on current topics from the

ﬁeld of microelectronics. Practical orientation, the very

latest aids, course material devised to modern

pedagogic guidelines and intensive support from

specialist lectures guarentee learning with success.

Highlights aus dem Kursprogramm:

Program highlights:

• 8-bit MC-Familie 8051/C500

• 16-bit MC-Familie C166

• Fuzzy-Logic

• 8-bit MC family 8051/C500

• 16-bit MC family C166

• Fuzzy logic

• ISDN, Telecom

• ISDN, telecom

• Rechnerfamilie 80x86/Pentium

• Hardwarebeschreibungssprache VHDL

• BLS Board Level Simulation

• 80x86/Pentium computer family

• VHDL hardware description language

• BLS Board Level Simulation

• Software:

Sprachen C, C++

C, C++ languages

Betriebssysteme RMOS, Windows, UNIX

– Windows Programmierung

RMOS, Windows, UNIX operating systems

– Windows programming

• Personalcomputer

• Netze, LWL

• Personal computers

• Networks, ﬁber optics

• EMC

• EMV

• Leistungshalbleiter

• Halbleitertechnologie

• Power semiconductors

• Semiconductor technology

Auf Wunsch

On request

„maßgeschneiderte“ Kurse in deutscher und

englischer Sprache in Ihrer Firma!

“tailored” courses on your premises!

Programmübersicht erhalten Sie kostenlos bei:

Call or write for a free syllabus:

MicroConsult GmbH

Schule für Mikroelektronik

Rosenheimer Str. 143 b

Schule für Mikroelektronik

Rosenheimer Str. 143 b

Frau Kandlbinder

D-81671 München

Frau Kandlbinder

D-81671 München

Tel. (089)4506 17-0

Fax (089)4506 17-17

Tel. (089)4506 17-0

Fax (089)4506 17-17

Leistungsbeweis ’95: 2.400 Kurs-Teilnehmer!

Popularity curve: 2.400 course participants in 1995!

Siemens Aktiengesellschaft

217

Literaturhinweise

Information on Literature

Siemens Aktiengesellschaft

219


型号：	PSB21525-H
厂家：	Infineon
描述：	Telecom Circuit, 1-Func, PQFP44, PLASTIC, MQFP-44 电信电信集成电路
文件：	总208页 (文件大小：3047K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PSB21525-H [INFINEON]

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