PSB4595 [INFINEON]
Analog Line Interface Solution ALIS; 模拟用户线接口方案ALIS
| 型号： | PSB4595 |
| 厂家： | 
Infineon |
| 描述： | Analog Line Interface Solution ALIS |
| 文件： | 总104页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for Communications
Analog Line Interface Solution
ALIS
PSB 4595 Version 2.1
PSB 4596 Version 2.1
Data Sheet 06.98
DS 1
ALIS
Revision History:
Current Version: 06.98
Previous Version:
Page
Page
Subjects (major changes since last revision)
(in previous (in new
Version)
Version)
Edition 06.98
This edition was realized using the software system FrameMaker .
Published by Siemens AG,
HL AT
© Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endan-
gered.
PSB 4595 / PSB 4596
Analog Line Interface Solution
Table of Contents
Page
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Definition of ALIS-A PSB 4595 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Definition of ALIS-D PSB 4596 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1
2.2
2.3
3
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ALIS with DSP-based Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ALIS with Software Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Hybrid Modem (ISDN plus Analog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Modem with Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Analog Videophone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1
3.2
3.3
3.4
3.5
4
4.1
4.2
ALIS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ALIS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ALIS AC Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
ALIS Ring and Caller ID Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . .23
Caller ID (CID) Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Ring-Level Metering (RLM) Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.2.1
4.2.2
4.2.3
4.2.4
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5
5.1
5.2
5.2.1
5.2.2
5.2.3
Configuration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Connection to the Telephone Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
The µ-Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
The Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2.3.1 Demux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2.3.2 Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.3
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Crystal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Capacitor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Caller ID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.3.1
5.3.2
5.4
5.5
6
Programming ALIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Semiconductor Group
3
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Table of Contents
Page
6.1
6.1.1
6.2
Types of Commands and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Storage of Programming Information: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
CR0 Configuration Register 0 (Filters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
CR1 Configuration Register 1 (Dialing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
CR2 Configuration Register 2 (Caller ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
CR3 Configuration Register 3 (Test Loops) . . . . . . . . . . . . . . . . . . . . . . . . . .42
CR4 Configuration Register 4 (Analog Gain) . . . . . . . . . . . . . . . . . . . . . . . . .43
CR5 Configuration Register 5 (Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
XOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
XR0 Extended Register 0 (Interrupt Register) . . . . . . . . . . . . . . . . . . . . . . . .44
XR1 Extended Register 1 (Interrupt Enable Register) . . . . . . . . . . . . . . . . . .46
XR2 Extended Register 2 (Cadence Time Out) . . . . . . . . . . . . . . . . . . . . . . .47
XR3 Extended Register 3 (DC Characteristic) . . . . . . . . . . . . . . . . . . . . . . . .47
XR4 Extended Register 4 (Cadence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
XR5 Extended Register 5 (Ring Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
XR6 Extended Register 6 (Power State) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
XR7 Extended Register 7 (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
CAO Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
CR Registers: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
XR Registers: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.4
6.5
6.6
6.6.1
6.6.2
7
7.1
ALIS Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
SOP Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
SOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
SOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
XOP Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
XOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
XOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
CAO Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
CAO - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
CAO - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Example of a Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.5
8
8.1
8.1.1
8.1.2
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Nature and Sources of Interrupts: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Interrupt Indication at Signal Change: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Interrupt Indication at Event: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Semiconductor Group
4
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Table of Contents
Page
8.1.3
Interrupt Indication at High Level: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Reset (Basic Settings Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Deep Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Ringing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Conversation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Pulse Dialing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Operating Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Flow of Ring Sequence and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Successful Ring Sequence, Auto Ring Enabled, no Caller ID . . . . . . . . . . . .67
Successful Ring Sequence, Auto Ring Enabled, Caller ID . . . . . . . . . . . . . .68
Unsuccessful Ring Sequence, Auto Ring Enabled, no Caller ID . . . . . . . . . .69
Unsuccessful Ring Sequence, Auto Ring Enabled, Caller ID . . . . . . . . . . . .70
Successful Ring Sequence, Auto Ring Disabled, No Caller ID . . . . . . . . . . .71
Successful Ring Sequence, Auto Ring Disabled, Caller ID . . . . . . . . . . . . . .72
Unsuccessful Ring Sequence, Auto Ring Disabled, no Caller ID . . . . . . . . .73
Unsuccessful Ring Sequence, Auto Ring Disabled, Caller ID . . . . . . . . . . . .74
Unsuccessful Ring Sequence, Auto Ring Enabled . . . . . . . . . . . . . . . . . . . .75
9.8
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
9.8.8
9.8.9
9.8.10 Unsuccessful Ring Sequence, Auto Ring Disabled . . . . . . . . . . . . . . . . . . . .76
9.8.11 Start from Deep Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
10
10.1
10.2
Modem Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
10.2.1 Programming the ALIS DTMF Tone Generators . . . . . . . . . . . . . . . . . . . . . .78
10.3 Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
10.3.1 Characteristics for Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
10.3.2 Storage and Reading of Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
10.3.3 Programming the ALIS Caller ID Coefficients . . . . . . . . . . . . . . . . . . . . . . . .81
10.4
10.5
Billing Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
10.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
10.5.2 Programming the ALIS Ring Detect Coefficients . . . . . . . . . . . . . . . . . . . . . .82
10.5.3 Ring Threshold in Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
11
11.1
11.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
11.2.1 DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.2.2 Programming Ranges for DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.2.3 Input Current in Puls Dialing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
11.3
AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Semiconductor Group
5
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Table of Contents
Page
11.3.1 Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
11.4 ALIS Caller ID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.4.1 Ring Detect Levels and Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.5
ALIS Cap Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
12
Electrical Performance Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
12.1
12.2
12.3
12.3.1 ALIS-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
12.3.2 ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
12.4
AC Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
12.4.1 Absolute Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
12.4.2 Gain Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
12.4.3 Harmonic Distortion plus Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
12.4.4 Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
12.4.5 Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
12.4.6 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12.4.6.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12.4.6.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.4.7 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.4.7.1 Group Delay Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.4.7.2 Group Delay Distortion Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.4.7.3 Group Delay Distortion Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.4.8 Out-of-Band Signals at TIP/RING Receive . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.4.9 Out-of-Band Signals at TIP/RING Transmit . . . . . . . . . . . . . . . . . . . . . . . . . .99
12.4.10 Trans-hybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
12.5
AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.5.1 Input/ Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.5.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.5.3 Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.5.4 Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.5.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Semiconductor Group
6
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Overview
1
Overview
The PSB 4595 and PSB 4596 two-chip solution forms the complete front end of a modem
or fax machine. This Analog Line Interface Solution (ALIS) consists of a DAA, a codec
and a hybrid circuit, and bridges the gap between the phone line and the data pump. The
analog PSB 4595 is manufactured in low-power BiCMOS technology and the digital PSB
4596 in CMOS technology. The ALIS concept is a fully programmable modem front end
which allows a single design for the worldwide market:
• Adaptation to specific countries and applications is achieved by downloading
appropriate coefficient sets.
• Isolation is achieved by a digital capacitor interface, without a transformer; making the
ALIS particularly suitable for designing PCMCIA modems.
• Thanks to an advanced digital-filter concept in combination with the programmable
electronic DAA, ALIS provides both excellent transmission performance and high
adaptability. This second-generation digital filter concept also allows maximum
autonomy between the various filter blocks. This performance makes ALIS suitable for
V.34+ and V.90 modem applications.
A minimum number of external components is required to complete the functional range
of ALIS. Its internal precision is based on a very accurate band-gap reference. The
frequency behavior is determined largely by digital filters which exhibit no fluctuations.
As a result of the ADC and DAC concepts, its linearity is limited only by second-order
parasitic effects.
The ALIS chip set can be easily adapted and connected to various modem data pumps
or to host-based modem solutions. The flexible digital interface of ALIS allows easy
programming via the modem data pump or a controller.
Siemens offers a range of reference and evaluation tools for the ALIS chip set. For
appropriate tools, please contact your nearest Siemens representative.
Semiconductor Group
7
Data Sheet 06.98
PSB 4595
PSB 4596
Analog Line Interface Solution
ALIS
CMOS
1.1
Features
• ALIS substitutes data access arrangement (DAA),
codec and hybrid
• Ring detection: level, frequency and cadence
• Caller ID: detection, decoding and storage
• Programmable to different country requirements
• Programmable DC characteristics
• ALIS supports V.34+ and V.90
P-TSSOP24
• ALIS complies with ETS 300 001 and FCC
requirements
• Isolation by digital capacitor interface
• Analog part powered from the tip/ring line by an
integrated voltage regulator
• High performance analog-to-digital and digital-to-
analog conversion
• DSP-based solution for adapting the transmission
behavior, especially for
- AC impedance matching
- trans-hybrid balancing
- frequency response
P-SSOP28
- gain
• Advanced test capabilities:
- digital loops
- analog loops
• High-pass filter in receive path to suppress line interference (50/60 Hz)
• Isolated control pins for general purpose use
• Advanced low-power 0.8µm analog BICMOS technology for ALIS analog and 0.8µm
CMOS technology for ALIS digital
• Two-chip solution: the P-TSSOP24 and P-SSOP28 packages are PCMCIA-compliant
Type
Ordering Code
Package
PSB 4595 V2.1
PSB 4596 V2.1
P-TSSOP24
P-SSOP28
Semiconductor Group
8
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
1.2
Logic Symbol
Isolation
MCLK RESET
Vdd Vss
Data
Interface
Cap
Interface
ALIS-A
ALIS-D
µC
Interface
SO
SI
SO
Caller ID
Interface
TIP/RING
Figure 1 Logic Symbol of the ALIS Chipset
Semiconductor Group
9
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Pin Definition and Functions
2
Pin Definition and Functions
Pin Configuration
2.1
1
24
23
22
21
20
19
18
17
16
15
14
13
CAP1
CAP2
VREF
GNDA
T1G
VDDA
VDD_SENS
NC
T2G
SI_0
SI_1
TEST
2
3
4
TIP
TIP_AC
RING
5
6
7
RING_AC
SO_0
SO_1Q
CAP_B22
CAP_B21
CAP_A22
8
9
10
11
12
CAP_C21
CAP_C22
CAP_A21
Figure 2 Pin Configuration of ALIS-A (Top View)
CAP_A12
CAP_B11
CAP_B12
ID_Ain
1
28
27
26
25
CAP_A11
CAP_C12
CAP_C11
VDDA
2
3
4
5
GNDA
Afeedback
ID_Bin
Bfeedback
VDD
24
23
22
21
20
19
18
17
16
15
6
RESET
SO
7
8
MCLK1
MCLK2
MODE
9
GND
10
11
12
13
14
CS
DAT_CLK
DAT_IN/SEL
DAT_OUT
FSC
DCLK
DIN
DOUT
INT
Figure 3 Pin Configuration of ALIS-D (Top View)
Semiconductor Group
10
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Pin Definition and Functions
2.2
Pin Definition of ALIS-A PSB 4595
Pin No.
22
Symbol
VDDA
Function
Power
Descriptions
Programmable supply for the circuitry
24
GNDA
Power
Analog ground: All signals are referred to
this pin
4
TIP
I
TIP AC+DC sense input
TIP AC sense input
5
TIP_AC
RING
I
6
I
RING AC+DC sense input
RING AC sense input
7
RING_AC
T1G
I
23
O
Gate for external transistor T1 (AC/DC
control)
19
T2G
O
Gate for external transistor T2 (VDDA
control)
21
3
VDD_SENS I
VDDA sense input
VREF
I/O
Reference voltage: Must be connected to
GNDA via an external capacitor of more
than 10 nF (typ. 15 nF)
1
CAP1
I/O
Pin for external capacitor of more than 1
µF for DC filtering to pin Cap2
2
CAP2
SI_0
I/O
See Cap1
18
17
8
I
Auxiliary input pin 0
SI_1
I
Auxiliary input pin 1
SO_0
SO_1Q
TEST
CAP_A21
O
O
I
Auxiliary output pin 0
Auxiliary output pin 1
Must be connected permanently to GNDA
9
16
13
I
Must be connected via a capacitor of more
than 5pF to CAP_A11.
12
11
10
CAP_A22
CAP_B21
CAP_B22
I
Must be connected via a capacitor of more
than 5pF to CAP_A12.
O
O
Must be connected via a capacitor of more
than 5pF to CAP_B11.
Must be connected via a capacitor of more
than 5pF to CAP_B12.
Semiconductor Group
11
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Pin Definition and Functions
Pin No.
Symbol
Function
Descriptions
15
CAP_C21
I
Must be connected via a capacitor of more
than 5pF to CAP_C11.
14
CAP_C22
I
Must be connected via a capacitor of more
than 5pF to CAP_C12.
Table 1: ALIS-A Pin Definition
Semiconductor Group
12
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Pin Definition and Functions
2.3
Pin Definition of ALIS-D PSB 4596
Pin No.
Symbol
VDD
Function
Power
Description
8
9
+5 Volt supply for the digital circuitry
GND
Power
Ground digital: All signals are referred to
this pin
25
24
VDDA
GNDA
Power
Power
+5 Volt supply for the analog circuitry
Ground analog: All analog signals are
referred to this pin
21
MCLK1
I
Master clock1: One pin of a crystal or
ceramic resonator is connected. This pin
can also be driven from an external
clocking source of 16.384 MHz,
synchronous to FSC (MCLK=FSC*2048)
20
MCLK2
O
Master clock2: The other pin of a crystal or
ceramic resonator is connected. When
MCLK1 is driven by an external clock, this
pin should be left open
23
15
RESET
FSC
I
Reset input: Forces the device to default
mode (low active)
BI
As input: Frame synchronisation clock,
8kHz, identifies the beginning of the
frame. FSC must be synchronous to
MCLK (MCLK=FSC*2048)
As Output: Indicates the beginning of a
new frame
17
DAT_IN /
SEL
I
Data interface: Receive data from the
DSP. The data is received in 16-bit bursts
every 125 ms.
Interface selection pin in MUX mode.
16
18
10
DAT_OUT
DAT_CLK
CS
O
I
Data interface: Transmit data to the DSP.
The data is transmitted in 16-bit bursts
every 125 ms
Data clock 128 to 1024 kHz: Determines
the rate at which data is shifted into or out
of the data interface
I
µ-controller interface: Chip select enable
to read or write data. Active low
Semiconductor Group
13
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Pin Definition and Functions
Pin No.
Symbol
Function
Description
11
DCLK
I
µ-controller interface: Clock. Maximum
clock rate 1024 kHz
12
13
DIN
I
µ-controller interface: Input data
DOUT
TRI
µ-controller interface: DOUT is high ’Z’ if
no data is transmitted
14
19
INT
O
I
µ-controller interface: Interrupt output pin
MODE
Interface mode pin (parallel or MUX
mode)
4
6
ID_Ain
ID_Bin
I
I
Input for caller ID comparator (connection
to TIP)
Input for caller ID comparator (connection
to RING)
5
A feedback
B feedback
CAP_A11
O
O
O
Feedback for caller ID comparator
Feedback for caller ID comparator
7
28
Must be connected via a capacitor of more
than 5pF to CAP_A21.
1
CAP_A12
CAP_B11
CAP_B12
CAP_C11
CAP_C12
SO
O
I
Must be connected via a capacitor of more
than 5pF to CAP_A22.
2
Must be connected via a capacitor of more
than 5pF to CAP_B21.
Must be connected via a capacitor of more
than 5pF to CAP_B22.
3
I
26
27
22
O
O
O
Must be connected via a capacitor of more
than 5pF to CAP_C21.
Must be connected via a capacitor of more
than 5pF to CAP_C22.
Auxiliary output pin
Table 2: ALIS-D Pin Definition
Semiconductor Group
14
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
System Integration
3
System Integration
ALIS can be used in different modem applications to connect the data pump to the TIP/
RING wire.
3.1
ALIS with DSP-based Modem
For a modem data pump, the ALIS provides the front-end to the tip/ring.
ALIS-D
ALIS-A
Data Pump
V.34
Tip/Ring
SI
PSB 4596
PSB 4595
V.90
Note: SI: Serial Interface
Figure 4 DSP-based Modem Application
Isolation is provided by a capacitor interface, without transformer. This allows very flat
frequency response over the entire voice band, even at low frequencies.
In V.90 Modem applications, the 50/60 Hz high-pass filter can be turned off.
Semiconductor Group
15
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
System Integration
3.2
ALIS with Software Modem
ALIS also supports software modems where V.34 runs on the host computer (e.g. in
combination with a USB controller).
ALIS-D
ALIS-A
Tip/Ring
PSB 4596
PSB 4595
SI
Microcontroller with USB or PCI Interface
USB or PCI
Figure 5 Software Modem Application
Semiconductor Group
16
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
System Integration
3.3
Hybrid Modem (ISDN plus Analog)
In combination with the SIEMENS ISDN chip set, ALIS supports hybrid modems, ,
allowing connection to either the TIP/RING line or to an S or U-interface for ISDN
applications.
ALIS-D
ALIS-A
Tip/Ring
PSB 4596
PSB 4595
SI
Flash
SRAM
ISAR34
ISAC-S TE
PSB 2186 *
IOM-2 Interface
S-Interface *
PSB 7115
Microcontroller with USB or V.24 Interface
USB or V.24
Figure 6 Hybrid Modem Application, with S-interface: ISAR34 Enhanced Data Ac-
cess Controller (PSB 7115) and ISDN Access Controller for S-Bus ISAC-S TE (PSB
2186)
* Figure 4 shows a hybrid modem with the ISDN S-interface. To meet the ISDN U-
interface, the ISAC-S TE PSB 2186 is replaced by the IEC-Q TE PSB 21911.
Semiconductor Group
17
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
System Integration
3.4
Modem with Speakerphone
ALIS-D
ALIS-A
PSB 4595
TIP/RING
PSB 4596
SI
Flash
SRAM
ISAR34
ARCOFI-SP
PSB 2163
IOM-2 Interface
PSB 7115
Microcontroller with USB or V.24 Interface
USB or V.24
Figure 7 Application with Speakerphone: ARCOFI-SP Audio Ringing Codec (PSB
2160, PSB 2163, PSB 2165, PSB 2168) and ISAR34 Enhanced Data Access Control-
ler (PSB 7115)
Semiconductor Group
18
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
System Integration
3.5
Analog Videophone
The diagram below shows a system solution for an analog videophone application using
a SIEMENS chip set.
ALIS-D
ALIS-A
Tip/Ring
PSB 4596
PSB 4595
SI
Flash
IOM-2 Interface
SRAM
ISAR34
ARCOFI-SP
PSB 7115
PSB 2163
JADE AN
PSB 7230
VIDEO
CODEC
Microcontroller with USB or V.24 Interface
USB or V.24
Figure 8 ARCOFI-(SP) Audio Ringing Codec (PSB 2160, PSB 2163, PSB 2165, PSB
2168) ; ISAR34 Enhanced Data Access Controller (PSB 7115); JADE Joint Audio
Decoder Encoder (PSB 7230, PSB 7238)
Semiconductor Group
19
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Implementation
4
ALIS Implementation
The ALIS chip set replaces all the major parts of a conventional front end for modem
solutions. The circuit consists of two major parts, a DSP-based codec and an electronic
DAA. Advanced features such as ring detection, pulse dialing and caller ID are
integrated on-chip. Additional operating modes such as sleep mode or ringing mode are
implemented to minimize power consumption.
4.1
ALIS Block Diagram
The tip/ring telephone line interface is connected mainly with the ALIS-A. It is also
connected with the ALIS-D for Caller ID functions..
Isolation
Control Data
Control
Control Interface
I/O
Vdd
Control
Cap. Interface
HW-
Filter
DSP
A/D
D/A
Hybrid
and
Filters
TIP/RING
Data Interface
Caller ID
ALIS-D
ALIS-A
Transmit/Receive Data
Figure 9 ALIS Block Diagram
The analog front end (ALIS-A) is connected to the line via TIP/RING. The programmable
supply voltage for ALIS-A is generated from the line by the Vdd control. Two/four wire
conversion is implemented in the hybrid circuit. Analog anti-aliasing pre-filters (PREFI)
and smoothing post-filters (POFI) are included for signal conditioning. High-performance
over-sampling analog-to-digital converters (ADCs) and digital-to-analog converters
(DACs) assure the required conversion accuracy. The ADCs and DACs are connected
to the digital signal processor (DSP) on the digital part (ALIS-D) via a dedicated capacitor
interface which also provides the required isolation to the line. Special hardware filters
perform filtering functions such as interpolation and decimation. The DSP handles all the
necessary algorithms. These include bandpass filtering, sample rate conversion, ringing
detection, and caller ID decoding. All programmable filters and functions are also
controlled and processed by the DSP. The control interface allows external control of the
ALIS features and provides transparent access to ALIS commands and signaling pins.
Thus pre-calculated sets of coefficients can be downloaded from the system to the on-
Semiconductor Group
20
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Implementation
chip coefficient RAM (CRAM) in order to program the filters. Transmit and receive data
is transferred to and from the data pump via the data interface.
4.2
ALIS AC Signal Flow Graph
ALIS architecture is based on digital filters. The data path through these filters is shown
in the next few diagrams. The filter concept also allows maximum autonomy between the
different filter blocks. Each filter block has a one-to-one correspondence with a specific
network element. Marked filters (grey) can be programmed by the user.
digital out
AR1
FRR
AR2
RFIX1
RFIX2
ADC
ADC
DAA
Tip/
Ring
IMFIX
IM
THFIX
TH
AX1
FRX
XFIX1
XFIX2
AX2
DAC
digital in
Legend:
DAA
AR1
Data Access Arrangement, Fixed Part
Amplification Receive Filter 1
Equalization Receive
FRR
RFIX1
AR2
Receive Filter Fixed Part 1
Amplification Receive Filter 2
Receive Filter Fixed Part 2
Analog-to-Digital Converter
Transhybrid Filter Fixed Part
Transhybrid Filter
RFIX2
ADC
THFIX
TH
IMFIX
IM
Impedance Filter Fixed Part
Impedance Filter
fixed functional block
fixed filter block
user-programmable block
AX1
Amplification Transmit Filter 1
Equalization Transmit
FRX
XFIX1
AX2
Definition:
Transmit:Digital-to-Analog
Receive :Analog-to-Digital
Transmit Filter Fixed Part 1
Amplification Transmit Filter 2
Transmit Filter Fixed Part 2
Digital-to-Analog Converter
XFIX2
DAC
Figure 10 AC Signal Flow Graph
Semiconductor Group
21
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Implementation
4.2.1
Receive Path
After passing the DAA and a simple anti-aliasing pre-filter with an analog gain stage, the
voice signal is converted to a 1-bit digital data stream in the sigma-delta converter. The
first down-sampling steps are performed in fast digital hardware filters. Subsequent
processing is implemented in the digital structure which allows easy and flexible
programming of parameters. Finally, the fully processed signal is transferred to the data
interface.
Subsequent processing is done by microcode in the digital filter structure to allow
adaptability. Gain adjustment is provided in two stages, AR1 and AR2. The total gain
adjustment is programmable in two ranges: from 14 to 24 dB, in steps of 0.5 dB; and from
-3 to 14 dB, with steps between 0.02 and 0.05 dB.
Located inbetween is a decimation stage to reduce the sampling rate to the 8 kHz PCM
rate, and a low-pass filter to band-limit the signal in accordance with ITU-T G.714 and
ETSI (NET33) recommendations (in RFIX1); also an equalization stage (in FRR).
Finally, the signal is passed out to the Serial Data Interface (SDI).
ALIS meets or exceeds all ITU and ETSI (NET33) recommendations on attenuation
distortion and group delay.
4.2.2
Transmit Path
The digital input signal is received via the data interface. Low-pass filtering, gain
correction and frequency-response correction are implemented in the digital filter
structure. The up-sampling interpolation is then performed by fast hardware structures
to reduce the DSP load. The up-sampled 1-bit data stream is converted to an analog
equivalent which is smoothed by a post-filter (POFI) and converted to a 2-wire signal in
the DAA.
There are also two independent tone generators which can insert tones into the Transmit
path. They have adjustable frequencies, default 2 kHz, and a programmable bandpass-
filter to adapt the output for DTMF. When either tone generator is on, the data signal
transmission is suppressed.
4.2.3
Loops
ALIS implementation includes two loops. One is used to generate the AC-termination
impedance (IM) and the other is used to perform proper hybrid balancing (TH). A simple
additional path IM (from the receive to the transmit path) supports the impedance-
matching function.
4.2.4
Test Features
Several analog and digital test loops are implemented in ALIS. The receive and transmit
paths may be short-circuited at two different points for test purposes.
Semiconductor Group
22
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Implementation
4.3
ALIS Ring and Caller ID Signal Flow Graph
CID out
CIDL
CIDBP
RLM
CIDH
Tip/Ring
ADC
RIM
FIX
RIM
DAC
Legend:
CIDL Caller ID Lowpass
CIDH Caller ID Hilbert Transformer
CIDBP Caller ID Bandpass
RLM
Ring Level Metering
ADC Analog-to-Digital Converter
RIMFIX Ringer Impedace Filter Fixed Part
RIM
Ringer Impedace Filter
user-programmable block
comparator for CID
fixed filter block
fixed functional block
DAC Digital-to-Analog Converter
Figure 11 Ring Signal Flow Graph
These data paths operate only when the ALIS is in Ringing state.
4.3.1
Caller ID (CID) Path
The Caller ID receiver meets Bellcore specifications TR-NWT-000030 and
SR-TSV-002476 for Caller ID. In this service, the calling party’s information (Calling Line
Identification Presentation (CLIP)) is transmitted in the silent interval between the first
and second ring. ALIS receives and stores up to 4096 bits of the 1200 baud FSK
(Frequency Shift Keying) signal. The decoding scheme meets the Bell 202 and ITU-T
V.23 specifications.
The FSK signal which contains the caller information is converted to a 1-bit data stream
by a comparator in order to minimize power consumption. Down-sampling steps are
performed in fast digital hardware filters. To decode the caller ID, bandpass filtering,
Hilbert transformation and other functions are implemented. The output CID-out is
sampled at 1200 baud, and stored in the CID-RAM.
Semiconductor Group
23
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Implementation
4.3.2
Ring-Level Metering (RLM) Path
The analog signal is converted to a 1-bit data stream in the ADC. After decimation in
hardware filters, the remaining processing is done in the digital filter structure (in RLM):
bandpass filtering to select the ringing frequency, and integration to determine if the
amount of energy in-band has exceeded the threshold for a valid ring signal. The
bandpass parameters and threshold are programmable.
Ringing is detected in this path. The digital input is bandpass filtered, integrated and
compared to a threshold to determine if a ringing signal has occurred. The threshold and
bandpass filters are programmable. The result of this operation can be monitored by
reading the RMR bit (see “CR1 Configuration Register 1 (Dialing)” on page 40).
4.3.3
Loops
A loop is available to generate the Ring-termination impedance (RIM).
4.3.3.1 Test Features
There are three loopbacks on ALIS-D to test interfaces:
- Host interface: loopback from the PCM interface (just inside ALIS-D)
- Caller ID interface: loopback from Caller ID input to capacitor interface
- Capacitor interface: loopback through different parts of the capacitor interface
There are two loopbacks on ALIS-A:
- Tip/ring interface: loopback from the tip/ring, before the ADC
- Codec: loopback from the tip/ring, after the codec
Semiconductor Group
24
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5
Configuration Overview
5.1
Connection to the Telephone Line
VDDA
SENS
VDD
T2
T2G
TIP
TIP-AC
TIP
T1
T1G
RING
RING-AC
RING
VREF
GNDA
CAP1
CAP2
Figure 12 Connection of ALIS-A to the Telephone Line
As shown in the figure, ALIS-A requires a minimum of components to complete the DAA:
- Protection circuit: not shown.
- Bridge: using Schottky diodes will improve the performance at low feeding conditions.
Recommended: Dual Schottky diode SIEMENS BAT 240A.
- Resistors for current sensing.
- Capacitors for AC coupling and VDD buffering.
Semiconductor Group
25
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
- Two transistors (T1, T2) to handle the line current. T2 must be of depletion type, in order
to deal with start-up. Recommended transistors: T1: SIEMENS BSP 88; T2: SIEMENS
BSP 129.
- Components for EMC protection: not shown, as they depend on the board layout.
ALIS-D can optionally be connected to the tip/ring to provide Caller ID functions. The CID
circuit requires two capacitors and four resistors.
5.2
Host Interface
The host interface consists of a serial µ-controller interface and a 16-bit linear data
interface. They are used to connect ALIS either to a µ-controller and or to a data pump.
The two serial interfaces can be accessed on two separate serial ports or in time-
multiplex (MUX) mode on a single serial port.
5.2.1
The µ-Controller Interface
The ALIS internal configuration registers, the auxiliary ports, and the Coefficient RAM
(CRAM) are programmable via the serial µ-controller interface. This interface consists of
four pins:
CS:
Chip select, to enable interface (active low)
Clock, 1 kHz to 1024 kHz
Data input
DCLK:
DIN:
DOUT:
Data output
CS is used to start serial access to the ALIS registers and the Coefficient RAM. Following
a CS falling edge, the first eight bits received at DIN specify the command. Subsequent
data bytes (the number depends on the command) are stored in the selected
configuration registers or the selected part of the CRAM.
Serial interface specification: 8 bit, no parity, no start/stop bit. Every command must
begin with a CS falling edge.
Semiconductor Group
26
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
CS
DCLK
DIN
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7
6 5 4 3 2 1 0
Control
Data Byte 1
Data Byte 2
High ’Z’
DOUT
Figure 13 Example of a Write Access, two Data Bytes transferred
If the first eight bits received via DIN specify a read command, ALIS will start to respond
via DOUT with its specific identification byte. The number of specified data bytes within
the command (contents of configuration registers or contents of the CRAM) will follow on
DOUT.
CS
DCLK
7
6 5 4 3 2 1 0
DIN
Control
High ’Z’
7
6 5 4 3 2 1 0
7
6 5 4 3 2 1 0
DOUT
Identification
Data Byte 1
Figure 14 Example of a Read Access, one Data Byte transferred via DOUT
Semiconductor Group
27
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
The data transfer is synchronized by DCLK. DIN is latched at the falling edge of DCLK,
while DOUT changes with the rising edge of DCLK. During the execution of a command
which is followed by output data (read command), the device will not accept any new
command via DIN. The data transfer sequence can be interrupted by setting CS to ’1’.
To reduce the number of connections to the µ-processor, DIN and DOUT may be
strapped together to form a bi-directional data pin.
5.2.2
The Data Interface
A serial data interface is used for transferring voice data. The interface consists of five
pins:
DAT_CLK:
FSC:
Clock, 128 kHz to 1024 kHz
Frame synchronization clock, 8 kHz
Transmit data input
DAT_IN:
DAT_OUT:
Receive data output
The Frame Sync (FSC) pulse identifies the beginning of a receive and a transmit frame.
DAT_CLK synchronizes the data transfer on DAT_IN and DAT_OUT. The data bytes are
first serialized to 16-bit width and MSB. The rising edge indicates the start of the bit, while
the falling edge is used to latch the contents of the received data.
125 µS
FSC
DAT_CLK
15 14 13 12 11 10 9
15 14 13 12 11 10 9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
1
1
2
2
0
DAT_IN
DAT_OUT 0
16 Bit Voicedata MSB first
Figure 15 Example of a Clock Rate of 128 kb/s
Semiconductor Group
28
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
125 µS
FSC
DAT_CLK
DAT_IN
DAT_OUT
151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9 8 7 6 5 4 3 2 1 0
t
Start
tVoice
tStop
Figure 16 Example of a Clock Rate higher than 128 kb/s
The data package must stay within the frame, tStart > 0 and tStop > 0.
The FSC signal can be generated externally by the host or by ALIS.
Semiconductor Group
29
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5.2.3
Interface Modes
5.2.3.1 Demux Mode
Connection of the MODE pin to GND allows the µC and the data interface to be
accessed via two serial ports.
DSP
ALIS-D
(Data Pump)
DCLK
CS
DIN
DOUT
INT
µC Interface
DAT_CLK
FSC
DAT_IN
DAT_OUT
Data
Interface
MODE
Figure 17 Host Interface in Demux Mode, FSC as Input
DSP
ALIS-D
(Data Pump)
DCLK
CS
DIN
DOUT
INT
µC Interface
DAT_CLK
FSC
DAT_IN
DAT_OUT
Data
Interface
MODE
Figure 18 Host Interface in Demux Mode, FSC as Output
Semiconductor Group
30
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5.2.3.2 Multiplex Mode
Connection of the MODE pin to VDD allows the two interfaces to be time-multiplexed on
a single port. The interfaces are selected by the DAT_IN/SEL pin.
DSP
ALIS-D
(Data Pump)
DCLK / DAT_CLK
CS / FSC
DIN / DAT_IN
DOUT / DAT_OUT
INT
µC Interface
Data
Interface
DAT_IN / SEL
VDD
MODE
Figure 19 Host Interface in MUX Mode, FSC as Input
DAT_IN / SEL = 0
DAT_IN / SEL = 1
PIN No
11
Function
DCLK
CS
PIN No
Function
11
10
12
13
DAT_CLK
FSC
10
12
DIN
DAT_IN
DAT_OUT
13
DOUT
Table 3: Pin Definition in MUX mode, FSC as Input
Semiconductor Group
31
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
DSP
ALIS-D
(Data Pump)
DCLK / DAT_CLK
CS
DIN / DAT_IN
DOUT / DAT_OUT
INT
µC Interface
FSC
DAT_IN / SEL
Data
Interface
VDD
MODE
Figure 20 Host Interface in MUX mode, FSC as Output
DAT_IN / SEL = 0
PIN No Function
DAT_IN / SEL = 1
PIN No
11
Function
DAT_CLK
VDD / GND1)
DAT_IN
11
10
12
13
15
DCLK
CS
10
DIN
12
DOUT
13
DAT_OUT
FSC (output)
FSC (output)
15
1) must be connected to a fixed potential
Table 4: Pin Definition in MUX Mode, FSC as Output
Semiconductor Group
32
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
E
D
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l
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k
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L
P
1
2
5
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s
F
R
A
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E
Figure 21 Protocol for Transmission of µC- and PCM Data in MUX Mode
5.3 Clocking
ALIS operates with a typical master clock frequency of 16.384 MHz. This clock can either
be supplied from an external source or generated with a crystal by ALIS-D.
It is essential that the ratio of the master clock frequency to the FSC frequency is exactly
2048. This is of course guaranteed if the FSC signal is generated internally.
5.3.1
External clock
When providing the master clock externally, an external clock signal must be connected
to pin MCLK1. The MCLK2 pin must remain unconnected and the CLK_EXT bit in CR0
must be programmed to a logic ’1’. (see the section “CR0 Configuration Register 0
(Filters)” on page 39).
Semiconductor Group
33
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5.3.2
Crystal clock
Because ALIS includes an on-chip oscillator circuit, an external crystal may be used.
This crystal is connected across the MCLK1 and MCLK2 pins with two capacitors (see
Figure 22
”External Crystal Connections” ) . The CLK_EXT bit in CR0 must be
programmed to a logic '0' (= default value after reset). The capacitor values depend on
the crystal type and are specified by the crystal manufacturer. A microprocessor-grade
crystal with a parallel-resonant fundamental frequency is recommended.
To ensure that the ratio between the master clock and the FSC signal is correct, ALIS
can be programmed to internal FSC generation (set Fsc_en bit in CR4 to a logic '1'). See
Figure 18 “Host Interface in Demux Mode, FSC as Output” on page 30 and Figure 20
“Host Interface in MUX mode, FSC as Output” on page 32.
XTAL 16.384 MHz
Cxtl
Cxtl
MCLK2
MCLK1
ALIS-D
Figure 22 External Crystal Connections
Semiconductor Group
34
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5.4
Capacitor Interface
A capacitor interface is used to decouple ALIS-A from ALIS-D. It is a bi-directional serial
interface and is used for exchanging control and data information between ALIS-A and
ALIS-D. The transmission format is digital to avoid distortion and for performance
reasons. For the size and tolerance of the capacitors, see the section “ALIS Cap
Interface” on page 86.
CAP_A1
CAP_A2
CAP_A11
CAP_A12
CAP_A21
CAP_A22
CAP_B1
CAP_B2
CAP_B11
CAP_B12
CAP_B21
CAP_B22
CAP_C1
CAP_C2
CAP_C11
CAP_C12
CAP_C21
CAP_C22
ALIS-D
ALIS-A
Figure 23 Connection of Capacitor Interface between ALIS-A and ALIS-D
Semiconductor Group
35
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Configuration Overview
5.5
Caller ID Interface
To receive the caller ID, ALIS-D must be connected to the line via an RC network. See
the section “ALIS Caller ID Interface” on page 86".
Afeedback
Rfb1
Cin1
TIP
Rin1
ID_Ain
RING
ID_Bin
Cin2
Rin2
Rfb2
Bfeedback
ALIS-D
Figure 24 Caller ID Interface Connection of ALIS-D to Tip/Ring
Semiconductor Group
36
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6
Programming ALIS
Appropriate commands via the serial µ-controller interface enable very flexible
programming and verification of ALIS.
Four different commands are used to access the various control registers and RAMs:
SOP (see page 38), XOP (see page 44), COP (see page 50) and CAO (see page 51).
The first byte received via DIN selects the command type. Each command can be used
as a write or read command. Thanks to the extended ALIS control facilities, the SOP,
XOP and COP commands contain additional information for programming (writing) and
verifying (reading) the ALIS status (e.g. number of subsequent bytes, software reset,
operating mode).
Up to 8 bytes of data can be read or written with an SOP, XOP or COP command. The
CAO command allows all 512 bytes of the caller ID RAM to be read or written. Any read
command causes ALIS to respond with its specific identification byte before sending the
requested information.
6.1
Types of Commands and Data Bytes
The ALIS commands are selected by bit 3, 4 and 6 of the command byte as shown
below.
SOP command
Bit
7
6
5
4
1
3
0
2
1
0
PU 1
PU 0
RW
LSEL2 LSEL1 LSEL0
XOP command
Bit
7
6
0
5
4
1
3
1
2
1
0
RST
RW
LSEL2 LSEL1 LSEL0
COP command
Bit
7
0
6
0
5
4
0
3
2
1
0
RW
CODE CODE CODE CODE
3
2
1
0
CAO command
Bit
7
0
6
1
5
4
1
3
1
2
0
1
0
0
0
RW
Semiconductor Group
37
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.1.1
Storage of Programming Information:
• 6 Configuration registers: CR0, CR1, etc. CR5 accessed by SOP commands
• 8 Extended registers:
• 1 Coefficient RAM:
• 1 Caller ID RAM:
XR0, XR1, etc. XR7 accessed by XOP commands
CRAM accessed by COP commands
RAM accessed by CAO commands
6.2
SOP Command
The SOP (status operation) command allows the ALIS status registers to be written or
read via the µ-controller interface.
Bit
7
6
5
4
1
3
0
2
1
0
PU 1
PU 0
RW
LSEL2 LSEL1 LSEL0
PU Power-up operation command (only with SOP write command)
PU = 0 0:
PU = 0 1:
PU = 1 0:
PU = 1 1:
ALIS is set to sleep mode
ALIS is set to ringing mode
ALIS is set to conversation mode
ALIS is set to pulse dialing mode
RW Read/Write: Enables reading from ALIS or writing information to ALIS
RW = 0:
RW = 1:
Write to ALIS
Read from ALIS
LSEL Length select information (see also programming procedure)
This field identifies the number of subsequent data bytes
LSEL = 000:1 byte of data follows (CR0)
LSEL = 001:2 bytes of data follow (CR1, CR0)
LSEL = 010:3 bytes of data follow (CR2. CR1, CR0)
LSEL = 011:4 bytes of data follow (CR3, CR2. CR1, CR0)
LSEL = 100:5 bytes of data follow (CR4, CR3, CR2, CR1, CR0)
LSEL = 101:6 bytes of data follow (CR5, ...., CR1, CR0)
Note: If only one configuration register requires modification, for example CR3, this can
be accomplished by setting LSEL=011 and releasing pin CS after CR3 is written, to.
Semiconductor Group
38
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.2.1
CR0 Configuration Register 0 (Filters)
Default value: 00H
Configuration register CR0 defines the basic ALIS settings, which are: enabling/
disabling the programmable digital filters and tone generators.
Bit
7
6
5
4
3
2
1
0
TH
IM
FRX
FRR
AX
AR
RIP
CLK_
EXT
TH Enable Trans-Hybrid Balancing (TH)-Filter
TH = 0:
TH = 1:
TH-filter disabled
TH-filter enabled
IM Enable Impedance Matching (IM)-Filter
IM = 0:
IM = 1:
IM-filter disabled
IM-filter enabled
FRX Enable Frequency Response Transmit (FRX)-Filter
FRX = 0:
FRX = 1:
FRX-filter disabled
FRX-filter enabled
FRR Enable Frequency Response Receive (FRR)-Filter
FRR = 0:
FRR = 1:
FRR-filter disabled
FRR-filter enabled
AX Enable Amplification/Attenuation Transmit (AX)-Filter
AX = 0:
AX = 1:
AX-filter disabled
AX-filter enabled
AR Enable Amplification/Attenuation Receive (AR)-Filter
AR = 0:
AR = 1:
AR-filter disabled
AR-filter enabled
RIP Enable Ringer Impedance (RIP)-Filter
RIP = 0:
RIP = 1:
RIP-filter disabled
RIP-filter enabled
CLK_EXT
External clock signal
CLK_EXT = 0: Crystal Oscillator is enabled, clock will be generated by crystal
CLK_EXT = 1: Crystal Oscillator is disabled, clock must be supplied by external
source
Semiconductor Group
39
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.2.2
Default value: 00H
Configuration register CR01 selects tone generator modes and other operating modes
CR1 Configuration Register 1 (Dialing)
Bit
7
6
5
4
3
2
1
0
E_
E_
P_
P_
Pulse
No_
auto_
ring
RMR
RM
Tone2 Tone1 Tone2 Tone1
E_Tone2
Enable programmable tone generator 2
E_Tone2= 0:
E_Tone2= 1:
E_Tone1
E_Tone1= 0:
E_Tone1= 1:
P_Tone2
P_Tone2= 0:
P_Tone2= 1:
P_Tone1
P_Tone1= 0:
P_Tone1= 1:
Pulse
Pulse = 1:
Programmable tone generator 2 disabled
Programmable tone generator 2 enabled
Enable programmable tone generator 1
Programmable tone generator 1 disabled
Programmable tone generator 1 enabled
User-programmed frequency or fixed frequency selected
Fixed frequency for tone generator 2 selected
Programmed frequency for tone generator 2 selected
User programmed frequency or fixed frequency selected
Fixed frequency for tone generator 1 selected
Programmed frequency for tone generator 1 selected
Pulse dialing
Make for pulse dialing
Break for pulse dialing
Pulse = 0:
No_auto_ring
No_auto_ring= 1:Test mode to disable automatic switching from sleep mode to
ringing mode after valid ring.
No_auto_ring= 0:Normal operating mode, ALIS switches automatically to ringing
mode after ringing detection
RMR
Result of ringing metering function (this bit cannot be written)
RMR = 0:
RMR = 1:
Detected level was lower than the programmed1) reference
Detected level was higher than the programmed reference. See
“Flow of Ring Sequence and Detection” on page 65.
RM
Ringing metering function2)
1
The threshold can be programmed in the CRAM. Coefficients see “Ring Detect” on page 81.
Semiconductor Group
40
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
RM = 0:
RM = 1:
Ringing metering function disabled
Ringing metering function enabled
6.2.3
CR2 Configuration Register 2 (Caller ID)
Bit
7
6
5
4
3
2
1
0
COT/R
IDR
Call_
pon
Call_
en
Call_I
Call_II
Default value: 00H
COT/R
0 0 0:
Select cut-off transmit/receive paths
Normal operation
0 0 1:
0 1 0:
1 0 1:
1 1 0:
COR16 Cut-off receive path at 16 kHz (input of TH filter)
COR8 Cut-off receive path at 8 kHz
COT2M Cut-off transmit path at 2 MHz (POFI output)
COT64 Cut-off transmit path at 64 KHz (IM filter input)
IDR
Initialize data RAM
IDR = 0:
IDR = 1:
Normal operation selected
Contents of data RAM set to 0 (for test purposes)
Call_pon
Enable the caller ID Path
Call_pon = 0: Caller ID Path disabled
Call_pon = 1: Caller ID Path enabled
(see Call_pctl in “CR3 Configuration Register 3 (Test Loops)” on
page 42)
Call_en
Enable the caller ID
Call_en = 1:
Call_en = 0:
Caller ID decoding enabled
Caller ID decoding disabled
Call_I
Result of caller ID decoding (this bit cannot be written, for test purposes
only)
Call_I = 1:
Call_I = 0:
1st tone of caller ID detected
1st tone of caller ID not detected
Call_II
Result of caller ID decoding (this bit can not be written, for test purpose
only)
Call_II = 1:
2nd tone of caller ID detected
2
Explanation of the ringing metering function: The ring signal is rectified, and the voltage is measured. If the
voltage exceeds a certain value, the bit RMR is set to ’1’.
Semiconductor Group
41
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
Call_II = 0:
2nd tone of caller ID not detected
6.2.4
CR3 Configuration Register 3 (Test Loops)
Bit
7
6
5
4
3
2
1
0
Test Loops
SEL
Call_
pctl
DHP-R DHP-X
Default value: 00H
Test Loops Four-bit field for selection of analog and digital loopbacks
0101
ALB_CIF: Cap. interface loop of the signal from the input circuit
(CAP_B11/12 is connected to the output drivers (CAP_A11/12,
CAP_C11/12)
1000
ALB-CID: Caller ID loop; the output signal from the caller ID
comparator is connected to the output drivers of the capacitor
interface (CAP_A11/12, CAP_C11/12);
1001
1100
1101
1111
DLB-2M: Loop via HW filters;
DLB-128k: Loop inside DSP;
DLB-64k: Loop inside DSP;
DLB-PCM: Loop via PCM interface; the received data is sent back
in the next frame;
SEL
Test loop selection
SEL = 0:
SEL = 1:
Test loops via impedance path selected
Test loops via receive path selected
Call_pctl
Caller ID path control
Call_pctl = 0: Caller ID interface enabled during ringing mode
Call_pctl = 1: Caller ID interface will be selected by the Call_pon bit in CR2
Note: The path can be controlled manually for test purposes. Must be ’0’ for normal
operation.
DHP-X
DHP-X = 0:
DHP-X = 1:
Disable high-pass in transmit direction
Transmit high-pass enabled
Transmit high-pass disabled
DHP-R
Disable high-pass in receive direction
DHP-R = 0:
DHP-R = 1:
Receive high-pass enabled
Receive high-pass disabled
Semiconductor Group
42
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.2.5
CR4 Configuration Register 4 (Analog Gain)
Bit
7
6
5
4
3
2
1
0
AGR_ AGR_ AGR_ AGR_ AGX 1 AGX 0 Int_en
Z 1 Z 0 R 1 R 0
Fsc_
en
Default value: 00H
AGR_Z Analog gain in impedance loop (can be used as AGC)
AGR_Z = 00: Analog gain A disabled (0 dB amplification)
AGR_Z = 11: Analog gain A enabled (2.5 dB amplification)
AGR_Z = 10: Analog gain A enabled (6 dB amplification)
AGR_Z = 01: Analog gain A enabled (-3.5 dB amplification)1)
AGR_R
Analog gain in receive direction (can be used as AGC)
AGR_R = 00: Analog gain B disabled (0 dB amplification)
AGR_R = 01: Analog gain B enabled (3.5 dB amplification)
AGR_R = 11: Analog gain B enabled (6 dB amplification)
Analog gain in transmit direction (can be used as AGC)
AGX
AGX = 00:
AGX = 01:
AGX = 10:
AGX = 11:
Analog gain A disabled (0 dB amplification)
Analog gain A enabled (-6 dB amplification)
Analog gain A enabled (3.5 dB amplification)
Analog gain A enabled (-2.5 dB amplification)
Int_en
Int_en = 1:
Int_en = 0:
Fsc_en
Fsc_en = 0:
Fsc_en = 1
Interrupt enable
Enable interrupts
Disable interrupts
FSC signal-source selection
FSC must be generated externally
FSC generated internally
1
Note: the sum of AGR_Z and AGX should be zero for stability reasons.
Semiconductor Group
43
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.2.6
CR5 Configuration Register 5 (Version)
Bit
7
6
5
4
3
2
1
0
V_7
V_6
V_5
V_4
V_3
V_2
V_1
V_0
V
The current version of ALIS (this byte cannot be written)
02H for ALIS V2.1
6.3
XOP Command
The ALIS digital command/indication interface to the line and external equipment is
configured and evaluated by the Extended Operation (XOP) command. Other common
functions are also assigned by this command.
Bit
7
6
0
5
4
1
3
1
2
1
0
RST
RW
LSEL2 LSEL1 LSEL0
RST
RW
Software reset (same as RESET pin)
No reset
RST = 0:
RST = 1:
ALIS is reset to the default settings
Read / Write: Enables reading from or writing to ALIS
Write to ALIS
RW = 0:
RW = 1:
Read from ALIS
LSEL
LSEL = 000
LSEL = 001
Length select information. Specifies the number of subsequent data bytes
1 byte of data follows (XR0)
2 bytes of data follow (XR1, XR0)
:
LSEL= 111
6.3.1
8 bytes of data follow (XR7, ...., XR1, XR0)
XR0 Extended Register 0 (Interrupt Register)
Any interrupt indications can be monitored in the interrupt register. Interrupts can be
signaled via a logic ’1’ on the INT line. After an indication has occurred, further loading
of the interrupt register is locked until its contents are read via the µ-controller interface.
Reading the interrupt register XR0 releases the lock and the INT line is set to low again.
See “Interrupt Controller” on page 60 for more details.
Semiconductor Group
44
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
For XOP Read Commands
Bit
7
0
6
5
4
3
2
1
0
Wake_
up
Ca-
dence
RING
Caller
_ID
VDD_
OK
SI_1
SI_0
Default value: 00H
Wake_up Wake_up Interrupt
Wake_up = 0: No Wake_up Interrupt
Wake_up = 1: If CLK_OFF bit is set (see “XR6 Extended Register 6 (Power
State)” on page 49) and a ringing signal occurs1), then a Wake_up
Interrupt is generated. To clear this interrupt, the CLK_OFF bit
must be reset and ALIS-D must be supplied with a clock.
Cadence
Cadence Interrupt
Cadence = 0: No cadence Interrupt
(time between two ring bursts is available from XR4)
Cadence = 1: Time between two ring bursts exceeds the programmed time
(see “XR2 Extended Register 2 (Cadence Time Out)” on page 47).
RING
Ring Interrupt
RING = 0:
RING = 1:
No ring burst
No_auto_ring=0: this bit is set after the second valid ring burst
No_auto_ring=1: ALIS stays in sleep mode and waits for a
command. This bit represents the ring detection signal from
ALIS-A. See“CR1 Configuration Register 1 (Dialing)” on page 40.
Note: In this case, a command is mandatory to avoid a deadlock.
Caller_ID Caller ID Interrupt
Caller_ID = 0: No caller ID preamble detected
Caller_ID = 1: Caller ID preamble detected
VDD_OK
Vdd at ALIS-A Interrupt
VDD_OK = 1: Power supply for ALIS-A is available and the connection between
ALIS-A and ALIS-D is working
VDD_OK = 0: No power supply for ALIS-A or no connection between ALIS-A and
ALIS-D
1
Any signal at the line with a voltage of more than 18 V. To decode a valid ring signal, ALIS must be switched
to the Ringing Mode.
Semiconductor Group
45
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
SI_0
SI_1
Status of pin SI_0 at ALIS-A is transferred to this register
Status of pin SI_1 at ALIS-A is transferred to this register
Note: The auxiliary pins (SO_0, SO_1, SI_0, SI_1) are isolated via the capacitor
interface.
With XOP-Write Commands to Control the SO Output Pins
Bit
7
0
6
0
5
0
4
0
3
0
2
1
0
SO_2
SO_1
SO_0
SO_0
SO_1
Pin SO_0 at ALIS-A is set to the assigned value if ALIS is not in
sleep mode
Pin SO_1Q at ALIS-A is set to the inverted assigned value if ALIS
is not in sleep mode
SO_2
6.3.2
Pin SO at ALIS-D is set to the assigned value
XR1 Extended Register 1 (Interrupt Enable Register)
Bit
7
0
6
5
4
3
2
1
0
M_Wa
M_
M_
M_
M_
M_
M_
ke_up Caden RING Caller_ VDD_
ce ID OK
SI_1
SI_0
Default value: 00H
M_Wake_up
M_Wake_up = 0:Disable Wake_up Interrupt
M_Wake_up = 1:Enable Wake_up Interrupt
M_Cadence
M_Cadence = 0:Disable Cadence Interrupt
M_Cadence = 1:Enable Cadence Interrupt
M_RING
M_RING = 0: Disable RING Interrupts
M_RING = 1: Enable RING Interrupts
M_Caller_ID
Semiconductor Group
46
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
M_Caller_ID = 0:Disable Caller_ID Interrupt
M_Caller_ID = 1:Enable Caller_ID Interrupt
M_VDD_OK
M_VDD_OK = 0:Disable VDD Interrupt
M_VDD_OK = 1:Enable VDD Interrupt
M_SI_1
M_SI_1 = 0:
M_SI_1 = 1:
M_SI_0
Disable SI_1 Interrupts
Enable SI_1 Interrupts
M_SI_0 = 0:
M_SI_0 = 1:
Disable SI_0 Interrupts
Enable SI_0 Interrupts
6.3.3
XR2 Extended Register 2 (Cadence Time Out)
Bit
7
6
5
4
3
2
1
0
CTO 7 CTO 6 CTO 5 CTO 4 CTO 3 CTO 2 CTO 1 CTO 0
Default value: 7DH
CTO ms Programmable Cadence Time Out:
If the time between the first two ring bursts exceeds the time
progammed in this register, a cadence interrupt is generated. The
time-out is programmable in steps of 64 ms up to 16 seconds.
Note: 00 means no cadence time-out programmed - no interrupt will be generated.
6.3.4
XR3 Extended Register 3 (DC Characteristic)
Bit
7
6
5
4
3
2
1
0
AGB1
AGB0
B_off
DCU 1 DCU 0
DCI
DCR 1 DCR 0
AGB
Analog gain for analog trans-hybrid filter
AGB = 00:
Gain for analog trans-hybrid filter = 1.9 dB
Gain for analog trans-hybrid filter = 0 dB
Gain for analog trans-hybrid filter = -2.1 dB
Gain for analog trans-hybrid filter = -3.4 dB
AGB = 01:
AGB = 10:
AGB = 11:
B_off
Enable analog trans-hybrid filter
Semiconductor Group
47
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
B_off = 0:
B_off = 1:
Analog trans-hybrid filter on
Analog trans-hybrid filter off
Note: The analog trans-hybrid filter is an analog pre-filter optimized for long loops with a
trans-hybrid loss of about 10 dB.
DCU = 00:
DCU = 01:
DCU = 10:
DCU = 11:
U0 for DC characteristic is 0 V
U0 for DC characteristic is 1.5 V
U0 for DC characteristic is 3.5 V
U0 for DC characteristic is 7.2 V
Note: These values do not include the voltage drop at the external diodes. See also “DC
Characteristics” on page 88.
DCI
Limit current for the DC characteristic
Limit current is 100 mA
DCI = 0:
DCI = 1:
Limit current is 50 mA
DCR
Resistance of the DC characteristic
DCR = 00:
DCR = 01:
DCR = 10:
DCR = 11:
R for DC characteristic is 280 Ω
R for DC characteristic is 240 Ω
R for DC characteristic is 200 Ω
R for DC characteristic is 100 Ω
Note: If DCU is programmed to 7.2V (DCU = 11), then R for the DC characteristic is
always 70 Ω irrespective of the contents of DCR. See “DC Termination” on page
84.
6.3.5
XR4 Extended Register 4 (Cadence)
Bit
7
6
5
4
3
2
1
0
C_7
C_6
C_5
C_4
C_3
C_2
C_1
C_0
C
ms (read only)
Contains the measured time between the two first ring bursts (time
step 64 ms) if the time is below the cadence time-out as
programmed in XR2.
Semiconductor Group
48
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.3.6
XR5 Extended Register 5 (Ring Timer)
Bit
7
6
5
4
3
2
1
0
T_7
T_6
T_5
T_4
T_3
T_2
T_1
T_0
Default value: 22H
T
ms
Ring latency timer, programmable in steps of 2 ms
ALIS-A decodes any signal of more than 18 V at TIP/RING. This
signal will be transferred over to ALIS-D for further processing.
This timer bridges the time when the sine wave of the ring signal is
below the 18 V mark to ensure that ALIS does not fall back into
sleep mode.
6.3.7
XR6 Extended Register 6 (Power State)
Bit
7
0
6
0
5
0
4
3
0
2
0
1
0
CKL_
OFF
CPS1
CPS0
Default value: 00H
CPS
Current Power State (read only)
Power state is sleep
CPS = 00
CPS = 01
CPS = 10
CPS = 11
Power state is ringing
Power state is conversation
Power state is pulse dialing
Note: The power mode can be programmed by the SOP command. The current power
state will be indicated in this register.
CLK_OFF
Turn off master clock (ALIS is programmed to deep-sleep mode)
CLK_OFF = 0 Master clock is not turned off internally
CLK_OFF = 1 Master clock is turned off internally
Note: The external clock can be turned off after setting the CLK_OFF bit. The clock must
be switched on for programming ALIS.
Semiconductor Group
49
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
Note: When a crystal is used, it will be turned off automatically when the CLK_OFF bit
is set. It will be switched on when the CS signal goes low. However, the user must
wait until the crystal is working before initiating a command.
6.3.8
XR7 Extended Register 7 (Vdd)
Bit
7
0
6
0
5
0
4
0
3
0
2
1
0
0
Vdd1
Vdd0
Default value: 00H
Vdd Current Power State
Vdd of ALIS-A is 4.25 V
Vdd = 00
Vdd = 01
Vdd = 10
Vdd = 11
Vdd of ALIS-A is 4.38 V (test purpose only)
Vdd of ALIS-A is 3.90 V (test purpose only)
Vdd of ALIS-A is 4 V
6.4
COP Command
A Coefficient Operation (COP) command allows the coefficients for the programmable
filters to be written to the ALIS coefficient RAM or read from this RAM via the µ-controller
interface for verification.
Bit
7
0
6
0
5
4
0
3
2
1
0
RW
CODE CODE CODE CODE
3
2
1
0
RW
Read/Write
RW = 0
RW = 1
Subsequent data is written to ALIS
Read data from ALIS
CODE
includes the number of following bytes and the filter address
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
TH filter coefficients (part 1)
TH filter coefficients (part 2)
TH filter coefficients (part 3)
Ringer impedance (part 1)
IM filter coefficients (part 1)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
Semiconductor Group
50
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
IM filter coefficients (part 2)
Ringer impedance (part 2)
FRR filter coefficients
FRX filter coefficients
AR filter coefficients
AX filter coefficients
Tone1 coefficients
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
(followed by 4 bytes of data)
(followed by 4 bytes of data)
(followed by 4 bytes of data)
(followed by 4 bytes of data)
(followed by 4 bytes of data)
(followed by 8 bytes of data)
(followed by 8 bytes of data)
Tone2 coefficients
Level metering ringing
Caller ID 1st tone
Caller ID 2nd tone
6.5
CAO Command
A CAO (caller ID operation) command allows the decoded caller ID to be read. A CAO
command is always followed by 512 bytes of data.
Bit
7
0
6
1
5
4
1
3
1
2
0
1
0
0
0
RW
RW
Read/Write
RW = 0
RW = 1
Subsequent data is written to ALIS (test purposes only)
Read data from ALIS
Semiconductor Group
51
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Programming ALIS
6.6
Register Summary
CR Registers:
6.6.1
Bit
7
6
5
4
3
2
1
0
CR0
TH
IM
FRX
FRR
AX
AR
RIP
CLK_E
XT
CR1
CR2
CR3
E_
Tone2
E_
Tone1
P_
Tone2
P_
Tone1
Pulse
No_
auto
RMR
RM
COT/R
IDR
Call_p
on
Call_e
n
Call_I
Call_II
TestLoops
SEL
Cal
DHP-R DHP-X
_pctl
CR4 AGR_
Z 1
AGR_
Z 0
AGR_
R1
AGR_
R 0
AGX 1 AGX 0
Int_en
V_1
Fsc_
en
CR5
V_7
V_6
V_5
V_4
V_3
V_2
V_0
Table 5: Summary of CR Registers
6.6.2
Bit
XR Registers:
7
6
5
4
3
2
1
0
XR0/
R
0
Wake_ Caden
RING
Caller_ VDD_
SI_1
SI_0
up
ce
ID
OK
XR0/
W
0
0
0
0
0
0
SO_2
SO_1
SO_0
XR1
M_Wa M_Cad
ke_up ence
M_
RING
M_Call M_VD
er_ID D_OK
M_
SI_1
M_
SI_0
XR2 CTO 7 CTO 6 CTO 5 CTO 4 CTO 3 CTO 2 CTO 1 CTO 0
XR3
XR4
XR5
XR6
AGB1
C_7
T_7
0
AGB0
C_6
T_6
0
B_off
C_5
T_5
0
DCU 1 DCU 0
DCI
C_2
T_2
0
DCR 1
C_1
DCR0
C_0
C_4
T_4
C_3
T_3
0
T_1
T_0
CLK_O
FF
CPS1
CPS0
XR7
0
0
0
0
0
Vdd1
Vdd0
0
Table 6: Summary of CR Registers
Semiconductor Group
52
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7
ALIS Command Structure
The sections below show the structure of the SOP, XOP, COP and CAO write and read
commands. Section 7.5 shows an example of a mixed command.
7.1
SOP Commands
7.1.1
SOP - Write Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
DOUT
SOP write 1 byte x x 0 1 0 0 0 0
Idle
Idle
CR0
DIN
Data
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
SOP write 2 bytes x x 0 1 0 0 0 1
Idle
Idle
Idle
CR1
CR0
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP write 3 bytes x x 0 1 0 0 1 0
Idle
Idle
Idle
Idle
CR2
CR1
CR0
Data
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP write 4 bytes x x 0 1 0 0 1 1
Idle
Idle
Idle
Idle
Idle
CR3
CR2
CR1
CR0
Data
Data
Data
Data
Semiconductor Group
53
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7.1.2
SOP - Read Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
Idle
DOUT
SOP read 1 byte x x 1 1 0 0 0 0
Idle
Idle
1 0 0 0 0 0 0 1
Data
ID
CR0
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP read 2 bytes x x 1 1 0 0 0 1
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
ID
CR1
CR0
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP read 3 bytes x x 1 1 0 0 1 0
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
Idle
ID
CR2
CR1
CR0
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP read 4 bytes x x 1 1 0 0 1 1
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
Idle
Idle
ID
CR3
CR2
CR1
CR0
Data
Data
Data
Note: x: in accordance with the description of the power-up operation command. See
“SOP Command” on page 38.
Semiconductor Group
54
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7.2
XOP Commands
7.2.1
XOP - Write Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
DOUT
XOP write 2 bytes 0 0 0 1 1 0 0 1
Idle
Idle
Idle
XR1
XR0
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
XOP write 3 bytes 0 0 0 1 1 0 1 0
Idle
Idle
Idle
Idle
XR2
XR1
XR0
Data
Data
Data
7.2.2
XOP - Read Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
Idle
DOUT
XOP read 1 byte 0 0 1 1 1 0 0 0
Idle
Idle
1 0 0 0 0 0 0 1
Data
ID
XR0
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
XOP read 2 bytes 0 0 1 1 1 0 0 1
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
ID
XR1
XR0
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
Idle
DOUT
XOP read 3 bytes 0 0 1 1 1 0 1 0
Semiconductor Group
55
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
Idle
Idle
Idle
Idle
1 0 0 0 0 0 0 1
ID
Data
Data
Data
XR2
XR1
XR0
7.3
COP Command
COP - Write Commands
7.3.1
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
COP write 4 bytes 0 0 0 0 b b b b
Idle
Idle
Idle
Idle
Idle
Coeff. 3
Coeff. 2
Coeff. 1
Coeff. 0
Data
Data
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
COP write 8 bytes 0 0 0 0 b b b b
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Coeff. 7
Coeff. 6
Coeff. 5
Coeff. 4
Coeff. 3
Coeff. 2
Coeff. 1
Coeff. 0
Data
Data
Data
Data
Data
Data
Data
Data
Semiconductor Group
56
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7.3.2
COP - Read Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
COP read 4 bytes 0 0 1 0 b b b b
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
Idle
Idle
ID
Coeff.3
Coeff.2
Coeff.1
Coeff.0
Data
Data
Data
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
COP read 8 bytes 0 0 1 0 b b b b
Idle
1 0 0 0 0 0 0 1
Data
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
ID
Coeff.7
Coeff.6
Coeff.5
Coeff.4
Coeff.3
Coeff.2
Coeff.1
Coeff.0
Data
Data
Data
Data
Data
Data
Data
Note: b: in accordance with the description of the COP command. See “COP Command”
on page 50.
Semiconductor Group
57
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7.4
CAO Command
7.4.1
CAO - Write Commands
DIN
CAO write
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
0 1 0 1 1 0 0 0
Caller ID 512
Caller ID 511
Caller ID 510
...
Idle
Idle
Idle
Idle
Idle
Idle
Caller ID 1
7.4.2
CAO - Read Commands
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
ID
CAO read
0 1 1 1 1 0 0 0
Idle
Idle
1 0 0 0 0 0 0 1
Data
Caller ID
512
Idle
Data
Data
Caller ID
511
Idle
Idle
...
Caller ID 1
Semiconductor Group
58
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
ALIS Command Structure
7.5
Example of a Mixed Command
Every single command must begin with a falling edge of CS.
DIN
7 6 5 4 3 2 1 0 Bit
7 6 5 4 3 2 1 0
DOUT
SOP write 4 bytes x x 0 1 0 0 1 1
Idle
CR3
CR2
CR1
CR0
Data
Data
Data
Data
Idle
Idle
Idle
Idle
XOP write 2 bytes 0 0 0 1 1 0 0 1
Idle
XR1
XR0
Data
Data
Idle
Idle
COP write 4 bytes 0 0 0 0 b b b b
Idle
Coeff. 3
Coeff. 2
Coeff. 1
Coeff. 0
Data
Data
Data
Data
Idle
Idle
Idle
Idle
SOP read 3 bytes x x 1 1 0 0 1 0
Idle
Idle
1 0 0 0 0 0 0 1
ID
Idle
Data
CR2
CR1
CR0
Idle
Data
Idle
Data
COP read 4 bytes 0 0 1 0 b b b b
Idle
Idle
1 0 0 0 0 0 0 1
ID
Idle
Data
Coeff.3
Coeff.2
Coeff.1
Coeff.0
Idle
Data
Idle
Data
Idle
Data
Idle
XOP read 1 byte 0 0 1 1 1 0 0 0
Idle
Idle
1 0 0 0 0 0 0 1
Data
ID
XR0
Semiconductor Group
59
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Interrupt Controller
8
Interrupt Controller
There are seven different sources that can cause interrupts in ALIS. The status of these
sources are read from interrupt register XR0. Every interrupt source can be enabled
individually in interrupt-enable register XR1.
To monitor an interrupt source, the corresponding bit must be set in XR1. If an enabled
interrupt indication occurs, the interrupt register XR0 is locked. The lock is released
when the interrupt register XR0 is read. Any interrupt indication occurring during a locked
period will be detected after the lock has been released.
NOTE: An interrupt is only acknowledged when the appropriate bit has been set in the
interrupt-enable register XR1.
The INT pin can be used as an indication to allow external hardware to read the interrupt
register. If the Int_en bit (CR4) is set, the INT pin goes to ’1’ whenever the interrupt
register is locked.
The host must analyze the bits in the interrupt register to determine the cause of the
pending interrupt. All interrupt sources that are not enabled must be ignored by the host
in its analysis. It is possible for several sources together to cause only one interrupt! (i.e.
breakdown of serial connection to ALIS-A: VDD_OK, SI_0, SI_1; if more interrupts occur
during the locked period). If the interrupt was caused by a CADENCE, RING,
CALLER_ID or WAKE_UP interrupt, the indication that caused the pending interrupt is
reset by reading interrupt register XR0.
As only one interrupt can be stored internally, the host must respond immediately to
avoid loss of interrupts.
8.1
Nature and Sources of Interrupts:
There are three different kinds of interrupt indications depending on their source as
shown in the sections below.
Semiconductor Group
60
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Interrupt Controller
8.1.1
Interrupt Indication at Signal Change:
Interrupts:
Sources:
SI_0, SI_1, VDD_OK;
Signaling pins at ALIS-A (SI_0, SI_1);
VDD_OK indicates that ALIS-A has a power supply and that
the serial connection via the cap. interface is working;
Interrupt indication:
Any change in the signals will generate an interrupt. The host
must store the previous state of these bits to check which
signal caused an interrupt.
Note:
These bits will go to ‘0’ when there is no connection to
ALIS-A via the cap. interface. This will cause interrupts!
Lock behaviour:
At lock-release time, the current signal is compared to the
signal stored at lock time. Any difference will cause another
interrupt.
8.1.2
Interrupt Indication at Event:
Interrupts:
Sources:
CALLER_ID, RING, CADENCE;
CALLER_ID:
Complete marker sequence of caller ID detected;
RING:
Depending on automatic mode switching:
- detection of more than 18 V at TIP/RING (No_auto_ring ’1’);
- 2nd valid ringing (No_auto_ring ’0’);
CADENCE:
Time-out for 2nd ring burst; the time can be programmed in
XR2 (No_auto_ring ’0’);
Interrupt indication:
Lock behaviour:
These interrupts indicate that a certain event has occurred.
The bits are set from their source and can be reset from the
host only by reading the interrupt register. Whenever one of
these bits is set, this is an indication that this event has
occurred.
If one of these events occurs while the register is locked,
another interrupt will be generated as soon as the lock is
released.
Semiconductor Group
61
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Interrupt Controller
8.1.3
Interrupt Indication at High Level:
If ALIS-D is set to deep-sleep mode (XR6, CLK_OFF = ’1’), this interrupt indicates that
there is a signal greater than 18 V at TIP/RING.
Interrupts:
WAKE_UP;
Source:
ring_detect signal from ALIS-A;
Interrupt indication:
More than 18 V at TIP/RING. It is cleared after the interrupt
register has been read. Another interrupt is generated if the
signal remains higher than 18 V.
Lock behaviour:
The interrupt will lock the register as soon as clock is turned
on again! (If no clock signal is applied to ALIS-D, the other
interrupts cannot occur anyway.)
Semiconductor Group
62
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9
Operating Modes
9.1
Reset (Basic Settings Mode)
Condition: RESET low, MCLK can be down
ALIS-D:
After initial application of VDD (power-on reset), reset of the setting pin to ’0’ during
operation or a software reset (see XOP command), ALIS-D enters the basic settings
mode. Basic settings means that the ALIS-D configuration registers CR0... CR5 and
XR0... XR7 are initialized to the default value (sleep mode). All programmable filters are
disabled.
If any voltage is applied to any input pin before the initial application of VDD, ALIS may
be unable to enter the basic settings mode. In this case, it is necessary to reset ALIS or
to initialize its configuration registers to the default value.
ALIS-A:
When the plug is connected to TIP/RING and the hook switch is closed, ALIS-A
generates its supply voltage from the line current and performs a power-on reset.
9.2
Deep Sleep Mode
Condition: RESET ’1’, if used the external master clock can be deactivated.
It can be entered from any mode by programming the CLK_OFF bit in XR6. During deep
sleep mode, the serial control interface is ready to receive and register commands only
when MCLK is switched on (see “XR6 Extended Register 6 (Power State)” on page 49).
Incoming rings will be indicated by the Wake_up interrupt.
9.3
Sleep Mode
Condition: RESET ’1’, if used the external master clock must be activated.
When the RESET pin (RESET state) is released, ALIS enters sleep mode. ALIS is forced
to sleep mode when the PU (power up) bits are set to '00' in the SOP command. During
sleep mode, the serial control interface is ready to receive commands and transmit data.
Voice data received on the DAT_IN pin will be ignored. The ALIS configuration registers
the caller ID RAM, and the coefficient RAM can be loaded and read back in this mode.
9.4
Ringing Mode
Condition: RESET ’1’, if used the external master clock must be activated.
This mode is entered automatically when bit No_auto_ring is set to 0 from sleep mode
after the first ringing pulse or when the PU bits are set to '01' in the SOP command. In
this mode, ALIS will measure the level, frequency and cadence of the ringing signal. The
cadence between the first two ring bursts is stored in XR4. If the Caller_en bit is enabled,
an incoming caller ID will be decoded and stored (see CAO command).
Semiconductor Group
63
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.5
Conversation Mode
Condition: RESET ’1’, if used the external master clock must be activated.
The operating mode is entered upon recognition of the PU bits set to '10' in a SOP
command.
In conversation mode, the AC impedance loops and the DC loops are switched on. The
programmed AC and DC characteristics are implemented by these loops. The receive
and transmit paths are on. The tone generators are available.
9.6
Pulse Dialing Mode
Condition: RESET ’1’, if used the external master clock must be activated.
The pulse dialing mode is entered by setting the PU bits to '11' in a SOP command.
In pulse dialing mode, the external transistor T1 is switched on and off in accordance with
the PULSE bit in CR1. The pulse timing must be controlled by the host.
Semiconductor Group
64
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.7
Operating Flowchart
clock_off Bit is 1
1
wake_up
DEEP
SLEEP
command
SLEEP
2
ring
(in no_auto_ring = 1 and
ring)
cadence
first ring ends & no caller ID ||
no valid ring
ringing &
no_auto_ring = 0
command
3
ring
(if no_auto_ring = 0 and
second valid ring)
RINGING
vdd
si0
si1
caller_id
command
on hook
vdd
si0
si1
PULSE
DIALING
CON
VERSATION
off hook
user has to programm clock_off bit and supply clock signal in case of external clock
1
2
after this interrupts the alis -d system will stay in sleep mode. A user command to ringing
is mandatory.
after this interrupts the alis -d system will stay in ringing mode. A user command to active
or sleep is mandatory.
3
Figure 25 Operating Mode Transitions and Interrupts
9.8 Flow of Ring Sequence and Detection
Ring detection works in ALIS as a two step procedure.
In a first step, ALIS-A will detect any AC signal at TIP and RING with a peak value of
more than 18 V and will generate the Ring_detect signal. This signal can either generate
an interrupt or switch ALIS to ringing mode depending on the No_auto_ring bit in CR1
(see “CR1 Configuration Register 1 (Dialing)” on page 40). The current power mode can
Semiconductor Group
65
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
be read from the register XR6 (see “XR6 Extended Register 6 (Power State)” on page
49).
As a second step, only if enabled by RM (see “CR1 Configuration Register 1 (Dialing)”
on page 40) in ringing mode, the TIP/RING signal will be band-filtered and compared to
a programmable threshold. If the result is higher than this threshold, the RMR-bit signal
is set to one. The ring threshold can be polled as the RMR bit in CR1. The following flow
charts show these sequences in more detail.
Note: The initial connection to TIP RING looks like a ring voltage to ALIS-A. The reaction
of ALIS-D depends on the auto_ring bit:
a) auto_ring: ALIS-D goes to ringing, since the spike is not a valid ringing signal.
ALIS-D then goes to sleep mode.
b) No_auto_ring: ALIS-D generates a ring interrupt, stays in sleep mode and waits
for a command. The user has to switch ALIS-D to ringing and poll the RMR bit. If
ringing is not valid (RMR bit = 0), the chip can be set back to sleep mode.
To detect a valid ring signal and caller ID, ALIS must be programmed to the following
setting:
• set RM to ’1’ (see “CR1 Configuration Register 1 (Dialing)” on page 40)
• cadence time-out must be programmed to PTT requirements (see “XR2 Extended
Register 2 (Cadence Time Out)” on page 47)
• ring latency timer must be programmed to a value higher than four times the ring
period (see “XR5 Extended Register 5 (Ring Timer)” on page 49)
• valid ring coefficients
• set No_auto_ring to ’0’ (see “CR1 Configuration Register 1 (Dialing)” on page 40)
• enable Call_en (see “CR2 Configuration Register 2 (Caller ID)” on page 41)
• enable corresponding interrupts
Semiconductor Group
66
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.1
Successful Ring Sequence, Auto Ring Enabled, no Caller ID
The following chart and diagram show the successful flow of a ring-event detection with
automatic power-mode change (No_auto_ring = 0, Caller_en = 0, RM = 1). In this
operating mode, ALIS will not decode a caller ID.
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
i
i
n
n
g
_
d
e
t
e
c
t
R
g
_
t
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
2nd ring
on
hook
off
hook
Line:
sleep
ringing
conv.
Mode:
ringcounter
ringcounter
Counter:
cadence counter
VDD_ok
VDD_ok
VDD_ok
VDD_ok VDD_ok
ring
Interrupt:
Figure 26 Successful Ring Sequence, No_auto_ring = 0; Caller_en = 0
Semiconductor Group
67
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.2
Successful Ring Sequence, Auto Ring Enabled, Caller ID
The following chart and diagram show the successful flow of a ring-event detection with
automatic power-mode change (No_auto_ring = 0, Caller_en = 1, RM = 1). In this
operating mode, ALIS will decode and store a caller ID.
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
C
a
l
l
e
r
I
D
R
e
a
d
i
n
g
C
a
l
l
e
r
I
d
R
R
i
i
n
n
g
_
d
e
t
e
c
t
g
t
_
h
r
e
s
h
o
l
d
on
hook
1st ring
on
hook
caller ID
on
hook
2nd ring
on hook
off
hook
Line:
sleep
ringing
conv.
Mode:
ringcounter
ringcounter
Counter:
Interrupt:
cadence counter
VDD_ok
VDD_ Caller_ID
ok
VDD_ok
Vdd_ok Vdd_ok
ring
Figure 27 Successful Ring Sequence, No_auto_ring = 0; Caller_en = 1
Semiconductor Group
68
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.3
Unsuccessful Ring Sequence, Auto Ring Enabled, no Caller ID
The following chart and diagram show the unsuccessful flow of a ring-event detection
because of no 2nd ring with automatic power-mode change (No_auto_ring = 0,
Caller_en = 0, RM = 1).
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
R
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
Line:
sleep
Mode:
ringcounter
Counter:
Interrupt:
cadence counter
VDD_ok
VDD_ok
cadence
Figure 28 Unsuccessful Ring Sequence, No_auto_ring = 0; Caller_en = 0
Semiconductor Group
69
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.4
Unsuccessful Ring Sequence, Auto Ring Enabled, Caller ID
The following chart and diagram show the unsuccessful flow of a ring-event detection
because of no 2nd ring with automatic power-mode change (No_auto_ring = 0,
Caller_en = 1, RM = 1).
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
C
a
l
l
e
r
I
D
R
e
a
d
i
n
g
C
a
l
l
e
r
I
d
R
i
i
n
n
g
g
_
_
d
e
t
e
c
t
R
t
h
r
e
s
h
o
l
d
on
hook
1st ring
on hook
ringing
caller ID
on hook
Line:
sleep
sleep
Mode:
ringcounter
Counter:
Interrupt:
cadence counter
VDD_ok
VDD_ok Caller_ID
cadence
Figure 29 Unsuccessful Ring Sequence, No_auto_ring = 0; Caller_en = 1
Semiconductor Group
70
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.5
Successful Ring Sequence, Auto Ring Disabled, No Caller ID
The following chart and diagram show the successful flow of a ring-event detection with
no automatic power-mode change (No_auto_ring = 1, Caller_en = 0, RM = 1). In this
operating mode, ALIS will not decode the caller ID.
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
i
i
n
n
g
_
d
e
t
e
c
t
R
g
t
_
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
2nd ring
on
hook
off
hook
Line:
sleep
ringing
conv.
Mode:
ring
VDD_ok
VDD_ok
ring
VDD_ok VDD_
ok
Interrupt:
ring mode
sleep mode
ring mode
close
hook;
conv.
Host
CMDs:
poll RMR √
poll RMR √
Figure 30 Successful Ring Sequence, No_auto_ring = 0; Caller_en = 0
Note: The RMR bit must be polled by the host to verify that the ringing signal is above
the programmed threshold level and check the VDD interrupts.
Semiconductor Group
71
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.6
Successful Ring Sequence, Auto Ring Disabled, Caller ID
The following chart and diagram show the successful flow of a ring-event detection with
no automatic power-mode change (No_auto_ring = 1, Caller_en = 1, RM = 1). In this
operating mode, ALIS will decode and store the caller ID.
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
C
a
l
l
e
r
I
D
R
e
a
d
i
n
g
C
a
l
l
e
r
I
d
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
R
h
r
e
s
h
o
l
d
on
hook
1st ring
on hook
2nd ring
on
hook
off
hook
Line:
sleep
ringing
conv.
Mode:
ring
VDD_ok
Caller_ID
VDD_ok
ring
VDD
_ok
VDD
_ok
Interrupt:
ring mode
close
hook;
conv.
Host
CMDs:
poll RMR √
poll RMR √
Figure 31 Successful Ring Sequence, No_auto_ring = 1; Caller_en = 1
Note: The RMR bit must be polled by the host to verify that the ringing signal is above
the programmed threshold level.
By leaving ALIS in ringing mode after the first ring, the caller ID can be detected
and stored.
Semiconductor Group
72
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.7
Unsuccessful Ring Sequence, Auto Ring Disabled, no Caller ID
The following chart and diagram show the unsuccessful flow of a ring-event detection
because of no 2nd ring with no automatic power-mode change (No_auto_ring = 1,
Caller_en = 0, RM = 1).
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
Line:
sleep
Mode:
ring
VDD_ok
Interrupt:
ring mode
sleep mode
Host
CMDs:
poll RMR √
Figure 32 Unsuccessful Ring Sequence, No_auto_ring = 1; Caller_en = 0
Note: The RMR bit must be polled by the host to verify that the ringing signal is above
the programmed threshold level.
The cadence time and number of rings must be calculated by the host.
Semiconductor Group
73
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.8
Unsuccessful Ring Sequence, Auto Ring Disabled, Caller ID
The following chart and diagram show the unsuccessful flow of a ring-event detection
because of no 2nd ring with no automatic power-mode change (No_auto_ring = 0,
Caller_en = 1, RM = 1). .
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
C
a
l
l
e
r
I
D
R
e
a
d
i
n
g
C
a
l
l
e
r
I
d
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
R
h
r
e
s
h
o
l
d
on
hook
1st ring
on
hook
caller ID
on hook
Line:
sleep
ringing
Mode:
ring
VDD_ok Caller_ID
Interrupt:
ring mode
Host
CMDs:
poll RMR √
Figure 33 Unsuccessful Ring Sequence, No_auto_ring = 1; Caller_en = 1
Note: The cadence time and the number of rings must be calculated by the host.
Semiconductor Group
74
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.9
Unsuccessful Ring Sequence, Auto Ring Enabled
The following chart and diagram shows an unsuccessful flow of a ring-event detection
because ringing is below the ring threshold level with an automatic power-mode change
(No_auto_ring = 0, RM = 1).
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
Line:
sleep
Mode:
ringcounter
Counter:
Interrupt:
VDD_ok
VDD_ok
Figure 34 Unsuccessful Ring Sequence, No_auto_ring = 0
Semiconductor Group
75
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.10 Unsuccessful Ring Sequence, Auto Ring Disabled
The following chart and diagram show an unsuccessful flow of a ring-event detection
because ringing is below the ring threshold level with no automatic power-mode change
(No_auto_ring = 1, RM = 1).
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
R
i
i
n
n
g
g
_
_
d
e
t
e
c
t
t
h
r
e
s
h
o
l
d
on
hook
1st ring
ringing
on hook
sleep
Line:
sleep
Mode:
ring
VDD_ok
Interrupt:
ring mode
sleep mode
Host
CMDs:
poll RMR √
Figure 35 Unsuccessful Ring Sequence, No_auto_ring = 0
Note: RMR will not be ’1’
Semiconductor Group
76
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Operating Modes
9.8.11 Start from Deep Sleep Mode
The following chart and diagram show a start-up procedure from deep sleep mode.
2
n
d
R
I
N
G
B
u
r
s
t
1
s
t
R
I
N
G
B
u
r
s
t
R
R
i
i
n
n
g
g
_
_
d
t
e
t
e
c
t
h
r
e
s
h
o
l
d
on
hook
1st ring
Line:
deep
sleep
Mode:
Wake_up
Interrupt:
enable MCLK on board
any power mode
Host
CMDs:
set CLK_OFF = 0
Figure 36 Deep Sleep Start
Note: After the wake_up interrupt, any power mode and operation flow can be
programmed as described in the previous sections .
Semiconductor Group
77
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Modem Functions
10
Modem Functions
Pulse Dialing
10.1
Pulse dialing will be implemented by shortening the line with external transistor T1. Pulse
timing must be controlled by the host. Pulse shaping is implemented in ALIS-A and
complies with ETS 300 001
10.2
DTMF Dialing
DTMF Dialing is implemented by two internal tone generators (see “Programming the
ALIS DTMF Tone Generators” on page 78). Since the level of tone generator 2 is 3 dB
higher than that of tone generator 1, the former should be used for the high frequency
group. The frequency accuracy of the tone generators is better than 1%. The absolute
±
transmission level can be programmed using the AX filter. Software for computing the
coefficients is available.
The tone generators can also be used to generate any in-band sine wave for test or
measurement purposes.
10.2.1 Programming the ALIS DTMF Tone Generators
Two independent tone generators are available. When one or both of them are turned
on, the voice signal is switched off automatically. A programmable bandpass filter is
included to make the generated signal suitable for DTMF. The default frequency for both
tone generators is 2000 Hz. Coefficients for other frequencies are generated by a
software tool.
Byte sequences for programming both tone generators and bandpass filters:
Frequency Command
Byte 1
11
Byte 2
B3
Byte 3
5A
Byte 4
2C
697 Hz
770 Hz
852 Hz
941 Hz
0B *)
0B *)
0B *)
0B *)
12
33
5A
C3
13
3C
5B
32
1D
1B
5C
CC
1209 Hz
1336 Hz
1477 Hz
1633 Hz
0C *)
0C *)
0C *)
0C *)
32
EC
AA
9B
32
1D
AC
3B
52
52
51
51
B3
22
D2
25
Semiconductor Group
78
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Modem Functions
*) 0B is used for programming tone generator 1
0C is used for programming tone generator 2
Table 7: Programming the tone generators
The sine wave is filtered by a bandpass, the Q factor of this band filter can be altered in
the range from 0 to 7 and can be programmed by setting the first nibble of byte 3 to the
corresponding value (always 5 in this table). The resulting signal amplitude can be set
by programming the filters AR1 and AR2.
10.3
Caller ID
The caller ID interface is compatible with Bellcore TR-NWT-000030 and SR-TSV-
002476 as regards generic requirements for transmitting asynchronous voice-band data
to customer premises equipment (CPE) from a serving stored-control switching system
(SPCS) or a central office (CO). In this service, the information about the calling party is
embedded in the silent interval between the first and the second ring. During this period,
ALIS receives and stores up to 4096 bits of the1200-baud FSK signal. The decoding also
complies with BELL 202 and CCITT V.23 specifications. (see “Programming the ALIS
Caller ID Coefficients” on page 81)
10.3.1 Characteristics for Caller ID
Parameter
Sym-
bol
Limit Values
typ
Unit
Reference
min
max
Input detection level
Detect frequencies
Vin
-36
12.3
-9
275
dBm
mV
Bell 202 1 (mark)
Bell 202 0 (space)
1188
2178
1200
2200
1212
2222
Hz
Hz
Bell 202
CCITT V.23 1 (mark)
CCITT V.23 0 (space)
1280.5 1300 1319.5
2068.5 2100 2131.5
Hz
Hz
CCITT V.23
Input noise tolerance
Input baud rate
SNR
20
dB
Hz
1188
1200
1212
Table 8: Characteristics of Caller ID
Semiconductor Group
79
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Modem Functions
10.3.2 Storage and Reading of Caller ID
The storage of the decoded caller ID is enabled after the first space following the mark
state. This event will be indicated by the caller ID interrupt. The maximum storage size
is 4096 bits. Start, stop-bit and check-sum decoding must be performed by the host.
CID FSK
First
Ringing
Second
Ringing
TIP/RING
DATA
mark
state
channel
seizure
Figure 37 CID Input Timing
When the RAM is read with the CAO command, the received bits will be sent from ALIS
in the following order:
DIN:
CAO-
com-
mand
DOUT:
id_byte
...
b0 is the first caller ID data bit after the ’0’ which ends the marker sequence, b1 the
second, b2 the third etc. ...
The host can read the caller ID RAM at any time. Note that the read data may be
erroneous when caller ID data is received at the same time, as old and new data might
be mixed. However, the received caller ID bits are stored correctly in the RAM!
-> Try not to read the RAM while the caller ID is being received!
Semiconductor Group
80
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Modem Functions
10.3.3 Programming the ALIS Caller ID Coefficients
Frequency Command
Byte 1,2
CA 0E
Byte 3,4
CA 09
Byte 5,6
99 99
Byte 7,8
99 99
BELL 202 /
CCITT V.23
0E (CID1)
0F (CID2)
FD B5
BA 07
DA XX
XX XX
Table 9: Programming the ALIS Caller ID Coefficients
10.4
Billing Pulse
Billing pulse frequencies of 12 and 16 kHz are filtered out by the digital part of ALIS. No
external components are necessary for blocking.
10.5
Ring Detect
10.5.1 Functional Description
In sleep mode, any signal greater than a typical value of 18 volts will be detected.
Depending on the No_auto_ring bit, either an interrupt will occur or ALIS will be switched
automatically to ringing mode. In this mode, the ringing signal will be passed to ALIS-D
and decoded. If the ring burst does not meet the programmed requirements within a
programmable time, ALIS will return to sleep mode. After a latency time, ALIS will
decode the caller ID. When the second valid ring burst occurs, a ring interrupt is
generated, signalling the incoming call to the host (see “Flow of Ring Sequence and
Detection” on page 65)
Semiconductor Group
81
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Modem Functions
10.5.2 Programming the ALIS Ring Detect Coefficients
Frequency Command
Byte 1
AA
Byte 2
05
Byte 3
0F
Byte 4
8E
25 Hz
70Vrms
10 kΩ
0D
Command
03
Byte 1,2
1C B3
2D 62
Byte 3,4
AB AB
A6 BB
Byte 5,6
54 2D
2A 7D
Byte 7,8
62 2D
0A D4
1.0 µF
06
Table 10: Programming ALIS Ring Detect Coefficients
Frequency Command
Byte 1
22
Byte 2
15
Byte 3
B5
Byte 4
84
50 Hz
50Vrms
10kΩ
0D
Command
03
Byte 1,2
1C A4
2B A2
Byte 3,4
AA AB
A6 BB
Byte 5,6
BD 2B
2C 63
Byte 7,8
A2 2D
3A D4
0.6 µF
06
Table 11: Programming ALIS Ring Detect Coefficients
10.5.3 Ring Threshold in Sleep Mode
Parameter
Symbol
Limit Values
Unit
Reference
min
typ
max
18
Ring Threshold
12
Vrms
Table 12: Ring Threshold in Sleep Mode
Semiconductor Group
82
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Characteristics
11
Electrical Characteristics
Programmable Filters
11.1
A set of programmable filters is used to adapt the whole system to:
• country standards
• board designs (EMI capacitors etc.)
• data pumps
• telephone lines
Note: All these coefficients will be computed by a coefficient program. Any change in
these computed values may cause a loss of performance or instability.
In detail, the following filters are programmable:
• Trans-hybrid balancing (TH) filter
• Trans-hybrid pre-balancing filter
• Impedance matching (IM) filter
• Frequency response receive (FRR) filter
• Frequency response transmit (FRX) filter
• Ringer impedance
Amplification/attenuation transmit (AX) filter
Gain for AX filter
range 3.. -14 dB:
step size 0.02 .. 0.05 dB
step size 0.5 dB
range -14 .. -24 dB:
Gain for AGX
range 3.5, 0 -2.5, -6
Amplification/attenuation receive (AR) filter
Gain for AR filter
range -3 .. 14 dB:
step size 0.02 .. 0.05 dB
step size 0.5 dB
range 14 .. 24 dB:
Gain for AGR_R:
range 0, 3.5, 6 dB
Gain for AGR_Z:
range -3.5, 0, 2.5, 6 dB
11.2
DC Characteristics
The filter coefficients are generated by a software tool including a high-level model of
ALIS and additional user-defined or application-specific system components.
Semiconductor Group
83
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Characteristics
11.2.1 DC Termination
The DC termination is enabled in conversation mode and is disabled during ringing
mode, puls dialing mode and sleep mode. The DC termination can be programmed
according to the formula:
for i < Imax
(u – Uo)
--------------------
i(u) =
for i > Imax
i(u) = Imax
R
Note: U0 is the sum of the U value listed in table 14 and the flow voltage of the diodes
in the external bridge (typ. 2 x 0.4 V)
11.2.2 Programming Ranges for DC Termination
Imax
50 mA
100 mA
Table 13: Programming Range for Imax
U (DCU)
0 V
1.5 V
3.5 V
7.2 V
Table 14: Programming Range for U
R (DCR)
70 Ω
100 Ω
200 Ω
240 Ω
280 Ω
Table 15: Programming Range for R
Note: For programming details, see “XR3 Extended Register 3 (DC Characteristic)” on
page 47
Semiconductor Group
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Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Characteristics
11.2.3 Input Current in Puls Dialing Mode
Uab = 30 V DC
Parameter
Symbol
Limit Values
min typ max
500
Unit
Input current at break
Iin
µA
Table 16: Input Current in Puls Dialing Mode
11.3
AC Termination
11.3.1 Ringer Impedance
Programming of the ringer impedance is supported by a software tool. The following
table shows typical values.
Uab = 70 Vrms
Parameter
Ringer impedance (20 Hz < f <60 Hz)1)
Typical capacitors
Symbol
Limit Values
Unit
min
typ
max
Rin
5
10
25
1
kΩ
Cin
0.6
µF
Ringer impedance in other modes2)
1) The frequency range can be changed
2) Ringer impedance is generated only in ring mode
Table 17: Ringer Impedance
Semiconductor Group
85
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Characteristics
11.4
ALIS Caller ID Interface
Parameter Symbol
Limit Values
Unit
min
typ
50
max
Capacitance
Cin
Rin
Rfb
nF
kΩ
kΩ
Rin
Rfb
50
200
Table 18: ALIS Caller ID Interface
11.4.1 Ring Detect Levels and Frequencies
.
Parameter
Symbol
Limit Values
min typ max
30 100
Unit
Tolerance
Range of programs for
ring-level detection
Vring
V
±10%
Ring-level detection step
size
∆ Vring
Fring
10
60
V
±10%
±10%
Range of programs for
frequency detection
20
Hz
Table 19: Ring Detect Levels and Frequencies
11.5
ALIS Cap Interface
Parameter
Symbol
Limit Values
Unit
min
typ
max
1000
5
Capacitance
Cin
5
10
pF
%
Tolerance between CAP_x1
and CAP_x2
Inductance
Isolation
10
nH
kV
2
4
Table 20: ALIS Cap Interface
Semiconductor Group
86
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12
Electrical Performance Characteristic
Absolute Maximum Ratings
12.1
Parameter
Symbol
Ratings
Unit
min
max
7.0
Digital supply voltage
VDD
VDDA
-0.3
-0.3
-0.3
V
V
V
Analog supply voltage
7.0
Analog input and output voltage
Vin, Vout
VDDA +
0.3
Digital input voltages
VDin
-0.3
VDD +
0.3
V
DC input and output current
Storage temperature
Iin, Iout
TST
-10
-60
-10
10
125
80
1
mA
°C
°C
W
Ambient temperature under bias
Max. power dissipation
TA
PDmax
Note: Stresses above the absolute maximum ratings may cause permanent damage to
the device. Extended operation at maximum levels may degrade performance and
affect reliability.
Table 21: Absolute Maximum Ratings
Semiconductor Group
87
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.2
Recommended Operating Conditions
Parameter
Symbol
Conditions
Unit
min
4.75
4.00
typ
max
Digital supply voltage
VDD
5.0
5.25
V
V
Analog supply voltage ALIS-A
(programmed to 4.25 V)
VDDA
4.25
Analog supply voltage ALIS-D
VDDA
TA
4.75
0
5.0
5.25
70
V
Ambient temperature under
bias
°C
Operating frequency
Clock duty cycle
fclk
16.384
50
20**
55
MHz
%
45
Signal rise and fall time
tr, tf
20
ns
Note: Extended operation outside the recommended limits may degrade performance
and affect reliability.
Note: **This value is guaranteed by design. Characterization and periodically samples
will be applied to production devices at this test conditions.
Table 22: Recommended Operating Conditions
12.3
DC Characteristics
12.3.1 ALIS-A
VDDA= 4.25V progr.; TA=0 - 70°C
Parameter
Symbol
tPU
Conditions
Spec. Limits
Unit
ms
min
typ
max
Power-up time
100
VDDA supply current1)
Ringing mode2)
IDDA1
Vring=60V DC +
90Vrms,
fring=25 - 50Hz
2.5
7
3
mA
Conversation mode3)
Pulse dialing mode
Digital interface
IDDA2 fclk=16.384MHz
10
mA
IDDA3
Vab=30 V DC
500
µA
Semiconductor Group
88
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
Low-level input voltage
High-level input voltage
Low-level output voltage
VIL4)
VIH4)
VOL5)
VOH5)
0.8
0.5
V
V
V
V
2.0
IOL=5mA
High-level output
voltage
IOH=-5mA
3.25
Input current low
Input current high
Input resistance
Sleep mode
IIL
VIL=GNDA
±1
±1
µA
µA
IIH
VIH=VDDA
Rin
Rin
Rin
note6)
MΩ
Ω
Conversation mode
Pulse dialing mode
see 10.2.3
Inter-pulsing
200
Ω
period (make)
Ring threshold
VRThresh VDDA=4.25V ext.
15 VRMS
Power supply rejection
PSRR
Ripple:
0-150kHz;
70mVrms
either supply/direction
either supply/direction
300Hz - 3.4kHz
3.4kHz - 150kHz
40
25
dB
dB
1) Will be taken from TIP/RING when the hook switch is open
2) In ringing mode the ringer impedance will be synthesized. Therefore a current according to this impedance will
flow from TIP/RING. This current is taken out of the ring burst as an AC current.
3) In conversation mode the DC characteristic will be synthesized and a current according to this characteristic will
flow from TIP/RING.
4) Digital Inputs: Test, SI_0, SI_1
5) Digital Outputs: SO_0, SO_1Q
6) Within this mode the hook switch must be open and the input resistance is infinite.
Table 23: DC Characteristics ALIS-A
Semiconductor Group
89
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.3.2 ALIS-D
VDD = VDDA= 5V± 5%; TA=0 - 70°C
Parameter
Symbol
Conditions
Spec. Limits
Unit
min
typ
max
Supply current
VDD=5V, no
loads
Deep sleep mode
Sleep mode
IDD0
IDD1
IDD2
IDD3
IDD4
<10
3.5
8.0
13
50
10
15
25
15
µA
fclk =
16.384 MHz
mA
mA
mA
mA
V
Ringing mode
Conversation mode
Pulse dialing mode
Low-level input voltage VIL11)
8.0
0.8
1.5
0.5
VIL22)
VIL33)
High-level input voltage VIH11)
2.0
3.5
3.5
V
VIH22)
VIH33)
Low-level output
voltage
VOL4)
VOH4)
IOL=5mA
0.5
V
V
High-level output
voltage
IOH=-5mA
VDD-
0.5
Input current low
IIL1,2)
VIL=GND
VIH=VDD
VIL=GND
VIH=VDD
±1
±1
±1
±1
µA
µA
µA
µA
Input current high
Tri-state current low
Tri-state current high
IIH1,2)
IOZL5)
IOZH5)
1) TTL Inputs: DCLK, CS, DIN, DAT_CLK, DAT_IN, MODE, FSC
2) CMOS Input: RESET
3) Clock Input: MCLK1
4) Outputs: DOUT, INT, DAT_OUT, FSC
5) Tristates, Bidirectionals: DOUT, FSC
Table 24: DC Characteristics ALIS-D
Semiconductor Group
90
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4
AC Transmission Characteristics
Unless otherwise stated, the transmission characteristics are guaranteed within the
following test conditions:
TA=0 °C to 70 °C
VDD=5V ±5%
VDDA=4.25V (generated from ALIS-A)
Line impedance ZL = 600 0.1% Ohms
±
Termination impedance ZM = 600 Ohms
digital: 0dBm0 = -3 dB FS
analog: 0 dBm is equal to the voltage of 0.775 Vrms when loaded with 600 Ohms
0 dBm = 0dBm0
f=1004Hz.
2 VRMS metering at 12 or 16 kHZ
VDDA programmed to 4,25 V: VTIP/RING>=6,8 V
VDDA programmed to 4 V: VTIP/RING>=6,5 V
12.4.1 Absolute Gain Error
AGX=AGR=0 dB
Parameter
Symbol
Limit Values
Unit
Test condition
min
typ max
Absolute gain error
receive
AE_R
-10 dBm
TA=25 °C;
-1
±0.5 +1
dB
VDDA=4.25V
TA=0-70 °C;
VDDA=4.25V
-1.2 ±0.7 +1.2 dB
Absolute gain error
transmit
AE_X
-10 dBm0
TA=25 °C;
-1
±0.5 +1
dB
VDDA=4.25V
TA=0-70 °C;
VDDA=4.25V
-1.2 ±0.7 +1.2 dB
Semiconductor Group
91
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
Table 25: Absolute gain error
12.4.2 Gain Tracking
AGX=AGR=0dB
Parameter
Symbol
Limit Values
min typ max
Unit
Test condition
Gain tracking receive
GT_R
-0.15 ±0.01 0.15
0 to -10 dBm
-0.15 ±0.01 0.15
-30 to -40 dBm
-40 to -50 0.dBm
0 to -10 dBm0
-0.3
-0.5
-0.1
-0.5
±0.07 0.3
±0.05 0.5
±0.07 0.1
±0.3 0.5
Gain tracking transmit
GT_X
-10 to -40 dBm0
-40 to -50 dBm0
Table 26: Gain Tracking
12.4.3 Harmonic Distortion plus Noise
-10 dBm0; ZL= 600 Ω; f=1004 Hz
Parameter
Symbol
Limit Values
Unit
Test condition
C-weighted
min typ max
HDN receive
THDN_Rc 74
THDN_Tc 74
THDN_Rl 72
THDN_Tl 72
77
77
75
75
dBFS
dBFS
dBFS
dBFS
HDN transmit
HDN receive
HDN transmit
linear-weighted1)
1) Linear weighted values are guaranteed by design, characterization, and periodically samples and testing
production devices at this test conditions
Table 27: Harmonic Distortion plus Noise
Semiconductor Group
92
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.4 Harmonic Distortion
-10 dBm0; ZL= 600 Ω; f=100 to 2000 Hz, 2nd and 3rd harmonic
Parameter
Symbol
Limit Values
min typ max
Unit
Test condition
HD receive
HDN_R
HDN_T
HDN_El
80
80
80
dB
HD transmit
dB
dB
HD of echo signals
via TIP/RING
Table 28: Harmonic Distortion for Echo Signals
12.4.5 Return Loss
The return loss at a level of 0 dBm0 will be better than 16 dB in a 300-3600 Hz bandwidth
using the following set of defined impedances
600 Ohms
220 Ohms + (820 Ohms in parallel with 115 nF)
120 Ohms + (820 Ohms in parallel with 110 nF)
370 Ohms + (620 Ohms in parallel with 310 nF)
Semiconductor Group
93
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.6 Frequency Response
12.4.6.1 Receive
Reference frequency 1kHz, input signal level 0dBm0
Figure 38 Frequency Response Receive
Semiconductor Group
94
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.6.2 Transmit
Reference frequency 1kHz, input signal level 0dBm0
Figure 39 Frequency Response Transmit
Semiconductor Group
95
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.7 Group Delay
Maximum delays when ALIS is operating with H(TH)=H(IM)=0 and H(FRR)=H(FRX)=1
including the delay through A/D- and D/A converters. Specific filter programming may
cause additional group delays.
Group Delay deviations remain within the limits in the figures below.
12.4.7.1 Group Delay Absolute Values
Parameter
Symbol
Limit Values
min typ max
Unit
Reference
Receive delay
DRA
340
µs
µs
Input signal
level 0 dBm0
Transmit delay
DXA
400
Table 29: Group Delay
12.4.7.2 Group Delay Distortion Receive
Input signal level 0dBm0
Figure 40 Group Delay Distortion Receive
Semiconductor Group
96
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.7.3 Group Delay Distortion Transmit
Input signal level 0dBm0 1))
Figure 41 Group Delay Distortion Transmit
1
R is switched on: reference point is at TGmin
HPR is switched off: reference point is at 1.5 kHz
Semiconductor Group
97
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.8 Out-of-Band Signals at TIP/RING Receive
When an 0dBm0 out-of-band sine-wave signal with a frequency of (<<100Hz or 3.4kHz
to 100kHz) is applied to the analog input, the level of any resulting frequency component
at the digital output will stay at least X dB below a 0dBm0, 1kHz sine wave reference
signal at the analog input.1))
Figure 42 Out of Band Receive
1
Poles at 12 kHz ± 150 Hz and 16 kHz ± 150 Hz will be provided
Semiconductor Group
98
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.9 Out-of-Band Signals at TIP/RING Transmit
When a 0 dBm0 sine wave with a frequency of (300Hz to 3.99kHz) is applied to the digital
input, the level of any resulting out-of-band signal at the analog output will stay at least
X dB below a 0 dBm0 1 kHz sine-wave reference signal at the analog output.
Figure 43 Out of Band Transmit
Semiconductor Group
99
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.4.10 Trans-hybrid Loss
The quality of trans-hybrid balancing is very sensitive to deviations in gain and group
delay. These deviations are inherent in ALIS A/D and D/A converters as well as in all the
external components used.
Measurement of ALIS trans-hybrid loss: A 0dBm0 sine wave signal and a frequency in
the range between 300 - 3400 Hz is applied to the digital input. The resulting analog
output signal VOUT at TIP RING is received and canceled by the TH filter. The
programmable filters FRR, AR, FRX, AX and IM and the balancing filter TH are enabled
with optimized coefficients.
The resulting echo measured at the digital output is at least X dB below the level of the
digital input signal as shown in the table below. (Filter coefficients will be provided.)
Parameter
Symbol
Limit
Unit
Test condition
Values
Trans-hybrid loss at
min
typ
40
45
40
35
35
300 Hz
THL 300
THL 500
THL2500
THL3000
THL3400
27
33
29
27
27
dB TA=25° C; VDDA=4.25V;
500 Hz
dB
dB
dB
dB
2500 Hz
3000 Hz
3400 Hz
Table 30: Trans-hybrid Loss
The listed values for THL correspond to a typical variation of the signal amplitude and
delay in the analog blocks.
Amplitude
=typ. ±0.8 dB
=typ. ±0.5 µs
Delay
Semiconductor Group
100
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.5
AC Timing Characteristics
12.5.1 Input/ Output Waveform for AC Tests
2,8
Device
under
Test
2,4
0,8
2,4
0,8
Test Points
= 50pF max
C
Load
0,4
Figure 44 Waveform for AC Tests
12.5.2 Reset Timing
For resetting ALIS to its basic settings mode, negative pulses applied to the RESET pin
have to be lower than 1.5 volts (CMOS Schmitt trigger input) and longer than 180 ns.
Signals shorter than 40 ns are ignored.
12.5.3 Control Interface Timing
C
D
S
C
t
s
u
(
C
S
)
t
c
(
D
C
L
K
)
t
h
d
(
C
S
)
L
K
s
u
(
D
I
N
)
h
d
(
D
I
N
)
t
t
D
D
I
O
N
t
t
p
d
(
D
O
U
T
)
p
d
(
D
)
O
U
T
Z
H
I
I
G
H
.
M
P
U
T
Figure 45 Control Interface Timing
Semiconductor Group
101
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
VDD=VDDA= 5V± 5%; TA= 0 - 70°C
Parameter Symbol
Limit Values
typ
Unit
min
1/1024
45
max
1
Clock cycle time
tc(DCLK)
tsu(CS)
ms
%
Clock duty cycle
50
55
Setup time, CS↓ before
DCLK↓
50
ns
2*tclk1)
Hold time, CS↑ after DCLK↓
thd(CS)
tsu(DIN)
120
60
ns
ns
Setup time, DIN before
DCLK↓
Hold time, DIN after DCLK↓
Delay time, DCLK↑, to DOUT
Delay time, CS↑ to DOUTZ
thd(DIN)
tpd(DOUT)
tpd(DOUTZ)
120
ns
ns
ns
100
100
1) tclk=1/fclk
Table 31: Control Interface Switching Characteristics
12.5.4 Data Interface Timing
c
(
F
S
C
)
t
w
(
F
S
C
)
t
F
D
S
C
t
p
d
(
F
S
C
)
t
c
(
D
A
T
_
C
L
K
)
t
i
d
l
e
(
F
S
C
)
A
T
_
C
L
K
s
u
(
D
A
T
_
I
h
N
d
)
(
D
A
T
_
I
N
)
t
t
D
D
A
A
T
T
_
I
N
t
p
d
(
D
A
T
_
O
U
T
)
O
U
T
Figure 46 Data Interface Timing
Semiconductor Group
102
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
VDD=VDDA= 5V± 5%; TA=0 - 70°C
Parameter
Symbol
Limit Values
Unit
min
typ
max
Data clock cycle time
tc(DAT_CLK)
1/
1/
ms
1024
128
Data clock duty cycle
45
50
55
%
µs
ns
µs
ns
Frame synch clock cycle time
FSC pulse width (as input)
FSC pulse width (as output)1)
tc(FSC)
tw(FSC)
125
488
tw(FSC)
tclk*20
Setup time, DAT_IN before
tsu(DAT_IN)
50
DAT_CLK↓
Hold time, DAT_IN after
DAT_CLK↓
thd(DAT_IN)
100
180
100
ns
ns
Delay time, DAT_CLK↑ to
tpd(DAT_OUT)
DAT_OUT
Idle time, DAT_CLK↓ to FSC↑
Delay time, DAT_CLK↑ to FSC↑
Setup time, FSC↑ to DAT_CLK↓
tidle(FSC)
tpd(FSC)
tsu(FSC)
488
ns
ns
ns
0
tclk+60
1) Guaranteed by design
Table 32: Data Interface Switching Characteristics
Semiconductor Group
103
Data Sheet 06.98
PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
12.5.5 Package Outlines
P-SSOP28
(Plastic Shrink
Small Outline Package)
P-TSSOP24
(Plastic Thin Shrink
Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
104
Data Sheet 06.98
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