Q67000-A9310-A702 [INFINEON]
High Performance Power Combi Controller; 高性能电源控制器Combi机
| 型号： | Q67000-A9310-A702 |
| 厂家： | 
Infineon |
| 描述： | High Performance Power Combi Controller |
| 文件： | 总39页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance Power Combi Controller
TDA 16888
1
Overview
1.1
Features
PFC Section
– IEC 1000-3 compliant
– Additional operation mode as auxiliary power supply
– Fast, soft switching totem pole gate drive (1 A)
– Dual loop control (average current and voltage
sensing)
P-DIP-20-5
– Leading edge triggered pulse width modulation
– Peak current limitation
– Topologies of PFC preconverter are boost or flyback
– Continuous/discontinuous mode possible
– 94% maximum duty cycle
P-DSO-20-1
PWM Section
– Improved current mode control
– Fast, soft switching totem pole gate drive (1 A)
– Soft-start management
– Trailing edge triggered pulse width modulation
– Topologies of PWM converter are feed forward or flyback
– 50% maximum duty cycle to prevent transformer saturation
– fPWM = fPFC
Type
Ordering Code
Package
▼ TDA 16888
▼ TDA 16888G
Q67000-A9284-X201-K5
Q67000-A9310-A702
P-DIP-20-5
P-DSO-20-1
▼ New type
Semiconductor Group
1
Data Sheet 1998-05-06
TDA 16888
Special Features
– High power factor
– Typical 50 µA start-up supply current
– Low quiescent current (15 mA)
– Undervoltage lockout with internal stand-by operation
– Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz
– External synchronization possible
– Shutdown of both outputs externally triggerable
– Peak current limitation
– Overvoltage protection
– Average current sensing by noise filtering
1.2
General Remarks
The TDA 16888 comprises the complete control for power factor controlled switched
mode power supplies. With its PFC and PWM section being internally synchronized, it
applies for off-line converters with input voltages ranging from 90 V to 270 V.
While the preferred topologies of the PFC preconverter are boost or flyback, the PWM
section can be designed as forward or flyback converter. In order to achieve minimal line
current gaps the maximum duty cycle of the PFC is about 94%. The maximum duty cycle
of the PWM, however, is limited to 50% to prevent transformer saturation.
Semiconductor Group
2
Data Sheet 1998-05-06
TDA 16888
P-DIP-20-5
P-DSO-20-1
PFC IAC
VREF
1
2
20
19
18
17
16
15
14
13
12
11
AUX VS
PFC VS
PFC VC
PFC FB
ROSC
PFC CC
PFC CS
GND S
PFC CL
GND
3
1
2
3
4
5
6
7
8
9
10
20
PFC IAC
VREF
AUX VS
PFC VS
PFC VC
PFC FB
ROSC
19
18
17
16
15
14
13
12
11
4
PFC CC
PFC CS
GND S
PFC CL
GND
5
PWM RMP
PWM IN
PWM SS
SYNC
6
PWM RMP
PWM IN
PWM SS
SYNC
7
PFC OUT
VCC
PFC OUT
VCC
8
PWM OUT
PWM CS
9
AEP02486
PWM OUT
10
PWM CS
AEP02461
Figure 1
Pin Configuration (top view)
Semiconductor Group
3
Data Sheet 1998-05-06
TDA 16888
1.3
Pin No.
1
Pin Definitions and Functions
Symbol
PFC IAC
VREF
Function
AC line voltage sensing input
7.5 V reference
2
3
PFC CC
PFC CS
GND S
PFC current loop compensation
PFC current sense
4
5
Ground sensing input
6
PFC CL
GND
Sensing input for PFC current limitation
Ground
7
8
PFC OUT
VCC
PFC driver output
9
Supply voltage
10
11
12
13
14
15
16
17
18
19
20
PWM OUT
PWM CS
SYNC
PWM driver output
PWM current sense
Oscillator synchronization input
PWM soft-start
PWM SS
PWM IN
PWM RMP
ROSC
PWM output voltage sensing input
PWM voltage ramp
Oscillator frequency set-up
PFC voltage loop feedback
PFC voltage loop compensation
PFC output voltage sensing input
Auxiliary power supply voltage sense
PFC FB
PFC VC
PFC VS
AUX VS
Semiconductor Group
4
Data Sheet 1998-05-06
TDA 16888
1.4
Block Diagram
V
V
V
V
V
R
1
R
Ι
V
V
R
Figure 2
Semiconductor Group
5
Data Sheet 1998-05-06
TDA 16888
2
Functional Description
Power Supply
The TDA 16888 is protected against overvoltages typically above 17.5 V by an internal
Zener diode Z3 at pin 9 (VCC) and against electrostatic discharging at any pin by special
ESD circuitry.
By means of its power management the TDA 16888 will switch from internal stand-by,
which is characterized by negligible current consumption, to operation mode as soon as
a supply voltage threshold of 14 V at pin 9 (VCC) is exceeded. To avoid uncontrolled
ringing at switch-over an undervoltage lockout is implemented, which will cause the
power management to switch from operation mode to internal stand-by as soon as the
supply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will
fall below 14 V, operation mode will be maintained as long as the supply voltage is well
above 11 V.
As soon as the supply voltage has stabilized, which is determined by the TDA 16888’s
power management and its soft-start feature at pin 13 (PWM SS), the PWM section will
be enabled by means of its internal bias control.
Protection Circuitry
Both PFC and PWM section are equipped with a fast overvoltage protection (C6)
sensing at pin 19 (PFC VS), which when being activated will immediately shut down both
gate drives. In addition to improve the PFC section’s load regulation it uses a fast but soft
overvoltage protection (OTA2) prior to the one described above, which when being
activated will cause a well controlled throttling of the multiplier output QM.
In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) by
comparator C4 the gate drive of the PWM section will be shut down in order to reduce
the load current and to increase the PFC output voltage. This undervoltage shutdown
has to be prior to the undervoltage lockout of the internal power management and
therefore has to be bound to a threshold voltage at pin 9 (VCC) well above 11 V.
In order to prevent the external circuitry from destruction the PFC output PFC OUT
(pin 8) will immediately be switched off by comparator C2, if the voltage at pin 19
(PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken
to handle a broken wire at any other pin in order to ensure a safe operation of the IC and
its adjoining circuitry.
If necessary both outputs, PFC OUT (pin 8) and PWM OUT (pin 10), can be shutdown
on external request. This is accomplished by shorting the external reference voltage at
pin 2 (VREF) to ground. To protect the external reference, it is equipped with a foldback
characteristic, which will cut down the output current when VREF (pin 2) is shorted (see
Figure 4).
Semiconductor Group
6
Data Sheet 1998-05-06
TDA 16888
Both PFC and PWM section are equipped with a peak current limitation, which is realized
by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS)
respectively. When being activated this current limitation will immediately shut down the
respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10).
Finally each pin is protected against electrostatic discharge.
Oscillator/Synchronization
The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by
the internal oscillator (see Figure 18). The oscillator’s frequency is set by an external
resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding
capacitor, however, is integrated to guarantee a low current consumption and a high
resistance against electromagnetic interferences. In order to ensure superior precision
of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of
a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50%
duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch
before being fed into the PFC and PWM section respectively (see Figure 18).
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge. This ramp has been reversed in contrast to the common practice, in
order to simultaneously allow for current measurement at pin 5 (GND S) and for external
compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC).
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). However, since the oscillator’s frequency is halved before being fed into the
PFC and PWM section, a synchronization frequency being twice the operating frequency
is recommended. As long as the synchronization signal is H the oscillator’s triangular
signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and
Figure 20). However, as soon as the external clock changes from H to L the oscillator is
released. Correspondingly, by means of an external clock signal supplied at pin 12
(SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be
varied on principle only within the range from 0.66 fOSC to 2 fOSC. If the oscillator has to
be synchronized over a wider frequency range, a synchronization by means of the sink
current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12
(SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently
shutdown both PFC and PWM section. It can be used to halt the oscillator freezing the
prevailing state of both drivers but does not allow to automatically shut them down. A
shutdown can be achieved by shorting pin 2 (VREF) to ground, instead.
Finally, In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Semiconductor Group
7
Data Sheet 1998-05-06
TDA 16888
PFC Section
At normal operation the PFC section operates with dual loop control. An inner loop,
which includes OP2, C1, FF1 and the PFC’s driver, controls the shape of the line current
by average current control enabling either continuous or discontinuous operation. By the
outer loop, which is supported by OP1, the multiplier, OP2, C1, FF1 and the PFC's driver,
the PFC output voltage is controlled. Furthermore there is a third control loop composed
of OTA1, OP2, C1, FF1 and the PFC’s driver, which allows the PFC section to be
operated as an auxiliary power supply even when the PWM section is disabled. With
disabled PWM section, however, the PFC section is operated with half of its nominal
operating frequency in order to reduce the overall current consumption.
Based on a pulse-width-modulation, which is leading edge triggered with respect to the
internal clock reference CLK OUT and which is trailing edge modulated according to the
PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), the
PFC section is designed for a maximum duty cycle of ca. 94% to achieve minimal line
current gaps.
PWM Section
The PWM section is equipped with improved current mode control containing effective
slope compensation as well as enhanced spike suppression in contrast to the commonly
used leading edge current blanking. This is achieved by the chain of operational amplifier
OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an external
capacitor, which is connected to pin 15 (PWM RMP). For crosstalk suppression between
PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled
PWM’s is set by operational amplifier OP3 performing a fivefold amplification of the PWM
load current, which is sensed by an external shunt resistor. In order to simultaneously
perform effective slope compensation and to suppress leading spikes, which are due to
parasitic capacitances being discharged whenever the power transistor is switched on,
the resulting signal is subsequently increased by the constant voltage of V1 and finally
fed into the 1st order low pass filter. The peak ramp voltage, that in this way can be
reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following
low pass filter a basic ramp (step response) with a leading notch is created, which will
fully compensate a leading spike (see Figure 12) provided, the external capacitor at
pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly.
Semiconductor Group
8
Data Sheet 1998-05-06
TDA 16888
The pulse-width-modulation of the PWM section is trailing edge modulated according to
the PWM ramp signal VPWM RMP at pin 15 (PWM RMP) and the input voltage VPWM IN at
pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulse-
width-modulation of the PWM section is trailing edge triggered with respect to the
internal clock reference CLK OUT in order to avoid undesirable electromagnetic
interference of both sections. Moreover the maximum duty cycle of the PWM is limited
to 50% to prevent transformer saturation.
By means of the above mentioned improved current mode control a stable pulse-width-
modulation from maximum load down to no load is achieved. Finally, in case of no load
conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to
ground.
Semiconductor Group
9
Data Sheet 1998-05-06
TDA 16888
3
Functional Block Description
Gate Drive
Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and
pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents
and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the
attached power transistors as well as to protect them against undesirable gate
overvoltages. At voltages below the undervoltage lockout threshold these gate drives are
active low. In order to keep the switching losses of the involved power diodes low and to
minimize electromagnetic emissions, both gate drives are optimized for soft switching
operation. This is achieved by a novel slope control of the rising edge at each driver’s
output (see Figure 13).
Oscillator
The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the
internal oscillator. The oscillator’s frequency is set by an external resistor connected to
pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is
integrated to guarantee a low current consumption and a high resistance against
electromagnetic interferences. In order to ensure superior precision of the clock
frequency, the clock signal CLK OSC is derived from the minima and maxima of a
triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock
reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillator’s clock
signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section
respectively.
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge, the latter of which is triggered by the rising edge of the clock
reference CLK OUT. This ramp has been reversed in contrast to the common practice,
in order to simultaneously allow for current measurement at pin 5 (GND S) and for
external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The
slope of the falling edge, which in conjunction with the output of OP2 controls the pulse-
width-modulation of the PFC output signal VPFC OUT, is derived from the current set by the
external resistor at pin 16 (ROSC). In this way a constant amplitude of the ramp signal
(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum
blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output
signal, is determined by an internal current source.
In contrast to the PFC section the ramp signal of the PWM section is trailing edge
triggered with respect to the internal clock reference CLK OUT to avoid undesirable
electromagnetic interference of both sections. Moreover, the maximum duty cycle of the
PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent
transformer saturation.
Semiconductor Group
10
Data Sheet 1998-05-06
TDA 16888
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is
interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However,
as soon as the external clock changes from H to L the oscillator is released.
Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the
oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied on
principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the
falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead
the lower voltage peak is modulated. Consequently, on the one hand at high
synchronization frequencies fSYNC > fOSC the amplitude of the ramp signal and
correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand
at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the
minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which
may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops
below this threshold. However, if the oscillator has to be synchronized over a wide
frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has
to be preferred to a synchronization by means of pin 12 (SYNC).
In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Multiplier
The multiplier serves to provide the controlled current IQM by combination of the shape
of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means
of the 10 kΩ resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18
Chapter
(PFC VC) and the possibility for soft overvoltage protection VM3 (see
Protection Circuitry
). By means of this current the required power factor as well as the
magnitude of the PFC output voltage is ensured. To achieve an excellent performance
over a wide range of output power and input voltage, the input voltage VM2 is amplified
by an exponential function before being fed into the multiplier (see Figure 8).
Voltage Amplifier OP1
Being part of the outer loop the error amplifier OP1 controls the magnitude of the PFC
output voltage by comparison of the PFC output voltage measured at pin 17 (PFC FB)
with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity
from external noise. To allow for individual feedback the output of OP1 is connected to
pin 18 (PFC VC).
Semiconductor Group
11
Data Sheet 1998-05-06
TDA 16888
Current Amplifier OP2
Being part of the inner loop the error amplifier OP2 controls the shape of the line current
by comparison of the controlled current IQM with the measured average line current. This
is achieved by setting the pulse width of the PFC gate drive in conjunction with the
comparator C1. In order to limit the voltage range supplied at pin 4 (PFC CS) and at pin 5
(GND S), clamping diodes D1, D2 and D3 are connected with these pins and ground. To
allow for individual feedback the output of OP2 is connected to pin 3 (PFC CC).
Ramp Amplifier OP3
For crosstalk suppression between PFC and PWM section a signal-to-noise ratio
comparable to voltage mode controlled PWMs is set by operational amplifier OP3
performing a fivefold amplification of the PWM load current, which is sensed by an
external shunt resistor. In order to suppress leading spikes, which are due to parasitic
capacitances being discharged whenever the power transistor is switched on, the
resulting signal is subsequently increased by the constant voltage of V1 and finally fed
into a 1st order low pass filter. By combination of voltage source V1 and the following low
pass filter a step response with a leading notch is created, which will fully compensate a
leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP)
and the external current sensing shunt resistor are scaled properly.
Operational Transconductance Amplifier OTA1
The TDA 16888’s auxiliary power supply mode is controlled by the fast operational
transconductance amplifier OTA1. When under low load or no load conditions a voltage
below 5 V is sensed at pin 20 (AUX VS), it will start to superimpose its output on the
output QM of the multiplier and in this way will replace the error amplifier OP1 and the
multiplier. At normal operation, however, when the voltage at pin 20 (AUX VS) is well
above 5 V, this operational transconductance amplifier is disabled.
Operational Transconductance Amplifier OTA2
By means of the operational transconductance amplifier OTA2 sensing at pin 19
(PFC VS) a fast but soft overvoltage protection of the PFC output voltage is achieved,
which when being activated (VPFC VS > 5.5 V) will cause a well controlled throttling of the
multiplier output QM (see Figure 9).
Operational Transconductance Amplifier OTA3
In order to achieve offset compensation of error amplifier OP2 under low load conditions,
that will not suffice to start OTA1, the operational transconductance amplifier OTA3 is
introduced. It will start operation as soon as these conditions are reached, i.e. the voltage
at pin 18 (PFC VC) falls below 1.2 V.
Semiconductor Group
12
Data Sheet 1998-05-06
TDA 16888
Comparator C1
The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is
achieved by comparison of the output voltage of OP2 given at pin 3 (PFC CC) and the
voltage ramp of the oscillator.
Comparator C2
The comparator C2 serves to prevent the external circuitry from destruction by
immediately switching the PFC output PFC OUT (pin 8) off, if the voltage at pin 19
(PFC VS) drops below 1 V due to a broken wire.
Comparator C3
By means of this extremely fast comparator sensing at pin 6 (PFC CL) peak current
limitation is realized. When being activated (VPFC CL < 1 V) it will immediately shut down
the gate drive of the PFC section (pin 8, PFC OUT). In order to protect C3 against
undervoltages at pin 6 (PFC CL) due to large inrush currents, this pin is equipped with
an additional clamping diode D4.
Comparator C4
This comparator along with the TDA 16888’s power management serves to reset the
PWM section’s soft start at pin 13 (PWM SS). C4 becomes active as soon as an
undervoltage (VPFC VS < 4 V) of the PFC output voltage is sensed at pin 19 (PFC VS).
Comparator C5
Based on the status of the PWM section’s soft start at pin 13 (PWM SS), the comparator
C5 controls the bias of the entire PWM section. In this way the PWM section is switched
off giving a very low quiescent current, until its soft start is released.
Comparator C6
Overvoltage protection of the PWM section’s input voltage sensed at pin 19 (PFC VS) is
realized by comparator C6, which when being activated will immediately shut down both
gate drives PFC OUT (pin 8) and PWM OUT (pin 10).
Comparator C7
This comparator sensing at pin 13 (PWM SS) and at pin 15 (PWM RMP) controls the
pulse width modulation of the PWM section during the soft start. This is done right after
the PWM section is biased by comparator C5.
Semiconductor Group
13
Data Sheet 1998-05-06
TDA 16888
Comparator C8
The control of the pulse width modulation of the PWM section is taken over by
comparator C8 as soon as the soft start is finished. This is achieved by comparison of
the PWM output voltage at pin 14 (PWM IN) and the PWM voltage ramp at pin 15
(PWM RMP).
Comparator C9
By means of this extremely fast comparator sensing at pin 11 (PWM CS) peak current
limitation is realized. When being activated (VPWM CS > 1 V) it will immediately shut down
the gate drive of the PWM section (PWM OUT).
Comparator C10
By means of the threshold of 0.4 V the comparator C10 allows the PWM duty cycle to be
continuously controlled from 0 to 50%. As long as the ramp voltage at pin 15
(PWM RMP) is below this threshold the gate drive of the PWM section (pin 10,
PWM OUT) is turned off.
Semiconductor Group
14
Data Sheet 1998-05-06
TDA 16888
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
TA = – 25 to 85 °C
Parameter#
Symbol Limit Values Unit Remarks
min. max.
VCC supply voltage
VS
– 0.3 VZ3
50
V
VZ3 = Zener voltage of Z3
Zener current of Z3
IZ3
–
mA
V
–
VREF voltage
VVREF
VROSC
VSYNC
VPFC FB
– 0.3 8
– 0.3 8
– 0.3 8
– 0.3 8
V
V
–
–
–
–
VREF < VS
ROSC voltage
V
ROSC < VS
SYNC voltage
V
PFC FB voltage
PFC IAC voltage
AUX VS voltage
PFC VS voltage
PFC CL voltage
PWM SS voltage
PWM IN voltage
PWM RMP voltage
PWM CS voltage
PFC VC voltage
PFC VC current
PFC CS current
GND S current
PFC CC voltage
PFC CC current
V
VPFC IAC – 0.3 15
V
VAUX VS
VPFC VS
VPFC CL
– 0.3 8
– 0.3 8
– 0.3 3
V
V
|IPFC VS| < 1 mA
V
–
VPWM SS – 0.3 8
– 0.3 8
V
V
–
V
–
–
–
–
–
–
–
–
PWM SS < VVREF
VPWM IN
V
VPWM RMP – 0.3 8
VPWM CS – 0.3 3
V
PWM RMP < VVREF
V
VPFC VC
IPFC VC
IPFC CS
IGND S
VPFC CC
IPFC CC
IOUT
– 0.3 8
V
– 20 20
mA
mA
mA
V
– 5
– 5
5
5
– 0.3 8
– 20 20
– 100 100
mA
mA
PFC/PWM OUT DC
current
PFC/PWM OUT peak
clamping current
IOUT
IOUT
TJ
–
200
mA
mA
°C
V
V
–
OUT = High
PFC/PWM OUT peak
clamping current
– 500 –
OUT = Low
Junction temperature
– 40 150
Semiconductor Group
15
Data Sheet 1998-05-06
TDA 16888
4.1
Absolute Maximum Ratings (cont’d)
TA = – 25 to 85 °C
Parameter#
Symbol Limit Values Unit Remarks
min. max.
Storage temperature
Thermal resistance
Thermal resistance
TS
– 65 150
°C
–
RthJA
RthJA
–
–
60
70
K/W
K/W
P-DIP-20-5
P-DSO-20-1
Note: Absolute maximum ratings are defined as ratings, which when being exceeded
may lead to destruction of the integrated circuit. To avoid destruction make sure,
that for any pin except for pins PFC OUT and PWM OUT the currents caused by
transient processes stay well below 100 mA. For the same reason make sure, that
any capacitor that will be connected to pin 9 (VCC) is discharged before
assembling the application circuit. In order to characterize the gate driver’s output
performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided,
instead of referring just to a single parameter like the maximum gate charge or the
maximum output energy.
4.2
Operating Range
Parameter
Symbol Limit Values Unit Remarks
min. max.
VCC supply voltage
VS
IZ3
0
VZ3
50
V
VZ3 = Zener voltage of Z3
Zener current
0
mA
A
Limited by TJ,max
PFC/PWM OUT current IOUT
– 1
0
1.5
1
–
–
–
–
PFC IAC input current
PFC/PWM frequency
Junction temperature
IPFC IAC
mA
kHz
°C
fOUT
TJ
15
– 25
200
125
Note: Within the operating range the IC operates as described in the functional
description. In order to characterize the gate driver’s output performance
Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring
just to a single parameter like the maximum gate charge or the maximum output
energy.
Semiconductor Group
16
Data Sheet 1998-05-06
TDA 16888
4.3
Characteristics
Supply Section
Parameter
Symbol
Limit Values
min. typ. max.
Unit
Test Condition
Zener voltage1)
Zener current
VZ3
IZ3
IS
16.0
–
17.5
–
19.0
500
12
V
IZ3 = 30 mA
VS ≤ 15.5 V2)
µA
mA
Quiescent supply
current
–
–
V
R
PWM SS = 0 V
ROSC = 51 kΩ
CL = 0 V
PFC enabled
PWM disabled
–
–
–
–
15
40
mA
mA
V
R
PWM SS = 6 V
ROSC = 51 kΩ
CL = 0 F
PFC enabled
PWM enabled
Supply current
IS
V
R
PWM SS = 6 V
ROSC = 51 kΩ
CL = 4.7 nF
PFC enabled
PWM enabled
1)
See Figure 3
2)
Design characteristics (not meant for production testing)
Note: The electrical characteristics involve the spread of values guaranteed within the
specified supply voltage and ambient temperature range TA from – 25 °C to 85 °C
Typical values represent the median values, which are related to production
processes. If not otherwise stated, a supply voltage of VS = 15 V is assumed.
Semiconductor Group
17
Data Sheet 1998-05-06
TDA 16888
Undervoltage Lockout
Parameter
Symbol
Limit Values
min. typ. max.
Unit
Test Condition
Power up,
VS,UP
13.0
10.5
–
14.0
11.0
23
14.5
11.5
100
V
–
rising voltage
threshold1)
Power down,
falling voltage
threshold1)
VS,DWN
V
–
Power up,
threshold current
IS,UP
µA
VS = VS,UP – 0.1 V
V
PFC CL < 0.3 V2)
Stand-by mode
1)
See Figure 3
2)
To ensure the voltage fallback of pin PFC CL is disabled.
Internal Voltage Reference
Parameter
Symbol
Limit Values
Unit
Test Condition
min. typ.
max.
Trimmed reference
voltage
VREF
4.9
5.0
5.1
V
Measured at
pin PFC VC
Line regulation
∆VREF
–
–
40
mV
∆VS = 3 V
Semiconductor Group
18
Data Sheet 1998-05-06
TDA 16888
External Voltage Reference
Parameter
Symbol
Limit Values
min. typ. max.
Unit
Test Condition
Buffered output voltage VVREF
7.2
–
7.5
–
7.8
50
V
– 3 mA ≤ IVREF ≤ 0
∆VS = 3 V
Line regulation
Load regulation
∆VVREF
∆VVREF
IVREF
mV
mV
mA
0
40
– 6
100
– 4
∆IVREF = 2 mA
Maximum output
current1)
– 10
V
VREF = 6.5 V
Short circuit current1)
IVREF
–
–
– 2
6.6
–
–
mA
V
V
VREF = 0 V
Shutdown hysteresis,
rising voltage threshold
VVREF
–
Shutdown hysteresis,
falling voltage threshold
VVREF
–
–
6.2
–
–
V
–
Shutdown delay
td,VREF
500
ns
V
V
V
VREF = 5 V2)3)
PFC OUT = 3 V2)3)
PWM OUT = 3 V2)3)
1)
See Figure 4
2)
Design characteristics (not meant for production testing)
Transient reference value
3)
Oscillator
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ.
max.
57
PFC/PWM frequency1)
PFC/PWM frequency1)
fOUT50
fOUT100
∆fOUT
43
87
–
50
100
–
kHz
kHz
%
R
R
ROSC = 110 kΩ
ROSC = 51 kΩ
113
1
PFC/PWM frequency,
line regulation
∆VS = 3 V
R
–
–
–
–
V
V
ROSC = 51 kΩ
Maximum ramp voltage VPFC RMP 5.0
Minimum ramp voltage VPFC RMP 0.8
5.4
1.1
–
5.6
1.4
0.4
V
V
V
SYNC, low level voltage VSYNC
SYNC, high level voltage VSYNC
–
3.5
–
–
–
–
VVREF
20
V
SYNC, input current
ISYNC
µA
µA
SYNC < 0.4 V
SYNC = 3.5 V
–
150
1)
See Figure 5
Semiconductor Group
19
Data Sheet 1998-05-06
TDA 16888
PFC Section
Parameter
Symbol
Limit Values
min. typ. max.
98
Unit Test Condition
Max duty cycle1)
Don,PFC 91
94
%
V
V
R
PFC OUT = 2 V3)
ROSC = 51 kΩ
CL = 4.7 nF
Multiplier throttling
(OTA2), threshold
voltage2)
VPFC VS 5.2
5.5
5.8
0.9 IPFC CS
IPFC IAC = 100 µA
V
PFC VC = 6 V
OTA1 disabled
Overvoltage protection
(C6), rising voltage
threshold
VPFC VS 5.8
6
6.2
V
–
Overvoltage protection
(C6), falling voltage
threshold
VPFC VS 5.3
5.5
5.7
V
–
Overvoltage protection
(C6), turn-off delay
td,OV
VPFC VS 0.93
IPFC VS 0.2
VPFC CL 0.93
IPFC CL
–
2
1
–
µs
V
V
V
PFC VS = 6.5 V3)4)
PFC OUT = 3 V3)4)
Broken wire detection
(C2), threshold voltage
1.07
–
V
–
Voltage sense, input
current
0.45 0.7
µA
V
PFC VS = 1 V
Current limitation (C3),
threshold voltage
1
–
1.07
10
Current limitation (C3),
input current
1
µA
V
PFC CL = 1 V
Current limitation (C3,
D4), clamping voltage
VPFC CL – 0.9 –
30
– 0.1 V
150 ns
IPFC CL = – 500 µA
Current limitation (C3),
turn-off delay
td,CL
–
V
V
PFC CL = 0.75 V3)
PFC OUT = 3 V3)
CL = 4.7 nF
1)
See Figure 6
2)
See Figure 9
3)
Transient reference value
4)
Design characteristics (not meant for production testing)
Semiconductor Group
20
Data Sheet 1998-05-06
TDA 16888
Multiplier
Parameter
Symbol
Limit Values
min. typ. max.
Unit
Test Condition
Input current
IPFC IAC
VPFC VC
VPFC VC
0
0
–
–
1
mA
V
–
Input voltage
–
6.7
–
–
1)2)
Exponential function,
threshold voltage
1.1
V
Maximum output current IPFC CS
– 320 – 420 – 550 µA
OTA1 disabled
Output current3)
IPFC CS
–
–
–
–
–
–
– 100 – 500 nA
I
V
PFC IAC = 0 A
PFC VC = 2 V
OTA1 disabled
PFC IAC = 25 µA
PFC VC = 2 V
OTA1 disabled
PFC IAC = 25 µA
PFC VC = 4 V
OTA1 disabled
PFC IAC = 100 µA
PFC VC = 4 V
OTA1 disabled
PFC IAC = 400 µA
PFC VC = 4 V
OTA1 disabled
PFC IAC = 100 µA
PFC VC = 6 V
OTA1 disabled
– 1.2
– 10
– 40
–
–
–
µA
µA
µA
µA
µA
I
V
I
V
I
V
– 150 –
– 170 –
I
V
I
V
1)
Design characteristics (not meant for production testing)
2)
For input voltages below this threshold the multiplier output current remains constant. For input voltages above
this threshold the output rises exponentially (see Figure 8).
3)
See Figure 7
Semiconductor Group
21
Data Sheet 1998-05-06
TDA 16888
Operational Transconductance Amplifier (OTA1)
Parameter Symbol Limit Values
min. typ. max.
Unit
Test Condition
Auxiliary power supply, VAUX VS
4.8
5.0
5.2
V
I
PFC CS = – 1 µA
threshold voltage1)
Multiplier disabled
Input current
IAUX VS
–
–
15
µA
µA
V
AUX VS > 5.2 V
AUX VS < 4.8 V
–
– 20
V
–
–
–
Output current
IPFC CS
–
–
0
µA
µA
V
V
AUX VS > 5.2 V1)
AUX VS < 4.8 V
– 30
1)
For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum
output current is reached.
Operational Transconductance Amplifier (OTA3)
Parameter
Symbol
Limit Values
min. typ. max.
Unit
Test Condition
Offset compensation,
threshold voltage
VPFC VC 1.1
1.2
–
V
–
1)
Input current
IPFC VC
IGND S
– 1
–
–
–
–
–
µA
µA
µA
Output current
0
V
PFC VC > 1.2 V
PFC VC < 1.1 V
–
– 10
V
1)
Design characteristics (not meant for production testing)
Semiconductor Group
22
Data Sheet 1998-05-06
TDA 16888
Voltage Amplifier (OP1)
Parameter
Symbol
Limit Values
min. typ. max.
Unit Test Condition
1)
Offset voltage
Input current
VOff
– 4
– 1
–
–
4
mV
µA
dB
V
IPFC FB
APFC VC
VPFC FB
–
1
V
2)
PFC FB = 4 V
Open loop gain
Input voltage range
85
–
–
0
6
–
–
Voltage sense,
threshold voltage
VPFC FB 4.9
VPFC VC 6.3
VPFC VC 0.5
5
5.1
V
Output, maximum
voltage
–
VVREF
1.1
–
V
I
PFC VC = – 500 µA
PFC VC = 500 µA
Output, minimum
voltage
–
V
I
Output, short circuit
source current
IPFC VC
–
–
– 10
10
mA
mA
V
V
PFC VC = 0 V
PFC FB = 4.9 V
Output, short circuit sink IPFC VC
–
V
PFC VC = 6.4 V
PFC FB = 5.1 V
current
V
1)
Guaranteed by wafer test
2)
Design characteristics (not meant for production testing)
Semiconductor Group
23
Data Sheet 1998-05-06
TDA 16888
Current Amplifier (OP2)
Parameter
Symbol
Limit Values
min. typ. max.
– 5 – 1
– 500 –
Unit Test Condition
Offset voltage
VOff
3
mV
nA
–
–
Input current
IPFC CS
IGND S
500
Open loop gain
APFC CC
–
–
–
110
–
dB
MHz
°
–
1)
Gain bandwidth product fT
Phase margin
2.5
60
–
1)
1)
–
ϕ
Common mode voltage VCMVR
– 0.2 –
0.5
V
range
Clamped input voltage, VPFC CS 0.4
–
1.0
V
I
I
PFC CS = 500 µA
GND S = 500 µA
upper threshold
VGND S
(D2, D3)
Multiplier, OTA1
and OTA3 disabled
Clamped input voltage, VPFC CS – 0.9 –
– 0.1 V
IPFC CS = – 500 µA
lower threshold (D1)
Multiplier and OTA1
disabled
Output, maximum
voltage
VPFC CC 6.3
VPFC CC 0.5
–
VVREF
1.1
–
V
I
PFC CC = – 500 µA
PFC CC = 500 µA
Output, minimum
voltage
–
V
I
Output, short circuit
source current
IPFC CC
–
–
– 10
mA
V
V
V
PFC CC = 0 V
PFC CS = 0 V
GND S = 0.5 V
Output, short circuit sink IPFC CC
current
10
–
mA
V
V
V
PFC CC = 6.5 V
PFC CS = 0.5 V
GND S = 0 V
1)
Design characteristics (not meant for production testing)
Semiconductor Group
24
Data Sheet 1998-05-06
TDA 16888
PWM Section
Parameter
Symbol
Limit Values
min. typ. max.
4.2
Unit Test Condition
Undervoltage protection (C4), VPFC VS 3.8
threshold voltage
4.0
0.45
0.4
30
V
V
V
–
–
–
Bias control (C5),
rising voltage threshold
VBC,Th
VBC,Th
II1
–
–
Bias control (C5),
falling voltage threshold
–
–
Softstart (I1),
20
40
µA –
charging current
Softstart, maximum voltage VPWM SS
–
6.7
–
–
V
V
–
–
Input voltage
VPWM IN 0.4
7.4
150
–
PWM IN – GND resistance
Ramp (OP3), voltage gain
R3
75
–
100
5
kΩ –
AOP3
VRMP
V/V –
Ramp (C10), pulse start
threshold voltage
0.36 0.4
0.5
V
–
Ramp, maximum voltage
VRMP
VV1
–
–
–
6.5
1.5
10
–
–
–
V
V
–
–
Ramp (V1), voltage offset
Ramp (R1),
ZRMP
kΩ –
output impedance
Maximum duty cycle
Don,PWM 41
–
50
%
V
R
PWM OUT = 2 V1)
ROSC = 51 kΩ
CL = 4.7 nF
Current sense (C9),
voltage threshold
VCS,Th 0.9
td,CS 30
1.0
–
1.1
V
–
Current sense (C9),
overload turn-off delay
250
ns
V
V
PWM CS = 1.25 V1)
PWM OUT = 3 V1)
CL = 4.7 nF
1)
Transient reference value
Semiconductor Group
25
Data Sheet 1998-05-06
TDA 16888
Gate Drive (PWM and PFC Section)
Parameter
Symbol
Limit Values
min. typ. max.
Unit Test Condition
Output, minimum
voltage
VOUT
–
–
1.2
V
V
VS = 5 V
OUT = 5 mA
VS = 5 V
I
–
–
1.5
I
I
I
I
OUT = 20 mA
–
–
0.8
1.6
–
V
V
V
V
OUT = 0 A
2.0
–
OUT = 50 mA
OUT = – 50 mA
– 0.2 0.2
10 11
Output, maximum
voltage
VOUT
12
VS = 16 V
tH = 10 µs
CL = 4.7 nF
10.0 10.5
–
–
V
V
VS = 12 V
tH = 10 µs
CL = 4.7 nF
8.8
–
VS = VS,DWN + 0.2 V
tH = 10 µs
CL = 4.7 nF
Rise time1)
Fall time
tr
–
150
100
30
40
–
–
ns
ns
ns
ns
A
V
OUT = 2 V … 8 V2)
CL = 4.7 nF
OUT = 3 V … 6 V2)
CL = 4.7 nF
OUT = 9 V … 3 V2)
CL = 4.7 nF
OUT = 9 V … 2 V2)
–
–
V
tf
–
–
V
–
–
V
CL = 4.7 nF
CL = 4.7 nF4)
Output current, rising
edge3)
IOUT
– 1
–
–
Output current, falling IOUT
–
1.5
A
CL = 4.7 nF4)
edge3)
1)
See Figure 13
2)
Transient reference value
3)
The gate driver’s output performance is characterized in Figure 14, Figure 15, Figure 16 and Figure 17.
4)
Design characteristics (not meant for production testing)
Semiconductor Group
26
Data Sheet 1998-05-06
TDA 16888
Note: If not otherwise stated the figures shown in this section represent typical
performance characteristics.
AED02462
Ι VCC
Ι S
Ι S, UP
VS, DWN
VS, UP
VZ3
VVCC
Figure 3
Undervoltage Lockout Hysteresis and Zener Diode Overvoltage
Protection
AED02463
-8
mA
-7
Ι VREF
-6
-5
-4
-3
-2
-1
0
0
1
2
3
4
5
6
7
V
8
VVREF
Figure 4
Foldback Characteristic of Pin 2 (VREF)
Semiconductor Group
27
Data Sheet 1998-05-06
TDA 16888
AED02464
400
kHz
fOUT
100
10
10
100
500
kΩ
ROSC
Figure 5
PFC/PWM Frequency
AED02465
100
%
Don, PFC, max
95
90
85
80
0
100
200
300
kΩ 400
ROSC
Figure 6
Maximum PFC Duty Cycle
Semiconductor Group
28
Data Sheet 1998-05-06
TDA 16888
AED02466
500
µ
A
VPFC VC = 7 V
Ι PFC CCS
400
300
200
100
0
6 V
5 V
4 V
3 V
2 V
0
0.2
0.4
0.6
0.8
mA
1
Ι PFC IAC
Figure 7
Multiplier Linearity
AED02356
500
µ
A
Ι PFC CCS
Ι PFC IAC = 800
µ
µ
µ
µ
µ
µ
A
400
300
200
100
0
400
200
100
50
A
A
A
A
A
25
0
1
2
3
4
5
6
V
7
VPFC VC
Figure 8
Multiplier Dynamic
Semiconductor Group
29
Data Sheet 1998-05-06
TDA 16888
AED02467
500
µ
A
Ι PFC IAC > 300
µ
A
VPFC VC = 6 V
Ι PFC CCS
400
300
200
250
200
µ
µ
A
A
150
100
µ
µ
A
A
50
µ
A
100
0
5.0
5.25
5.5
5.75
V 6.0
VPFC VS
Figure 9
Multiplier Throttling by OTA2
AED02468
100
dB
APFC VC
0
deg
φ
80
60
40
-30
-60
-90
φ
APFC VC
20
0
-120
-150
10-2
10-1
100
101
102
103
104
105
106 Hz 107
Frequency
Figure 10
Open Loop Gain and Phase Characteristic of Voltage Amplifier OP1
Semiconductor Group
30
Data Sheet 1998-05-06
TDA 16888
AED02469
120
dB
0
deg
APFC CC
φ
100
-30
φ
APFC CC
80
-60
60
-90
40
-120
20
0
-150
-180
10-2
10-1
100
101
102
103
104
105
106 Hz 107
Frequency
Figure 11
Open Loop Gain and Phase Characteristic of Current Amplifier OP2
AED02470
V1
VPWM CS
V1 /2
0
4V1
VPWM RMP
VPWMCS = 0
3V1
2V1
V1
0
0
T/2
T
Time
Figure 12
PWM Ramp Composition Scheme
Semiconductor Group
31
Data Sheet 1998-05-06
TDA 16888
AED02471
12
V
VPFC OUT
10
8
6
4
2
0
0
0.1
0.2
0.3
µs 0.4
Time
Figure 13
Rising Edge of Driver Output
AED02542
150
R L = 0
R L = 1
R L = 2
R L = 5
Ω
Ω
Ω
Ω
mW
PD
R L = 10
Ω
100
50
0
f OUT = 15 kHz
PD0 = 0.194 W
0
10
20
30
40
nF
50
C L
Figure 14
Power Dissipation of Single Gate Driver at fOUT = 15 kHz
Semiconductor Group
32
Data Sheet 1998-05-06
TDA 16888
AED02543
500
mW
R L = 0
R L = 1
R L = 2
R L = 5
Ω
Ω
Ω
Ω
PD
400
300
200
100
0
R L = 10
Ω
f OUT = 50 kHz
PD0 = 0.197 W
0
10
20
30
40
nF
50
C L
Figure 15
Power Dissipation of Single Gate Driver at fOUT = 50 kHz
AED02544
1
R L = 0
R L = 1
R L = 2
R L = 5
Ω
Ω
Ω
Ω
mW
PD
0.8
R L = 10
Ω
0.6
0.4
0.2
0
f OUT = 100 kHz
PD0 = 0.201 W
0
10
20
30
40
nF
50
C L
Figure 16
Power Dissipation of Single Gate Driver at fOUT = 100 kHz
Semiconductor Group
33
Data Sheet 1998-05-06
TDA 16888
AED02545
1.5
R L = 0
R L = 1
R L = 2
R L = 5
Ω
Ω
Ω
Ω
mW
PD
R L = 10
Ω
1.0
0.5
0
f OUT = 200 kHz
PD0 = 0.212 W
0
10
20
30
40
nF
50
C L
Figure 17
Power Dissipation of Single Gate Driver at fOUT = 200 kHz
Semiconductor Group
34
Data Sheet 1998-05-06
TDA 16888
VOSC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
VPWM RMP
VPWM OUT
t on, max
VPWM IN
VBC, Th
t on, max
Time
AET02546
Figure 18
Timing Diagram without Synchronization
Semiconductor Group
35
Data Sheet 1998-05-06
TDA 16888
VOSC
VSYNC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
VPWM RMP
VPWM OUT
t on, max
VPWM IN
VBC, Th
t on, max
Time
AET02547
Figure 19
Timing Diagram with Synchronization (fSYNC > fOSC)
Semiconductor Group
36
Data Sheet 1998-05-06
TDA 16888
VOSC
VSYNC
CLK OSC
CLK OUT
VPFC RMP
VPFC CC
VPFC OUT
VPWM RMP
VPWM OUT
t on, max
VPWM IN
VBC, Th
t on, max
Time
AET02548
Figure 20
Timing Diagram with Synchronization (fSYNC < fOSC)
Semiconductor Group
37
Data Sheet 1998-05-06
TDA 16888
5
Package Outlines
P-DIP-20-5
(Plastic Dual In-line Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
38
Data Sheet 1998-05-06
TDA 16888
P-DSO-20-1
(Plastic Dual Small Outline)
0.35 x 45˚
1)
7.6 -0.2
+0.09
0.23
8˚ max
0.4 +0.8
10.3 ±0.3
1.27
0.35 +0.152)
0.1
0.2 24x
11
20
1
GPS05094
10
1)
12.8-0.2
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
39
Data Sheet 1998-05-06
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