Q67007-A9690 [INFINEON]
Dual Low Drop Voltage Regulator; 双路低压差稳压器
| 型号： | Q67007-A9690 |
| 厂家： | 
Infineon |
| 描述： | Dual Low Drop Voltage Regulator |
| 文件： | 总21页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Low Drop Voltage Regulator
TLE 7469
Features
•
Dual output
5 V (±2%), 320mA and 2.6 V1) (±4%), 300mA or
5 V (±2%), 320mA and 3.3 V (±3%), 300mA
Ultra low quiescent current consumption < 55 µA
Inhibit function
•
•
•
•
•
•
•
•
•
•
•
•
P-DSO-12-4, -5
Very low dropout voltage
Reset with power-on delay
Early Warning comparator
Window watchdog
Power sequencing for dual voltage µC
Output protected against short circuit
Wide operation range: up to 45 V
Wide temperature range: -40 °C to 150 °C
Overtemperature protection
Overload protection
Functional Description
The TLE 7469 is a monolithic integrated voltage regulator with two voltage outputs
specially designed to supply microcontrollers with dual supply voltage: 2.6 V1) or 3.3 V
core and 5 V I/O voltage like the Infineon XC164 and XC161.
1) 2.5 V nominal specification range of most µCs is compatible with the 2.6 V output voltage range of the
TLE 7469.
Type
Ordering Code
Q67007-A9689
Q67007-A9690
Package
TLE 7469 GV52
TLE 7469 GV53
P-DSO-12-4
P-DSO-12-4
Final Data Sheet
1
Rev. 1.3, 2004-10-28
TLE 7469
The voltage regulator features an integrated reset circuitry which monitors the 2.6 V/
3.3 V supply voltage. At power on the reset checks both supply voltages and performs
the power-on reset with an adjustable delay time. The voltage difference is kept in the
range -0.5 V < (VQ1 - VQ2) < 3.0 V even during power-on and power-down time enabling
save µC operation without external clamping. Using the integrated early warning
comparator an external voltage can be supervised. An integrated output sink current
circuitry keeps the voltage at the Q1 pin below 5.5 V even when reverse currents are
applied. Thus connected devices are protected from overvoltage damage. The regulator
can be shut down via the Inhibit input causing the current consumption to drop below
9 µA.
The TLE 7469 is designed for use under the severe conditions of automotive
applications, and is therefore equipped with protection functions against overload, short
circuit and overtemperature. It operates in the wide junction temperature range from
-40 °C to 150 °C and offers the low quiescent current consumption required for body
applications.
For applications requiring extremely low noise levels the Infineon voltage regulator family
TLE 42XY and TLE 44XY is more suited than the TLE 7469. A mV-range output noise
on the TLE 7469 caused by the charge pump operation is unavoidable due to the ultra
low quiescent current concept.
Final Data Sheet
2
Rev. 1.3, 2004-10-28
TLE 7469
TLE 7469
12
10
I2
Q2
Overtemperature
Shutdown
Reset
Generator
and
Window
Watchdog
9
5
RO
WDI
Bandgap
Reference
1
7
DT
Charge
Pump
8
2
1
4
3
Early
Warning
SI
INH
I1
SO
Q1
Inhibit
Overtemperature
Shutdown
1
Charge
Pump
GND
11
AEB03530_1.VSD
Figure 1
Block Diagram
Final Data Sheet
3
Rev. 1.3, 2004-10-28
TLE 7469
t
P-DSO-12-4
I1
IN H
Q 1
I2
1
2
3
4
5
6
12
11
10
9
G N D
Q 2
S O
R O
S I
W D I
G N D
8
D T
7
A E P 03531.V S D
Figure 2
Table 1
Pin Configuration (top view)
Pin Definitions and Functions
Pin No. Symb. Function
1
I1
Input voltage 1; block to ground directly at the IC with a 100 nF
ceramic capacitor
2
3
INH
Q1
Inhibit Input; low level disables the IC. Integrated pull-down resistor
Output voltage 1; 5.0 V, block to GND with a capacitor
CQ1 ≥ 1 µF, ESR < 6 Ω at 10 kHz
4
SO
Sense output; Output of Early Warning Comparator, open collector
output
5
WDI
GND
DT
Watchdog Input; Trigger Input for Watchdog pulses
6, 11
7
Ground; Pin 6, 11 and heat slug must be connected to GND
DT Delay timing; connect to GND, Q1 or Q2 to select Reset and
Watchdog timing
8
9
SI
Sense input; Input for Early Warning comparator
RO
Reset output; open collector output with integrated 20 kΩ pull-up
resistor
10
12
Q2
I2
Output voltage 2; 2.6 V (TLE 7469 GV52), 3.3 V (TLE 7469 GV53);
block to GND with a capacitor CQ2 ≥ 1 µF, ESR < 6 Ω at 10 kHz
Input voltage 2; block to ground directly at the IC with a 100 nF
ceramic capacitor
Final Data Sheet
4
Rev. 1.3, 2004-10-28
TLE 7469
Table 2
Absolute Maximum Ratings
-40 °C < Tj < 150 °C
Parameter
Symbol Limit Values Unit
Remarks
Min.
Max.
Input I1
Voltage
VI1
II1
-0.3
–
45
–
V
–
Current
mA
Internally limited
Input I2
Voltage
VI2
II2
-0.3
–
45
–
V
–
Current
mA
Internally limited
Output Q1
Voltage
VQ1
VQ1
IQ1
-0.3
-0.3
–
5.5
6.2
2
V
Permanent
t < 10 s1)
Voltage
V
Current
mA
Internally limited
Output Q2
Voltage
VQ2
VQ2
IQ2
-0.3
-0.3
–
5.5
6.2
–
V
Permanent
t < 10 s1)
Voltage
V
Current
mA
Internally limited
Inhibit Input INH
Voltage
VINH
IINH
-0.3
-1
45
1
V
Observe current limit
IINHmax
2)
Current
mA
–
Reset Output RO
Voltage
VRO
VRO
IRO
-0.3
-0.3
–
5.5
6.2
–
V
Permanent
t < 10 s1)
Voltage
V
Current
mA
internally limited
Delay Timing DT
Voltage
VDT
VDT
IDT
-0.3
-0.3
-5
5.5
6.2
5
V
Permanent
t < 10 s1)
–
Voltage
V
Current
mA
Final Data Sheet
5
Rev. 1.3, 2004-10-28
TLE 7469
Table 2
Absolute Maximum Ratings (cont’d)
-40 °C < Tj < 150 °C
Parameter
Symbol Limit Values Unit
Remarks
Min.
Max.
Watchdog Input WDI
Voltage
VWDI
VWDI
IWDI
-0.3
-0.3
–
5.5
6.2
–
V
Permanent
t < 10 s1)
Voltage
V
Current
mA
internally limited
Sense Input SI
Voltage
VSI
ISI
-0.3
-1
45
1
V
Observe current limit
ISImax
2)
Current
mA
–
Sense Output SO
Voltage
VSO
VSO
ISO
-0.3
-0.3
–
5.5
6.2
–
V
Permanent
t < 10 s1)
Voltage
V
Current
mA
internally limited
Temperatures
Junction temperature
Storage temperature
Tj
–
150
150
°C
°C
–
–
Tstg
-50
1) Exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability.
2) External resistor required to keep current below absolute maximum rating when voltages ≥ 5.5 V are applied.
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit. Integrated protection functions
are designed to prevent IC destruction under fault conditions. Fault conditions are
considered as outside normal operating range. Protections functions are not
designed for continuous repetitive operation.
Final Data Sheet
6
Rev. 1.3, 2004-10-28
TLE 7469
Table 3
Operating Range
Parameter
Symbol Limit Values Unit
Remarks
Min.
5.6
6.0
4.2
-40
Max.
45
Input voltage
Input voltage
Input voltage
VI1
VI2
VI2
V
–
45
V
VI1 > 8V
VI1 < 8V
–
45
V
Junction temperature
Thermal Resistances P-DSO-12-4
Tj
150
°C
Junction case
Rthjc
–
–
–
4.4
107
58
K/W
K/W
K/W
–
Junction ambient
Junction ambient
Rthj-a
Rthj-a
PCB, only Footprint1)
PCB Heat Sink Area
300 mm2 1)
Junction ambient
Rthj-a
–
48
K/W
PCB Heat Sink Area
600 mm2 1)
1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; zero airflow; 85 °C ambient temperature.
Note: In the operating range the functions given in the circuit description are fulfilled.
Final Data Sheet
7
Rev. 1.3, 2004-10-28
TLE 7469
Table 4
Electrical Characteristics
VI1 = 13.5 V; VI2 = 13.5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Output Q1
Output voltage
VQ1
IQ1
4.90 5.0
5.10
700
600
V
1 mA < IQ1 < 215 mA,
6 V < VI1 < 16 V
Output current
limitation
320
–
–
mA
mV
VQ1 = 4.0 V
Output drop voltage; VDRQ1
DRQ1 = VI1 - VQ1
300
I
Q1 = 215 mA1)
V
Load regulation
Line regulation
∆VQ1,Lo
∆VQ1,Li
–
–
25
20
60
50
mV
mV
1 mA < IQ1 < 215 mA
Q1 = 1 mA,
I
10 V < VI < 28 V
Power Supply Ripple PSRR
Rejection
–
–
60
–
–
dB
V
fr = 100 Hz,
Vr = 1 Vpp
Reverse Output
VQ,REV
5.5
IQ,REV = 1 mA,
Current Protection
VINH = 0 V
Output Q2
Output voltage
VQ2
2.50 2.60 2.70
3.20 3.30 3.40
V
V
1 mA < IQ2 < 200 mA,
6 V < VI2 < 16 V,
TLE 7469 GV52
Output voltage
VQ2
1 mA < IQ2 < 200 mA,
6 V < VI2 < 16 V,
TLE 7469 GV53
Absolute differential
voltage
V
Q1 - VQ2 -0.5
–
–
3.0
V
VQ1, VQ2 > 1 V
Output current
limitation
IQ2
300
500
mA
VQ2 = 2.0 V
Load regulation
Line regulation
∆VQ2,Lo
∆VQ22,Li
–
–
25
20
60
50
mV
mV
1 mA < IQ2 < 200 mA
Q2 = 1 mA,
I
10 V < VI < 28 V
Power Supply Ripple PSRR
Rejection
–
60
–
dB
fr = 100 Hz,
Vr = 1 Vpp
Final Data Sheet
8
Rev. 1.3, 2004-10-28
TLE 7469
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VI2 = 13.5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Current Consumption
Quiescent current;
Iq = II1 + II2 - IQ1 - IQ2
Iq
–
–
–
5
55
9
µA
µA
I
Q2 = IQ1 = 100 µA,
Tj < 80 °C
INH = 0 V,
Tj < 80 °C
Quiescent current;
inhibited
Iq
V
Inhibit Input INH
Turn-on Voltage
Turn-off Voltage
H-input current
L-input current
VINH ON
–
–
3.1
–
V
V
V
V
V
Q1 & VQ2 on
Q1 & VQ2 off
INH = 5 V
VINH OFF 0.8
–
V
IINH ON
–
–
3
4
µA
µA
IINH OFF
0.5
1
INH = 0 V, Tj < 80 °C
Delay Timing DT
Threshold Fast
Timing Select
VDT,FAST 4.5
VDT,SLOW 2.3
VDT,SLOW 2.3
–
–
–
–
–
V
V
V
V
–
Threshold Slow
Timing Select
3.3
3.6
0.8
TLE 7469 GV52
TLE 7469 GV53
–
Threshold Slow
Timing Select
Threshold Watchdog VDT,OFF
–
Turn Off2)
Watchdog Input WDI
H-input voltage
threshold
VWDIH
VWDIL
–
–
–
–
3.0
0.8
V
V
–
–
L-input voltage
threshold
Watchdog sampling tsam
time
0.20 0.25 0.30 ms
0.80 1.00 1.20 ms
25.6 32.0 38.4 ms
Fast Timing
Slow Timing
Fast Timing
Slow Timing
Fast Timing
Slow Timing
Ignore window time tOW
102 128
25.6 32.0 38.4 ms
102 128 154 ms
154
ms
Open window time
Final Data Sheet
tOW
9
Rev. 1.3, 2004-10-28
TLE 7469
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VI2 = 13.5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Closed window time tCW
25.6 32.0 38.4 ms
102 128 154 ms
39.0 44.8 50.6 ms
Fast Timing
Slow Timing
Fast Timing
Slow Timing
Window watchdog
trigger time
tWD
156 179
202
ms
Reset Output RO
Reset switching
threshold 2
VRT2
2.35 2.38 2.48
V
TLE 7469 GV52,
Q2 decreasing
V
Reset Headroom 2
VRH2
VRT2
130 190
mV
V
TLE 7469 GV52
Reset switching
threshold 2
3.00 3.07 3.15
TLE 7469 GV53,
VQ2 decreasing
Reset Headroom 2
Reset hysteresis 2
VRH2
VRH2
165 240
mV
mV
mV
V
TLE 7469 GV53
TLE 7469 GV52 3)
TLE 7469 GV53 4)
–
–
45
60
–
–
Reset switching
threshold 1
VRT1
4.50 4.65 4.80
VQ1 decreasing
Reset hysteresis 1
Reset sink current
VRH1
IRO
–
–
–
90
–
–
1
mV
mA
V
–
VQ = 5 V, VRO = 0.5 V
Reset output low
voltage
VROL
0.15 0.25
V
Q2 ≥ 1 V
Reset high voltage
VROH
4.5
10
–
–
V
–
Integrated reset pull- RRO
20
40
kΩ
Internally connected to
Q1
up resistor
Power-up Reset
delay time
TRD
6.0
8.0
10.0 ms
Fast Timing
(VDT ≥ 4.5 V)
24.0 32.0 40
10 26
ms
Slow Timing
(VDT ≤ 3.3 V)
Reset Reaction Time TRR
–
µs
–
Final Data Sheet
10
Rev. 1.3, 2004-10-28
TLE 7469
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VI2 = 13.5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Input Voltage Sense
Sense threshold high VSIH
1.10 1.16 1.22
1.06 1.12 1.18
V
V
V
VSI increasing (see
Figure 4)
Sense threshold low VSIL
VSI decreasing (see
Figure 4)
Sense output low
voltage
VSOL
–
0.1
–
0.4
–
VSI < 1.01 V;
VI1 > 4.20 V;
ISO = 0.5 mA
External SO pull-up RSO ext
9.2
kΩ
VQ1 = 5V
resistor
Sense input current ISI
-1
–
0.1
4.0
1
–
µA
µs
VSI = 5 V
Sense high reaction tpd SO LH
–
time
Sense low reaction tpd SO HL
–
4.0
–
µs
–
time
1) Measured when the output voltage has dropped 100 mV from the nominal Value obtained at VI1 = 13.5 V,
I2 = 13.5 V.
V
2) Watchdog off, Reset in slow mode.
3) Specified by design, not subject of production test.
4) Specified by design, not subject of production test.
Final Data Sheet
11
Rev. 1.3, 2004-10-28
TLE 7469
Application Information
RVi
*
VBat
TLE 7469
I2
Q2
DT
47
µF
47
µF
100 nF
100 k
1 µF
INH
SI
WDI
RO
SO
e. g.
Ignition
Key
XC 164
10 k
I1
Q1
GND
47
µF
100 nF
1 µF
= Optional
AEA03529_2.VSD
Figure 3
Application Diagram with Typical External Components
A typical application of the TLE 7469 is shown in Figure 3. To prevent the regulation
loop from oscillating a ceramic capacitor of CQ1/2 ≥ 1 µF is required at each of the outputs
Q1 and Q2. In contrast to most low drop voltage regulators the TLE 7469 only needs
moderate capacitance at the outputs and tolerates ceramic capacitors to keep the
stability. This offers more design flexibility to the circuit designer enabling also to operate
the device without tantalum capacitors.
Additional a capacitor CB of 10 … 47 µF should be used for each output Q1 and Q2 to
suppress influences from load surges to the voltage levels. This one can either be an
aluminum electrolytic capacitor or a tantalum capacitor following the application
requirements.
General recommendation at Tj<90°C is to keep the drop over the equivalent serial
resistor (ESR) together with the discharge of the blocking capacitor below 300mV.
Since the regulator output current roughly rises linearly with time the discharge of the
capacitor can be calculated as:
dVCB = dIQ*dt/CB
Final Data Sheet
12
Rev. 1.3, 2004-10-28
TLE 7469
The drop across the ESR calculates as:
DVESR = DI*ESR (5.2)
To prevent a reset the following relationship must be fullfilled:
DVC + DVESR < 300mV (5.3)
Example: let us assume we have a load current change of 100mA and a blocking
capacitor of 22µF.
DVC = 0.1A * 25µs/22µF = 114mV
So for the ESR we can allow
DVESR = 300mV - 114mV = 186mV
The permissible ESR becomes:
ESR = 186mV/100mA = 1.86Ohm
As a dual regulator the TLE 7469 for correct operation should be always supplied at both
input pins I1 and I2 out of one voltage supply. The dual voltage regulator with both inputs
accessible, offers the possibility to reduce the power dissipation in the package. This can
be achived by two different input voltages or a Drop Resistor* RVi (see Figure 3) at the
input pin I2 for the 2.6V output. If one of this options is chosen,care should be taken, to
apply the device as descibet under “Table 3: Operating Range”.
The reset output RO features an integrated pull-up resistor. Thus it can be directly
coupled to the microcontroller reset input.
The sense comparator output SO is an open collector. An appropriate external pull-up
resistor is typ. 5.6 kΩ … 47 kΩ, the minimum value of 5.6 kΩ being defined by the max.
sink current capability of the SO output transistor. If the sense comparator is not used of
course the pull-up resistor can be spared. In this case the SI pin should be directly
connected to Q1 in order to keep the comparator inactive.
Final Data Sheet
13
Rev. 1.3, 2004-10-28
TLE 7469
Sense
Input
Voltage
VSIH
VSIL
t
Sense
Output
t PD SO LH
t PD SO HL
High
Low
t
AED02559_7469
Figure 4
Sense Timing Diagram
Final Data Sheet
14
Rev. 1.3, 2004-10-28
TLE 7469
Circuit Description
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed.
When the level of VQ2 reaches the reset threshold VRT, the signal at RO remains LOW
for the Power-up reset delay time TRD. Then a second comparator checks whether
V
Q1 ≥ VRT1 and only if this test is passed the reset output is switched to HIGH. The Reset
output is only released (set to High level) if both output voltages have passed their
specific reset threshold VRT1/2. The reset function and timing is illustrated in Figure 5.
The reset reaction time TRR avoids wrong triggering caused by short “glitches” on the
VQ2-line. For power-fail, in case of VQ2 or VQ1 power down (VQ2 < VRT2 or VQ1 < VRT1 for
t > TRR) a logic LOW signal is generated at the pin RO to reset an external
microcontroller.
Final Data Sheet
15
Rev. 1.3, 2004-10-28
TLE 7469
V I
t
t
t
V Q 1
V R T 1
V Q 2
V R T 2
T R R
T R R
T R D
T R D
T R D
V R O
V R O H
V R O L
t
A E T 0 3 5 3 2 .V S D
Figure 5
Reset Function and Timing Diagram
Watchdog Operation
The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase.
Connecting the DT pin to Q1 or to Q2 the watchdog timebase can be adjusted. The
watchdog can be turned off by a low level (VDT ≤ 0.8 V) applied to the DT pin. The timing
values used in this text refer to typ. values with DT connected to Q1 (fast timing).
Figure 6 shows the state diagram of the window watchdog (WWD). After power-on, the
reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay
time TRD of typ. 8 ms. With the LOW to HIGH transition of the signal at RO the device
starts the ignore window time tCW (32 ms). During this window the signal at the WDI pin
is ignored. Next the WWD starts the open window. When a valid trigger signal is detected
during the open window a closed window is initialized immediately. A trigger signal within
Final Data Sheet
16
Rev. 1.3, 2004-10-28
TLE 7469
the closed window is interpreted as a pretrigger failure and results in a reset. After the
closed window the open window with the duration tOW is started again. The open window
lasts at minimum until the trigger process has occurred, at maximum tOW is 32 ms (typ.
value with fast timing).
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger.
To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two
LOW samples (sample period tsam typ. 0.25 ms) are decoded as a valid trigger (see
Figure 7). A reset is generated (RO goes LOW) if there is no trigger pulse during the
open window or if a pretrigger occurs during the closed window. The triggering is correct
also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are
inside the closed window and only the fourth sample (the second LOW sample) is taken
in the open window.
A lw ays
Ignore
R eset
W indow
Trigger D uring
C losed W indow
N o Trigger D uring
O pen W indow
A lw ays
Trigger
C losed
W indow
O pen
W indow
N o Trigger
AEA03533.VSD
Figure 6
Window Watchdog State Diagram
Final Data Sheet
17
Rev. 1.3, 2004-10-28
TLE 7469
Watchdog
trigger signal
Closed window
Open window
Open window
Closed window
WDI
WDI
WDI
Valid
Indifferent
Not valid
tECW
= Watchdog decoder sample point
tEOW
AET02952
Figure 7
Window Watchdog Definitions
Final Data Sheet
18
Rev. 1.3, 2004-10-28
TLE 7469
Package Outlines
1)
±0.1
7.5
B
±0.15
0.7
0.1
±0.1
7.8
±0.3
10.3
(Heatslug)
0.25 B
+0.13
7.6
Bottom View
-0.1
7
1)
±0.1
6.4
(Mold)
B
7
12
12
1
6
1
6
Index Marking
Heatslug
1
0.4+0.13
12x
0.25 C A B
±0.1
5.1
(Metal)
M
5 x 1 = 5
1) Does not include plastic or metal protrusion of 0.15 max. per side
GPS09628
Figure 8
P-DSO-12-4 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Final Data Sheet
19
Rev. 1.3, 2004-10-28
TLE 7469
Revision History:
2004-10-28
Rev. 1.3
Previous Version:
1.21
status final both products
Template: central_tmplt_a5.fm / 5 / 2003-04-01
Edition 2004-10-28
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
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相关型号：
Q67007A9397A702
Buffer/Inverter Based Peripheral Driver, 4A, PDSO36, GREEN, PLASTIC, 36 PIN
INFINEON
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