S25FL127SABBHBC03_技术文档

S25FL127S

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Features

• CMOS 3.0 V core

• Density

- 128 Mb (16 MB)

• SPI with multi-I/O

- SPI clock polarity and phase modes 0 and 3

- Extended addressing: 24- or 32-bit address options

- Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families

- Multi I/O command set and footprint compatible with S25FL-P SPI family

• READ commands

- Normal, Fast, Dual, Quad

- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected

address

- Common flash interface (CFI) data for configuration information.

• Programming (0.8 MBps)

- 256- or 512-byte page programming buffer options

- Quad-input page programming (QPP) for slow clock systems

- Automatic ECC -internal hardware error correction code generation with single bit error correction

• Erase (0.5 MBps)

- Hybrid sector size option - physical set of sixteen 4-KB sectors at top or bottom of address space with all

remaining sectors of 64 KB

- Uniform sector option - always erase 256-KB blocks for software compatibility with higher density and future

devices.

• Cycling endurance

- 100,000 program-erase cycles per sector, minimum

• Data retention

- 20 year data retention, minimum

• Security features

- One-time programmable (OTP) array of 1024 bytes

- Block protection:

• Status Register bits to control protection against program or erase of a contiguous range of sectors.

• Hardware and software control options

- Advance sector protection (ASP)

• Individual sector protection controlled by boot code or password

• 65-nm MIRRORBIT™ technology with Eclipse architecture

• Supply voltage: 2.7 V to 3.6 V

• Temperature range:

- Industrial (–40°C to +85°C)

- Industrial Plus (–40°C to +105°C)

- Automotive AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive AEC-Q100 grade 2 (–40°C to +105°C)

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Performance summary

• Packages (all Pb-free)

- 8-lead SOIC (208 mil)

- 16-lead SOIC (300 mil)

- 8-contact WSON 6 x 5 mm

- BGA-24 6 x 8 mm

• 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options

- Known good die (KGD) and known tested die

Performance summary

Maximum read rates

Command

Clock rate (MHz)

MBps

6.25

13.5

27

Read

50

Fast Read

Dual Read

Quad Read

108

54

Typical program and erase rates

Operation

Page programming (256-byte page buffer)

Page programming (512-byte page buffer)

4-KB physical sector erase (hybrid sector option)

64-KB physical sector erase (hybrid sector option)

256-KB logical sector erase (uniform sector option)

KBps

650

800

30

500

Current consumption

Operation

Serial read 50 MHz

Serial read 108 MHz

Quad read 108 MHz

Program

Current (mA)

16 (max)

24 (max)

47 (max)

50 (max)

0.07 (typ)

Erase

Standby

Datasheet

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001-98282 Rev. *K

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Table of contents

Features ...........................................................................................................................................1

Performance summary ......................................................................................................................2

Table of contents...............................................................................................................................3

1 Overview .......................................................................................................................................5

1.1 General description ................................................................................................................................................5

1.2 Migration notes .......................................................................................................................................................5

2 SPI with multiple input / output (SPI-MIO) ........................................................................................9

3 Signal descriptions .......................................................................................................................10

3.1 Input/output summary.........................................................................................................................................10

3.2 Address and data configuration...........................................................................................................................11

3.3 Hardware Reset (RESET#).....................................................................................................................................11

3.4 Serial Clock (SCK)..................................................................................................................................................11

3.5 Chip Select (CS#)...................................................................................................................................................11

3.6 Serial Input (SI) / IO0.............................................................................................................................................12

3.7 Serial Output (SO) / IO1 ........................................................................................................................................12

3.8 Write Protect (WP#) / IO2......................................................................................................................................12

3.9 Hold (HOLD#) / IO3 / RESET#................................................................................................................................12

3.10 Voltage Supply (V_CC) ...........................................................................................................................................13

3.11 Supply and Signal Ground (V_SS) .........................................................................................................................13

3.12 Not Connected (NC) ............................................................................................................................................13

3.13 Reserved for Future Use (RFU) ...........................................................................................................................14

3.14 Do Not Use (DNU)................................................................................................................................................14

3.15 Block diagrams ...................................................................................................................................................14

4 Signal protocols............................................................................................................................16

4.1 SPI clock modes ....................................................................................................................................................16

4.2 Command protocol...............................................................................................................................................17

4.3 Interface states .....................................................................................................................................................21

4.4 Configuration register effects on the interface ...................................................................................................27

4.5 Data protection.....................................................................................................................................................27

5 Electrical specifications.................................................................................................................28

5.1 Absolute maximum ratings ..................................................................................................................................28

5.2 Thermal resistance ...............................................................................................................................................28

5.3 Operating ranges ..................................................................................................................................................29

5.4 Power-up and power-down..................................................................................................................................30

5.5 DC characteristics .................................................................................................................................................31

6 Timing specifications ....................................................................................................................33

6.1 Key to switching waveforms.................................................................................................................................33

6.2 AC test conditions .................................................................................................................................................34

6.3 Reset ......................................................................................................................................................................35

6.4 AC characteristics..................................................................................................................................................39

7 Physical interface .........................................................................................................................43

7.1 SOIC 8-lead package.............................................................................................................................................43

7.2 SOIC 16-lead package...........................................................................................................................................45

7.3 WSON 6 x 5 package..............................................................................................................................................47

7.4 FAB024 24-ball BGA package................................................................................................................................49

7.5 FAC024 24-ball BGA package................................................................................................................................51

8 Address space maps ......................................................................................................................53

8.1 Overview................................................................................................................................................................53

8.2 Flash memory array ..............................................................................................................................................54

8.3 ID-CFI address space.............................................................................................................................................54

8.4 JEDEC JESD216B serial flash discoverable parameters (SFDP) space...............................................................55

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Table of contents

8.5 OTP address space................................................................................................................................................55

8.6 Registers................................................................................................................................................................57

9 Data protection ............................................................................................................................69

9.1 Secure silicon region (OTP) ..................................................................................................................................69

9.2 Write Enable command ........................................................................................................................................69

9.3 Block protection ...................................................................................................................................................70

9.4 Advanced sector protection .................................................................................................................................71

10 Commands .................................................................................................................................76

10.1 Command set summary .....................................................................................................................................77

10.2 Identification commands ...................................................................................................................................84

10.3 Register Access commands ................................................................................................................................87

10.4 Read memory array commands.........................................................................................................................99

10.5 Program Flash Array commands......................................................................................................................108

10.6 Erase Flash Array commands ...........................................................................................................................113

10.7 One Time Program Array commands...............................................................................................................119

10.8 Advanced Sector Protection commands.........................................................................................................120

10.9 Reset commands ..............................................................................................................................................127

10.10 Embedded algorithm performance tables ....................................................................................................128

11 Data integrity ........................................................................................................................... 130

11.1 Erase endurance ...............................................................................................................................................130

11.2 Data retention ...................................................................................................................................................130

12 Software interface reference ..................................................................................................... 131

12.1 Command summary .........................................................................................................................................131

13 Serial flash discoverable parameters (SFDP) address map............................................................ 133

13.1 SFDP header field definitions...........................................................................................................................134

13.2 Device ID and Common Flash Interface (ID-CFI) address map .......................................................................137

13.3 Device ID and Common Flash Interface (ID-CFI) ASO Map — Automotive Only.............................................162

13.4 Registers............................................................................................................................................................163

13.5 Initial delivery state ..........................................................................................................................................167

14 Ordering information ................................................................................................................ 168

14.1 Valid combinations ...........................................................................................................................................169

14.2 Valid combinations — automotive grade / AEC-Q100.....................................................................................169

Revision history ............................................................................................................................ 170

Datasheet

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001-98282 Rev. *K

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1

Overview

1.1

General description

The S25FL127S device is a flash non-volatile memory product using:

• MIRRORBIT™ technology - that stores two data bits in each memory array transistor

• Eclipse architecture - that dramatically improves program and erase performance

• 65-nm process lithography

This device connects to a host system via an SPI. Traditional SPI single bit serial input and output (Single I/O or

SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands.

This multiple width interface is called SPI multi-I/O or MIO.

The Eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or

256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase

than prior generation SPI program or erase algorithms.

Executing code directly from flash memory is often called eXecute-in-Place (XIP). By using FL-S devices at the

higher clock rates supported, with QIO command, the instruction read transfer rate can match or exceed

traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.

The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a

variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.

1.2

Migration notes

1.2.1

Features comparison

The S25FL127S device is command set and footprint compatible with prior generation FL-K, FL-P, and FL-S family

devices.

Table 1

FL generations comparison

FL-K

Parameter

FL-P

90-nm

MIRRORBIT™

FL-S

65-nm

FL127S

65-nm

Technology Node

Architecture

90-nm

Floating Gate

MIRRORBIT™ Eclipse MIRRORBIT™ Eclipse

128 Mb, 256 Mb,

Density

4 Mb–128 Mb

x1, x2, x4

32 Mb–256 Mb

x1, x2, x4

128 Mb

512 Mb, 1 Gb

Bus Width

Supply Voltage

x1, x2, x4

2.7V - 3.6V / 1.65V - 3.6V

V_IO

x1, x2, x4

2.7V - 3.6V

Normal Read

Speed (SDR)

Fast Read Speed

(SDR)

Dual Read Speed

(SDR)

6 MBps (50 MHz)

5 MBps (40 MHz)

6 MBps (50 MHz)

17 MBps (133 MHz)

26 MBps (104 MHz)

6 MBps (50 MHz)

13.5 MBps (108 MHz)

27 MBps (108 MHz)

13 MBps (104 MHz) 13 MBps (104 MHz)

26 MBps (104 MHz) 20 MBps (80 MHz)

Notes

1. 256B program page option only for 128 Mb and 256-Mb density FL-S devices.

2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density). FL128P does not support MIO, OTP or

4-KB sectors.

3. 64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.

4. FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.

5. Refer to individual datasheets for further details.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

Table 1

FL generations comparison (Continued)

FL-K FL-P

52 MBps (104 MHz) 40 MBps (80 MHz)

Parameter

Quad Read Speed

(SDR)

FL-S

FL127S

52 MBps (104 MHz)

54 MBps (108 MHz)

Fast Read Speed

(DDR)

Dual Read Speed

(DDR)

Quad Read Speed

(DDR)

Program Buffer

Size

Uniform Sector

Size

Parameter Sector

Size

Number of

Parameter Sector

–

16 MBps (66 MHz)

33 MBps (66 MHz)

66 MBps (66 MHz)

256B / 512B

–

256B

–

256B

4 KB

N/A

0

256B / 512B

64 KB / 256 KB

4 KB (option)

16 (option)

64 KB / 256 KB

4 KB

64 KB / 256 KB

4 KB (option)

32

32 (option)

30 KBps (4 KB),

500 KBps

(64 KB / 256 KB)

30 KBps (4 KB),

500 KBps

(64 KB / 256 KB)

Sector Erase Rate

(typ.)

135 KBps (4 KB),

435 KBps (64 KB)

130 KBps (64 KB)

Page Programming

Rate (typ.)

1000 KBps (256B),

1500 KBps (512B)

650 KBps (256B),

800 KBps (512B)

365 KBps (256B)

170 KBps (256B)

OTP

Advanced Sector

Protection

Auto Boot Mode

Erase

Suspend/Resume

768B (3 x 256B)

506B

No

1024B

No

Yes

No

Yes

No

Yes

Program Suspend/

Resume

Yes

No

Yes

Operating

Temperature

–40 °C to +85 °C /

+105 °C

–40 °C to +85 °C /

+105 °C

–40 °C to +85 °C /

+105 °C

–40 °C to +85 °C

Notes

1. 256B program page option only for 128 Mb and 256-Mb density FL-S devices.

2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density). FL128P does not support MIO, OTP or

4-KB sectors.

3. 64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.

4. FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.

5. Refer to individual datasheets for further details.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1.2.2

Known differences from prior generations

Error reporting

1.2.2.1

Prior generation FL memories either do not have error status bits or do not set them if program or erase is

attempted on a protected sector. The FL-S family does have error reporting status bits for program and erase

operations. These can be set when there is an internal failure to program or erase or when there is an attempt to

program or erase a protected sector. In either case the program or erase operation did not complete as requested

by the command.

1.2.2.2

Secure silicon region (OTP)

The size and format (address map) of the one time program area is different from prior generations. The method

for protecting each portion of the OTP area is different. For additional details see “Secure silicon region (OTP)”

on page 69.

1.2.2.3

Configuration Register Freeze Bit

The Configuration Register Freeze Bit CR1[0], locks the state of the Block Protection bits as in prior generations.

In the FL-S family it also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and

the secure silicon region (OTP) area.

1.2.2.4

Sector architecture

The FL127S has sixteen 4-KB sectors that may be located at the top or bottom of address space. Other members

of the FL-S family and FL-P family have thirty two 4-KB sectors that may be located at the top or bottom of address

space.

These smaller parameter sectors may also be removed, leaving all sectors uniform in size, depending on the

selected configuration (SR2[7]).

1.2.2.5

Sector Erase commands

The command for erasing an 8-KB area (two 4-KB sectors) is not supported.

The command for erasing a 4-KB sector is supported only for use on the 4-KB parameter sectors at the top or

bottom of the device address space. The 4-KB erase command will only erase the parameter sectors.

The erase command for 64-KB sectors is supported when the configuration option for 4-KB parameter sectors

with 64-KB uniform sectors is used. The 64-KB erase command may be applied to erase a group of sixteen 4-KB

sectors.

The erase command for a 256-KB sector replaces the 64-KB erase command when the configuration option for

256-KB uniform sectors is used.

1.2.2.6

Deep power down

The Deep power down (DPD) function is not supported in FL-S family devices.

The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the

former DPD command, to access a new bank address register. The bank address register allows SPI memory

controllers that do not support more than 24 bits of address, the ability to provide higher order address bits for

commands, as needed to access the larger address space of the 256-Mb and 512-Mb density FL-S devices. For

additional information see “Extended address” on page 53.

1.2.2.7

Hardware reset

A separate hardware reset input is provided in packages with greater than 8 connections. In 8-connection

packages, a new option is provided to replace the HOLD# / IO3 input with an IO3 / RESET# input to allow for

hardware reset in small packages.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1.2.2.8

New features

The FL-S family introduces several new features to SPI category memories:

• Extended address for access to higher memory density.

• AutoBoot for simpler access to boot code following power up.

• Enhanced high performance read commands using mode bits to eliminate the overhead of SIO instructions

when repeating the same type of read command.

• Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock

rate read commands.

• Automatic ECC for enhanced data integrity.

• Advanced sector protection for individually controlling the protection of each sector. This is very similar to the

advanced sector protection feature found in several other parallel interface NOR memory families.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

SPI with multiple input / output (SPI-MIO)

2

SPI with multiple input / output (SPI-MIO)

Many memory devices connect to their host system with separate parallel control, address, and data signals that

require a large number of signal connections and larger package size. The large number of connections increase

power consumption due to so many signals switching and the larger package increases cost.

The S25FL-S family of devices reduces the number of signals for connection to the host system by serially

transferring all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory

package, reduces signal switching power, and either reduces the host connection count or frees host connectors

for use in providing other features.

The S25FL-S family of devices uses the industry standard single bit serial peripheral interface (SPI) and also

supports optional extension commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple

width interface is called SPI multi-I/O or SPI-MIO.

Datasheet

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001-98282 Rev. *K

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

3

Signal descriptions

3.1

Input/output summary

Table 2

Signal list

Type

Signal name

Description

Hardware Reset. The signal has an internal pull-up resistor and should be left

unconnected in the host system if not used.

RESET#

Input

SCK

CS#

SI / IO0

SO / IO1

Input

I/O

Serial Clock.

Chip Select.

Serial Input for single bit data commands or IO0 for Dual or Quad commands.

Serial Output for single bit data commands. IO1 for Dual or Quad commands.

I/O

Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an

internal pull-up resistor and may be left unconnected in the host system if not

used for Quad commands.

Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O

mode. RESET# when enabled by SR2[5] = 1 and not in Quad I/O mode,

CR1[1] = 0. or when CS# is HIGH. The signal has an internal pull-up resistor and

may be left unconnected in the host system if not used for Quad commands.

WP# / IO2

I/O

HOLD# / IO3

or IO3 /

RESET#

V_CC

V_SS

Supply

Power Supply.

Ground.

Not Connected. No device internal signal is connected to the package

connector nor is there any future plan to use the connector for a signal. The

connection may safely be used for routing space for a signal on a printed circuit

board (PCB). However, any signal connected to an NC must not have voltage

NC

Unused

levels higher than V_CC

.

Reserved for Future Use. No device internal signal is currently connected to

the package connector but there is potential future use of the connector for a

RFU

Reserved signal. It is recommended to not use RFU connectors for PCB routing channels

so that the PCB may take advantage of future enhanced features in compatible

footprint devices.

Do Not Use. A device internal signal may be connected to the package

connector. The connection may be used by Infineon for test or other purposes

and is not intended for connection to any host system signal. Any DNU signal

Reserved related function will be inactive when the signal is at V_IL. The signal has an

internal pull-down resistor and may be left unconnected in the host system or

may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to this connection.

DNU

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

3.2

Address and data configuration

Traditional SPI single bit wide commands (single or SIO) send information from the host to the memory only on

the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.

Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will

be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and

IO3.

Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0

and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on

IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

3.3

Hardware Reset (RESET#)

The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a

command. When RESET# is driven to logic LOW (V_IL) for at least a period of t_RP, the device:

• terminates any operation in progress,

• tristates all outputs,

• resets the volatile bits in the Configuration Register,

• resets the volatile bits in the Status Registers,

• resets the Bank Address Register to 0,

• loads the Program Buffer with all 1s,

• reloads all internal configuration information necessary to bring the device to standby mode,

• and resets the internal Control Unit to standby state.

RESET# causes the same initialization process as is performed when power comes up and requires t_PUtime.

RESET# may be asserted LOW at any time. To ensure data integrity any operation that was interrupted by a

hardware reset should be reinitiated once the device is ready to accept a command sequence.

When RESET# is first asserted LOW, the device draws I_CC1(50 MHz value) during t_PU. If RESET# continues to be

held at V_SSthe device draws CMOS standby current (I_SB).

RESET# has an internal pull-up resistor and should be left unconnected in the host system if not used.

The RESET# input is not available on all packages options. When not available the RESET# input of the device is

tied to the inactive state, inside the package.

3.4

Serial Clock (SCK)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data

input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK.

3.5

Chip Select (CS#)

The chip select signal indicates when a command for the device is in process and the other signals are relevant

for the memory device. When the CS# signal is at the logic HIGH state, the device is not selected and all input

signals are ignored and all output signals are high impedance. Unless an internal program, erase or write registers

(WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input

to logic LOW state enables the device, placing it in the Active Power mode. After power-up, a falling edge on CS#

is required prior to the start of any command.

CS# toggle with no CLK and data is considered as non-valid. The flash should not be selected (CS# LOW with no

CLK and data) when it’s not being addressed. This is considered as a spec violation and can eventually cause the

device to remain in busy state (SR1 = 0x03) after an embedded operation (program/erase/and so on).

Datasheet

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001-98282 Rev. *K

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

3.6

Serial Input (SI) / IO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to

be programmed. Values are latched on the rising edge of serial SCK clock signal.

SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and

data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on

the falling edge of SCK).

3.7

Serial Output (SO) / IO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the

serial SCK clock signal.

SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be

programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling

edge of SCK.

3.8

Write Protect (WP#) / IO2

When WP# is driven LOW (V_IL), during a WRR command and while the Status Register Write Disable (SRWD) bit of

the Status Register is set to a 1, it is not possible to write to the Status and Configuration Registers. This prevents

any alteration of the Block Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a consequence, all

the data bytes in the memory area that are protected by the Block Protect and TBPROT bits, are also hardware

protected against data modification if WP# is LOW during a WRR command.

The WP# function is not available when the Quad mode is enabled (CR[1] = 1). The WP# function is replaced by

IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are

latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK).

WP# has an internal pull-up resistor; when unconnected, WP# is at V_IHand may be left unconnected in the host

system if not used for Quad mode.

3.9

Hold (HOLD#) / IO3 / RESET#

The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the

device or stopping the serial clock. The HOLD# input and function is available when enabled by a configuration

bit SR2[5] = 0.

To enter the Hold condition, the device must be selected by driving the CS# input to the logic LOW state. It is

recommended that the user keep the CS# input LOW state during the entire duration of the Hold condition. This

is to ensure that the state of the interface logic remains unchanged from the moment of entering the Hold

condition. If the CS# input is driven to the logic HIGH state while the device is in the Hold condition, the interface

logic of the device will be reset. To restart communication with the device, it is necessary to drive HOLD# to the

logic HIGH state while driving the CS# signal into the logic LOW state. This prevents the device from going back

into the Hold condition.

The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with SCK

being at the logic LOW state. If the falling edge does not coincide with the SCK signal being at the logic LOW state,

the Hold condition starts whenever the SCK signal reaches the logic LOW state. Taking the HOLD# signal to the

logic LOW state does not terminate any write, program or erase operation that is currently in progress.

During the Hold condition, SO is in high impedance and both the SI and SCK input are Don’t Care.

The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK

signal being at the logic LOW state. If the rising edge does not coincide with the SCK signal being at the logic LOW

state, the Hold condition ends whenever the SCK signal reaches the logic LOW state.

The HOLD# function is not available when the Quad mode is enabled (CR1[1] = 1). The Hold function is replaced

by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed (values are

latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK.

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Signal descriptions

A configuration bit SR2[5] may be set to 1 to replace the HOLD# / IO3 functions with the IO3 / RESET# functions.

Then the IO3 / RESET# may be used to initiate the hardware reset function. The IO3 / RESET# input is only treated

as RESET# when the device is not in Quad-I/O mode, CR1[1] = 0, or when CS# is HIGH.

When Quad I/O mode is in use, CR1[1] = 1, and the device is selected with CS# LOW, the IO3 / RESET# is used only

as IO3 for information transfer. When CS# is HIGH, the IO3 / RESET# is not in use for information transfer and is

used as the RESET# input. By conditioning the reset operation on CS# HIGH during Quad mode, the reset function

remains available during Quad mode.

When the system enters a reset condition, the CS# signal must be driven HIGH as part of the reset process and

the IO3 / RESET# signal is driven LOW. When CS# goes HIGH, the IO3 / RESET# input transitions from being IO3 to

being the RESET# input. The reset condition is then detected when CS# remains HIGH and the IO3 / RESET# signal

remains LOW for t_RP

.

The HOLD#/IO3 or IO3/RESET# signals have an internal pull-up resistor and may be left unconnected in the host

system if not used for Quad mode or the reset function.

When Quad mode is enabled, IO3 / RESET# is ignored for t_CSfollowing CS# going HIGH. This allows some time for

the memory or host system to actively drive IO3 / RESET# to a valid level following the end of a transfer. Following

the end of a Quad I/O read, the memory will actively drive IO3 HIGH before disabling the output during t_DIS

.

Following a transfer in which IO3 was used to transfer data to the memory, e.g. the QPP command, the host

system is responsible for driving IO3 HIGH before disabling the host IO3 output. This will ensure that IO3 / Reset

is not left floating or being pulled slowly to HIGH by the internal or an external passive pull-up. Thus, an

unintended reset is not triggered by the IO3 / RESET# not being recognized as HIGH before the end of t_RP. Once

IO3 / RESET# is HIGH, the memory or host system can stop driving the signal. The integrated pull-up on IO3 will

then hold IO3 HIGH unless the host system actively drives IO3 / RESET# to initiate a reset.

Note that IO3 / Reset# cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad

I/O mode as IO3 being driven to or from one selected memory may look like a reset signal to a second not selected

memory sharing the same IO3 / RESET# signal (see “IO3 / RESET# input initiated hardware (warm) reset” on

page 37 for the IO3 / RESET timing).

CS#

SCLK

HOLD#

Hold Condition

Standard Use

Hold Condition

Non-standard Use

SI_or_IO_(during_input)

SO_or_IO_(internal)

SO_or_IO_(external)

Valid Input

Don't Care

B

Valid Input

C

Don't Care

D

Valid Input

A

E

B

C

D

E

Figure 1

HOLD mode operation

3.10

Voltage Supply (V_CC)

V_CCis the voltage source for all device internal logic. It is the single voltage used for all device internal functions

including read, program, and erase. The voltage may vary from 2.7 V to 3.6 V.

3.11

Supply and Signal Ground (V_SS)

V_SSis the common voltage drain and ground reference for the device core, input signal receivers, and output

drivers.

3.12

Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector

for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).

However, any signal connected to an NC must not have voltage levels higher than V_CC

.

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Signal descriptions

3.13

Reserved for Future Use (RFU)

No device internal signal is currently connected to the package connector but is there potential future use of the

connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take

advantage of future enhanced features in compatible footprint devices.

3.14

Do Not Use (DNU)

A device internal signal may be connected to the package connector. The connection may be used by Cypress for

test or other purposes and is not intended for connection to any host system signal. Any DNU signal related

function will be inactive when the signal is at V_IL. The signal has an internal pull-down resistor and may be left

unconnected in the host system or may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to these connections.

3.15

Block diagrams

Reset#

WP#

SI

WP#

SI

SO

SCK

CS2#

CS1#

SPI

Bus Master

FL127S

Flash

FL127S

Flash

Figure 2

Bus master and memory devices on the SPI bus - single bit data path

Reset#

WP#

IO1

WP#

IO1

IO0

SCK

CS2#

CS1#

SPI

Bus Master

FL127S

Flash

FL127S

Flash

Figure 3

Bus master and memory devices on the SPI bus - dual bit data path

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Signal descriptions

Reset#

IO3

IO2

Reset#

IO3

IO2

IO1

IO0

IO1

IO0

SCK

CS2#

CS1#

SPI

Bus Master

FL127S

Flash

FL127S

Flash

Figure 4

Bus master and memory devices on the SPI bus - quad bit data path

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Signal protocols

4

Signal protocols

SPI clock modes

4.1

4.1.1

Single data rate (SDR)

The S25FL-S family of devices can be driven by an embedded microcontroller (bus master) in either of the two

following clocking modes.

• Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

• Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the

output data is always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not

transferring any data.

• SCK will stay at logic LOW state with CPOL = 0, CPHA = 0

• SCK will stay at logic HIGH state with CPOL = 1, CPHA = 1

CPOL=0_CPHA=0_SCLK

CPOL=1_CPHA=1_SCLK

CS#

SI

MSB

SO

MSB

Figure 5

SPI Modes Supported

Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by

showing SCK as both HIGH and LOW at the fall of CS#. In some cases a timing diagram may show only Mode 0 with

SCK LOW at the fall of CS#. In this case, Mode 3 timing simply means clock is HIGH at the fall of CS# so no SCK

rising edge set up or hold time to the falling edge of CS# is needed for Mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0, the

beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of

SCK because SCK is already LOW at the beginning of a command.

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Signal protocols

4.2

Command protocol

All communication between the host system and S25FL-S family of memory devices is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to

the host serially on the SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be

returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or,

four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1

or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Commands are structured as follows:

• Each command begins with CS# going LOW and ends with CS# returning HIGH. The memory device is selected

by the host driving the Chip Select (CS#) signal LOW throughout a command.

• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.

• Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a single

bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK

rising edge. The instruction selects the type of information transfer or device operation to be performed.

• The instruction may be standalone or may be followed by address bits to select a byte location within one of

several address spaces in the device. The instruction determines the address space used. The address may be

either a 24-bit or a 32-bit address. The address transfers occur on SCK rising edge.

• The width of all transfers following the instruction are determined by the instruction sent. Following transfers

may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit

groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on

the IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0. More significant bits are

placed in significance order on each higher numbered IO signal. Single bits or parallel bit groups are transferred

in most to least significant bit order.

• Some instructions send an instruction modifier called mode bits, following the address, to indicate that the

next command will be of the same type with an implied, rather than an explicit, instruction. The next command

thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to

send each command when the same command type is repeated in a sequence of commands. The mode bit

transfers occur on SCK rising edge.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Write data bit transfers occur on SCK rising edge.

• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles

(also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from

the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered

transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising

edge.

• If the command returns read data to the host, the device continues sending data transfers until the host takes

the CS# signal HIGH. The CS# signal can be driven HIGH after any transfer in the read data sequence. This will

terminate the command.

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Signal protocols

• At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must go

HIGH after the eighth bit, of a standalone instruction or, of the last write data byte that is transferred. That is,

the CS# signal must be driven HIGH when the number of clock cycles after CS# signal was driven LOW is an exact

multiple of eight cycles. If the CS# signal does not go HIGH exactly at the eight SCK cycle boundary of the

instruction or write data, the command is rejected and not executed.

• All instruction, address, and mode bits are shifted into the device with the Most Significant bits (MSb) first. The

data bits are shifted in and out of the device MSb first. All data is transferred in byte units with the lowest address

byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address

increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

4.2.1

Command sequence examples

CS#

SCK

SI

SO

Phase

Instruction

Figure 6

Standalone Instruction command

CS#

SCK

SI

SO

Instruction

Input Data

Phase

Figure 7

Single Bit Wide Input command

CS#

SCK

SI

SO

Phase

Data 2

Instruction

Data 1

Figure 8

Single Bit Wide Output command

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Signal protocols

CS#

SCK

SI

SO

Instruction

Address

Data 1

Phase

Data 2

Figure 9

Single Bit Wide I/O command without latency

CS#

SCK

SI

SO

Phase

Instruction

Address

Data 1

Dummy Cyles

Figure 10

Single Bit Wide I/O command with latency

CS#

SCK

IO0

IO1

Phase

Instruction

Address

6 Dummy

Data 1

Data 2

Figure 11

Dual Output command

CS#

SCK

IO0

IO1

IO2

IO3

Instruction

Address Data 1 Data 2 Data 3 Data 4 Data 5

Phase

Figure 12

Quad Output command without latency

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Signal protocols

CS#

SCK

IO0

IO1

Phase

Dummy

Data 1

Instruction

Address

Mode

Data 2

Figure 13

Dual I/O command

CS#

SCK

IO0

IO1

IO2

IO3

Phase

Instruction

Address Mode Dummy

D1 D2

D3

D4

Figure 14

Quad I/O command

Additional sequence diagrams, specific to each command, are provided in “Commands” on page 76.

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Signal protocols

4.3

Interface states

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 3

Interface states summary with separate reset

HOLD#/ WP# / SO / SI /

Interface state

V_CC

RESET#

SCK

X

CS#

X

IO3

IO2 IO1 IO0

Power-Off

Low Power Hardware Data

Protection

<V_CC(low)

<V_CC(cut-off)

X

Z

X

Z

X

Power-On (Cold) Reset

Hardware (Warm) Reset

Interface Standby

Instruction Cycle

Hold Cycle

V_CC(min)

X

HH

X

HH

HL

X

HH

HL

X

HV

X

Z

X

HV

X

HL

HH

HT

HV or HT HL

Single Input Cycle Host to

Memory Transfer

Single Latency (Dummy)

Cycle

Single Output Cycle Memory

to Host Transfer

V_CC(min)

HH

HT

HL

HH

X

Z

HV

X

MV

X

Dual Input Cycle Host to

Memory Transfer

DualLatency(Dummy)Cycle

Dual Output Cycle Memory

to Host Transfer

V_CC(min)

HH

HT

HL

HH

X

HV

X

HV

X

MV MV

QPP Address Input Cycle

Host to Memory Transfer

Quad Input Cycle Host to

Memory Transfer

Quad Latency (Dummy)

Cycle

Quad Output Cycle Memory

to Host Transfer

V_CC(min)

HH

HT

HL

X

HV

X

HV

X

HV

X

HV

X

MV

MV MV

Legend

Z = No driver - floating signal

HL = Host driving V_IL

HH = Host driving V_IH

HV = Either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V_IL

MH = Memory driving V_IH

MV = Either ML or MH

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Signal protocols

Table 4

Interface states summary with IO3 / RESET# enabled

HOLD#/ WP# / SO / SI /

Interface state

V_CC

SCK

CS#

X

IO3

IO2 IO1 IO0

Power-Off

Low Power Hardware Data

Protection

Power-On (Cold) Reset

Hardware (Warm) Reset —

Non-Quad Mode

<V_CC(low)

<V_CC(cut-off)

V_CC(min)

X

Z

X

HH

X

HL

Hardware (Warm) Reset — Quad

Mode

V_CC(min)

X

HH

HL

X

Z

X

Interface Standby

Instruction Cycle (Legacy SPI)

V_CC(min)

X

HT

HH

HL

X

HH

X

HV

Z

X

HV

Single Input Cycle

V_CC(min)

HT

HL

HH

X

Z

HV

X

Host to Memory Transfer

Single Latency (Dummy) Cycle

Single Output Cycle Memory to

Host Transfer

MV

X

Dual Input Cycle Host to Memory

Transfer

Dual Latency (Dummy) Cycle

Dual Output Cycle Memory to Host

Transfer

V_CC(min)

HT

HL

HH

X

HV

X

HV

X

MV MV

QPP Address Input Cycle Host to

Memory Transfer

V_CC(min)

HT

HL

X

HV

Quad Input Cycle Host to Memory

Transfer

Quad Latency (Dummy) Cycle

Quad Output Cycle Memory to Host

Transfer

V_CC(min)

HT

HL

HV

X

HV

X

HV

X

HV

X

MV

MV MV

Legend

Z = No driver - floating signal

HL = Host driving V_IL

HH = Host driving V_IH

HV = Either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V_IL

MH = Memory driving V_IH

MV = Either ML or MH

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Signal protocols

Table 5

Interface states summary with HOLD# / IO3 enabled

HOLD#/ WP# / SO / SI /

Interface State

V_DD

SCK

X

CS#

X

IO3

IO2 IO1 IO0

Power-Off

Low Power Hardware Data

Protection

<V_CC(low)

<V_CC(cut-off)

X

Z

X

Z

X

Power-On (Cold) Reset

Interface Standby

Instruction Cycle (Legacy SPI)

Hold Cycle

V_CC(min)

X

HT

HH

HL

X

HH

HL

X

HV

X

Z

X

HV

X

HV or HT HL

Single Input Cycle

V_CC(min)

HT

HL

HH

X

Z

HV

X

Host to Memory Transfer

Single Latency (Dummy) Cycle

Single Output Cycle Memory to

Host Transfer

MV

X

Dual Input Cycle Host to Memory

Transfer

Dual Latency (Dummy) Cycle

Dual Output Cycle Memory to Host

Transfer

V_CC(min)

HT

HL

HH

X

HV

X

HV

X

MV MV

QPP Address Input Cycle Host to

Memory Transfer

V_CC(min)

HT

HL

X

HV

Quad Input Cycle Host to Memory

Transfer

Quad Latency (Dummy) Cycle

Quad Output Cycle Memory to Host

Transfer

V_CC(min)

HT

HL

HV

X

HV

X

HV

X

HV

X

MV

MV MV

Legend

Z = No driver - floating signal

HL = Host driving V_IL

HH = Host driving V_IH

HV = Either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V_IL

MH = Memory driving V_IH

MV = Either ML or MH

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Signal protocols

4.3.1

Power-off

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

4.3.2

Low power hardware data protection

When V_CCis less than V_CC(cut-off), the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.3.3

Power-on (cold) reset

When the core voltage supply remains at or below the V_CC(low) voltage for t_PDtime, then rises to  V_{CC (Minimum)}

the device will begin its power-on reset (POR) process. POR continues until the end of t_PU. During t_PU, the device

does not react to external input signals nor drive any outputs. Following the end of t_PUthe device transitions to

the Interface Standby state and can accept commands. For additional information on POR, see “Power-on (cold)

reset” on page 35.

4.3.4

Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven low for t_RPtime the device

starts the hardware reset process. The process continues for t_RPHtime. Following the end of both t_RPHand the

reset hold time following the rise of RESET# (t_RH) the device transitions to the Interface Standby state and can

accept commands. For additional information on hardware reset, see “Separate RESET# input initiated

hardware (warm) reset” on page 36.

A configuration option is provided to allow IO3 to be used as a hardware reset input when the device is not in

Quad mode or when it is in Quad mode and CS# is HIGH. When IO3 / RESET# is driven LOW, for t_RPtime the device

starts the hardware reset process. The process continues for t_RPHtime. Following the end of both t_RPHand the

reset hold time following the rise of RESET# (t_RH), the device transitions to the Interface Standby state and can

accept commands. For additional information on hardware reset, see “Reset” on page 35.

4.3.5

Interface standby

When CS# is HIGH, the SPI interface is in Standby state. Inputs other than RESET# are ignored. The interface waits

for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a

new command.

While in Interface Standby state, the memory device draws standby current (I_SB) if no embedded algorithm is in

progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm

when the entire device returns to standby current draw.

4.3.6

Instruction cycle

When the host drives the MSb of an instruction and CS# goes LOW, on the next rising edge of SCK the device

captures the MSb of the instruction that begins the new command. On each following rising edge of SCK, the

device captures the next lower significance bit of the 8-bit instruction. The host keeps RESET# HIGH, CS# LOW,

HOLD# HIGH, and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only relevant

during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder

of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, or Quad I/O. The

expected next interface state depends on the instruction received.

Some commands are standalone, needing no address or data transfer to or from the memory. The host returns

CS# HIGH after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface

state in this case is Interface Standby.

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Signal protocols

4.3.7

Hold (HOLD# / IO3 selected by SR2[5])

When Quad mode is not enabled (CR[1] = 0), the HOLD# / IO3 signal is used as the HOLD# input. The host keeps

RESET# HIGH, HOLD# LOW, SCK may be at a valid level or continue toggling, and CS# is LOW. When HOLD# is LOW

a command is paused, as though SCK were held LOW. SI / IO0 and SO / IO1 ignore the input level when acting as

inputs and are high impedance when acting as outputs during Hold state. Whether these signals are input or

output depends on the command and the point in the command sequence when HOLD# is asserted LOW.

When HOLD# returns HIGH, the next state is the same state the interface was in just before HOLD# was asserted

LOW.

When Quad mode is enabled, the HOLD# / IO3 signal is used as IO3.

4.3.8

Single input cycle - Host to Memory transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the

memory device. The Dual Output, and Quad Output commands send address to the memory using only SI but

return read data using the I/O signals. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives SI as

needed for the command. The memory does not drive the Serial Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or

data to the memory using additional single input cycles. Others may transition to Single Latency, or directly to

Single, Dual, or Quad Output.

4.3.9

Single latency (dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the latency code in

the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and

HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or

the host may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals during

the latency cycles. In Dual or Quad Read commands, the host must stop driving the I/O signals on the falling edge

at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles

so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the

latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The

memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.

The next interface state depends on the command structure i.e. the number of latency cycles, and whether the

read is single, dual, or quad width.

4.3.10

Single output cycle - Memory to Host transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps

RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory ignores the

Serial Input (SI) signal. The memory drives SO with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to HIGH ending the

command.

4.3.11

Dual input cycle - Host to Memory transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps

RESET# HIGH, CS# LOW, HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host drives address on

SI / IO0 and SO / IO1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency

cycles needed or Dual Output Cycle if no latency is required.

Datasheet

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2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal protocols

4.3.12

Dual latency (dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the latency code in

the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and

HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during

these cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data driven on

SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the falling edge

at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles

so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the

latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The

memory does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

4.3.13

Dual output cycle - Memory to Host transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET#

HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory drives data on the

SI / IO0 and SO / IO1 signals during the dual output cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to HIGH ending the

command.

4.3.14

QPP or QOR address input cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The other

IO signals are ignored because the device must be in Quad mode for these commands thus the Hold and Write

Protect features are not active. The host keeps RESET# HIGH, CS# LOW, and drives IO0.

For QPP the next interface state following the delivery of address is the quad input cycle.

For QOR the next interface state following address is a quad latency cycle if there are latency cycles needed or

quad output cycle if no latency is required.

4.3.15

Quad Input Cycle - Host to Memory Transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page

Program command transfers four data bits to the memory in each cycle. The host keeps RESET# high, CS# low,

and drives the IO signals.

For Quad I/O Read, the next interface state following the delivery of address and mode bits is a quad latency cycle

if there are latency cycles needed or quad output cycle if no latency is required. For Quad Page Program, the host

returns CS# HIGH following the delivery of data to be programmed and the interface returns to Standby state.

4.3.16

Quad latency (dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the Configuration Register (CR[7:6]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW. The host

may drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any

data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the

end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory

does not drive the IO signals during the latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

Datasheet

26

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal protocols

4.3.17

Quad output cycle - Memory to Host transfer

The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps RESET#

HIGH, and CS# LOW. The memory drives data on IO0-IO3 signals during the Quad output cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to HIGH ending the

command.

4.4

Configuration register effects on the interface

The Configuration Register Bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code

selects the number of mode bit and latency cycles for each type of instruction.

The Configuration Register Bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and

allow Quad Page Program, Quad Output Read, and Quad I/O Read commands.

4.5

Data protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the

hardware design. These are described below in the Data protection on page 69.

4.5.1

Power-up

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

Program and erase operations continue to be prevented during the power-on reset because no command is

accepted until the exit from POR to the Interface Standby state.

4.5.2

Low power

When V_CCis less than V_CC(cut-off), the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.5.3

Clock pulse count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count

that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse count is

ignored and no error status is set for the command.

Datasheet

27

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

5

Electrical specifications

5.1

Absolute maximum ratings

Table 6

Absolute maximum ratings

Parameter

Value

–65°C to +150°C

–65°C to +125°C

–0.5 V to +4.0 V

–0.5 V to + (V_CC+ 0.5 V)

100 mA

Storage temperature plastic packages

Ambient temperature with power applied

V_CC

[6]

Input voltage with respect to Ground (V_SS

Output short circuit current^[7]

Notes

)

6. See “Input signal overshoot” on page 29 for allowed maximums during signal transition.

7. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be

greater than one second.

8. Stresses above those listed in this table may cause permanent damage to the device. This is a stress rating

only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this datasheet is not implied. Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

5.2

Thermal resistance

Table 7

Thermal resistance

Parameter

Description

Test conditions SOC008 SO3016 WND008 FAB024 FAC024 Unit

Thermal resistance Test conditions

Theta JA

Theta JB

(Junction to

ambient)

follow standard

test methods and

procedures for

measuring

63

40

31

39

°C/W

Thermal resistance

(Junction to board)

36.6

20.6

8.4

21.9

thermal

impedance in

accordance with

EIA/JESD51. with

Still Air (0 m/s).

Thermal resistance

(Junction to case)

Theta JC

29.4

12

20.8

14

°C/W

Datasheet

28

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

5.3

Operating ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

5.3.1

Temperature ranges

Table 8

Temperature ranges

Symbol

Spec

Parameter

Device

Unit

Min

–40

Max

+85

+105

+85

Industrial (I)

Industrial Plus (V)

Ambient

temperature

T_A

°C

Automotive, AEC-Q100 grade 3 (A)

Automotive, AEC-Q100 grade 2 (B)

+105

Industrial Plus operating and performance parameters will be determined by device characterization and may

vary from standard industrial temperature range devices as currently shown in this specification.

5.3.2

Power supply voltage

V_CC: 2.7 V to 3.6 V

5.3.3

Input signal overshoot

During DC conditions, input or I/O signals should remain equal to or between V_SSand V_CC. During voltage

transitions, inputs or I/Os may overshoot V_SSto –2.0 V or overshoot to V_CC+ 2.0 V, for periods up to 20 ns.

20 ns

V_IL

- 2.0V

20 ns

Figure 15

Maximum negative overshoot waveform

20 ns

V_CC+ 2.0V

V_IH

20 ns

Figure 16

Maximum positive overshoot waveform

Datasheet

29

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

5.4

Power-up and power-down

The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on V_CC

until V_CCreaches the correct value as follows:

)

• V_CC(min) at power-up, and then for a further delay of t_PU

• V_SSat power-down

A simple pull-up resistor (generally of the order of 100 k) on Chip Select (CS#) can usually be used to insure safe

and proper power-up and power-down.

The device ignores all instructions until a time delay of t_PUhas elapsed after the moment that V_CCrises above the

minimum V_CCthreshold (see Figure 17). However, correct operation of the device is not guaranteed if V_CCreturns

below V_CC(min) during t_PU. No command should be sent to the device until the end of t_PU

.

The device draws I_PORduring t_PU. After power-up (t_PU), the device is in Standby mode, draws CMOS standby

current (I_SB), and the WEL bit is reset.

During power-down or voltage drops below V_CC(cut-off), the voltage must drop below V_CC(low) for a period of

t_PDfor the part to initialize correctly on power-up (see Figure 18). If during a voltage drop the V_CCstays above V_CC

(cut-off) the part will stay initialized and will work correctly when V_CCis again above V_CC(min). In the event

power-on reset did not complete correctly after power up, the assertion of the RESET# signal or receiving a

software reset command (RESET) will restart the POR process.

Normal precautions must be taken for supply rail decoupling to stabilize the V_CCsupply at the device. Each device

in a system should have the V_CCrail decoupled by a suitable capacitor close to the package supply connection

(this capacitor is generally of the order of 0.1 µF).

Table 9

Symbol

_CC(min)

Power-up/power-down voltage and timing

Parameter

V_CC(minimum operation voltage)

Min

2.7

2.4

1.0

–

Max

–

300

–

Unit

V

µs

V

_CC(cut-off) V_CC(cut 0ff where re-initialization is needed)

_CC(low)

t_PU

t_PD

V_CC(low voltage for initialization to occur)

V_CC(min) to Read operation

V_CC(low) time

1.0

V_CC

(max)

V_CC

(min)

V_CC

t_PU

Full Device Access

Time

Figure 17

Power-up

Datasheet

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001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

V_CC

(max)

V_CC

No Device Access Allowed

(min)

V_CC

t_PU

Device Access

Allowed

(cut-off)

V_CC

(low)

V_CC

t_PD

Time

Figure 18

Power-down and voltage drop

5.5

DC characteristics

Applicable within operating ranges.

Table 10

Symbol

V_IL

V_IH

V_OL

V_OH

DC characteristics

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

Test conditions

Min

Typ^[9]

Max

0.2 × V_CC

V_CC+ 0.4

0.15 x V_CC

–

Unit

–

–0.5

0.7 × V_CC

–

V

I_OL= 1.6 mA, V_CC= V_CCmin

I_OH= –0.1 mA

0.85 x V_CC

V_CC= V_CCMax,

V_IN= 0 to V_ILMax or V_IH,

CS# = V_IH

I_LI

Input leakage current

Output leakage current

Input leakage current

–

± 2

± 4

µA

(Industrial)

I_LO

(Industrial)

V_CC= V_CCMax, V_IN= V_IHor V_IL

V_CC= V_CCMax,

V_IN= 0 to V_ILMax or V_IH,

CS# = V_IH

I_LI(Industrial

Plus)

I_LO

(Industrial

Plus)

Output leakage current

V_CC= V_CCMax, V_IN= V_IHor V_IL

–

± 4

µA

Serial @50 MHz

16

24

47

Serial @108 MHz

Active power supply current

(READ)

I_CC1

Quad @108 MHz

–

mA

Outputs unconnected

during read data return^[10]

Active power supply current

(Page Program)

I_CC2

CS# = V_CC

50

Notes

9. Typical values are at T_AI= 25°C and V_CC= 3 V.

10.Output switching current is not included.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

Table 10

Symbol

DC characteristics (Continued)

Parameter

Test conditions

Min

Typ^[9]

Max

Unit

Active power supply current

(WRR)

Active power supply current

(SE)

Active power supply current

(BE)

I_CC3

I_CC4

I_CC5

CS# = V_CC

–

50

mA

CS# = V_CC

–

50

mA

µA

CS# = V_CC

I_SB(–40°C to

85°C)

I_SB(–40°C to

105°C)

RESET#, CS# = V_CC;

SI, SCK = V_CCor V_SS

RESET#, CS# = V_CC

SI, SCK = V_CCor V_SS

RESET#, CS# = V_CC

SI, SCK = V_CCor V_SS

Standby current

70

–

100

300

63

;

Standby current

µA

;

I_POR

Power on reset current

mA

Notes

9. Typical values are at T_AI= 25°C and V_CC= 3 V.

10.Output switching current is not included.

5.5.1

Active Power and Standby Power modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is LOW. When CS# is HIGH, the device

is disabled, but may still be in an Active Power mode until all program, erase, and write operations have

completed. The device then goes into the Standby Power mode, and power consumption drops to I_SB

.

Datasheet

32

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6

Timing specifications

6.1

Key to switching waveforms

Input

Symbol

Output

Valid at logic high or low

High Impedance

Any change permitted

Logic high Logic low

Valid at logic high or low

High Impedance Changing, state unknown Logic high Logic low

Figure 19

Waveform element meanings

Input Levels

Output Levels

0.85 x V_CC

V_IO+ 0.4V

0.7 x V_CC

Timing Reference Level

0.5 x V_CC

0.2 x V_CC

- 0.5V

0.15 x V_CC

Figure 20

Input, output, and timing reference levels

Datasheet

33

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6.2

AC test conditions

Device

Under

Test

C

L

Figure 21

Test setup

Table 11

Symbol

C_L

AC measurement conditions

Parameter

Load capacitance

Input rise and fall times

Input pulse voltage

Input timing ref voltage

Output timing ref voltage

Min

Max

Unit

pF

ns

V

30

–

2.4

0.2 × V_CCto 0.8 × V_CC

0.5 × V_CC

6.2.1

Capacitance characteristics

Table 12

Symbol

Capacitance

Parameter

Test conditions

Min

Max

Unit

Input capacitance

(applies to SCK, CS#, RESET#)

C_IN

1 MHz

–

8

pF

Output capacitance

(applies to All I/O)

C_OUT

1 MHz

–

8

pF

Notes

11.Output High-Z is defined as the point where data is no longer driven.

12.Input slew rate: 1.5 V/ns.

13.AC characteristics tables assume clock and data signals have the same slew rate (slope).

14.Parameter values are not 100% tested. For more information on capacitance, please consult the IBIS models.

Datasheet

34

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6.3

Reset

6.3.1

Power-on (cold) reset

The device executes a POR process until a time delay of t_PUhas elapsed after the moment that V_CCrises above

the minimum V_CCthreshold. See Figure 17, Table 9, and Figure 22. The device must not be selected (CS# to go

HIGH with V_CC) during power-up (t_PU), i.e. no commands may be sent to the device until the end of t_PU

.

The IO3 / RESET# signal functions as the RESET# input when CS# is HIGH for more than t_RPtime or when Quad

Mode is not enabled CR1V[1] = 0.

RESET# is ignored during POR. If RESET# is LOW during POR and remains LOW through and beyond the end of

t

_PU, CS# must remain HIGH until t_RHafter RESET# returns HIGH. RESET# must return HIGH for greater than t_RS

before returning LOW to initiate a hardware reset.

VCC

tPU

RESET#

If RESET# is low at tPU end

CS# must be high at tPU end

tRH

CS#

Figure 22

Figure 23

Figure 24

Reset LOW at the end of POR

VCC

tPU

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

Reset HIGH at the end of POR

VCC

tPU

tRS

RESET#

CS#

POR followed by hardware reset

Datasheet

35

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6.3.2

Separate RESET# input initiated hardware (warm) reset

When the RESET# input transitions from V_IHto V_ILfor > t_RP, the device will reset register states in the same manner

as POR but, does not go through the full reset process that is performed during POR. The hardware reset process

requires a period of t_RPHto complete. If the POR process did not complete correctly for any reason during

power-up (t_PU), RESET# going LOW will initiate the full POR process instead of the hardware reset process and

will require t_PUto complete the POR process.

A separate RESET# input is available only in the SOIC16 and BGA package options. The RESET# input has an

internal pull-up to V_CCand should be left unconnected if not used. The RESET command is independent of the

state of RESET#. If RESET# is HIGH or unconnected, and the RESET instruction is issued, the device will perform

software reset.

The RESET# input provides a hardware method of resetting the flash memory device to Standby state.

• RESET# must be HIGH for t_RSfollowing t_PUor t_RPH, before going LOW again to initiate a hardware reset.

• When RESET# is driven LOW for at least a minimum period of time (t_RP), the device terminates any operation in

progress, makes all outputs high impedance, and ignores all read/write commands for the duration of t_RPH. The

device resets the interface to standby state.

• If CS# is LOW at the time RESET# is asserted, CS# must return HIGH during t_RPHbefore it can be asserted LOW

again after t_RH

.

Table 13

Hardware reset parameters

Parameter

Description

Limit

Min

Max

Min

Time

50

35

200

5

50

Unit

ns

µs

ns

µs

t_RS

t_RPH

t_RP

t_RH

Reset setup - prior reset end and RESET# HIGH before RESET# LOW

Reset pulse hold - RESET# LOW to CS# LOW

RESET# pulse width

RESET# pulse width (only when AutoBoot enabled)

Reset hold - RESET# HIGH before CS# LOW

ns

tRP

RESET#

Any prior reset

tRPH

tRH

tRS

tRPH

CS#

Figure 25

Separate RESET# input initiated hardware reset

Notes

15.RESET# LOW is ignored during power-up (t_PU). If Reset# is asserted during the end of t_PU, the device will

remain in the Reset state and t_RHwill determine when CS# may go LOW.

16.Sum of t_RPand t_RHmust be equal to or greater than t_RPH

.

Datasheet

36

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6.3.3

IO3 / RESET# input initiated hardware (warm) reset

The IO3 / RESET# signal functions as a RESET# input when enabled by SR2[5] = 1 and CS# is HIGH for more than

t_CStime or when Quad mode is not enabled (CR1V[1] = 0). The IO3 RESET# input provides a hardware method of

resetting the flash memory device to standby state. The IO3 / RESET# input has an internal pull-up to V_CCand may

be left unconnected if Quad mode is not used.

When the IO3 / RESET# feature and Quad mode are both enabled, IO3 / RESET# is ignored for t_CSfollowing CS#

going HIGH, to avoid an unintended Reset operation. This allows some time for the memory or host system to

actively drive IO3 / RESET# to a valid level following the end of a transfer. Following the end of a Quad I/O read

the memory will actively drive IO3 HIGH before disabling the output during t_DIS. Following a transfer in which IO3

was used to transfer data to the memory, e.g. the QPP command, the host system is responsible for driving IO3

HIGH before disabling the host IO3 output. The integrated pull-up on IO3 will then hold IO3 until the host system

actively drives IO3 / RESET# to initiate a reset. If CS# is driven LOW to start a new command, IO3 / RESET# is used

as IO3.

When the device is not in quad mode or when CS# is HIGH, and the IO3 / RESET# transitions from V_IHto V_ILfor

> t_RP, the device terminates any operation in progress, makes all outputs high impedance, ignores all read/write

commands and resets the interface to standby state. The hardware reset process requires a period of t_RPHto

complete. During t_RPH, the device will reset register states in the same manner as power-on reset but, does not

go through the full reset process that is performed during POR. If the POR process did not complete correctly for

any reason during power-up (t_PU), RESET# going LOW for t_RPwill initiate the full POR process instead of the

hardware reset process and will require t_PUto complete the POR process. IO3 / RESET# must be HIGH for t_RS

following t_PUor t_RPH, before going LOW again to initiate a hardware reset.

If Quad mode is not enabled, and if CS# is LOW at the time IO3 / RESET# is asserted LOW, CS# must return HIGH

during t_RPHbefore it can be asserted LOW again after t_RH

.

The RESET command is independent of the state of RESET#. If IO3 / RESET# is HIGH or unconnected, and the

RESET instruction is issued, the device will perform software reset.

Table 14

Parameter

t_RS

t_RPH

t_RP

Hardware reset parameters

Description

Reset setup - prior reset end and RESET# HIGH before RESET# LOW

Reset Pulse Hold - RESET# LOW to CS# LOW

RESET# Pulse Width

Limit

Min

Max

Min

Time

50

35

200

5

50

Unit

ns

µs

ns

µs

t_RP

t_RH

RESET# Pulse Width (only when AutoBoot enabled)

Reset Hold - RESET# HIGH before CS# LOW

ns

Notes

17.IO3 / RESET# LOW is ignored during power-up (t_PU). If Reset# is asserted during the end of t_PU, the device

will remain in the Reset state and t_RHwill determine when CS# may go LOW.

18.If Quad mode is enabled, IO3 / RESET# LOW is ignored during t_CS.

19.Sum of t_RPand t_RHmust be equal to or greater than t_RPH

.

Datasheet

37

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

tRP

IO3_RESET#

CS#

Any prior reset

tRPH

tRH

tRS

tRPH

Figure 26

Hardware reset when quad mode is not enabled and IO3 / Reset# is enabled

tDIS

tRP

IO3_RESET#

Reset Pulse

tCS

tRH

tRPH

CS#

Prior access using IO3 for data

Figure 27

Hardware reset when quad mode and IO3 / Reset# are enabled

Datasheet

38

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

6.4

AC characteristics

Table 15

Symbol

AC characteristics

Parameter

Min

Typ

Max

Unit

SCK clock frequency for READ and 4READ

instructions

F_{SCK, R}

F_{SCK, C}

DC

–

50

MHz

SCK clock frequency for single commands as

DC

–

108

MHz

shown in Table 40^[23]

SCK clock frequency for the following Dual and

Quad commands: DOR, 4DOR, QOR, 4QOR,

DIOR, 4DIOR, QIOR, 4QIOR

SCK clock frequency for the QPP, 4QPP

commands

F_{SCK, C}

F_{SCK, QPP}

80

P_SCK

t_WH, t_CH

SCK clock period

Clock high time^[24]

Clock low time^[24]

1/ FSCK

50%PSCK–5%

0.1

–



50%PSCK+5% ns

t

_WL, t_CL

_CRT, t_CLCHClock rise time (slew rate)

_CFT, t_CHCLClock fall time (slew rate)

–

V/ns

0.1

CS# high time (read instructions) CS# high time

10

20^[26]

50

(read instructions when Reset feature and Quad

mode are both enabled) CS# high time

(program/erase instructions)

t_CS

–

ns

t_CSS

t_CSH

t_SU

CS# active setup time (relative to SCK)

CS# active hold time (relative to SCK)

Data in setup time

3

1.5

2

–

ns

t_HD

Data in hold time

8.0 ^[21]

7.65^[22]

6.5^[23]

t_V

Clock low to output valid

1

–

ns

t_HO

Output hold time

Output disable time^[25]

2

–

ns

8

t_DIS

Output disable time (when Reset feature and

Quad mode are both enabled)

WP# setup time

–

20^[26]

ns

t_WPS

t_WPH

t_HLCH

t_CHHH

t_HHCH

Notes

20^[20]

100^[20]

–

ns

WP# hold time

HOLD# active setup time (relative to SCK)

HOLD# active hold time (relative to SCK)

HOLD# non active setup time (relative to SCK)

3

20.Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

21.Full V_CCrange (2.7 V–3.6 V) and CL = 30 pF.

22.Regulated V_CCrange (3.0 V–3.6 V) and CL = 30 pF.

23.Regulated V_CCrange (3.0 V–3.6 V) and CL = 15 pF.

24.±10% duty cycle is supported for frequencies  50 MHz.

25.Output High-Z is defined as the point where data is no longer driven.

26.t_CSand t_DISrequire additional time when the Reset feature and Quad mode are enabled (CR2V[5] = 1 and

CR1V[1] = 1).

Datasheet

39

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

Table 15

Symbol

t_CHHL

t_HZ

AC characteristics (Continued)

Parameter

Min

3

–

Typ

–

Max

Unit

ns

HOLD# non active hold time (relative to SCK)

HOLD# enable to output invalid

HOLD# enable to output valid

–

8

t_LZ

–

ns

Notes

20.Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

21.Full V_CCrange (2.7 V–3.6 V) and CL = 30 pF.

22.Regulated V_CCrange (3.0 V–3.6 V) and CL = 30 pF.

23.Regulated V_CCrange (3.0 V–3.6 V) and CL = 15 pF.

24.±10% duty cycle is supported for frequencies  50 MHz.

25.Output High-Z is defined as the point where data is no longer driven.

26.t_CSand t_DISrequire additional time when the Reset feature and Quad mode are enabled (CR2V[5] = 1 and

CR1V[1] = 1).

6.4.1

Clock timing

P_SCK

tCH

V_{IH min}

V_{CC / 2}

V_{IL max}

tCFT

tCRT

tCL

Figure 28

Clock timing

6.4.2

Input / output timing

tCS

CS#

tCSH

tCSS

SCK

tSU

tHD

MSB IN

SI

LSB IN

SO

Figure 29

SPI single bit input timing

Datasheet

40

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

tCS

CS#

SCK

SI

tLZ

tHO

tV

tDIS

SO

MSB OUT

LSB OUT

Figure 30

SPI single bit output timing

tCS

CS#

tCSS

tCSH

tCSS

SCK

IO

tSU

tHD

tLZ

tHO

tV

tDIS

MSB IN

LSB IN

.

MSB OUT

.

LSB OUT

Figure 31

SPI MIO timing

CS#

SCK

tHLCH

tCHHL

tHHCH

tCHHH

tHLCH

tCHHL

tHHCH

tCHHH

HOLD#

Hold Condition

Standard Use

Hold Condition

Non-standard Use

SI_or_IO_(during_input)

tHZ

tLZ

B

tHZ

tLZ

SO_or_IO_(during_output)

A

B

C

D

E

Figure 32

Hold timing

Datasheet

41

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

CS#

tWPS

WP#

SCK

tWPH

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

WRR Instruction

Input Data

Figure 33

WP# input timing

Datasheet

42

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7

Physical interface

Table 16

Model specific connections

Signal name

Description

RESET# or RFU - Some device models bond this connector to the device RESET# signal,

other models bond the RESET# signal to Vcc within the package leaving this package

connector unconnected.

RESET# / RFU

7.1

SOIC 8-lead package

7.1.1

SOIC-8 connection diagram

8

7

VCC

1

2

CS#

SO / IO1

HOLD# / IO3 or IO3 / RESET#

SOIC

CLK

3

4

6

5

WP# / IO2

GND

SI / IO0

Figure 34

8-pin plastic small outline package (SO)^[28]

Notes

27.Refer to Table 2 for signal descriptions.

28.Lead 7 HOLD# / IO3 or IO3 / RESET# function depends on the selected configuration, If the IO3 / RESET#

function is used, the host system should actively or passively pull-up the IO3 / RESET# connection when Quad

mode is not enabled, or when CS# is HIGH and a Reset operation is not intended.

Datasheet

43

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.1.2

SOIC 8 physical diagram

NOTES:

DIMENSIONS

SYMBOL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.

MIN.

1.75

NOM.

MAX.

2.16

-

A

A1

A2

b

3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER

END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.

D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.

4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS

D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF

THE PLASTIC BODY.

0.05

1.70

0.25

1.90

0.48

0.46

0.36

0.33

0.19

0.15

b1

c

0.24

0.20

c1

5. DATUMS A AND B TO BE DETERMINED AT DATUM H.

6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED

PACKAGE LENGTH.

7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO

0.25 mm FROM THE LEAD TIP.

8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT

D

E

5.28 BSC

8.00 BSC

5.28 BSC

E1

e

1.27 BSC

-

L

0.76

0.51

MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OF THE LEAD FOOT.

9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1

IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.

L1

L2

N

1.36 REF

0.25 BSC

8

10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

0

-

0°

5°

8°

0 1

0 2

15°

0-8° REF

002-15548 **

Figure 35

8-lead SOIC (5.28 × 5.28 × 2.16 mm) package outline, 002-15548

Datasheet

44

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.2

SOIC 16-lead package

SOIC 16 connection diagram

7.2.1

16

15

14

SCK

1

HOLD#/IO3/RESET#

VCC

2

3

SI/IO0

NC

RESET#

DNU

13

12

4

5

NC

DNU

RFU

6

11

DNU

VSS

CS#

7

8

10

9

SO/IO1

WP#/IO2

Figure 36

16-lead SOIC package, top view

Datasheet

45

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.2.2

SOIC 16 physical diagram

A-B

C

0.20

0.10

C

D

2X

0.33

C

0.25

0.10

M

C A-B D

C

0.10

C

DIMENSIONS

NOTES:

SYMBOL

MIN.

NOM.

MAX.

2.65

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.

A

A1

A2

b

2.35

0.10

2.05

-

3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER

END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.

D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.

4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS

D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF

THE PLASTIC BODY.

-

0.30

2.55

0.51

0.48

-

0.31

0.27

0.20

-

b1

c

-

0.33

0.30

-

c1

5. DATUMS A AND B TO BE DETERMINED AT DATUM H.

6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED

PACKAGE LENGTH.

7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO

0.25 mm FROM THE LEAD TIP.

8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT

MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OF THE LEAD FOOT.

D

E

10.30 BSC

7.50 BSC

E1

e

1.27 BSC

-

L

1.27

0.40

L1

L2

N

9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1

IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.

10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

1.40 REF

0.25 BSC

16

h

0.25

0°

-

0.75

8°

0

0 1

0 2

5°

15°

-

0°

002-15547 *A

Figure 37

16-lead SOIC (10.30 × 7.50 × 2.65 mm) package outline, 002-15547

Datasheet

46

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.3

WSON 6 x 5 package

WSON 6 x 5 mm connection diagram

7.3.1

CS#

SO/IO1

WP#/IO2

VSS

VCC

8

7

6

1

2

HOLD#/IO3 or IO3/RESET#

WSON

3

4

SCK

SI/IO0

5

Figure 38

8-Contact WSON 6 x 5 mm, top view^{[29, 30]}

Notes

29.Lead 7 HOLD# / IO3 or IO3 / RESET# function depends on the selected configuration, If the IO3 / RESET#

function is used, the host system should actively or passively pull-up the IO3 / RESET# connection when

Quad mode is not enabled, or when CS# is HIGH and a Reset operation is not intended.

30.There is an exposed central pad on the underside of the WSON package. This pad should not be connected

to any voltage or signal line on the PCB. Connecting the central pad to GND (V_SS) is possible, provided PCB

routing ensures 0 mV difference between voltage at the WSON GND (V_SS) lead and the central exposed pad.

Datasheet

47

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.3.2

WSON physical diagram

NOTES:

DIMENSIONS

NOM.

SYMBOL

e

1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. N IS THE TOTAL NUMBER OF TERMINALS.

MIN.

0.55

MAX.

0.65

1.27 BSC.

8

4

0.60

N

ND

4

DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS

THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE

DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.

L

b

D2

E2

D

0.35

3.90

3.30

0.40

4.00

0.45

4.10

3.50

5

3.40

5.00 BSC

6. MAX. PACKAGE WARPAGE IS 0.05mm.

7.

MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.

PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.

BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK

SLUG AS WELL AS THE TERMINALS.

E

6.00 BSC

0.75

0.02

8

9

0.70

0.00

0.80

0.05

A

A1

0.20 REF

A3

K

10 A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.

0.20 MIN.

002-18755 **

Figure 39

8-lead DFN (5.0 × 6.0 × 0.8 mm) package outline, 002-18755

Datasheet

48

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.4

FAB024 24-ball BGA package

Connection diagram

7.4.1

1

2

3

4

5

A

B

C

D

E

NC

VSS

RESET#/

RFU

NC

DNU

NC

SCK

CS#

VCC

RFU WP#/IO2

SO/IO1 SI/IO0 HOLD#/IO3 NC

NC

RFU

NC

Figure 40

24-ball BGA, 5 x 5 ball footprint (FAB024), top view^[31]

Note

31.Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use

either package.

Datasheet

49

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.4.2

Physical diagram

NOTES:

DIMENSIONS

SYMBOL

MIN.

NOM.

MAX.

1.

2.

3.

DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

A

-

1.20

-

ALL DIMENSIONS ARE IN MILLIMETERS.

A1

D

0.20

BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

8.00 BSC

4.

5.

e REPRESENTS THE SOLDER BALL GRID PITCH.

E

6.00 BSC

4.00 BSC

5

D1

E1

MD

ME

N

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

5

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

24

0.40

b

0.35

0.45

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE

POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

eE

eD

SD

SE

1.00 BSC

0.00 BSC

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND

"SE" = eE/2.

8.

9.

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALLIZED MARK INDENTATION OR OTHER MEANS.

002-15534 **

Figure 41

24-ball FBGA (8.0 × 6.0 × 1.2 mm) package outline, 002-15534

Datasheet

50

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.5

FAC024 24-ball BGA package

7.5.1

Connection diagram

1

2

3

4

A

B

C

D

NC

VSS

RESET#/

RFU

DNU

SCK

CS#

VCC

RFU WP#/IO2

SO/IO1 SI/IO0 HOLD#/IO3

E

F

NC

RFU

NC

Figure 42

24-ball BGA, 4 x 6 ball footprint (FAC024), top view^[31]

Note

32.Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use

either package.

Datasheet

51

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

7.5.2

Physical diagram

NOTES:

DIMENSIONS

SYMBOL

MIN.

-

NOM.

MAX.

1.20

-

1.

2.

3.

DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

ALL DIMENSIONS ARE IN MILLIMETERS.

A

A1

D

-

0.25

BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

8.00 BSC

4.

5.

e

REPRESENTS THE SOLDER BALL GRID PITCH.

E

6.00 BSC

5.00 BSC

3.00 BSC

6

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

D1

E1

MD

ME

N

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

4

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

24

0.40

b

0.35

0.45

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE

POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

eE

eD

SD

SE

1.00 BSC

0.50 BSC

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND

"SE" = eE/2.

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

8.

9.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALLIZED MARK INDENTATION OR OTHER MEANS.

002-15535 **

Figure 43

24-ball FBGA (8.0 × 6.0 × 1.2 mm) package outline, 002-15535

7.5.3

Special handling instructions for FBGA packages

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

Datasheet

52

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

8

Address space maps

8.1

Overview

8.1.1

Extended address

The FL-S family of devices supports 32-bit addresses to enable higher density devices than allowed by previous

generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access

only 16 MB (128 Mb) of maximum density. A 32-bit byte resolution address allows direct addressing of up to a

4 Gbytes (32 Gbits) of address space.

Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit

addresses are enabled in three ways:

• Bank Address register — a software (command) loadable internal register that supplies the high order bits of

address when legacy 24-bit addresses are in use.

• Extended Address mode — a bank address register bit that changes all legacy commands to expect 32 bits of

address supplied from the host system.

• New commands — that perform both legacy and new functions, which expect 32-bit address.

The default condition at power-up or reset, is the Bank address register loaded with zeros and the extended

address mode set for 24-bit addresses. This enables legacy software compatible access to the first 128 Mb of a

device.

The S25FL127S, 128 Mb density member of the FL-S Family, supports the extended address features in the same

way but in essence ignores bits 31 to 24 of any address because the main flash array only needs 24 bits of address.

This enables simple migration from the 128-Mb density to higher density devices without changing the address

handling aspects of software.

8.1.2

Multiple address spaces

Many commands operate on the main flash memory array. Some commands operate on address spaces separate

from the main flash array. Each separate address space uses the full 32-bit address but may only define a small

portion of the available address space.

Datasheet

53

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

8.2

Flash memory array

The main flash array is divided into erase units called sectors. The sectors are organized either as a hybrid

combination of 4-KB and 64-KB sectors, or as uniform 256-KB sectors. The sector organization depends on the

D8h_O control bit configuration in the Status Register 2 (SR2[7]).

Table 17

S25FL127S sector and memory address map, bottom 4-KB sectors

Address range

Sector size (KB)

Sector count

Sector range

Notes

(byte address)

4

16

SA00

:

00000000h–00000FFFh Sector Starting Address

:

SA15

SA16

:

0000F000h–0000FFFFh

00010000h–0001FFFFh

—

64

255

:

SA270

00FF0000h–00FFFFFFh Sector Ending Address

Table 18

S25FL127S sector and memory address map, top 4-KB sectors

Address range

Sector size (KB)

Sector count

Sector range

Notes

(byte address)

SA00

:

0000000h–000FFFFh Sector Starting Address

:

64

255

SA255

SA256

:

00FE0000h–00FEFFFFh

00FF0000h–00FF0FFFh

—

4

16

:

SA270

00FFF000h–00FFFFFFh Sector Ending Address

Table 19

S25FL127S sector and memory address map, uniform 256-KB sectors

Address range

Sector size (KB)

Sector count

Sector range

Notes

(byte address)

0000000h–003FFFFh Sector Starting Address

SA00

:

256

64

:

—

SA63

0FC0000h–0FFFFFFh

Sector Ending Address

Note These are condensed tables that use a couple of sectors as references. There are address ranges that are

not explicitly listed. All 4-KB sectors have the pattern XXXX000h–XXXXFFFh. All 64-KB sectors have the pattern

XXX0000h–XXXFFFFh. All 256-KB sectors have the pattern XX00000h–XX3FFFFh, XX40000h–XX7FFFFh,

XX80000h–XXCFFFFh, or XXD0000h–XXFFFFFh.

8.3

ID-CFI address space

The RDID command (9Fh) reads information from a separate flash memory address space for device

identification (ID) and Common Flash Interface (CFI) information. See “Device ID and Common Flash Interface

(ID-CFI) address map” on page 137 for the tables defining the contents of the ID-CFI address space. The ID-CFI

address space is programmed by Infineon and read-only for the host system.

Datasheet

54

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

8.4

JEDEC JESD216B serial flash discoverable parameters (SFDP) space

The RSFDP command (5Ah) reads information from a separate Flash memory address space for device

identification, feature, and configuration information, in accord with the JEDEC JESD216B standard for serial

flash discoverable parameters. The ID-CFI address space is incorporated as one of the SFDP parameters. See

“Serial flash discoverable parameters (SFDP) address map” on page 133 for the tables defining the contents

of the SFDP address space. The SFDP address space is programmed by Infineon and read-only for the host

system.

8.5

OTP address space

Each FL-S family memory device has a 1024-byte one time program (OTP) address space that is separate from

the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

In the 32-byte region starting at address 0:

• The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able

to program these bytes.

• The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently

protect each region from programming. The bytes are erased when shipped from Infineon. After an OTP region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the OTP Lock Bytes.

• The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU

bytes may be programmed by the host system but it must be understood that a future device may use those

bits for protection of a larger OTP space. The bytes are erased when shipped from Cypress.

The remaining regions are erased when shipped from Cypress, and are available for programming of additional

permanent data.

Refer to Figure 44 for a pictorial representation of the OTP memory space.

The OTP memory space is intended for increased system security. OTP values, such as the random number

programmed by Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device

substitution.

The Configuration Register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when

set to 1. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent

further OTP memory space programming during the remainder of normal power-on system operation.

32-byte OTP Region 31

32-byte OTP Region 30

32-byte OTP Region 29

.

When programmed to

“0” each lock bit

protects its related 32

byte region from any

further programming

.

32-byte OTP Region 3

32-byte OTP Region 2

32-byte OTP Region 1

32-byte OTP Region 0

...

Lock Bits 31 to 0

Reserved

Lock Bytes

16-byte Random Number

Contents of Region 0

{

Byte 1Fh

Byte 10h

Byte 0h

Figure 44

OTP address space

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Table 20

Region

OTP address map

Byte address range

(Hex)

Contents

Initial delivery state (Hex)

Least Significant Byte of Infineon

programmed random number

...

Most Significant Byte of Infineon

programmed random number

000

...

Cypress Programmed Random

Number

00F

Region Locking Bits

Region 0

Byte 10 [bit 0] locks region 0 from

programming when = 0

...

010 to 013

All bytes = FF

Byte 13 [bit 7] locks region 31 from

programming when = 0

014 to 01F

020 to 03F

040 to 05F

...

Reserved for Future Use (RFU)

Available for user programming

All bytes = FF

Region 1

Region 2

...

Region 31

3E0 to 3FF

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8.6

Registers

Registers are small groups of memory cells used to configure how the S25FL-S memory device operates or to

report the status of device operations. The registers are accessed by specific commands. The commands (and

hexadecimal instruction codes) used for each register are noted in each register description. The individual

register bits may be volatile, nonvolatile, or one time programmable (OTP). The type for each bit is noted in each

register description. The default state shown for each bit refers to the state after power-on reset, hardware reset,

or software reset if the bit is volatile. If the bit is nonvolatile or OTP, the default state is the value of the bit when

the device is shipped from Cypress. Nonvolatile bits have the same cycling (erase and program) endurance as the

main flash array.

Table 21

Register descriptions

Register

Abbreviation

SR1[7:0]

Type

Volatile

RFU

Nonvolatile

Volatile

OTP

Bit location

Status Register 1

Configuration Register 1

Status Register 2

AutoBoot Register

Bank Address Register

ECC Status Register

ASP Register

7:0

31:0

7:0

15:1

0

CR1[7:0]

SR2[7:0]

ABRD[31:0]

BRAC[7:0]

ECCSR[7:0]

ASPR[15:1]

ASPR[0]

ASP Register

RFU

Password Register

PPB Lock Register

PASS[63:0]

PPBL[7:1]

Nonvolatile OTP

Volatile

63:0

7:1

Volatile

Read Only

PPBL[0]

0

PPB Access Register

DYB Access Register

SPI DDR Data Learning Registers

PPBAR[7:0]

DYBAR[7:0]

NVDLR[7:0]

VDLR[7:0]

Nonvolatile

Volatile

Nonvolatile

Volatile

7:0

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8.6.1

Status Register 1 (SR1)

Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h),

Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).

Table 22

Bits

Status Register 1 (SR1)

Function

Field

Type

Default State

Description

Name

1 = Locks state of SRWD, BP, and

Configuration Register bits when

WP# is LOW by ignoring WRR

command

0 = No protection, even when WP#

is LOW

Status Register

Write Disable

7

SRWD

Nonvolatile

0

Programming Error

Volatile,

1 = Error occurred

0 = No Error

1 = Error occurred

0 = No Error

6

5

P_ERR

E_ERR

0

Occurred

Read only

Erase Error

Occurred

Volatile,

Read only

4

3

2

BP2

BP1

BP0

Volatile if

CR1[3] = 1,

Nonvolatile

if CR1[3] = 0

1 if CR1[3] = 1,

0 when shipped

from Cypress

Protects selected range of sectors

(Block) from Program or Erase.

Block Protection

1 = Device accepts Write Registers

(WRR), Program or Erase

commands

0 = Device ignores Write Registers

(WRR), Program or Erase

commands

This bit is not affected by WRR, only

WREN and WRDI commands affect

this bit.

1 = Device Busy, a Write Registers

(WRR), program, erase or other

operation is in progress

0 = Ready Device is in Standby

mode and can accept commands

1

0

WEL

WIP

Write Enable Latch

Volatile

0

Volatile,

Read only

Write in Progress

The Status Register contains both status and control bits:

Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit

is set to ‘1’ and the WP# input is driven LOW. In this mode, the Write Registers (WRR) command is no longer

accepted for execution, effectively locking the state of the SRWD bit, BP bits, and Configuration Register bits by

making the Status Register and Configuration Register read-only. If WP# is HIGH, the SRWD bit and BP bits may

be changed by the WRR command. If SRWD is ‘0’, WP# has no effect and the SRWD bit and BP bits may be changed

by the WRR command. The SRWD bit has the same nonvolatile endurance as the main flash array.

Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure

indication. When the Program Error bit is set to ‘1’, it indicates that there was an error in the last program

operation. This bit will also be set when the user attempts to program within a protected main memory sector or

locked OTP region. When the Program Error bit is set to ‘1’, this bit can be reset to 0 with the Clear Status Register

(CLSR) command. This is a read-only bit and is not affected by the WRR command.

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Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When

the Erase Error bit is set to ‘1’, it indicates that there was an error in the last erase operation. This bit will also be

set when the user attempts to erase an individual protected main memory sector. The Bulk Erase command will

not set E_ERR if a protected sector is found during the command execution. When the Erase Error bit is set to ‘1’,

this bit can be reset to 0 with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected

by the WRR command.

Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected

against program and erase commands. The BP bits are either volatile or nonvolatile, depending on the state of

the BP nonvolatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to ‘1’, the

relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed

only when the BP bits are cleared to 0’s. See “Block protection” on page 70 for a description of how the BP bit

values select the memory array area protected. The BP bits have the same nonvolatile endurance as the main

flash array.

Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to ‘1’ to enable program, write, or erase operations

as a means to provide protection against inadvertent changes to memory or register values. The Write Enable

(WREN) command execution sets the Write Enable Latch to ‘1’ to allow any program, erase, or write commands

to execute afterwards. The Write Disable (WRDI) command can be used to set the Write Enable Latch to ‘0’ to

prevent all program, erase, and write commands from execution. The WEL bit is cleared to ‘0’ at the end of any

successful program, write, or erase operation. Following a failed operation the WEL bit may remain set and

should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence,

hardware reset, or software reset, the Write Enable Latch is set to ‘0’. The WRR command does not affect this bit.

Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation,

or any other operation, during which a new operation command will be ignored. When the bit is set to ‘1’, the

device is busy performing an operation. While WIP is ‘1’, only Read Status (RDSR1 or RDSR2), Erase Suspend

(ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands may be

accepted. ERSP and PGSP will only be accepted if memory array erase or program operations are in progress. The

status register E_ERR and P_ERR bits are updated while WIP = 1. When P_ERR or E_ERR bits are set to one, the

WIP bit will remain set to1 indicating the device remains busy and unable to receive new operation commands.

A Clear Status Register (CLSR) command must be received to return the device to standby mode. When the WIP

bit is cleared to ‘0’, no operation is in progress. This is a read-only bit.

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8.6.2

Configuration Register 1 (CR1)

Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration

Register bits can be changed using the WRR command with sixteen input cycles.

The configuration register controls certain interface and data protection functions.

Table 23

Configuration Register (CR1)

Default

state

Bits Field Name

Function

Type

Description

7

6

LC1

LC0

0

Selects number of initial read

latency cycles

See Table 24

Latency Code

Nonvolatile

0

1 = BP starts at bottom (Low

address)

0 = BP starts at top (High address)

Configures Start of

Block Protection

5

TBPROT

OTP

0

4

3

DNU

OTP

0

Do Not Use

1 = Volatile

0 = Nonvolatile

Configures BP2-0 in

Status Register

BPNV

1 = 4-KB physical sectors at top,

(high address)

Configures Parameter

Sectors location

2

1

TBPARM

QUAD

OTP

0

0 = 4-KB physical sectors at bottom

(Low address)

RFU in uniform sector devices

1 = Quad

0 = Dual or Serial

Puts the device into

Quad I/O operation

Nonvolatile

Lock current state of

BP2-0 bits in Status

Register, TBPROT and

TBPARM in

Configuration Register,

and OTP regions

1 = Block Protection and OTP

locked

0 = Block Protection and OTP

un-locked

0

FREEZE

Volatile

0

Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end

of address and the start of read data output for all read commands.

Some read commands send mode bits following the address to indicate that the next command will be of the

same type with an implied, rather than an explicit, instruction. The next command thus does not provide an

instruction byte, only a new address and mode bits. This reduces the time needed to send each command when

the same command type is repeated in a sequence of commands.

Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array

before data can be returned to the host system. Some read commands require additional latency cycles as the

SCK frequency is increased.

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The following latency code tables provide different latency settings that are configured by Cypress.

Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported

at the frequency shown. Read is supported only up to 50 MHz but the same latency value is assigned in each

latency code and the command may be used when the device is operated at  50 MHz with any latency code

setting. Similarly, only the Fast Read command is supported up to 108 MHz but the same 10b latency code is used

for Fast Read up to 108 MHz and for the other dual and quad read commands up to 108 MHz. It is not necessary

to change the latency code from a higher to a lower frequency when operating at lower frequencies where a

particular command is supported. The latency code values for a higher frequency can be used for accesses at

lower frequencies.

Table 24

Freq.

Latency codes

Read

(03h, 13h)

Fast Read

(0Bh, 0Ch)

Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read

(3Bh, 3Ch) (6Bh, 6Ch) (BBh, BCh) (EBh, ECh)

LC

(MHz)

Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy

≤ 50 11

≤ 80 00

≤ 90 01

≤104 10

≤ 108 10

0

–

0

–

0

8

0

–

0

8

–

0

–

0

8

–

4

–

0

4

1

2

–

2

–

1

4

5

–

Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2,

BP1, and BP0 in the Status Register. As described in the status register section, the BP2–0 bits allow the user to

optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is

set to ‘0’, the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT is

set to ‘1’, the Block Protection is defined to start from the bottom (zero address) of the array. The TBPROT bit is

OTP and set to ‘0’ when shipped from Cypress. If TBPROT is programmed to ‘1’, an attempt to change it back to

0 will fail and set the Program Error bit (P_ERR in SR1[6]).

The desired state of TBPROT must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPROT must not be

programmed after programming or erasing is done in the main flash array.

CR1[4]: Do Not Use

Block Protection Nonvolatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2–0 bits in the Status

Register are volatile or nonvolatile. The BPNV bit is OTP and cleared to ‘0’ with the BP bits cleared to 000 when

shipped from Cypress. When BPNV is set to a 0 the BP2–0 bits in the Status Register are nonvolatile. The time

required to write the BP bits when they are nonvolatile is t_W. When BPNV is set to ‘1’, the BP2–0 bits in the Status

Register are volatile and will be reset to binary 111 after POR, hardware reset, or command reset. This allows the

BP bits to be written an unlimited number of times because they are volatile and the time to write the volatile BP

bits is the much faster t_CSvolatile register write time. If BPNV is programmed to ‘1’, an attempt to change it back

to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).

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TBPARM CR1[2]: TBPARM defines the logical location of the parameter block. The parameter block consists of

sixteen 4-KB small sectors, which replace one 64-KB sector. When TBPARM is set to ‘1’, the parameter block is in

the top of the memory array address space. When TBPARM is set to a 0 the parameter block is at the Bottom of

the array. TBPARM is OTP and set to a 0 when it ships from Cypress. If TBPARM is programmed to ‘1’, an attempt

to change it back to ‘0’ will fail and set the Program Error bit (P_ERR in SR1[6]).

The desired state of TBPARM must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPARM must not be

programmed after programming or erasing is done in the main flash array.

TBPROT can be set or cleared independent of the TBPARM bit. Therefore, the user can elect to store parameter

information from the bottom of the array and protect boot code starting at the top of the array, and vice versa.

Or the user can select to store and protect the parameter information starting from the top or bottom together.

When the memory array is logically configured as uniform 256-KB sectors, the TBPARM bit is Reserved for Future

Use (RFU) and has no effect because all sectors are uniform size.

Quad Data Width (QUAD) CR1[1]: When set to ‘1’, this bit switches the data width of the device to 4-bit Quad

mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not monitored for their

normal functions and are internally set to high (inactive). The commands for Serial, Dual Output, and Dual I/O

Read still function normally but, there is no need to drive WP# and Hold# inputs for those commands when

switching between commands using different data path widths. The QUAD bit must be set to ‘1’ when using Read

Quad Out, Quad I/O Read, and Quad Page Program commands. The QUAD bit is nonvolatile.

Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to ‘1’, locks the current state of the BP2–0 bits in

Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This

prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains cleared to logic 0 the

other bits of the Configuration Register, including FREEZE, are writable, and the OTP address space is

programmable. Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off

to power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit. The FREEZE bit

is volatile and the default state of FREEZE after power-on is 0. The FREEZE bit can be set in parallel with updating

other values in CR1 by a single WRR command.

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8.6.3

Status Register 2 (SR2)

Related Commands: Read Status Register 2 (RDSR2 07h), Write Registers (WRR 01h). The Status Register 2 OTP

bits can be changed using the WRR command with 24 input cycles.

Table 25

Status Register 2 (SR2)

Default

state

Bits Field name

Function

Type

Description

1 = 256 KB Erase (Uniform sectors).

0 = 64 KB Erase (Hybrid 4-KB / 64-KB

sectors).

7

D8h_O

Block Erase Size

OTP

0

6

5

02h_O

Page Buffer Wrap

IO3 Reset

OTP

0

1 = Wrap at 512B 0 = Wrap at 256B.

1 = IO3 alternate function is RESET#.

0 = IO3 alternate function is HOLD#.

IO3R_O

4

3

2

RFU

Reserved

0

Reserved for Future Use.

Volatile,

1 = In Erase Suspend mode.

1

0

ES

PS

Erase Suspend

0

Read only

0 = Not in Erase Suspend mode.

Volatile,

Read only

1 = In Program Suspend mode.

0 = Not in Program Suspend mode.

Program Suspend

D8h SR2[7]: This bit controls the area erased by the D8h instruction. The D8h instruction can be used to erase

64-KB or 256-KB size and aligned blocks. The option to erase 256-KB blocks in the lower density family members

allows for consistent software behavior across all densities that can ease migration between different densities.

When the default 64-KB erase option is in use the flash memory array has a hybrid of sixteen 4-KB sectors at the

top or bottom of the array with all other sectors being 64 KB. Individual 4-KB sectors are erased by the 20h

instruction. A 64-KB block of 4-KB sectors or an individual 64-KB sector can be erased by the D8h instruction.

When the 256-KB option is in use, the flash memory array is treated as uniform 256-KB blocks that are individually

erased by the D8h instruction.

The desired state of this bit (D8h_O) must be selected during the initial configuration of the device during system

manufacture - before the first program or erase operation on the main flash array is performed. D8h_O must not

be programmed after programming or erasing is done in the main flash array.

02h SR2[6]: This bit controls the page programming buffer address wrap point. Legacy SPI devices generally have

used a 256-byte page programming buffer and defined that if data is loaded into the buffer beyond the 255-byte

location, the address at which additional bytes are loaded would be wrapped to address 0 of the buffer. The FL-S

Family provides a 512-byte page programming buffer that can increase programming performance. For legacy

software compatibility, this configuration bit provides the option to continue the wrapping behavior at the

256-byte boundary or to enable full use of the available 512-byte buffer by not wrapping the load address at the

256-byte boundary.

IO3 Reset Nonvolatile SR2[5]: This bit controls the POR, hardware reset, or software reset state of the IO3 signal

behavior. Most legacy SPI devices do not have a hardware reset input signal due to the limited signal count and

connections available in traditional SPI device packages. The S25FL127S device provides the option to use the

IO3 signal as a hardware reset input when the IO3 signal is not in use for transferring information between the

host system and the memory. This OTP IO3 Reset configuration bit enables the device to start immediately (boot)

with IO3 enabled for alternate use as a RESET# signal. When left in the default state, the IO3 signal has an alternate

use as HOLD#.

Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend

mode. This is a status bit that cannot be written. When Erase Suspend bit is set to ‘1’, the device is in erase

suspend mode. When Erase Suspend bit is cleared to 0, the device is not in erase suspend mode. Refer to “Erase

Suspend and Resume commands (ERSP 75h or ERRS 7Ah)” on page 116 for details about the Erase

Suspend/Resume commands.

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Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program

Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to ‘1’, the device is in

program suspend mode. When the Program Suspend bit is cleared to 0, the device is not in program suspend

mode. Refer to “Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)” on page 112 for details.

8.6.4

AutoBoot Register

Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).

The AutoBoot Register provides a means to automatically read boot code as part of the power on reset, hardware

reset, or software reset process.

Table 26

AutoBoot Register

Default

state

Bits Field name

Function

Type

Description

AutoBoot Start

Address

512-byte boundary address for the start of

boot code access

Number of initial delay cycles between

CS# going LOW and the first bit of boot

code being transferred

31to9

8 to 1

0

ABSA

ABSD

ABE

Nonvolatile 000000h

AutoBoot Start

Delay

Nonvolatile

00h

0

1 = AutoBoot is enabled

0 = AutoBoot is not enabled

AutoBoot Enable Nonvolatile

8.6.5

Bank Address Register

Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h)

and Bank Register Write (BRWR 17h).

The Bank Address register supplies additional high order bits of the main flash array byte boundary address for

legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of

address (above A23) for all 3-byte address commands when EXTADD = 0. The Bank Address is not used when

EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.

Table 27

Bank Address Register (BAR)

Default

state

Bits Field name

Function

Type

Description

1 = 4 byte (32 bits) addressing required

from command.

0 = 3 byte (24 bits) addressing from

command + Bank Address.

Extended Address

Enable

7

EXTADD

Volatile

0b

6 to 2

1

0

RFU

BA25

BA24

Reserved

Bank Address

Volatile

00000b Reserved for Future Use.

0

RFU.

Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By default

(power up reset, hardware reset, and software reset), it is cleared to 0 for 3 bytes (24 bits) of address. When set to

1, the legacy commands will require 4 bytes (32 bits) for the address field. This is a volatile bit.

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8.6.6

ECC Status Register (ECCSR)

Related Commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable nonvolatile bits. All

defined bits are volatile read only status. The default state of these bits are set by hardware. See “Automatic

ECC” on page 108.

The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read

command is written followed by an ECC unit address. The contents of the status register then indicates, for the

selected ECC unit, whether there is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes

of data, or that ECC is disabled for that ECC unit.

Table 28

ECC Status Register (ECCSR)

Default

state

Bits Field name

Function

Type

Description

7 to 3

2

RFU

Reserved

0

Reserved for Future Use

1 = Single Bit Error found in the ECC unit

eight bit error correction code

0 = No error.

Volatile,

Read only

EECC

Error in ECC

0

1 = Single Bit Error corrected in ECC unit

Error in ECC unit

data

Volatile,

1

0

EECCD

ECCDI

0

data.

Read only

0 = No error.

1 = ECC is disabled in the selected ECC

unit.

0 = ECC is enabled in the selected ECC unit.

Volatile,

Read only

ECC Disabled

ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC

unit data. ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures

and ECC is enabled.

ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to

another. These bits should be treated as “don’t care” and ignored by any software reading status.

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Address space maps

8.6.7

ASP Register (ASPR)

Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).

The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector

Protection (ASP) features.

Table 29

ASP Register (ASPR)

Default

State

Bits Field Name

Function

Type

Description

15to9

RFU

Reserved

OTP

1

Reserved for Future Use.

8

7

6

5

4

3

Note [33] Reserved for Future Use.

1

Reserved for Future Use.

Note [33] Reserved for Future Use.

0 = Password Protection Mode

Password

Protection Mode

Lock Bit

permanently enabled.

2

1

PWDMLB

OTP

1

1 = Password Protection Mode not

permanently enabled.

0 = Persistent Protection Mode

Persistent

Protection Mode

Lock Bit

permanently enabled.

PSTMLB

RFU

OTP

1

1 = Persistent Protection Mode not

permanently enabled.

0

Reserved

Note [33] Reserved for Future Use.

Note

33.Default value depends on ordering part number, see “Initial delivery state” on page 167.

Reserved for Future Use (RFU) ASPR[15:3, 0].

Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection

Mode is permanently selected.

Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection

Mode is permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to 0.

When the ASP protection mode is selected by programming either ASPR[2] or ASPR[1], certain OTP configuration

bits are locked and permanently protected from further programming. The bits protected are:

• SR2[7:5]

• ASPR

• PASS

The OTP configuration must be selected before selecting the ASP protection mode.

Attempting to program the listed OTP configuration bits when ASPR[2:1] is not = 11b will result in a programming

error with P_ERR (SR1[6]) set to 1.

The ASP protection mode should be selected during system configuration to ensure that a malicious program

does not select an undesired protection mode at a later time. By locking all the protection configuration via the

ASP mode selection, later alteration of the protection methods by malicious programs is prevented.

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8.6.8

Password Register (PASS)

Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).

Table 30

Bits

Password Register (PASS)

Field

Function

Type

Default State

Description

Name

Nonvolatile OTP storage of 64-bit

password. The password is no longer

Hidden

Password

63to0

PWD

OTP

FFFFFFFF–FFFFFFFFh readable after the password protection

mode is selected by programming ASP

register bit 2 to 0.

8.6.9

PPB Lock Register (PPBL)

Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h).

Table 31

Bits

PPB Lock Register (PPBL)

Field

Function

Type

Default State

Description

Name

7 to 1

RFU

Reserved Volatile

00h

Reserved for Future Use

Persistent Protection 0 = PPB array protected until next power

Mode = 1 cycle or hardware reset

Password Protection 1 = PPB array may be programmed or

Mode = 0 erased.

Protect PPB

Volatile

Array

0

PPBLOCK

8.6.10

PPB Access Register (PPBAR)

Related Commands: PPB Read (PPBRD E2h), PPB Program (PPBP E3), PPB Erase (PPBE E4).

Table 32

PPB Access Register (PPBAR)

Default

State

Bits Field Name

Function

Type

Description

00h = PPB for the sector addressed by the

PPBRD or PPBP command is programmed

to ‘0’, protecting that sector from

program or erase operations.

FFh = PPB for the sector addressed by the

PPBRD or PPBP command is erased to ‘1’,

not protecting that sector from program

or erase operations.

Read or Program

per sector PPB

7 to 0

PPB

Nonvolatile

FFh

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8.6.11

DYB Access Register (DYBAR)

Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBWR E1h).

Table 33

DYB Access Register (DYBAR)

Default

State

Bits Field Name

Function

Type

Description

00h = DYB for the sector addressed by the DYBRD

or DYBP command is cleared to ‘0’, protecting

that sector from program or erase operations.

FFh = DYB for the sector addressed by the DYBRD

or DYBP command is set to ‘1’, not protecting that

sector from program or erase operations.

Read or

Write per

sector DYB

7 to 0

DYB

Volatile

FFh

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9

Data protection

9.1

Secure silicon region (OTP)

The device has a 1024-byte one time program (OTP) address space that is separate from the main flash array. The

OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with

the system CPU/ASIC to prevent device substitution. See “OTP address space” on page 55, “One Time Program

Array commands” on page 119, and “OTP Read (OTPR 4Bh)” on page 119.

9.1.1

Reading OTP memory space

The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-KB OTP

address range will yield indeterminate data.

9.1.2

Programming OTP memory space

The protocol of the OTP programming command is the same as Page Program. The OTP Program command can

be issued multiple times to any given OTP address, but this address space can never be erased.

Automatic ECC is programmed on the first programming operation to each 16-byte region. Programming within

a 16-byte region more than once disables the ECC. It is recommended to program each 16-byte portion of each

32-byte region once so that ECC remains enabled to provide the best data integrity.

The valid address range for OTP Program is depicted in Figure 44. OTP Program operations outside the valid OTP

address range will be ignored and the WEL in SR1 will remain high (set to ‘1’). OTP Program operations while

FREEZE = 1 will fail with P_ERR in SR1 set to 1.

9.1.3

Infineon programmed random number

Infineon standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF)

with a 128-bit random number using the Linear Congruential Random Number method. The seed value for the

algorithm is a random number concatenated with the day and time of tester insertion.

9.1.4

Lock bytes

The LSb of each Lock byte protects the lowest address region related to the byte, the MSb protects the highest

address region related to the byte. The next higher address byte similarly protects the next higher 8 regions. The

LSb bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest address region. In other

words, the LSb of location 0x10 protects all the Lock Bytes and RFU bytes in the lowest address region from

further programming. See “OTP address space” on page 55.

9.2

Write Enable command

The Write Enable (WREN) command must be written prior to any command that modifies nonvolatile data. The

WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to ‘0’ (disables writes) during

power-up, hardware reset, or after the device completes the following commands:

• Reset

• Page Program (PP)

• Sector Erase (SE)

• Bulk Erase (BE)

• Write Disable (WRDI)

• Write Registers (WRR)

• Quad-input Page Programming (QPP)

• OTP Byte Programming (OTPP)

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9.3

Block protection

The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register

TBPROT bit can be used to protect an address range of the main flash array from program and erase operations.

The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range

is selected by the TBPROT bit of the Configuration Register.

Table 34

Upper array start of protection (TBPROT = 0)

Status register content

Protected memory

(KB)

Protected fraction

of memory array

FL127S

128 Mb

BP2

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

256

512

1024

2048

4096

8192

16384

Upper 64th

Upper 32nd

Upper 16th

Upper 8th

Upper 4th

Upper Half

All Sectors

Table 35

Lower array start of protection (TBPROT = 1)

Status register content

Protected memory

(KB)

Protected fraction

of memory array

FL127S

128 Mb

BP2

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

256

512

1024

2048

4096

8192

16384

Lower 64th

Lower 32nd

Lower 16th

Lower 8th

Lower 4th

Lower Half

All Sectors

When Block Protection is enabled (i.e., any BP2–0 are set to 1), advanced sector protection (ASP) can still be used

to protect sectors not protected by the Block Protection scheme. In the case that both ASP and block protection

are used on the same sector the logical OR of ASP and block protection related to the sector is used.

Recommendation: ASP and block protection should not be used concurrently. Use one or the other, but not both.

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Data protection

9.3.1

Freeze bit

Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and

the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once the FREEZE

bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the

FREEZE bit is cleared to logic 0 the status register BP bits and the TBPROT bit of the Configuration Register are

writable. The FREEZE bit also protects the entire OTP memory space from programming when set to 1. Any

attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no error status is set.

9.3.2

Write Protect signal

The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide hardware

input signal controlled protection. When WP# is LOW and SRWD is set to 1 the Status and Configuration register

is protected from alteration. This prevents disabling or changing the protection defined by the Block Protect bits.

See “Status Register 1 (SR1)” on page 58.

9.4

Advanced sector protection

Advanced sector protection (ASP) is the name used for a set of independent hardware and software methods

used to disable or enable programming or erase operations, individually, in any or all sectors. An overview of

these methods is shown in Figure 45.

Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each

sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. Refer to “Block

protection” on page 70 for full details of the BP2–0 bits.

ASP Register

One Time Programmable

Password Method Persistent Method

(ASPR[2]=0)

(ASPR[1]=0)

6.) Password Method requires a

password to set PPB Lock to “1”

to enable program or erase of

PPB bits

7.) Persistent Method only allows

PPB Lock to be cleared to “0” to

prevent program or erase of PPB

bits. Power off or hardware reset

required to set PPB Lock to “1”

64-bit Password

(One Time Protect)

4.) PPB Lock bit is volatile and

defaults to “1” (persistent

mode).or “0” (password mode)

upon reset

PBB Lock Bit

“0” = PPBs locked

“1”=PPBs unlocked

5.) PPB Lock = “0” locks all PPBs

to their current state

Persistent

Protection Bit

(PPB)

Dynamic

Protection Bit

(DYB)

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

PPB 1

PPB 2

DYB 0

DYB 1

DYB 2

Sector N-2

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

-

Sector N 1

Sector N

3.) DYB are volatile bits

1.) N = Highest Address Sector

a sector is protected if its PPB =”0”

or its DYB = “0”

PPB are programmed individually

but erased as a group

2.)

Figure 45

Advanced sector protection overview

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Data protection

Every main flash array sector has a nonvolatile (PPB) and a volatile (DYB) protection bit associated with it. When

either bit is 0, the sector is protected from program and erase operations.

The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for

managing the state of the PPB Lock bit, Persistent Protection and Password Protection.

The Persistent Protection method sets the PPB Lock bit to 1 during POR, or Hardware Reset so that the PPB bits

are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB. There is

no command in the Persistent Protection method to set the PPB Lock bit to ‘1’, therefore the PPB Lock bit will

remain at ‘0’ until the next power-off or hardware reset. The Persistent Protection method allows boot code the

option of changing sector protection by programming or erasing the PPB, then protecting the PPB from further

change for the remainder of normal system operation by clearing the PPB Lock bit to ‘0’. This is sometimes called

Boot-code controlled sector protection.

The Password method clears the PPB Lock bit to ‘0’ during POR, or Hardware Reset to protect the PPB. A 64 bit

password may be permanently programmed and hidden for the password method. A command can be used to

provide a password for comparison with the hidden password. If the password matches, the PPB Lock bit is set

to ‘1’ to unprotect the PPB. A command can be used to clear the PPB Lock bit to ‘0’. This method requires use of

a password to control PPB protection.

The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so

as to permanently select the method used.

9.4.1

ASP Register

The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features.

See Table 29.

As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors

unprotected, when power is applied. The device programmer or host system must then choose which sector

protection method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits, locks

the part permanently in the selected mode:

• ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.

• ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.

• ASPR[2:1] = 01 = Password Protection Mode permanently selected.

• ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to ‘0’ results in a programming failure.

ASP register programming rules:

• If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock

Bits.

• Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from

programming and no further changes to the ASP register is allowed.

The programming time of the ASP Register is the same as the typical page programming time. The system can

determine the status of the ASP register programming operation by reading the WIP bit in the Status Register.

See “Status Register 1 (SR1)” on page 58 for information on WIP.

After selecting a sector protection method, each sector can operate in each of the following states:

• Dynamically Locked — A sector is protected and can be changed by a simple command.

• Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is ‘0’.

• Unlocked — The sector is unprotected and can be changed by a simple command. The Block Protection bits

may be used to lock a sector/sectors.

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9.4.2

Persistent protection bits

The persistent protection bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related

to each sector. When a PPB is ‘0’, its related sector is protected from program and erase operations. The PPB are

programmed individually but must be erased as a group, similar to the way individual words may be programmed

in the main array but an entire sector must be erased at the same time. The PPB have the same program and erase

endurance as the main flash memory array. Preprogramming and verification prior to erasure are handled by the

device.

Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector

erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status register.

Reading of a PPB bit requires the initial access time of the device.

Notes

• Each PPB is individually programmed to ‘0’ and all are erased to ‘1’ in parallel.

• If the PPB Lock bit is ‘0’, the PPB Program or PPB Erase command does not execute and fails without

programming or erasing the PPB.

• The state of the PPB for a given sector can be verified by using the PPB Read command.

9.4.3

Dynamic protection bits

Dynamic protection bits are volatile and unique for each sector and can be individually modified. DYB only

control the protection for sectors that have their PPB set to ‘1’. By issuing the DYB Write command, a DYB is

cleared to ‘0’ or set to ‘1’, thus placing each sector in the protected or unprotected state respectively. This feature

allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of

protection when changes are needed. The DYBs can be set or cleared as often as needed as they are volatile bits.

9.4.4

PPB Lock Bit (PPBL[0])

The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to ‘0’, it locks all PPBs and when set to

‘1’, it allows the PPBs to be changed.

The PLBWR command is used to clear the PPB Lock bit to ‘0’. The PPB Lock Bit must be cleared to ‘0’ only after

all the PPBs are configured to the desired settings.

In Persistent Protection mode, the PPB Lock is set to ‘1’ during POR or a hardware reset. When cleared to ‘0’, no

software command sequence can set the PPB Lock bit to ‘1’, only another hardware reset or power-up can set

the PPB Lock bit.

In the Password Protection mode, the PPB Lock bit is cleared to ‘0’ during POR or a hardware reset. The PPB Lock

bit can only be set to ‘1’ by the Password Unlock command.

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9.4.5

Sector protection states summary

Each sector can be in one of the following protection states:

• Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection

state defaults to unprotected after a power cycle, software reset, or hardware reset. The Block Protection bits

may be used to protect a sector/sectors.

• Dynamically Locked — A sector is protected and protection can be changed by a simple command. The

protection state is not saved across a power cycle or reset.

• Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to 1.

The protection state is nonvolatile and saved across a power cycle or reset. Changing the protection state

requires programming and or erase of the PPB bits.

Table 36

Sector protection states

Protection bit values

Sector state

PPB lock

PPB

1

0

1

0

DYB

1

0

1

0

1

0

1

0

1

0

Unprotected – PPB and DYB are changeable

Protected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB not changeable, DYB is changeable

9.4.6

Persistent Protection mode

The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits

are unprotected. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock

bit to 0 to protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain

at 0 until the next power-off or hardware reset.

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9.4.7

Password Protection mode

Password Protection mode allows an even higher level of security than the Persistent Sector Protection Mode,

by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password requirement, after

power up and hardware reset, the PPB Lock bit is cleared to 0 to ensure protection at power-up. Successful

execution of the Password Unlock command by entering the entire password sets the PPB Lock bit to 1, allowing

for sector PPB modifications.

Password protection notes:

• Once the Password is programmed and verified, the Password Mode (ASPR[2] = 0) must be set in order to prevent

reading the password.

• The Password Program Command is only capable of programming “0”s. Programming a 1 after a cell is

programmed as a 0 results in the cell left as a 0 with no programming error set.

• The password is all 1’s when shipped from Cypress. It is located in its own memory space and is accessible

through the use of the Password Program and Password Read commands.

• All 64-bit password combinations are valid as a password.

• The Password mode, once programmed, prevents reading the 64-bit password and further password

programming. All further program and read commands to the password region are disabled and these

commands are ignored. There is no means to verify what the password is after the Password Mode Lock Bit is

selected. Password verification is only allowed before selecting the Password Protection mode.

• The Protection mode Lock Bits are not erasable.

• The exact password must be entered in order for the unlocking function to occur. If the password unlock

command provided password does not match the hidden internal password, the unlock operation fails in the

same manner as a programming operation on a protected sector. The P_ERR bit is set to one, the WIP Bit remains

set, and the PPB Lock bit remains cleared to ‘0’.

• The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it

take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an

attempt to correctly match a password. The Read Status Register 1 command may be used to read the WIP bit

to determine when the device has completed the password unlock command or is ready to accept a new

command. When a valid password is provided the password unlock command does not insert the 100 µs delay

before returning the WIP bit to 0.

• If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.

• ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced

to the boot sector address. ECC status is shown in that sector while read protection mode is active.

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Commands

10

Commands

All communication between the host system and S25FL127S memory devices is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to

the host serially on SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be

returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or,

four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1

or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Commands are structured as follows:

• Each command begins with an eight bit (byte) instruction.

• The instruction may be standalone or may be followed by address bits to select a location within one of several

address spaces in the device. The address may be either a 24-bit or 32-bit address.

• The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data

information to be done one, two, or four bits in parallel. This enables a trade off between the number of signal

connections (IO bus width) and the speed of information transfer. If the host system can support a two or four

bit wide IO bus the memory performance can be increased by using the instructions that provide parallel two

bit (dual) or parallel four bit (quad) transfers.

• The width of all transfers following the instruction are determined by the instruction sent.

• All single bits or parallel bit groups are transferred in most to least significant bit order.

• Some instructions send instruction modifier (mode) bits following the address to indicate that the next

command will be of the same type with an implied, rather than an explicit, instruction. The next command thus

does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send

each command when the same command type is repeated in a sequence of commands.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Read latency may be zero to several SCK cycles (also referred to as dummy cycles).

• All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted

into the device with the most significant byte first. All data is transferred with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions. While a program, erase, or write operation is in progress, it is recommended to check that the

Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to ensure the new command can

be accepted.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

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Commands

• Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces

of the host system and the memory device generally handle the details of signal relationships and timing. For

this reason, signal relationships and timing are not covered in detail within this software interface focused

section of the document. Instead, the focus is on the logical sequence of bits transferred in each command

rather than the signal timing and relationships. Following are some general signal relationship descriptions to

keep in mind. For additional information on the bit level format and signal timing relationships of commands,

see “Command protocol” on page 17.

- The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide

transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately

drive the IO0-IO3 signals during Dual and Quad transfers.

- All commands begin with the host selecting the memory by driving CS# LOW before the first rising edge of

SCK. CS# is kept LOW throughout a command and when CS# is returned high the command ends. Generally,

CS# remains LOW for eight bit transfer multiples to transfer byte granularity information. Some commands

will not be accepted if CS# is returned high not at an 8 bit boundary.

10.1

Command set summary

Extended addressing

10.1.1

To accommodate addressing above 128 Mb, there are three options:

1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.

Table 37

Instructions and corresponding details

Instruction name

Description

Code (Hex)

4FAST_READ

4READ

4DOR

Read Fast (4-byte Address)

Read (4-byte Address)

0C

13

3C

6C

BC

EC

12

34

Read Dual Out (4-byte Address)

Read Quad Out (4-byte Address)

Dual I/O Read (4-byte Address)

Quad I/O Read (4-byte Address)

Page Program (4-byte Address)

4QOR

4DIOR

4QIOR

4PP

4QPP

Quad Page Program (4-byte

Address)

4P4E

4SE

Parameter 4-KB Erase (4-byte

Address)

Erase 64/256 KB (4-byte Address)

21

DC

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Commands

2. For backward compatibility to the 3-byte address instructions, the standard instructions can be used in

conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0

(following power up and hardware reset), to enable 3-byte (24-bit) addressing. When set to 1, the legacy

commands are changed to require 4 bytes (32 bits) for the address field. The following instructions can be used

in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes of address field.

Table 38

Instructions and corresponding details

Instruction name Description

Code (Hex)

READ

FAST_READ

DOR

Read (3-byte Address)

Read Fast (3-byte Address)

03

0B

3B

6B

BB

EB

02

32

Read Dual Out (3-byte Address)

Read Quad Out (3-byte Address)

Dual I/O Read (3-byte Address)

Quad I/O Read (3-byte Address)

Page Program (3-byte Address)

QOR

DIOR

QIOR

PP

QPP

Quad Page Program (3-byte

Address)

P4E

SE

Parameter 4-KB Erase (3-byte

Address)

Erase 64 / 256 KB (3-byte Address)

20

D8

3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction

with the Bank Address Register:

a. The Bank Address Register is used to switch between 128-Mb (16-MB) banks of memory, The standard 3-byte

address selects an address within the bank selected by the Bank Address Register.

i. The host system writes the Bank Address Register to access beyond the first 128 Mb of memory.

ii. This applies to read, erase, and program commands.

b. The Bank Register provides the high order (4th) byte of address, which is used to address the available

memory at addresses greater than 16 MB.

c. Bank Register bits are volatile.

i. On power up, the default is Bank0 (the lowest address 16 MB).

d. For Read, the device will continuously transfer out data until the end of the array.

i. There is no bank to bank delay.

ii. The Bank Address Register is not updated.

iii.The Bank Address Register value is used only for the initial address of an access.

Table 39

Bank address map

Bank address register bits

Bank

Memory array address range (Hex)

00000000 00FFFFFF

Bit 1

Bit 0

0

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Commands

10.1.2

Command summary sorted by function

Table 40

S25FL127S command set (sorted by function)

Command

Maximum

frequency

(MHz)

Instruction

value (Hex)

Function

Command description

name

READ_ID

(REMS)

Read Electronic Manufacturer Signature

90

9F

5A

108

Read ID (JEDEC Manufacturer ID and JEDEC

CFI)

Read JEDEC Serial Flash Discoverable

Parameters

RDID

Read Device

Identification

RSFDP

RES

RDSR1

RDSR2

RDCR

WRR

Read Electronic Signature

Read Status Register 1

Read Status Register 2

Read Configuration Register 1

Write Register (Status-1, Configuration-1)

Write Disable

AB

05

07

35

01

04

06

50

108

WRDI

WREN

Write Enable

Clear Status Register 1 - Erase/Prog. Fail

Reset

ECC Read (4-byte address)

CLSR

30

18

108

ECCRD

108

(QUAD=0)

108

(QUAD=1)

Register Access

ABRD

AutoBoot Register Read

14

ABWR

BRRD

BRWR

AutoBoot Register Write

Bank Register Read

Bank Register Write

15

16

17

108

Bank Register Access

(Legacy Command formerly used for Deep

Power Down)

BRAC

B9

108

DLPRD

PNVDLR

WVDLR

Data Learning Pattern Read

Program NV Data Learning Register

Write Volatile Data Learning Register

41

43

4A

108

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Commands

Table 40

Function

S25FL127S command set (sorted by function) (Continued)

Maximum

frequency

(MHz)

Command

name

Instruction

value (Hex)

Command description

READ

4READ

Read (3- or 4-byte address)

Read (4-byte address)

03

13

0B

0C

3B

3C

6B

6C

BB

BC

EB

EC

02

12

32

50

FAST_READ Fast Read (3- or 4-byte address)

4FAST_READ Fast Read (4-byte address)

108

80

DOR

4DOR

QOR

4QOR

DIOR

4DIOR

QIOR

4QIOR

PP

Read Dual Out (3- or 4-byte address)

Read Dual Out (4-byte address)

Read Quad Out (3- or 4-byte address)

Read Quad Out (4-byte address)

Dual I/O Read (3- or 4-byte address)

Dual I/O Read (4-byte address)

Quad I/O Read (3- or 4-byte address)

Quad I/O Read (4-byte address)

Page Program (3- or 4-byte address)

Page Program (4-byte address)

Read Flash Array

4PP

QPP

Quad Page Program (3- or 4-byte address)

Program Flash

Array

Quad Page Program - Alternate instruction

(3- or 4-byte address)

QPP

38

80

4QPP

PGSP

PGRS

Quad Page Program (4-byte address)

Program Suspend

Program Resume

34

85

8A

80

108

Parameter 4-KB, sector Erase (3- or 4-byte

address)

Parameter 4-KB, sector Erase (4-byte

address)

P4E

20

21

108

4P4E

BE

SE

Bulk Erase

60

C7

D8

DC

75

7A

42

4B

108

Erase Flash Array

Bulk Erase (alternate command)

Erase 64 KB or 256 KB (3- or 4-byte address)

Erase 64 KB or 256 KB (4-byte address)

Erase Suspend

Erase Resume

OTP Program

4SE

ERSP

ERRS

OTPP

OTPR

One Time Program

Array

OTP Read

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Commands

Table 40

Function

S25FL127S command set (sorted by function) (Continued)

Maximum

frequency

(MHz)

Command

name

Instruction

value (Hex)

Command description

DYBRD

DYBWR

PPBRD

PPBP

PPBE

ASPRD

ASPP

PLBRD

PLBWR

PASSRD

PASSP

PASSU

RESET

MBR

DYB Read

DYB Write

PPB Read

PPB Program

PPB Erase

E0

E1

E2

E3

E4

2B

2F

A7

A6

E7

E8

E9

F0

FF

108

ASP Read

ASP Program

Advanced Sector

Protection

PPB Lock Bit Read

PPB Lock Bit Write

Password Read

Password Program

Password Unlock

Software Reset

Mode Bit Reset

Reset

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Commands

10.1.3

Read Device identification

There are multiple commands to read information about the device manufacturer, device type, and device

features. SPI memories from different vendors have used different commands and formats for reading

information about the memories. The FL-S Family supports the three most common device information

commands.

10.1.4

Register read or write

There are multiple registers for reporting embedded operation status or controlling device configuration

options. There are commands for reading or writing these registers. Registers contain both volatile and

nonvolatile bits. Nonvolatile bits in registers are automatically erased and programmed as a single (write)

operation.

10.1.4.1

Monitoring operation status

The host system can determine when a write, program, erase, suspend or other embedded operation is complete

by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register 1 command

provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register

indicate whether the most recent program or erase command has not completed successfully. When P_ERR or

E_ERR bits are set to one, the WIP bit will remain set to 1 indicating the device remains busy and unable to receive

most new operation commands. Only status read (RDSR1 05h), status clear (CLSR 30h), write disable (WRDI 04h),

and software reset (RESET 0Fh) are valid commands when P_ERR or E_ERR is set to 1. A Clear Status Register

(CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby state. CLSR

clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, hardware reset, or software reset

(RESET) may be used to return the device to standby state.

10.1.4.2

Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing,

interface address length, and some aspects of data protection.

10.1.5

Read flash array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from

incrementally higher byte addresses until the host ends the data transfer by driving CS# input HIGH. If the byte

address reaches the maximum address of the memory array, the read will continue at address 0 of the array.

There are several different read commands to specify different access latency and data path widths.

• The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning

a single bit per SCK falling edge on the SO signal. This command has zero latency between the address and the

returning data but is limited to a maximum SCK rate of 50 MHz.

• Other read commands have a latency period between the address and returning data but can operate at higher

SCK frequencies. The latency depends on the configuration register latency code.

• The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data

returning a single bit per SCK falling edge on the SO signal and may operate up to 108 MHz.

• Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0 signal with

read data returning two bits, or four bits of data per SCK falling edge on the IO0–IO3 signals.

• Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data

returning two bits, or four bits of data per SCK falling edge on the IO0–IO3 signals.

10.1.6

Program flash array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page

Program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in

one operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing bits

from 0 to 1 requires an erase operation.

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Commands

10.1.7

Erase flash array

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1.

A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually

programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.

The Write Enable (WREN) command must precede an erase command.

10.1.8

OTP, block protection, and advanced sector protection

There are commands to read and program a separate OTP array for permanent data such as a serial number.

There are commands to control a contiguous group (block) of flash memory array sectors that are protected from

program and erase operations. There are commands to control which individual flash memory array sectors are

protected from program and erase operations.

10.1.9

Reset

There is a command to reset to the default conditions present after power on to the device. There is a command

to reset (exit from) the Enhanced Performance Read modes.

10.1.10

Reserved

Some instructions are reserved for future use. In this generation of the FL-S family, some of these command

instructions may be unused and not affect device operation, some may have undefined results.

Some commands are reserved to ensure that a legacy or alternate source device command is allowed without

affect. This allows legacy software to issue some commands that are not relevant for the current generation FL-S

Family with the assurance these commands do not cause some unexpected action.

Some commands are reserved for use in special versions of the FL-S not addressed by this document or for a

future generation. This allows new host memory controller designs to plan the flexibility to issue these command

instructions. The command format is defined if known at the time this document revision is published.

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Commands

10.2

Identification commands

Read Identification - REMS (Read_ID or REMS 90h)

10.2.1

The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also referred to

as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The command is initiated by shifting on SI the instruction code “90h” followed by a 24-bit address of 00000h.

Following this, the Manufacturer ID and the Device ID are shifted out on SO starting at the falling edge of SCK after

address. The Manufacturer ID and the Device ID are always shifted out with the MSb first. If the 24-bit address is

set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and

Device ID output data toggles between address 000000H and 000001H until terminated by a LOW to HIGH

transition on CS# input. The maximum clock frequency for the READ_ID command is 108 MHz.

CSS#

28 29 30 31

0

1

2

3

4

5

6

7

8

9

10

SCK

Instruction

90h

ADD (1)

23 22 21

MSB

3

2

1

0

SI

SO

High Impedance

CSS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

47

SCK

SI

Device ID

Manufacture ID

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

Figure 46

Table 41

READ_ID command sequence

Read_ID values

Device

Manufacturer ID (Hex)

Device ID (Hex)

S25FL127S

01

17

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Commands

10.2.2

Read Identification (RDID 9Fh)

The Read Identification (RDID) command provides read access to manufacturer identification, device

identification, and Common Flash Interface (CFI) information. The manufacturer identification is assigned by

JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by

Cypress.

The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a

vendor-specified software flash management program (driver) to be used for entire families of flash devices.

Software support can then be device-independent, JEDEC manufacturer ID independent, forward and

backward-compatible for the specified flash device families. System vendors can standardize their flash drivers

for long-term software compatibility by using the CFI values to configure a family driver from the CFI information

of the device in use.

Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on

execution of the program, erase, or write cycle that is in progress.

The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of

manufacturer identification, two bytes of device identification, extended device identification, and CFI

information will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See “ID-CFI

address space” on page 54 for the detail description of the ID-CFI contents.

Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The

RDID command sequence is terminated by driving CS# to the logic high state anytime during data output.

The maximum clock frequency for the RDID command is 108 MHz.

C S#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

32

34

33

655

652 653 654

S CK

Instruction

SI

Extended Device Information

Manufacturer / Device Identification

High Impedance

644

645

646

1 647

0

1

2

20

21

22

23

24

25

26

SO

Figure 47

Read Identification (RDID) command sequence

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Commands

10.2.3

Read Electronic Signature (RES) (ABh)

The RES command is used to read a single byte Electronic Signature from SO. RES is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The RES instruction is shifted in followed by three dummy bytes onto SI. After the last bit of the three dummy

bytes are shifted into the device, a byte of Electronic Signature will be shifted out of SO. Each bit is shifted out by

the falling edge of SCK. The maximum clock frequency for the RES command is 50 MHz.

The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.

The RES command sequence is terminated by driving CS# to the logic high state anytime during data output.

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCK

3 Dummy

Bytes

Instruction

23 22 21

MSB

3

2

1

0

SI

Electonic ID

High Impedance

7

6

5

4

3

2

1

0

SO

MSB

Figure 48

Read Electronic Signature (RES) command sequence

Table 42

RES values

Device

Device ID (Hex)

S25FL127S

17

10.2.4

Read Serial Flash Discoverable Parameters (RSFDP 5Ah)

The command is initiated by shifting on SI the instruction code “5Ah”, followed by a 24-bit address of 000000h,

followed by eight dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK

after the eight dummy cycles. The SFDP bytes are always shifted out with the MSb first. If the 24-bit address is set

to any other value, the selected location in the SFDP space is the starting point of the data read. This enables

random access to any parameter in the SFDP space. The maximum clock frequency for the RSFDP command is

108 MHz.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

23

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Address

Dummy Cycles

Data 1

Figure 49

RSFDP command sequence

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Commands

10.3

Register Access commands

Read Status Register 1 (RDSR1 05h)

10.3.1

The Read Status Register 1 (RDSR1) command allows the Status Register 1 contents to be read from SO. The

Status Register 1 contents may be read at any time, even while a program, erase, or write operation is in progress.

It is possible to read the Status Register 1 continuously by providing multiples of eight clock cycles. The status is

updated for each eight cycle read. The maximum clock frequency for the RDSR1 (05h) command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Instruction

SI

Status Register-1 Out

High Impedance

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SO

MSB

Figure 50

Read Status Register 1 (RDSR1) command sequence

10.3.2

Read Status Register 2 (RDSR2 07h)

The Read Status Register (RDSR2) command allows the Status Register 2 contents to be read from SO. The Status

Register 2 contents may be read at any time, even while a program, erase, or write operation is in progress. It is

possible to read the Status Register 2 continuously by providing multiples of eight clock cycles. The status is

updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Instruction

SI

7

6

5

4

3

2

1

0

Status Register-2 Out

High Impedance

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SO

MSB

Figure 51

Read Status Register 2 (RDSR2) command

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Commands

10.3.3

Read Configuration Register (RDCR 35h)

The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read from

SO. It is possible to read the Configuration Register continuously by providing multiples of eight clock cycles. The

Configuration Register contents may be read at any time, even while a program, erase, or write operation is in

progress.

CS#

SCLK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Register Read

Repeat Register Read

Figure 52

Read Configuration Register (RDCR) command sequence

10.3.4

Bank Register Read (BRRD 16h)

The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The

instruction is first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the

Bank Register continuously by providing multiples of eight clock cycles. The maximum operating clock frequency

for the BRRD command is 108 MHz.

CSS##

0

11

22

33

44

55

66

77

88

99

1100

1111

1122

1133

14 15

1166

17 18

1199

2200

21 22

2233

SCCKK

Instruuccttiioonn

7

66

55

44

3

22

11

00

SI

MMSSBB

Bank Register OOut

55 4

Bank Regiisstteer OOuut

55 4

High Impedance

7

66

3

22

11

00

SO

7

66

3

22

11

00

7

MSB

MSSBB

Figure 53

Read Bank Register (BRRD) command

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Commands

10.3.5

Bank Register Write (BRWR 17h)

The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address Register

(BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in BAR[7]. BAR

provides the high order addresses needed by devices having more than 128 Mb (16 MB), when using 3-byte

address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of

the addressing method and is not changing data in the flash memory, this command does not require the WREN

command to precede it.

The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length.

The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration Registers.

Any bank address bit reserved for the future should always be written as a 0.

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Bank Register In

14

15

SCK

Instruction

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 54

Bank Register Write (BRWR) command

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Commands

10.3.6

Bank Register Access (BRAC B9h)

The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but they are

both commands that are not present in legacy SPI memory devices. Host system SPI memory controller

interfaces may not be able to easily support such new commands. The Bank Register Access (BRAC) command

uses the same command code and format as the Deep Power Down (DPD) command that is available in legacy

SPI memories. The FL-S family does not support a DPD feature but assigns this legacy command code to the BRAC

command to enable write access to the Bank Address Register for legacy systems that are able to send the legacy

DPD (B9h) command.

When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write

Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used between

the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR command code

are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR command second data

byte are ignored. Following the WRR command the access to BAR is closed and the device interface returns to the

standby state. The combined BRAC followed by WRR command sequence has no affect on the value of the ExtAdd

bit (BAR[7]).

Commands other than WRR may immediately follow BRAC and execute normally. However, any command other

than WRR, or any other sequence in which CS# goes LOW and returns HIGH, following a BRAC command, will close

the access to BAR and return to the normal interpretation of a WRR command as a write to Status Register 1 and

the Configuration Register.

The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase suspend

states. This command sequence is illegal when the device is performing an embedded algorithm or when the

program (P_ERR) or erase (E_ERR) status bits are set to ‘1’.

CS#

0

1

2

3

4

5

6

7

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 55

BRAC (B9h) command sequence

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Commands

10.3.7

Write Registers (WRR 01h)

The Write Registers (WRR) command allows new values to be written to Status Register 1, Configuration Register,

and Status Register 2. Before the Write Registers (WRR) command can be accepted by the device, a Write Enable

(WREN) command must be received. After the Write Enable (WREN) command has been decoded successfully,

the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI.

The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation.

Any Status or Configuration Register bit that is:

• reserved for the future, must be written as a 0

• read only, is not affected by the value written to that bit

• OTP, may be written to ‘1’ but, if the value is already ‘1’, it cannot be written to ‘0’, it will remain ‘1’.

CS# must be driven to the logic high state after the eighth, sixteenth, or twenty-fourth bit of data has been

latched. If not, the Write Registers (WRR) command is not executed. If CS# is driven high after the eighth cycle

then only the Status Register 1 is written; after the sixteenth cycle both the Status and Configuration Registers

are written; after the twenty fourth cycle the Status Register 1, Configuration Register, and Status Register 2 are

written. When the configuration register QUAD bit CR[1] is ‘1’, only the WRR command formats with 16 or 24 data

bits may be used.

As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While

the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is ‘1’ during the self-timed Write Registers (WRR)

operation, and is ‘0’ when it is completed. When only changing the value of volatile bits, the operation is

completed in t_CStime (the WIP bit will be ‘0’ before a status read can be completed). When changing nonvolatile

bits, the WRR operation is completed in t_Wtime. When the Write Registers (WRR) operation is completed, the

Write Enable Latch (WEL) is set to ‘0’. The maximum clock frequency for the WRR command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Status Register In

14 15

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 56

Write Registers (WRR) command sequence – 8 data bits

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SPI Multi-I/O, 3.0 V

Commands

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13

Status Register In

14

15

16 17 18 19 20 21

Configuration Register In

22

23

SCK

Instruction

7

6

5

4

3

2

1

0

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 57

Write Registers (WRR) command sequence – 16 data bits

CS#

SCK

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SO

Phase

Instruction

Input Status Register-1

Input Status Register-2

Figure 58

Write Registers (WRR 01h) command sequence – 24 data bits

The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and

BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR) command also

allows the user to set the Status Register Write Disable (SRWD) bit to ‘1’ or ‘0’. The Status Register Write Disable

(SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.

When the Status Register Write Disable (SRWD) bit of the Status Register is ‘0’ (its initial delivery state), it is

possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to the logic HIGH

or logic LOW state.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two cases need to be

considered, depending on the state of Write Protect (WP#):

• If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration

Registers provided that the Write Enable Latch (WEL) bit has previously been set to ‘1’ by initiating a Write Enable

(WREN) command.

• If Write Protect (WP#) signal is driven to the logic LOW state, it is not possible to write to the Status and

Configuration Registers even if the Write Enable Latch (WEL) bit has previously been set to ‘1’ by a Write Enable

(WREN) command. Attempts to write to the Status and Configuration Registers are rejected, and are not

accepted for execution. As a consequence, all the data bytes in the memory area that are protected by the Block

Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected by WP#.

The WP# hardware protection can be provided:

• by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic LOW

state;

• or by driving Write Protect (WP#) signal to the logic LOW state after setting the Status Register Write Disable

(SRWD) bit to ‘1’.

The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state.

If WP# is permanently tied high, hardware protection of the BP bits can never be activated.

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Commands

Table 43

WP#

Block Protection modes

Memory content

Protected area Unprotected area

SRWD

bit

Mode

Write protection of registers

1

0

Status and Configuration Registers

are Writable (if WREN command

has set the WEL bit). The values in

the SRWD, BP2, BP1, and BP0 bits

and those in the Configuration

Register and Status Register 2 can

be changed.

Protected against Ready to accept

Page Program,

Quad Input

Page Program,

Quad Input

Software

Protected

Program, Sector

Erase, and Bulk

Erase

Program and

Sector Erase

commands

0

Status and Configuration Registers

are Hardware Write Protected. The Protected against

Ready to accept

Page Program or

Erase commands

Hardware values in the SRWD, BP2, BP1, and Page Program,

Protected BP0 bits and those in the Sector Erase, and

Configuration Register and Status Bulk Erase

Register 2 cannot be changed.

0

1

Notes

34.The Status Register originally shows 00h when the device is first shipped from Cypress to the customer.

35.Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP#

becomes IO2; therefore, it cannot be utilized.

The WRR command has an alternate function of loading the Bank Address Register if the command immediately

follows a BRAC command. See “Bank Register Access (BRAC B9h)” on page 90.

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Commands

10.3.8

Write Enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to a 1.

The Write Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to enable write,

program and erase commands.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI.

Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on

SI, the write enable operation will not be executed.

CS#

0

1

2

3

4

5

6

7

SCK

SI

Instruction

Figure 59

Write Enable (WREN) command sequence

10.3.9

Write Disable (WRDI 04h)

The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to a 0.

The Write Enable Latch (WEL) bit may be set to a 0 by issuing the Write Disable (WRDI) command to disable Page

Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and other

commands, that require WEL be set to 1 for execution. The WRDI command can be used by the user to protect

memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The WRDI

command is ignored during an embedded operation while WIP bit = 1.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI.

Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on

SI, the write disable operation will not be executed.

CS#

0

1

2

3

4

5

6

7

SCK

SI

Instruction

Figure 60

Write Disable (WRDI) command sequence

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

10.3.10

Clear Status Register (CLSR 30h)

The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It is not

necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will be accepted

even when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set.

The WEL bit will be unchanged after this command is executed.

CS#

0

1

2

3

4

5

6

7

SCK

SI

Instruction

Figure 61

Clear Status Register (CLSR) command sequence

10.3.11

ECC Status Register Read (ECCRD 18h)

To read the ECC Status Register, the command is followed by the ECC unit (32 bit) address, the four least

significant bits (LSb) of address must be set to zero. This is followed by eight dummy cycles. Then the 8-bit

contents of the ECC Register, for the ECC unit selected, are shifted out on SO 16 times, once for each byte in the

ECC Unit. If CS# remains LOW the next ECC unit status is sent through SO 16 times, once for each byte in the ECC

Unit, this continues until CS# goes HIGH. The maximum operating clock frequency for the ECC READ command

is 133 MHz. See “Automatic ECC” on page 108 for details on ECC unit.

CS#

0

7

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCK

32-Bit

Instruction

Dummy Byte

Address

SI

6

5

4

3

2

1

0

31 30 29

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 1

DATA OUT 2

High Impedance

SO

7

6

5

4

3

2

1

0

7

MSB

Figure 62

ECC Status Register Read command sequence

Datasheet

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Commands

10.3.12

AutoBoot

SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And,

in order to read boot code from an SPI device, the host memory controller or processor must supply the read

command from a hardwired state machine or from some host processor internal ROM code.

Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to

start reading boot code.

The AutoBoot feature allows the host memory controller to take boot code from an FL-S Family device

immediately after the end of reset, without having to send a read command. This saves 32 or more cycles and

simplifies the logic needed to initiate the reading of boot code.

• As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically

starts a read access from a pre-specified address. At the time the reset process is completed, the device is ready

to deliver code from the starting address. The host memory controller only needs to drive CS# signal from HIGH

to LOW and begin toggling the SCK signal. The FL-S Family device will delay code output for a pre-specified

number of clock cycles before code streams out.

- The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by

the host.

- The host cannot send commands during this time.

- If ABSD = 0, the maximum SCK frequency is 50 MHz.

- If ABSD > 0, the maximum SCK frequency is 108 MHz if the QUAD bit CR1[1] is 0 or 108 MHz if the QUAD bit is

set to 1.

• The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address

(ABSA) field of the AutoBoot Register which specifies a 512-byte boundary aligned location; the default address

is 00000000h.

- Data will continuously shift out until CS# returns HIGH.

• At any point after the first data byte is transferred, when CS# returns HIGH, the SPI device will reset to standard

SPI mode; able to accept normal command operations.

- A minimum of 1 byte must be transferred.

- AutoBoot mode will not initiate again until another power cycle or a reset occurs.

• An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.

The AutoBoot register bits are nonvolatile and provide:

• The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the ABSA field

is 23 bits for devices up to 32-Gbit.

• The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.

• The AutoBoot Enable.

If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the same

manner as a Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same manner as a

Read command.

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

0

-

n

n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9

Wait State

tWS

Don’t care or High Impedance

SI

DATA OUT 1

DATA OUT 2

High Impedance

7

6

5

4

3

2

1

0

7

SO

MSB

Figure 63

AutoBoot Sequence (CR1[1] = 0)

CS#

0

-

n

n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9

SCK

IO0

Wait State

tWS

High Impedance

4

0

4

0

4

0

4

0

4

DATA OUT 1

High Impedance

5

6

1

2

5

6

1

5

1

5

6

1

2

5

6

IO1

IO2

2

6

2

High Impedance

IO3

7

3

7

3

7

3

7

3

7

MSB

Figure 64

AutoBoot Sequence (CR1[1] = 1)

10.3.13

AutoBoot Register Read (ABRD 14h)

The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO,

least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register

continuously by providing multiples of 32 clock cycles. If the QUAD bit CR1[1] is cleared to 0, the maximum

operating clock frequency for ABRD command is 108 MHz. If the QUAD bit CR1[1] is set to 1, the maximum

operating clock frequency for ABRD command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11

37 38 39 40

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

AutoBoot Register

26 25 24

High Impedance

7

6

5

4

SO

MSB

Figure 65

AutoBoot Register Read (ABRD) command

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

10.3.14

AutoBoot Register Write (ABWR 15h)

Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by

the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,

most significant bit of each byte first. The ABWR data is 32 bits in length.

The ABWR command has status reported in Status Register 1 as both an erase and a programming operation. An

E_ERR or a P_ERR may be set depending on whether the erase or programming phase of updating the register

fails.

CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR command

is not executed. As soon as CS# is driven to the logic high state, the self-timed ABWR operation is initiated. While

the ABWR operation is in progress, Status Register 1 may be read to check the value of the Write-In Progress (WIP)

bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ABWR operation, and is a 0 when it is completed.

When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for

the ABWR command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37

38

39

SCK

Instruction

AutoBoot Register

SI

7

6

5

4

3

2

1

0

7

6

5

27

26

25

24

MSB

High Impedance

SO

Figure 66

AutoBoot Register Write (ABWR) command

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

10.4

Read memory array commands

Read commands for the main flash array provide many options for prior generation SPI compatibility or

enhanced performance SPI:

• Some commands transfer address one bit per rising edge of SCK and return data 1, 2, or 4 bits of data per rising

edge of SCK. These are called Read or Fast Read for 1 bit data; Dual Output Read for 2 bit data, and Quad Output

for 4 bit data.

• Some commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual I/O for

2 bit and Quad I/O for 4 bit.

All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The

instruction is followed by either a 3- or 4-byte address. Commands transferring address or data 2 or 4 bits per

clock edge are called Multiple I/O (MIO) commands. For FL-S Family devices at 256 Mb or higher density, the

traditional SPI 3-byte addresses are unable to directly address all locations in the memory array. These device

have a bank address register that is used with 3-byte address commands to supply the high order address bits

beyond the address from the host system. The default bank address is 0. Commands are provided to load and

read the bank address register. These devices may also be configured to take a 4-byte address from the host

system with the traditional 3-byte address commands. The 4-byte address mode for traditional commands is

activated by setting the External Address (EXTADD) bit in the bank address register to 1. In the FL127S, higher

order address bits above A23 in the 4-byte address commands, commands using Extended Address mode, and

the Bank Address Register are not relevant and are ignored because the flash array is only 128 Mb in size.

The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent

following the address bits. The mode bits indicate whether the command following the end of the current read

will be another read of the same type, without an instruction at the beginning of the read. These mode bits give

the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.

Some commands require delay cycles following the address or mode bits to allow time to access the memory

array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus

any data provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high

impedance during the dummy cycles. When MIO commands are used the host must stop driving the IO signals

(outputs are high impedance) before the end of last dummy cycle. The number of dummy cycles varies with the

SCK frequency or performance option selected via the Configuration Register 1 (CR1) Latency Code (LC). Dummy

cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are traditionally driven to a new

value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the memory on

the same falling edge of SCK that the host stops driving address or mode bits.

Each read command ends when CS# is returned HIGH at any point during data return. CS# must not be returned

HIGH during the mode or dummy cycles before data returns as this may cause mode bits to be captured

incorrectly; making it indeterminate as to whether the device remains in enhanced high performance read mode.

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

10.4.1

Read (Read 03h or 4READ 13h)

The instruction

• 03h (ExtAdd=0) is followed by a 3-byte address (A23–A0) or

• 03h (ExtAdd=1) is followed by a 4-byte address (A31–A0) or

• 13h is followed by a 4-byte address (A31–A0)

Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency

for the READ command is 50 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

A

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Address

Data 1

Data N

Figure 67

Read command sequence (READ 03h or 13h)^[36]

Note

36.A = MSb of address = 23 for ExtAdd = 0, or 31 for ExtAdd = 1 or command 13h.

Datasheet

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SPI Multi-I/O, 3.0 V

Commands

10.4.2

Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)

The instruction

• 0Bh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 0Bh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 0Ch is followed by a 4-byte address (A31–A0)

The address is followed by zero or eight dummy cycles depending on the latency code set in the Configuration

Register. The dummy cycles allow the device internal circuits additional time for accessing the initial address

location. During the dummy cycles the data value on SO is “don’t care” and may be high impedance. Then the

memory contents, at the address given, are shifted out on SO.

The maximum operating clock frequency for FAST READ command is 108 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

A

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Address

Dummy Cycles

Data 1

Figure 68

Fast Read (FAST_READ 0Bh or 0Ch) command sequence with read latency

CS#

SCK

SI

7

6

5

4

3

2

1

0

A

1

0

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Address

Data 1

Data N

Figure 69

Fast Read Command (FAST_READ 0Bh or 0Ch) sequence without read latency

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.4.3

Dual Output Read (DOR 3Bh or 4DOR 3Ch)

The instruction

• 3Bh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 3Bh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 3Ch is followed by a 4-byte address (A31–A0)

Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO).

Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for the Dual Output Read command is 108 MHz. For Dual Output Read

commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI before data

begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s internal circuitry

enough time to read from the initial address. During the dummy cycles, the data value on SI is a “don’t care” and

may be high impedance. The number of dummy cycles is determined by the frequency of SCK (refer to Table 24).

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

23 22 21

Address

0

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Phase

Instruction

8 Dummy Cycles

Data 1

Data 2

Figure 70

Dual Output Read command sequence (3-byte address, 3Bh [ExtAdd = 0], LC = 10b)

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31 30 29

Address

0

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Phase

Instruction

8 Dummy Cycles

Data 1

Data 2

Figure 71

Dual Output Read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd = 1, LC = 10b])

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

31 30 29

Address

0

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Phase

Instruction

Data 1

Data 2

Figure 72

Dual Output Read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd = 1, LC = 11b])

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.4.4

Quad Output Read (QOR 6Bh or 4QOR 6Ch)

The instruction

• 6Bh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 6Bh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 6Ch is followed by a 4-byte address (A31–A0)

Then the memory contents, at the address given, is shifted out four bits at a time through IO0–IO3. Each nibble

(4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for Quad Output Read command is 108 MHz. For Quad Output Read

Mode, there may be dummy cycles required after the last address bit is shifted into SI before data begins shifting

out of IO0–IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to set

up for the initial address. During the dummy cycles, the data value on IO0–IO3 is a “don’t care” and may be high

impedance. The number of dummy cycles is determined by the frequency of SCK (refer to Table 24).

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

The QUAD bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability.

CS#

0

7

1

6

2

5

3

4

5

2

6

1

7

0

8

30 31 32 33 34 35 36 37 38 39 40 41 42 43

SCLK

Instruction

24 Bit Address

23

8 Dummy Cycles

Data 1

Data 2

IO0

IO1

IO2

IO3

4

3

1

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

Figure 73

Quad Output Read (QOR 6Bh or 4QOR 6Ch) command sequence with read latency^{[37, 38]}

CS#

0

7

1

6

2

5

3

4

5

2

6

1

7

0

8

38 39 40 41 42 43 44 45 46 47 48 49 50 51

SCLK

Instruction

32 Bit Address

31

8 Dummy Cycles

Data 1

Data 2

IO0

IO1

IO2

IO3

4

3

1

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

Figure 74

Quad Output Read (QOR 6Bh or 4QOR 6Ch) command sequence without read latency^{[37, 39]}

Notes

37.A = MSb of address = A23 for ExtAdd = 0, or A31 for ExtAdd = 1 or command 6Ch.

38.LC = 01b shown.

39.LC = 11b shown.

Datasheet

103

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.4.5

Dual I/O Read (DIOR BBh or 4DIOR BCh)

The instruction

• BBh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• BBh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• BCh is followed by a 4-byte address (A31–A0)

The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the

Dual Output Read command but takes input of the address two bits per SCK rising edge. In some applications,

the reduced address input time might allow for code execution in place (XIP) i.e. directly from the memory device.

The maximum operating clock frequency for Dual I/O Read is 108 MHz.

For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and SO

before data begins shifting out of IO0 and IO1.

This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial

address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The

number of dummy cycles is determined by the frequency of SCK (Table 24). The number of dummy cycles is set

by the LC bits in the Configuration Register (CR1).

The Latency Code table provides cycles for mode bits so a series of Dual I/O Read commands may eliminate the

8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the

following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts

with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a latency period.

If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read command that

does not provide instruction bits. That command starts with address, followed by mode bits, followed by latency.

The enhanced high performance feature removes the need for the instruction sequence and greatly improves

code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read

command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the

Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the device remains

in Dual I/O enhanced high performance Read Mode and the next address can be entered (after CS# is raised HIGH

and then asserted LOW) without the BBh or BCh instruction, as shown in Figure 77; thus, eliminating eight cycles

for the command sequence. The following sequences will release the device from Dual I/O enhanced high

performance Read mode; after which, the device can accept standard SPI commands:

1. During the Dual I/O enhanced high performance Command Sequence, if the Mode bits are any value other than

Axh, then the next time CS# is raised high the device will be released from Dual I/O Read enhanced high

performance Read mode.

2. During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0 and IO1)

are not set for a valid instruction sequence, then the device will be released from Dual I/O enhanced high

performance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency

time to access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).

It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock.

At higher clock speeds the time available to turn off the host outputs before the memory device begins to drive

(bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention, for the host

system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t care” mode

cycles or during any dummy cycles.

Following the latency period the memory content, at the address given, is shifted out two bits at a time through

IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.

Datasheet

104

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

22

23

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Phase

Instruction

Address

Mode

Dum

Data 1

Data 2

Figure 75

Dual I/O Read command sequence (3-byte address, BBh [ExtAdd = 0])

CS#

SCK

IO0

7

6

5

4

3

2

1

0

30

31

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

IO1

1

Phase

Instruction

Address

Mode

Dum

Data 1

Data 2

Figure 76

Dual I/O Read command sequence (4-byte address, BCh or BBh [ExtAdd = 1])^[40]

CS#

SCK

IO0

6

7

4

5

2

3

0

1

30

31

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

IO1

Phase

Data N

Address

Mode

Dum

Data 1

Data 2

Figure 77

Continuous Dual I/O Read command sequence (4-byte address, BCh or BBh [ExtAdd = 1])^[40]

Note

40.Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may

turn off drive during these cycles to increase bus turn around time between Mode bits from host and

returning data from the memory.

Datasheet

105

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.4.6

Quad I/O Read (QIOR EBh or 4QIOR ECh)

The instruction

• EBh (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• EBh (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• ECh is followed by a 4-byte address (A31–A0)

The Quad I/O Read command improves throughput with four I/O signals — IO0–IO3. It is similar to the Quad

Output Read command but allows input of the address bits four bits per serial SCK clock. In some applications,

the reduced instruction overhead might allow for code execution (XIP) directly from FL-S Family devices. The

QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad capability of FL-S Family

devices.

The maximum operating clock frequency for Quad I/O Read is 108 MHz.

For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data

begins shifting out of IO0–IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry

enough time to access data at the initial address. During latency cycles, the data value on IO0–IO3 are “don’t care”

and may be high impedance. The number of dummy cycles is determined by the frequency of SCK and the latency

code table (refer to Table 24). The number of dummy cycles is set by the LC bits in the Configuration Register

(CR1). However, both latency code tables use the same latency values for the Quad I/O Read command.

Following the latency period, the memory contents at the address given, is shifted out four bits at a time through

IO0–IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through

the setting of the Mode bits (after the address sequence, as shown in Figure 78 or Figure 80). This added feature

removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits

7–4) of the Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the

first byte instruction code. The lower nibble (bits 3–0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal

Axh, then the device remains in Quad I/O high performance Read Mode and the next address can be entered (after

CS# is raised HIGH and then asserted LOW) without requiring the EBh or ECh instruction, as shown in Figure 79

or Figure 81; thus, eliminating eight cycles for the command sequence. The following sequences will release the

device from Quad I/O high performance Read mode; after which, the device can accept standard SPI commands:

1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next

time CS# is raised HIGH the device will be released from Quad I/O high performance Read mode.

2. During any operation, if CS# toggles HIGH to LOW to HIGH for eight cycles (or less) and data input (IO0–IO3) are

not set for a valid instruction sequence, then the device will be released from Quad I/O high performance Read

mode.

Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal

circuitry latency time to access the initial address after the last address cycle that is clocked into IO0–IO3.

It is important that the IO0–IO3 signals be set to high-impedance at or before the falling edge of the first data out

clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to

drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0–IO3 signal contention,

for the host system to turn off the IO0–IO3 signal outputs (make them high impedance) during the last “don’t

care” mode cycle or during any dummy cycles.

CS# should not be driven HIGH during mode or dummy bits as this may make the mode bits indeterminate.

Datasheet

106

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

20

21

22

23

4

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

5

IO2

6

7

IO3

Phase

Instruction

Address

Mode

Dummy

D1

D2

D3

D4

Figure 78

Quad I/O Read command sequence (3-byte address, EBh [ExtAdd = 0])

CS#

SCK

IO0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

4

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

6

7

4

5

2

0

IO1

5

3

1

IO2

6

7

IO3

Phase

DN-1

DN

Address

Mode

Dummy

D1

D2

D3

D4

Figure 79

Continuous Quad I/O Read command sequence (3-byte address)

CS#

SCK

IO0

7

6

5

4

3

2

1

0

28

29

30

31

4

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

0

1

2

3

IO1

5

6

7

IO2

6

7

IO3

Phase

Instruction

Address

Mode

Dummy

D1

D2

D3

D4

Figure 80

Quad I/O Read command sequence (4-byte address, ECh or EBh [ExtAdd = 1])

CS#

SCK

IO0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

28

29

30

31

4

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

6

7

4

5

2

3

0

1

IO1

5

IO2

6

7

IO3

Phase

DN-1

DN

Address

Mode

Dummy

D1

D2

D3

D4

Figure 81

Continuous Quad I/O Read command sequence (4-byte address)

Datasheet

107

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.5

Program Flash Array commands

10.5.1

Program granularity

10.5.1.1

Automatic ECC

Each 16 byte aligned and 16 byte length Programming Block has an automatic error correction code (ECC) value.

The data block plus ECC form an ECC unit. In combination with error detection and correction (EDC) logic the ECC

is used to detect and correct any single bit error found during a read access. When data is first programmed within

an ECC unit the ECC value is set for the entire ECC unit. If the same ECC unit is programmed more than once the

ECC value is changed to disable the Error Detection and Correction (EDC) function. A sector erase is needed to

again enable Automatic ECC on that Programming Block. The 16 byte Program Block is the smallest program

granularity on which Automatic ECC is enabled.

These are automatic operations transparent to the user. The transparency of the Automatic ECC feature

enhances data accuracy for typical programming operations which write data once to each ECC unit but,

facilitates software compatibility to previous generations of FL-S family of products by allowing for single byte

programming and bit walking in which the same ECC unit is programmed more than once. When an ECC unit has

Automatic ECC disabled, EDC is not done on data read from the ECC unit location.

An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have

been detected and corrected in the ECC unit data or the ECC (see “ECC Status Register (ECCSR)” on page 65.)

The ECC Status Register Read (ECCRD) command is used to read the ECC status on any ECC unit.

EDC is applied to all parts of the Flash address spaces other than registers. An ECC is calculated for each group of

bytes protected and the ECC is stored in a hidden area related to the group of bytes. The group of protected bytes

and the related ECC are together called an ECC unit.

ECC is calculated for each 16 byte aligned and length ECC unit.

• Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag.

• Sector erase resets all ECC bits and ECC disable flags in a sector to the default state (enabled).

• ECC is programmed as part of the standard Program commands operation.

• ECC is disabled automatically if multiple programming operations are done on the same ECC unit.

• Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16-byte

ECC unit.

• The ECC disable flag is programmed when ECC is disabled.

• To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased.

• To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC

is stored for that unit and not disabled.

• The calculation, programming, and disabling of ECC is done automatically as part of a programming operation.

The detection and correction, if needed, is done automatically as part of read operations. The host system sees

only corrected data from a read operation.

• ECC protects the OTP region - however a second program operation on the same ECC unit will disable ECC

permanently on that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC

enable/indicator bit is prohibited).

Datasheet

108

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.5.1.2

Page programming

Page programming is done by loading a Page Buffer with data to be programmed and issuing a programming

command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that

can be programmed with a single programming command. Page programming allows up to a page size (either

256 or 512 bytes) to be programmed in one operation. The page size is determined by a configuration bit (SR2[6]).

The page is aligned on the page size address boundary. It is possible to program from one bit up to a page size in

each Page programming operation. It is recommended that a multiple of 16-byte length and aligned Program

Blocks be written. For the very best performance, programming should be done in full, aligned, pages of 512 bytes

aligned on 512-byte boundaries with each Page being programmed only once.

10.5.1.3

Single byte programming

Single byte programming allows full backward compatibility to the standard SPI page programming (PP)

command by allowing a single byte to be programmed anywhere in the memory array. While single byte

programming is supported, this will disable Automatic ECC on the 16 byte ECC unit where the byte is located.

Datasheet

109

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.5.2

Page Program (PP 02h or 4PP 12h)

The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from 1 to 0).

Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must

be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully,

the device sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The instruction

• 02h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 02h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 12h is followed by a 4-byte address (A31–A0)

and at least one data byte on SI. Depending on the device configuration, the page size can either be 256 or

512 bytes. Up to a page can be provided on SI after the 3-byte address with instruction 02h or 4-byte address with

instruction 12h has been provided. If the 9 least significant address bits (A8–A0) are not all 0, all transmitted data

that goes beyond the end of the current page are programmed from the start address of the same page (from the

address whose 9 least significant bits (A8–A0) are all 0) i.e. the address wraps within the page aligned address

boundaries. This is a result of only requiring the user to enter one single page address to cover the entire page

boundary.

If more than a page of data is sent to the device, the data loading sequence will wrap from the last byte in the

page to the zero byte location of the same page and begin overwriting data previously loaded in the page. The

last page worth of data (either 256 or 512 bytes) is programmed in the page. This is a result of the device being

equipped with a page program buffer that is only page size in length. If less than a page of data is sent to the

device, these data bytes will be programmed in sequence, starting at the provided address within the page,

without having any affect on the other bytes of the same page.

Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall

programming time versus loading less than a page into the program buffer.

The programming process is managed by the flash memory device internal control logic. After a programming

command is issued, the programming operation status can be checked using the Read Status Register 1

command. The WIP bit (SR1[0]) will indicate when the programming operation is completed. The P_ERR bit

(SR1[6]) will indicate if an error occurs in the programming operation that prevents successful completion of

programming. This includes attempted programming of a protected area.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

A

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1 0

Phase

Instruction

Address

Input Data 1

Input Data 2

Figure 82

Page Program (PP 02h or 4PP 12h) command sequence^[41]

Note

41.A = MSb of address = A23 for PP 02h, or A31 for 4PP 12h.

Datasheet

110

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.5.3

Quad Page Program (QPP 32h or 38h, or 4QPP 34h)

The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits

from 1 to 0). The Quad-input Page Program (QPP) command allows up to a page size (either 256 or 512 bytes) of

data to be loaded into the Page Buffer using four signals: IO0–IO3. QPP can improve performance for PROM

Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4 bits of data per clock cycle.

Systems with faster clock speeds do not realize as much benefit for the QPP command since the inherent page

program time becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP

command is 80 MHz.

To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write

Enable command must be executed before the device will accept the QPP command (Status Register 1, WEL = 1).

The instruction

• 32h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 32h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 38h (ExtAdd = 0) is followed by a 3-byte address (A23–A0) or

• 38h (ExtAdd = 1) is followed by a 4-byte address (A31–A0) or

• 34h is followed by a 4-byte address (A31–A0)

and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory

locations.

QPP requires programming to be done one full page at a time. While less than a full page of data may be loaded

for programming, the entire page is considered programmed, any locations not filled with data will be left as

ones, the same page must not be programmed more than once.

All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the Figure 83.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

A

1

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

IO2

6

IO3

7

Phase

Instruction

Address

Data 1 Data 2 Data 3 Data 4 Data 5

...

Figure 83

Quad Page Program command sequence

Datasheet

111

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.5.4

Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)

The Program Suspend command allows the system to interrupt a programming operation and then read from

any other non-erase-suspended sector or non-program-suspended-page. Program Suspend is valid only during

a programming operation.

Commands allowed after the Program Suspend command is issued:

• Read Status Register 1 (RDSR1 05h)

• Read Status Register 2 (RDSR2 07h)

The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the programming

operation has stopped. The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to

determine if a programming operation has been suspended or was completed at the time WIP changes to ‘0’. The

time required for the suspend operation to complete is t_PSL, see Table 46.

See Table 44 for the commands allowed while programming is suspend.

The Program Resume command 8Ah must be written to resume the programming operation after a Program

Suspend. If the programming operation was completed during the suspend operation, a resume command is not

needed and has no effect if issued. Program Resume commands will be ignored unless a Program operation is

suspended.

After a Program Resume command is issued, the WIP bit in the Status Register 1 will be set to ‘1’ and the

programming operation will resume. Program operations may be interrupted as often as necessary e.g. a

program suspend command could immediately follow a program resume command but, in order for a program

operation to progress to completion there must be some periods of time between resume and the next suspend

command greater than or equal to t_PRS. See Table 46.

tPSL

CS#

SCK

Prog. Suspend

Program Suspend Instruction

Read Status

0

Mode Command

SI

7

6

5

4

3

2

1

0

7

6

7

6

5

SO

7

0

Figure 84

Program Suspend command sequence

CSS#

0

1

2

3

4

5

6

7

SCK

Instruction (8Ah)

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Resume Programming

Figure 85

Program Resume command sequence

Datasheet

112

001-98282 Rev. *K

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.6

Erase Flash Array commands

Parameter 4-KB Sector Erase (P4E 20h or 4P4E 21h)

10.6.1

The P4E command is implemented only in FL127S. The P4E command is ignored when the device is configured

with the 256-KB sector option.

The Parameter 4-KB Sector Erase (P4E) command sets all the bits of a 4-KB parameter sector to 1 (all bytes are

FFh). Before the P4E command can be accepted by the device, a Write Enable (WREN) command must be issued

and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write

operations.

The instruction

• 20h [ExtAdd = 0] is followed by a 3-byte address (A23–A0), or

• 20h [ExtAdd = 1] is followed by a 4-byte address (A31–A0), or

• 21h is followed by a 4-byte address (A31–A0)

CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has been

latched in on SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and

erase of the chosen sector of the flash memory array. If CS# is not driven HIGH after the last bit of address, the

sector erase operation will not be executed.

As soon as CS# is driven HIGH, the internal erase cycle will be initiated. With the internal erase cycle in progress,

the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has been

completed. The WIP bit will indicate a 1. when the erase cycle is in progress and a 0 when the erase cycle has been

completed.

A P4E command applied to a sector that has been write protected through the Block Protection bits or ASP, will

not be executed and will set the E_ERR status. A P4E command applied to a sector that is larger than 4 KB will not

be executed and will not set the E_ERR status.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

A

1

0

Phase

Instruction

Address

Figure 86

Parameter Sector Erase (P4E 20h or 4P4E 21h) command sequence^[42]

Note

42.A = MSb of address = A23 for P4E 20h with ExtAdd = 0, or A31 for P4E 20h with ExtAdd = 1 or 4P4E 21h.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.6.2

Sector Erase (SE D8h or 4SE DCh)

The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector

Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be issued and

decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write

operations.

The instruction

• D8h [ExtAdd = 0] is followed by a 3-byte address (A23–A0), or

• D8h [ExtAdd = 1] is followed by a 4-byte address (A31–A0), or

• DCh is followed by a 4-byte address (A31–A0)

CS# must be driven into the logic HIGH state after the twenty-fourth or thirty-second bit of address has been

latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the chosen

sector. If CS# is not driven HIGH after the last bit of address, the sector erase operation will not be executed.

As soon as CS# is driven into the logic HIGH state, the internal erase cycle will be initiated. With the internal erase

cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been

completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been

completed.

A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection bits

or ASP, will not be executed and will set the E_ERR status.

A device configuration determines whether the SE command erases 64 KB or 256 KB. The option to use this

command to always erase 256 KB provides for software compatibility with higher density and future S25FL family

devices.

ASP has a PPB and a DYB protection bit for each sector, including any 4-KB sectors. If a sector erase command is

applied to a 64-KB range that includes a protected 4-KB sector, or to a 256-KB range that includes a 64-KB

protected address range, the erase will not be executed on the range and will set the E_ERR status.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

A

1

0

Phase

Instruction

Address

Figure 87

Sector Erase (SE D8h or 4SE DCh) command sequence^[43]

Note

43.A = MSb of address = A23 for SE D8h with ExtAdd = 0, or A31 for SE D8h with ExtAdd = 1 or 4P4E DCh.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.6.3

Bulk Erase (BE 60h or C7h)

The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the

BE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by

the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.

This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array.

If CS# is not driven HIGH after the last bit of instruction, the BE operation will not be executed.

As soon as CS# is driven into the logic HIGH state, the erase cycle will be initiated. With the erase cycle in progress,

the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has been

completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been

completed.

A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. If the BP bits

are not 0, the BE command is not executed and E_ERR is not set. The BE command will skip any sectors protected

by the DYB or PPB and the E_ERR status will not be set.

CS#

0

1

2

3

4

5

6

7

SCK

Instruction

SI

Figure 88

Bulk Erase command sequence

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.6.4

Erase Suspend and Resume commands (ERSP 75h or ERRS 7Ah)

The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or

program data to, any other sector. Erase Suspend is valid only during a sector erase operation. The Erase Suspend

command is ignored if written during the Bulk Erase operation.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum

of t_ESL(erase suspend latency) to suspend the erase operation and update the status bits. See Table 47.

Commands allowed after the Erase Suspend command is issued:

• Read Status Register 1 (RDSR1 05h)

• Read Status Register 2 (RDSR2 07h)

The Write in Progress (WIP) bit in Status Register 1 (SR1[0]) must be checked to know when the erase operation

has stopped. The Erase Suspend bit in Status Register 2 (SR2[1]) can be used to determine if an erase operation

has been suspended or was completed at the time WIP changes to 0.

If the erase operation was completed during the suspend operation, a resume command is not needed and has

no effect if issued. Erase Resume commands will be ignored unless an Erase operation is suspended.

See Table 44 for the commands allowed while erase is suspend.

After the erase operation has been suspended, the sector enters the erase-suspend mode. The system can read

data from or program data to the device. Reading at any address within an erase-suspended sector produces

undetermined data.

A WREN command is required before any command that will change nonvolatile data, even during erase suspend.

The WRR and PPB Erase commands are not allowed during Erase Suspend, it is therefore not possible to alter the

Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase

suspend, these sectors should be protected only by DYB bits that can be turned off during Erase Suspend.

However, WRR is allowed immediately following the BRAC command; in this special case the WRR is interpreted

as a write to the Bank Address Register, not a write to SR1 or CR1.

If a program command is sent for a location within an erase suspended sector the program operation will fail with

the P_ERR bit set.

After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The

system can determine the status of the program operation by reading the WIP bit in the Status Register, just as

in the standard program operation.

The Erase Resume command 7Ah must be written to resume the erase operation if an Erase is suspended. Erase

Resume commands will be ignored unless an Erase is suspended.

After an Erase Resume command is sent, the WIP bit in the status register will be set to a 1 and the erase operation

will continue. Further Resume commands are ignored.

Erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately

follow an erase resume command but, in order for an erase operation to progress to completion there must be

some periods of time between resume and the next suspend command greater than or equal to t_ERS. See

Table 47.

tESL

CS#

SCLK

Erase Suspend

Erase Suspend Instruction

Read Status

0

Mode Command

SI

7

6

5

4

3

2

1

0

7

6

7

6

5

SO

7

0

Figure 89

Erase Suspend command sequence

Datasheet

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2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

CSS#

SCK

0

1

2

3

4

5

6

7

Instruction (7Ah)

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Resume Sector or Block Erase

Figure 90

Table 44

Erase Resume command sequence

Commands allowed during program or erase suspend

Allowed Allowed

Instruction Instruction

during

erase

during

Comment

name

code (Hex)

program

suspend suspend

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

Bank address register may need to be changed during a

suspend to reach a sector for read or program.

Clear status may be used if a program operation fails

during erase suspend.

BRAC

BRRD

BRWR

CLSR

B9

16

17

30

X

It may be necessary to remove and restore dynamic

protection during erase suspend to allow programming

during erase suspend.

It may be necessary to remove and restore dynamic

protection during erase suspend to allow programming

during erase suspend.

DYBRD

DYBWR

E0

E1

X

ERRS

FAST_READ

4FAST_READ

MBR

7A

0B

0C

FF

X

Required to resume from erase suspend.

All array reads allowed in suspend.

X

May need to reset a read operation during suspend.

Needed to resume a program operation. A program

resume may also be used during nested program suspend

within an erase suspend.

PGRS

8A

X

PGSP

PP

4PP

85

02

12

X

Program suspend allowed during erase suspend.

Required for array program during erase suspend.

Allowed for checking persistent protection before

attempting a program command during erase suspend.

PPBRD

E2

X

QPP

4QPP

32, 38

34

X

Required for array program during erase suspend.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

Table 44

Commands allowed during program or erase suspend (Continued)

Allowed Allowed

Instruction Instruction

during

erase

during

Comment

name

code (Hex)

program

suspend suspend

4READ

RDCR

DIOR

4DIOR

DOR

4DOR

QIOR

4QIOR

QOR

4QOR

RDSR1

13

35

BB

BC

3B

3C

EB

EC

6B

6C

05

X

All array reads allowed in suspend.

Needed to read WIP to determine end of suspend process.

Needed to read suspend status to determine whether the

operation is suspended or complete.

RDSR2

07

X

READ

RESET

WREN

03

F0

06

X

All array reads allowed in suspend.

Reset allowed anytime.

Required for program command within erase suspend.

Bank register may need to be changed during a suspend

to reach a sector needed for read or program. WRR is

allowed when following BRAC.

WRR

01

X

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.7

One Time Program Array commands

OTP Program (OTPP 42h)

10.7.1

The OTP Program command programs data in the One Time Program region, which is in a different address space

from the main array data. The OTP region is 1024 bytes so, the address bits from A23 to A10 must be 0 for this

command. Refer to “OTP address space” on page 55 for details on the OTP region. The protocol of the OTP

Program command is the same as the Page Program command. Before the OTP Program command can be

accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets

the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1 may be

checked to determine when the operation is completed. The P_ERR bit in SR1 may be checked to determine if

any error occurred during the operation.

To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.

Each region in the OTP memory space can be programmed one or more times, provided that the region is not

locked. Attempting to program 0s in a region that is locked will fail with the P_ERR bit in SR1 set to 1 Programming

ones, even in a protected area does not cause an error and does not set P_ERR. Subsequent OTP programming

can be performed only on the un-programmed bits (that is, 1 data).

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCK

SI

24-Bit

Instruction

Data Byte 1

Address

23 22 21

0

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

MSB

CS#

40 41 42 43 44 45 46 47 48 49 59 51 52 53 54 55

SCK

SI

Data Byte 2

Data Byte 3

Data Byte 512

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

Figure 91

OTP Program command sequence

10.7.2

OTP Read (OTPR 4Bh)

The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits from

A23 to A10 must be 0 for this command. Refer to “OTP address space” on page 55 for details on the OTP region.

The protocol of the OTP Read command is similar to the Fast Read command except that it will not wrap to the

starting address after the OTP address is at its maximum; instead, the data beyond the maximum OTP address

will be undefined. Also, the OTP Read command is not affected by the latency code. The OTP read command

always has one dummy byte of latency as shown below.

CSS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCK

24-Bit

Address

Instruction

Dummy Byte

SI

23 22 21

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 1

DATA OUT 2

High Impedance

SO

7

6

5

4

3

2

1

0

7

MSB

Figure 92

OTP Read command sequence

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8

Advanced Sector Protection commands

ASP Read (ASPRD 2Bh)

10.8.1

The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register

contents are shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK

frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by providing

multiples of 16 clock cycles. The maximum operating clock frequency for the ASP Read (ASPRD) command is

108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Instruction

SI

SO

7

6

5

4

3

2

1

0

MSB

Register Out

High Impedance

7

6

5

4

3

2

1

0

7

15 14 13 12 11 10

9

8

MSB

Figure 93

ASPRD command

10.8.2

ASP Program (ASPP 2Fh)

Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The ASPP command is entered by driving CS# to the logic LOW state, followed by the instruction and two data

bytes on SI, least significant byte first. The ASP Register is two data bytes in length.

The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner

as any other programming operation.

CS# input must be driven to the logic HIGH state after the sixteenth bit of data has been latched in. If not, the

ASPP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed ASPP operation

is initiated. While the ASPP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP operation, and is a 0

when it is completed. When the ASPP operation is completed, the Write Enable Latch (WEL) is set to a 0.

CS#

16 17 18 19 20 21 22 23

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

SI

Instruction

Register In

15 14 13 12 11 10

9

8

7

6

3

2

1

0

4

7

6

5

4

3

2

1

0

5

MSB

High Impedance

SO

Figure 94

ASPP command

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.3

DYB Read (DYBRD E0h)

The instruction E0h is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 32-bit

address selecting location zero within the desired sector Note: the high order address bits not used by a particular

density device must be 0. Then the 8-bit DYB access register contents are shifted out on the serial output SO. Each

bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB

access register continuously by providing multiples of eight clock cycles. The address of the DYB register does

not increment so this is not a means to read the entire DYB array. Each location must be read with a separate DYB

Read command. The maximum operating clock frequency for READ command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCK

32-Bit

Address

Instruction

SI

7

6

5

4

3

2

1

0

31 30 29

3

2

1

0

DATA OUT 1

High Impedance

SO

7

6

5

4

3

2

1

0

MSB

Figure 95

DYBRD command sequence

10.8.4

DYB Write (DYBWR E1h)

Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The DYBWR command is entered by driving CS# to the logic LOW state, followed by the instruction, the 32-bit

address selecting location zero within the desired sector (note, the high order address bits not used by a

particular density device must be 0), then the data byte on SI. The DYB Access Register is one data byte in length.

The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same

manner as any other programming operation. CS# must be driven to the logic HIGH state after the eighth bit of

data has been latched in. If not, the DYBWR command is not executed. As soon as CS# is driven to the logic HIGH

state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the Status Register

may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the

self-timed DYBWR operation, and is a 0 when it is completed. When the DYBWR operation is completed, the Write

Enable Latch (WEL) is set to a 0.

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCK

SI

32-Bit

Instruction

Data Byte 1

Address

31 30 29

MSB

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

Figure 96

DYBWR command sequence

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.5

PPB Read (PPBRD E2h)

The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address selecting

location zero within the desired sector. Note: the high order address bits not used by a particular density device

must be 0. Then the 8-bit PPB access register contents are shifted out on SO.

It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles. The

address of the PPB register does not increment so this is not a means to read the entire PPB array. Each location

must be read with a separate PPB Read command. The maximum operating clock frequency for the PPB Read

command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCK

32-Bit

Address

Instruction

SI

7

6

5

4

3

2

1

0

31 30 29

3

2

1

0

DATA OUT 1

High Impedance

SO

7

6

5

4

3

2

1

0

MSB

Figure 97

PPBRD command sequence

10.8.6

PPB Program (PPBP E3h)

Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must

be issued. After the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The PPBP command is entered by driving CS# to the logic LOW state, followed by the instruction, followed by the

32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a

particular density device must be 0).

The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner

as any other programming operation.

CS# must be driven to the logic HIGH state after the last bit of address has been latched in. If not, the PPBP

command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PPBP operation is

initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PPBP operation, and is a 0

when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a 0.

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37

38

39

35

SCK

Instruction

32 bit Address

3

SI

7

6

5

4

3

2

1

0

31 30 29

MSB

2

1

0

MSB

High Impedance

SO

Figure 98

PPBP command sequence

Datasheet

122

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.7

PPB Erase (PPBE E4h)

The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the

device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable

Latch (WEL) in the Status Register to enable any write operations.

The instruction E4h is shifted into SI by the rising edges of the SCK signal.

CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI.

This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the entire

PPB memory array. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction, the

PPB erase operation will not be executed.

With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if

the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when

the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.

CS#

0

1

2

3

4

5

6

7

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 99

PPB Erase command sequence

10.8.8

PPB Lock Bit Read (PLBRD A7h)

The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is

possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock

Register contents may only be read when the device is in standby state with no other operation in progress. It is

recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new command to

the device.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Register Read

Repeat Register Read

Figure 100

PPB Lock Register Read command sequence

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.9

PPB Lock Bit Write (PLBWR A6h)

The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to 0. Before the PLBWR command can be

accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets

the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The PLBWR command is entered by driving CS# to the logic LOW state, followed by the instruction.

CS# must be driven to the logic HIGH state after the eighth bit of instruction has been latched in. If not, the PLBWR

command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PLBWR operation is

initiated. While the PLBWR operation is in progress, the Status Register may still be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PLBWR operation, and is a

0 when it is completed. When the PLBWR operation is completed, the Write Enable Latch (WEL) is set to a 0. The

maximum clock frequency for the PLBWR command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

High Impedance

SO

Figure 101

PPB Lock Bit Write command sequence

10.8.10

Password Read (PASSRD E7h)

The correct password value may be read only after it is programmed and before the Password Mode has been

selected by programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password

Protection Mode is selected the PASSRD command is ignored.

The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least

significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the

falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of 64 clock

cycles. The maximum operating clock frequency for the PASSRD command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10 11

69 70 71 72

SCK

Instruction

SI

7

6

5

4

3

2

1

0

MSB

Password Least Sig. Byte First

58 57 56

High Impedance

7

6

5

4

SO

MSB

Figure 102

Password Read command sequence

Datasheet

124

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.11

Password Program (PASSP E8h)

Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device. After the Write Enable (WREN) command has been

decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.

The password can only be programmed before the Password Mode is selected by programming the Password

Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP

command is ignored.

The PASSP command is entered by driving CS# to the logic LOW state, followed by the instruction and the

password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is

sixty-four (64) bits in length.

CS# must be driven to the logic HIGH state after the sixty-fourth (64^th) bit of data has been latched. If not, the

PASSP command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSP operation

is initiated. While the PASSP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSP cycle, and is a 0 when

it is completed. The PASSP command can report a program error in the P_ERR bit of the status register. When the

PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the

PASSP command is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10

68 69

70

71

SCK

Instruction

Password

SI

7

6

5

4

3

2

1

0

7

6

5

59

58

57

56

MSB

High Impedance

SO

Figure 103

Password Program command sequence

Datasheet

125

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.8.12

Password Unlock (PASSU E9h)

The PASSU command is entered by driving CS# to the logic LOW state, followed by the instruction and the

password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is

sixty-four (64) bits in length.

CS# must be driven to the logic HIGH state after the sixty-fourth (64^th) bit of data has been latched. If not, the

PASSU command is not executed. As soon as CS# is driven to the logic HIGH state, the self-timed PASSU operation

is initiated. While the PASSU operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU cycle, and is a 0 when

it is completed.

If the PASSU command supplied password does not match the hidden password in the Password Register, an

error is reported by setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary

to use the CLSR command to clear the status register, the RESET command to software reset the device, or drive

the RESET# input LOW to initiate a hardware reset, in order to return the P_ERR and WIP bits to 0. This returns

the device to standby state, ready for new commands such as a retry of the PASSU command.

If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU command

is 108 MHz.

CS#

0

1

2

3

4

5

6

7

8

9

10

68 69

70

71

SCK

Instruction

Password

SI

7

6

5

4

3

2

1

0

7

6

5

59

58

57

56

MSB

High Impedance

SO

Figure 104

Password Unlock command sequence

Datasheet

126

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.9

Reset commands

10.9.1

Software Reset Command (RESET F0h)

The Software Reset command (RESET) restores the device to its initial power up state, except for the volatile

FREEZE bit in the Configuration register CR1[1] and the volatile PPB Lock bit in the PPB Lock Register. The Freeze

bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the FREEZE bit and

set the PPB Lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware

reset must be done. Note that the nonvolatile bits in the configuration register, TBPROT, TBPARM, and BPNV,

retain their previous state after a Software Reset. The Block Protection bits BP2, BP1, and BP0, in the status

register will only be reset if they are configured as volatile via the BPNV bit in the Configuration Register (CR1[3])

and FREEZE is cleared to 0. The software reset cannot be used to circumvent the FREEZE or PPB Lock bit

protection mechanisms for the other security configuration bits. The reset command is executed when CS# is

brought to HIGH state and requires t_RPHtime to execute.

CS#

0

1

2

3

4

5

6

7

SCK

SI

Instruction

Figure 105

Software Reset command sequence

10.9.2

Mode Bit Reset (MBR FFh)

The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance read

mode back to normal standby awaiting any new command. Because some device packages lack a hardware

RESET# input and a device that is in a continuous high performance read mode may not recognize any normal

SPI command, a system hardware reset or software reset command may not be recognized by the device. It is

recommended to use the MBR command after a system reset when the RESET# signal is not available or, before

sending a software reset, to ensure the device is released from continuous high performance read mode.

The MBR command sends Ones on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these cycles.

CSS#

0

1

2

3

4

5

6

7

SCK

Instruction (FFh)

High Impedance

SI

SO

Figure 106

Mode Bit Reset command sequence

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

10.10

Embedded algorithm performance tables

The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural

requirements for performing valid endurance and retention tests based on a qualification specification. This

methodology is intended to determine the ability of a flash device to sustain repeated data changes without

failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and

retention qualification specifications are specified in JESD47 or may be developed using knowledge-based

methods as in JESD94.

Table 45

Symbol

t_W

Program and erase performance

Parameter

WRR write time

Min

Typ^[44]

130

Max^[45]

780

Unit

ms

Page programming (512 bytes)

Page programming (256 bytes)

Sector erase time (64-KB / 4-KB physical sectors)

640

395

130

1480

t_PP

µs

1185^[46]

780^[47]

ms

Sector erase time

(64 KB top/bottom: logical sector = 16 x 4-KB physical

sectors)

2,100

12,600

ms

t_SE

Sector erase time

520

3120

ms

sec

(256-KB logical sectors = 4 x 64-KB physical sectors)

Bulk erase time (hybrid 4 KB top/bottom with 64-KB

uniform)

Bulk erase time (256-KB uniform)

Erase per sector

35

33

210

200

t_BE

sec

cycles

100,000

Notes

44.Typical program and erase times assume the following conditions: 25°C, V_CC= 3.0 V; random data pattern.

45.Under worst case conditions of 90 °C; 100,000 cycles max.

46.The programming time for any OTP programming command is the same as t_PP. This includes OTPP 42h,

PNVDLR 43h, ASPP 2Fh, and PASSP E8h. The programming time for the PPBP E3h command is the same as

t_PP

.

47.The erase time for PPBE E4h command is the same as t_SE

.

48.Data retention of 20 years is based on 1k erase cycles or less.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

Table 46

Program suspend AC parameters

Parameter

Program Suspend Latency

(t_PSL

Min

Typical

Max

Unit

Comments

The time from Program Suspend

command until the WIP bit is 0

45

µs

)

Minimum is the time needed to issue the

next Program Suspend command but ≥

typical periods are needed for Program to

progress to completion

Program Resume to next

Program Suspend (t_PRS

0.06

100

µs

)

Table 47

Erase suspend AC parameters

Parameter

Min

Typical

Max

Unit

Comments

Erase Suspend Latency

The time from Erase Suspend command

until the WIP bit is 0

45

µs

(t_ESL

)

Minimum is the time needed to issue the

next Erase Suspend command but ≥

typical periods are needed for the Erase to

progress to completion

Erase Resume to next Erase

Suspend (t_ERS)

0.06

100

µs

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Data integrity

11

Data integrity

11.1

Erase endurance

Table 48

Erase endurance

Parameter

Minimum

100K

Unit

PE cycle

Program/erase cycles per main Flash array sectors

Program/erase cycles per PPB array or nonvolatile register array^[49]

Note

49.Each write command to a nonvolatile register causes a PE cycle on the entire nonvolatile register array. OTP

bits and registers internally reside in a separate array that is not PE cycled.

100K

11.2

Data retention

Table 49

Data retention

Parameter

Test conditions

10K program/erase cycles

100K program/erase cycles

Minimum time

Unit

Years

20

2

Data Retention Time

Contact Infineon Sales and FAE for further information on the data integrity. An application note is available at:

www.infineon.com/appnotes.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Software interface reference

12

Software interface reference

12.1

Command summary

Table 50

Parameter

01

FL127S command set (sorted by instruction)

Minimum

Unit

Parameter

108

50

WRR

PP

Write Register (Status-1, Configuration-1)

Page Program (3- or 4-byte address)

Read (3- or 4-byte address)

Write Disable

Read Status Register 1

Write Enable

02

03

04

05

06

07

0B

0C

12

13

14

15

16

17

18

20

21

2B

2F

30

32

34

35

38

3B

3C

42

4B

5A

60

6B

6C

75

READ

WRDI

RDSR1

WREN

RDSR2

FAST_READ

4FAST_READ

4PP

108

50

108

80

Read Status Register 2

Fast Read (3- or 4-byte address)

Fast Read (4-byte address)

Page Program (4-byte address)

Read (4-byte address)

AutoBoot Register Read

AutoBoot Register Write

Bank Register Read

Bank Register Write

ECC Read

4READ

ABRD

ABWR

BRRD

BRWR

ECCRD

P4E

Parameter 4 KB-sector Erase (3- or 4-byte address)

Parameter 4 KB-sector Erase (4-byte address)

ASP Read

4P4E

ASPRD

ASPP

CLSR

ASP Program

Clear Status Register - Erase/Program Fail Reset

Quad Page Program (3- or 4-byte address)

Quad Page Program (4-byte address)

Read Configuration Register 1

Quad Page Program (3- or 4-byte address)

Read Dual Out (3- or 4-byte address)

Read Dual Out (4-byte address)

OTP Program

QPP

4QPP

RDCR

QPP

80

108

80

DOR

108

4DOR

OTPP

OTPR

RSFDP

BE

OTP Read

Read JEDEC Serial Flash Discoverable Parameters

Bulk Erase

QOR

4QOR

ERSP

Read Quad Out (3- or 4-byte address)

Read Quad Out (4-byte address)

Erase Suspend

7A

85

ERRS

Erase Resume

PGSP

Program Suspend

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Software interface reference

Table 50

FL127S command set (sorted by instruction) (Continued)

Parameter

Minimum

Unit

Parameter

108

8A

90

9F

A3

A6

A7

AB

PGRS

Program Resume

READ_ID (REMS) Read Electronic Manufacturer Signature

108

50

RDID

Reserved-A3

PLBWR

PLBRD

Read ID (JEDEC Manufacturer ID and JEDEC CFI)

Reserved

PPB Lock Bit Write

PPB Lock Bit Read

Read Electronic Signature

RES

Bank Register Access

(Legacy Command formerly used for Deep Power Down)

B9

BRAC

108

BB

BC

C7

D8

DC

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EB

EC

F0

FF

DIOR

4DIOR

BE

SE

4SE

DYBRD

DYBWR

PPBRD

PPBP

Dual I/O Read (3- or 4-byte address)

Dual I/O Read (4-byte address)

Bulk Erase (alternate command)

Erase 64 KB or 256 KB (3- or 4-byte address)

Erase 64 KB or 256 KB (4-byte address)

DYB Read

DYB Write

PPB Read

PPB Program

PPB Erase

108

PPBE

Reserved-E5

Reserved-E6

PASSRD

PASSP

PASSU

QIOR

Reserved

Password Read

Password Program

108

Password Unlock

Quad I/O Read (3- or 4-byte address)

Quad I/O Read (4-byte address)

Software Reset

4QIOR

RESET

MBR

Mode Bit Reset

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13

Serial flash discoverable parameters (SFDP) address map

The SFDP address space has a header starting at address 0 that identifies the SFDP data structure and provides

a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B standard. Two

optional parameter tables for Sector Map and 4-byte Address Instructions follow the Basic Flash table. Cypress

provides an additional parameter by pointing to the ID-CFI address space i.e. the IDCFI address space is a sub-set

of the SFDP address space. The parameter tables portion of the SFDP data structure are located within the ID-CFI

address space and is thus both a CFI parameter and an SFDP parameter. In this way both SFDP and ID-CFI infor-

mation can be accessed by either the RSFDP or RDID commands.

Table 51

SFDP overview map

Parameter

Minimum

Location zero within JEDEC JESD216B SFDP space 

0000h

,,,

start of SFDP header

Remainder of SFDP header followed by undefined

space

Location zero within ID-CFI space  start of ID-CFI

1000h

...

parameter tables

ID-CFI parameters

Start of SFDP parameter which is one of the CFI

parameter tables

1120h

Remainder of SFDP parameter tables followed by

either more CFI parameters or undefined space

...

Datasheet

133

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13.1

SFDP header field definitions

Table 52

SFDP header

Minimum

Parameter

Unit

Parameter

This is the entry point for Read SFDP (5Ah) command i.e. location

zero within SFDP space ASCII “S”

46h ASCII “F”

44h ASCII “D”

50h ASCII “P”

00h

53h

SFDP Header

1st DWORD

01h

02h

03h

SFDP Minor Revision (06h = JEDEC JESD216 Revision B) This revision

is backward compatible with all prior minor revisions. Minor

revisions are changes that define previously reserved fields, add

fields to the end, or that clarify definitions of existing fields.

Increments of the minor revision value indicate that previously

reserved parameter fields may have been assigned a new definition

or entire Dwords may have been added to the parameter table.

However, the definition of previously existing fields is unchanged

06h and therefore remain backward compatible with earlier SFDP

parameter table revisions. Software can safely ignore increments of

the minor revision number, as long as only those parameters the

software was designed to support are used i.e. previously reserved

fields and additional Dwords must be masked or ignored. Do not do

a simple compare on the minor revision number, looking only for a

match with the revision number that the software is designed to

handle. There is no problem with using a higher number minor

revision.

04h

05h

SFDP Header

2nd DWORD

SFDP Major Revision. This is the original major revision. This major

01h

revision is compatible with all SFDP reading and parsing software.

06h

07h

08h

05h Number of Parameter Headers (zero based, 05h = 6 parameters)

FFh Unused

00h Parameter ID LSb (00h = JEDEC SFDP Basic SPI Flash Parameter)

Parameter Minor Revision (00h = JESD216)

- This older revision parameter header is provided for any legacy

SFDP reading and parsing software that requires seeing a minor

revision 0 parameter header.

09h

00h

SFDP software designed to handle later minor revisions should

Parameter Header

continue reading parameter headers looking for a higher numbered

minor revision that contains additional parameters for that

software revision.

0

1st DWORD

Parameter Major Revision (01h = The original major revision - all

0Ah

0Bh

0Ch

01h

SFDP software is compatible with this major revision.

Parameter Table Length (in double words = Dwords = 4 byte units)

09h 09h = 9

Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC

20h

Basic SPI Flash parameter byte offset = 1120h

Parameter Header

0Dh

0Eh

0Fh

11h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

FFh Parameter ID MSb (FFh = JEDEC defined legacy Parameter ID)

0

2nd DWORD

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 52

Parameter

10h

SFDP header (Continued)

Minimum

Unit

Parameter

00h Parameter ID LSb (00h = JEDEC SFDP Basic SPI Flash Parameter)

Parameter Minor Revision (05h = JESD216 Revision A) - This older

revision parameter header is provided for any legacy SFDP reading

and parsing software that requires seeing a minor revision 5

11h

05h

parameter header. SFDP software designed to handle later minor

Parameter Header

revisions should continue reading parameter headers looking for a

later minor revision that contains additional parameters.

1

1st DWORD

Parameter Major Revision (01h = The original major revision - all

12h

13h

14h

01h

SFDP software is compatible with this major revision.

Parameter Table Length (in double words = Dwords = 4 byte units)

10h

10h = 16 Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC

20h

Basic SPI Flash parameter byte offset = 1120h address

Parameter Header

15h

16h

17h

18h

19h

11h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

FFh Parameter ID MSb (FFh = JEDEC defined Parameter)

00h Parameter ID LSb (00h = JEDEC SFDP Basic SPI Flash Parameter)

06h Parameter Minor Revision (06h = JESD216 Revision B)

1

2nd DWORD

Parameter Header

Parameter Major Revision (01h = The original major revision - all

2

1Ah

1Bh

1Ch

01h

SFDP software is compatible with this major revision.

1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units)

10h

10h = 16 Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC

20h

Basic SPI Flash parameter byte offset = 1120h address

Parameter Header

1Dh

1Eh

1Fh

20h

11h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

FFh Parameter ID MSb (FFh = JEDEC defined Parameter)

81h Parameter ID LSb (81h = SFDP Sector Map Parameter)

2

2nd DWORD

Parameter Minor Revision (00h = Initial version as defined in

21h

22h

23h

24h

00h

JESD216 Revision B)

Parameter Header

3 1st DWORD

Parameter Major Revision (01h = The original major revision - all

01h SFDP software that recognizes this parameter’s ID is compatible

with this major revision.

Parameter Table Length (in double words = Dwords = 4 byte units)

0Eh

0Eh = 14 Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC

60h parameter byte

offset = 1160h

Parameter Header

3 2nd DWORD

25h

26h

27h

11h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

FFh Parameter ID MSb (FFh = JEDEC defined Parameter)

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 52

SFDP header (Continued)

Parameter

Minimum

Unit

Parameter

Parameter ID LSb (00h = SFDP 4 Byte Address Instructions

Parameter)

Parameter Minor Revision (00h = Initial version as defined in

JESD216 Revision B)

28h

29h

84h

00h

Parameter Header

4 1st DWORD

Parameter Major Revision (01h = The original major revision - all

2Ah

01h SFDP software that recognizes this parameter’s ID is compatible

with this major revision.

Parameter Table Length (in double words = Dwords = 4 byte units)

2Bh

2Ch

02h

(2h = 2 Dwords)

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC

98h

parameter byte offset = 1198h

Parameter Header

4 2nd DWORD

2Dh

2Eh

2Fh

11h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

FFh Parameter ID MSb (FFh = JEDEC defined Parameter)

Parameter ID LSb (Cypress Vendor Specific ID-CFI parameter)

30h

31h

01h

Legacy Manufacturer ID 01h = AMD / Cypress

Parameter Minor Revision (01h = ID-CFI updated with SFDP Rev B

01h

table)

Parameter Major Revision (01h = The original major revision - all

01h SFDP software that recognizes this parameter’s ID is compatible

with this major revision.

32h

33h

34h

Parameter Header

5 1st DWORD

Parameter Table Length (in double words = Dwords = 4 byte units)

CFI starts at 1000h, the final SFDP parameter (CFI ID = A5) starts at

111Eh (SFDP starting point of 1120h -2hB of CFI parameter header),

68h for a length of 11EhB excluding the CFI A5 parameter. The final CFI

A5 parameter adds an additional 82hB for a total of 11Eh + 82h =

1A0hB.

1A0hB/4 = 68h Dwords

Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) Entry point

00h for ID-CFI parameter is byte offset = 1000h relative to SFDP location

zero.

10h Parameter Table Pointer Byte 1

00h Parameter Table Pointer Byte 2

Parameter Header

5 2nd DWORD

35h

36h

37h

01h Parameter ID MSb (01h = JEDEC JEP106 Bank Number 1)

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13.2

Device ID and Common Flash Interface (ID-CFI) address map

13.2.1

Field definitions

Table 53

Manufacturer and Device ID

Byte address

00h

Data

01h

Description

Manufacturer ID for Cypress

Device ID Most Significant Byte - Memory Interface

Type

Device ID Least Significant Byte - Density

01h

02h

20h (128 Mb)

18h (128 Mb)

ID-CFI Length - number bytes following. Adding this

value to the current location of 03h gives the address

of the last valid location in the legacy ID-CFI address

map. This only includes up to the end of the Primary

Vendor Specific table. The Alternate Vendor Specific

table contains additional information.

03h

4Dh

00h (Uniform 256-KB sectors)

01h (4-KB parameter sectors with Sector Architecture

uniform 64-KB sectors)

04h

05h

06h

80h (FL-S Family)

xxh

Family ID

ASCII characters for Model

Refer to “Ordering information” on page 168 for the

model number definitions.

07h

xxh

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

xxh

Reserved

Table 54

CFI query identification string

Byte address

Data

Description

10h

11h

12h

51h

52h

59h

Query Unique ASCII string “QRY”

13h

14h

02h

00h

Primary OEM Command Set

FL-P backward compatible command set ID

15h

16h

40h

00h

Address for Primary Extended Table

Alternate OEM Command Set

ASCII characters “FS” for SPI (F) interface, S

Technology

17h

18h

53h

46h

19h

1Ah

51h

00h

Address for Alternate OEM Extended Table

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 55

Byte address

1Bh

CFI system interface string

Data

27h

36h

00h

06h

Description

V_CCMin. (erase/program): 100 millivolts

_CCMax. (erase/program): 100 millivolts

_PPMin. voltage (00h = no V_PPpresent)

_PPMax. voltage (00h = no V_PPpresent)

Typical timeout per single byte program 2^Nµs

Typical timeout for Min. size Page program 2^Nµs

(00h = not supported)

1Ch

1Dh

1Eh

1Fh

V

0Ah (256B page)

0Ah (512B page)

08h (4 KB or 64 KB)

0Ah (256 KB)

20h

21h

22h

Typical timeout per individual sector erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not

supported)

0Fh (128 Mb)

23h

24h

02h

Max. timeout for byte program 2^Ntimes typical

Max. timeout for page program 2^Ntimes typical

Max. timeout per individual sector erase 2^Ntimes

typical

25h

26h

03h

Max. timeout for full chip erase 2^Ntimes typical

(00h = not supported)

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 56

Device geometry definition for bottom boot initial delivery state

Byte address

Data

18h (128 Mb)

02h

Description

Device Size = 2^Nbytes;

27h

28h

Flash Device Interface Description;

0000h = x8 only

0001h = x16 only

0002h = x8/x16 capable

0003h = x32 only

29h

01h

0004h = Single I/O SPI, 3-byte address

0005h = Multi I/O SPI, 3-byte address

0102h = Multi I/O SPI, 3- or 4-byte address

2Ah

2Bh

08h

00h

Max. number of bytes in multi-byte write = 2^N

(0000 = not supported

0008h = 256B page

0009h = 512B page)

Number of Erase Block Regions within device

1 = Uniform Device, 2 = Boot Device

2Ch

02h

2Dh

2Eh

2Fh

0Fh

00h

10h

Erase Block Region 1 Information (refer to JEDEC

JEP137)

16 sectors = 16-1 = 000Fh

4-KB sectors = 256 bytes x 0010h

30h

00h

31h

32h

33h

34h

FEh

00h (128 Mb)

00h

Erase Block Region 2 Information

255 sectors = 255-1 = 00FEh (128 Mb)

64-KB sectors = 0100h x 256 bytes

01h

35h thru 3Fh

FFh

RFU

Note

50.FL127S 128 Mb devices have either a hybrid sector architecture with sixteen 4 KB sectors and all remaining

sectors of 64 KB or with uniform 256 KB sectors. Devices with the hybrid sector architecture are initially

shipped from Cypress with the 4 KB sectors located at the bottom of the array address map. However, the

device configuration TBPARM bit CR1[2] may be programed to invert the sector map to place the 4 KB

sectors at the top of the array address map. The CFI geometry information of the above table is relevant

only to the initial delivery state of a hybrid sector device. The Flash device driver software must examine

the TBPARM bit to determine if the sector map was inverted at a later time.

Datasheet

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 57

Device geometry definition for uniform sector devices

Byte address

Data

18h (128 Mb)

02h

Description

Device Size = 2^Nbytes;

27h

28h

Flash Device Interface Description;

0000h = x8 only

0001h = x16 only

0002h = x8/x16 capable

0003h = x32 only

29h

01h

0004h = Single I/O SPI, 3-byte address

0005h = Multi I/O SPI, 3-byte address

0102h = Multi I/O SPI, 3- or 4-byte address

2Ah

2Bh

09h

00h

Max. number of bytes in multi-byte write = 2^N

(0000 = not supported

0008h = 256B page

0009h = 512B page)

Number of Erase Block Regions within device

1 = Uniform Device, 2 = Boot Device

2Ch

01h

2Dh

2Eh

2Fh

3Fh (128 Mb)

Erase Block Region 1 Information (refer to JEDEC

JEP137)

00h

04h

FFh

64 sectors = 64-1 = 003Fh (128 Mb)

256-KB sectors = 256 bytes x 0400h

30h

31h thru 3Fh

RFU

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 58

CFI primary vendor-specific extended query

Byte address

Data

50h

52h

49h

31h

33h

Description

40h

41h

42h

43h

44h

Query-unique ASCII string “PRI”

Major version number = 1, ASCII

Minor version number = 3, ASCII

Address Sensitive Unlock (Bits 1–0)

00b = Required

01b = Not Required

Process Technology (Bits 5-2)

0000b = 0.23 µm Floating Gate

0001b = 0.17 µm Floating Gate

0010b = 0.23 µm MirrorBit

0011b = 0.11 µm Floating Gate

0100b = 0.11 µm MirrorBit

0101b = 0.09 µm MirrorBit

1000b = 0.065 µm MirrorBit

45h

21h

Erase Suspend

0 = Not Supported

1 = Read Only

2 = Read and Program

46h

02h

Sector Protect

47h

48h

01h

00h

00 = Not Supported

X = Number of sectors in group

Temporary Sector Unprotect

00 = Not Supported

01 = Supported

Sector Protect/Unprotect Scheme

04 = High Voltage Method

05 = Software Command Locking Method

08 = Advanced Sector Protection Method

09 = Secure

49h

08h

Simultaneous Operation

00 = Not Supported

4Ah

4Bh

00h

01h

X = Number of Sectors

Burst Mode (Synchronous sequential read) support

00 = Not Supported

01 = Supported

Page Mode Type, model dependent

00 = Not Supported

Model Dependent

03h (Models x0)

04h (Models x1)

01 = 4 Word Read Page

4Ch

02 = 8 Read Word Page

03 = 256-Byte Program Page

04 = 512-Byte Program Page

ACC (Acceleration) Supply Minimum

00 = Not Supported, 100 mV

ACC (Acceleration) Supply Maximum

00 = Not Supported, 100 mV

4Dh

4Eh

00h

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 58

CFI primary vendor-specific extended query (Continued)

Byte address

Data

Description

WP# Protection

01 = Whole Chip

4Fh

50h

07h

04 = Uniform Device with Bottom WP Protect

05 = Uniform Device with Top WP Protect

07 = Uniform Device with Top or Bottom Write Protect (user select)

Program Suspend

00 = Not Supported

01 = Supported

01h

The alternate vendor-specific extended query provides information related to the expanded command set

provided by the FL-S family. The alternate query parameters use a format in which each parameter begins with

an identifier byte and a parameter length byte. Driver software can check each parameter ID and can use the

length value to skip to the next parameter if the parameter is not needed or not recognized by the software.

Table 59

Byte address

51h

CFI alternate vendor-specific extended query header

Data

41h

4Ch

54h

32h

30h

Description

52h

53h

54h

55h

Query-unique ASCII string “ALT”

Major version number = 2, ASCII

Minor version number = 0, ASCII

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 60

CFI Alternate Vendor-Specific Extended Query Parameter 0

Parameter

relative byte

Data

00h

Description

Parameter ID (ordering part number)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of

the next parameter)

address offset

00h

01h

10h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

53h

32h

35h

46h

4Ch

ASCII “S” for manufacturer (Infineon)

ASCII “25” for Product Characters (Single Die SPI)

ASCII “FL” for Interface Characters (SPI 3 Volt)

31h (128 Mb)

32h (128 Mb)

38h (128 Mb)

53h

ASCII characters for density

ASCII “S” for technology (65-nm MIRRORBIT™)

ASCII characters for speed grade

Refer to “Ordering information” on page 168 for the speed grade

definitions.

ASCII “??” for Package (Generally the package is not specified for an

individual memory device because the choice of package is generally

made after the device is tested and this parameter is programmed.

However, space is provided in this parameter for special cases where

devices are tested and programmed for use only in a specific

package)

41h

0Ch

0Dh

42h

3Fh

0Eh

3Fh

0Fh

10h

49h

xxh

ASCII character for temperature range

ASCII characters for Model

Refer to “Ordering information” on page 168 for the model number

11h

xxh

definitions.

Table 61

CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options

Parameter

relative byte

Data

80h

Description

address offset

00h

01h

Parameter ID (address options)

Parameter Length (The number of following bytes in this parameter. Adding

this value to the current location value + 1 = the first byte of the next

parameter)

01h

Bits 7:4 - Reserved = 1111b

Bit 3 - AutoBoot support - Ye s= 0b, No = 1b

Bit 2 - 4-byte address instructions supported - Yes = 0b, No = 1b

Bit 1 - Bank address + 3-byte address instructions supported - Yes = 0b, No

= 1b

02h

F0h

Bit 0 - 3-byte address instructions supported - Yes = 0b, No = 1b

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 62

CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands

Parameter

relative byte

Data

84h

Description

Parameter ID (Suspend Commands)

Parameter Length (The number of following bytes in this parameter. Adding

this value to the current location value + 1 = the first byte of the next

parameter)

address offset

00h

01h

08h

02h

03h

04h

05h

06h

07h

08h

09h

85h

2Dh

8Ah

64h

75h

2Dh

7Ah

64h

Program suspend instruction code

Program suspend latency maximum (µs)

Program resume instruction code

Program resume to next suspend typical (µs)

Erase suspend instruction code

Erase suspend latency maximum (µs)

Erase resume instruction code

Erase resume to next suspend typical (µs)

Table 63

CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection commands

Parameter

relative byte

Data

88h

Description

address offset

00h

01h

Parameter ID (Data Protection)

Parameter Length (The number of following bytes in this parameter. Adding

this value to the current location value + 1 = the first byte of the next

parameter)

OTP size 2^Nbytes, FFh = not supported

04h

02h

03h

0Ah

01h

OTP address map format, 01h = FL-S format, FFh = not supported

Block Protect Type, model dependent

00h = FL-P, FL-S, FFh = not supported

Advanced Sector Protection type, model dependent

01h = FL-S ASP.

04h

05h

xxh

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 64

CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing

Parameter

relative byte

Data

8Ch

06h

Description

Parameter ID (Reset Timing)

Parameter Length (The number of following bytes in this parameter.

Adding this value to the current location value + 1 = the first byte of

the next parameter)

address offset

00h

01h

02h

03h

96h

01h

POR maximum value

POR maximum exponent 2^Nµs

FFh (without

RESET# input)

23h (with RESET#

input)

04h

Hardware Reset maximum value

05h

06h

07h

00h

23h

00h

Hardware Reset maximum exponent 2^Nµs

Software Reset maximum value, FFh = not supported

Software Reset maximum exponent 2^Nµs

Datasheet

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 65

CFI Alternate Vendor-Specific Extended Query Parameter 90h – latency code

Parameter

relative byte

Data

90h

Description

Parameter ID (Latency Code Table)

Parameter Length (The number of following bytes in this parameter. Adding

this value to the current location value + 1 = the first byte of the next

parameter)

address offset

00h

01h

56h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

06h

0Eh

46h

43h

03h

13h

0Bh

0Ch

3Bh

3Ch

6Bh

6Ch

BBh

BCh

EBh

ECh

32h

03h

00h

04h

00h

02h

01h

50h

00h

FFh

Number of rows

Row length in bytes

Start of header (row 1), ASCII “F” for frequency column header

ASCII “C” for Code column header

Read 3-byte address instruction

Read 4-byte address instruction

Read Fast 3-byte address instruction

Read Fast 4-byte address instruction

Read Dual Out 3-byte address instruction

Read Dual Out 4-byte address instruction

Read Quad Out 3-byte address instruction

Read Quad Out 4-byte address instruction

Dual I/O Read 3-byte address instruction

Dual I/O Read 4-byte address instruction

Quad I/O Read 3-byte address instruction

Quad I/O Read 4-byte address instruction

Start of row 2, SCK frequency limit for this row (50 MHz)

Latency Code for this row (11b)

Read mode cycles

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 3, SCK frequency limit for this row (80 MHz)

Latency Code for this row (00b)

Read mode cycles (FFh = command not supported at this frequency)

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 65

CFI Alternate Vendor-Specific Extended Query Parameter 90h – latency code (Continued)

Parameter

relative byte

Data

Description

address offset

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

FFh

00h

08h

00h

08h

00h

08h

04h

00h

02h

04h

5Ah

01h

FFh

00h

08h

00h

08h

00h

08h

04h

01h

02h

04h

68h

02h

FFh

00h

08h

00h

08h

00h

08h

04h

02h

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 4, SCK frequency limit for this row (90 MHz)

Latency Code for this row (01b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Start of row 5, SCK frequency limit for this row (108 MHz)

Latency Code for this row (10b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 65

CFI Alternate Vendor-Specific Extended Query Parameter 90h – latency code (Continued)

Parameter

relative byte

Data

Description

address offset

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

05h

85h

02h

FFh

00h

08h

FFh

Quad I/O Read latency cycles

Start of row 6, SCK frequency limit for this row (133 MHz)

Latency Code for this row (10b)

Read mode cycles (FFh = command not supported at this frequency)

Read latency cycles

Read Fast mode cycles

Read Fast latency cycles

Read Dual Out mode cycles

Read Dual Out latency cycles

Read Quad Out mode cycles

Read Quad Out latency cycles

Dual I/O Read mode cycles

Dual I/O Read latency cycles

Quad I/O Read mode cycles

Quad I/O Read latency cycles

Table 66

CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU

Parameter

relative byte

Data

F0h

Description

address offset

00h

01h

Parameter ID (RFU)

Parameter Length (The number of following bytes in this parameter. Adding

this value to the current location value + 1 = the first byte of the next

parameter)

0Fh

02h

...

10h

FFh

RFU

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time. The

parameter is used to reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a

required boundary.

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

00h

—

N/A

A5h

CFI Parameter ID (A5h = JEDEC SFDP)

CFI Parameter Length (The number of

following bytes in this parameter. Adding

this value to the current location value + 1

= the first byte of the next parameter)

01h

—

N/A

80h

E7h

Start of SFDP JEDEC parameter, located

at 1120h in the overall SFDP address

space. Bits 7:5 = unused = 111b

Bit 4:3 = 06h is status register write

instruction & status register is default

nonvolatile= 00b

02h

03h

04h

00h

01h

02h

Bit 2 = Program Buffer > 64Bytes = 1 Bits

1:0 = Uniform 4KB erase unavailable = 11b

JEDEC Basic

Flash

Bits 15:8 = Uniform 4KB erase opcode =

not supported = FFh

FFh

F3h

Parameter

Dword-1

Bit 23 = Unused = 1b

Bit 22 = Supports Quad Out Read, Yes = 1b

Bit 21 = Supports Quad I/O Read, Yes =1b

Bit 20 = Supports Dual I/O Read, Yes = 1b

(FLxxxSAG) Bit19 = Supports DDR, No = 0h

Bit 18:17 = Number of Address Bytes, 3 or

4 = 01b

Bit 16 = Supports Dual Out Read, Yes = 1b

05h

06h

03h

04h

FFh

Bits 31:24 = Unused = FFh

Density in bits, zero based, 128Mb =

07FFFFFFh

JEDEC Basic

Flash

07h

08h

09h

05h

06h

07h

FFh

07h

Parameter

Dword-2

Bits 7:5 = number of Quad I/O Mode cycles

= 010b

0Ah

08h

44h

Bits 4:0 = number of Quad I/O Dummy

cycles = 00100b for default latency code

00b

JEDEC Basic

Flash

0Bh

0Ch

0Dh

09h

0Ah

0Bh

EBh

08h

6Bh

Quad I/O instruction code

Parameter

Dword-3

Bits 23:21 = number of Quad Out Mode

cycles = 000b

Bits 20:16 = number of Quad Out Dummy

cycles = 01000b

Quad Out instruction code

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SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

Bits 7:5 = number of Dual Out Mode cycles

= 000b

0Eh

0Fh

10h

11h

12h

0Ch

0Dh

0Eh

0Fh

10h

08h

3Bh

80h

BBh

EEh

Bits 4:0 = number of Dual Out Dummy

cycles = 01000b for default latency code

JEDEC Basic

Flash

Dual Out instruction code

Parameter

Dword-4

Bits 23:21 = number of Dual I/O Mode

cycles

20:16 = number of Dual I/O Dummy cycles

Default Latency code = 00b

Dual I/O instruction code

Bits 7:5 RFU = 111b

Bit 4 = Quad All not supported = 0b

Bits 3:1 RFU = 111b

JEDEC Basic

Flash

Bit 0 = Dual All not supported = 0b

Parameter

Dword-5

13h

14h

15h

16h

17h

11h

12h

13h

14h

15h

FFh

Bits 15:8 = RFU = FFh

Bits 23:16 = RFU = FFh

Bits 31:24 = RFU = FFh

Bits 7:0 = RFU = FFh

Bits 15:8 = RFU = FFh

JEDEC Basic

Flash

Bits 23:21 = number of Dual All Mode

cycles = 111b

Parameter

Dword-6

18h

16h

FFh

Bits 20:16 = number of Dual All Dummy

cycles = 11111b

19h

1Ah

1Bh

17h

18h

19h

FFh

Dual All instruction code

Bits 7:0 = RFU = FFh

Bits 15:8 = RFU = FFh

JEDEC Basic

Flash

Bits 23:21 = number of Quad All Mode

cycles = 111b

Parameter

Dword-7

1Ch

1Ah

FFh

Bits 20:16 = number of Quad All Dummy

cycles = 11111b

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

FFh

0Ch

20h

10h

D8h

12h

D8h

00h

Quad All instruction code

Erase type 1 size 2^NBytes = 4KB = 0Ch (for

Hybrid Sector Initial Delivery State)

JEDEC Basic

Flash

Erase type 1 instruction

Erase type 2 size 2^NBytes = 64KB = 10h (for

Hybrid Sector Initial Delivery State)

Erase type 2 instruction

Erase type 3 size 2^NBytes = 256KB = 12h (if

Uniform Sectors enabled)

Erase type 3 instruction

Erase type 4 size 2^NBytes = not supported

= 00h

Parameter

Dword-8

JEDEC Basic

Flash

Parameter

Dword-9

Erase type 4 instruction = not supported =

FFh

25h

23h

FFh

Datasheet

150

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

26h

27h

28h

24h

25h

26h

82h

02h

0Eh

Bits 31:30 = Erase type 4 Erase, Typical

time units (00b: 1 ms, 01b: 16 ms,

10b: 128 ms, 11b: 1 s) = RFU = 11b

Bits 29:25 = Erase type 4 Erase, Typical

time count = RFU = 11111b (typ erase time

= count + 1 * units = RFU)

Bits 24:23 = Erase type 3 Erase, Typical

time units (00b: 1 ms, 01b: 16 ms, 10b: 128

ms, 11b: 1 s) = 128mS = 10b

Bits 22:18 = Erase type 3 Erase, Typical

time count = 00011b ( typ erase time =

count + 1 * units = 4 * 128 ms = 512 ms)

Bits 17:16 = Erase type 2 Erase, Typical

time units (00b: 1 ms, 01b: 16 ms,

10b: 128 ms, 11b: 1 s) = 128 ms = 10b

Bits 15:11 = Erase type 2 Erase, Typical

time count = 00000b ( typ erase time =

count + 1 * units = 1 * 128 ms = 128 ms)

Bits 10:9 = Erase type 1 Erase, Typical time

units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms,

11b: 1 s) = 16 ms = 01b

JEDEC Basic

Flash

Parameter

Dword-10

29h

27h

FFh

Bits 8:4 = Erase type 1 Erase, Typical time

count = 01000b (typ erase time = count + 1

* units = 9 * 16 ms = 144 ms)

Bits 3:0 = Multiplier from typical erase

time to maximum erase time = 2 * (N + 1),

N = 2h = 6x multiplier

Binary Fields:

11-11111-10-00011-10-00000-01-01000-

0010

Nibble Format:

1111_1111_0000_1110_0000_0010_1000

_0010

Hex Format: FF_0E_02_82

Datasheet

151

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

2Ah

2Bh

2Ch

28h

29h

2Ah

92h

29h

07h

Bit 31 Reserved = 1b

Bits 30:29 = Chip Erase, Typical time units

(00b: 16 ms, 01b: 256 ms, 10b: 4 s,

11b: 64 s) = 4s = 10b

Bits 28:24 = Chip Erase, Typical time

count, (count + 1) * units, count = 01000b,

(typ Program time = count + 1 * units =

9 * 4 s = 36 s

Bits 23 = Byte Program Typical time,

additional byte units (0b:1 µs, 1b:8 µs) =

1 µs = 0b

Bits 22:19 = Byte Program Typical time,

additional byte count, (count + 1) * units,

count = 0000b, (typ Program time =

count + 1 * units = 1 * 1 µs = 1 µs

Bits 18 = Byte Program Typical time, first

byte units (0b:1 µs, 1b:8 µs) = 8 µs = 1b

Bits 17:14 = Byte Program Typical time,

first byte count, (count + 1) * units, count

= 1100b, (typ Program time =

JEDEC Basic

Flash

Parameter

Dword-11

count + 1 * units = 13 * 8 µs = 104 µs

Bits 13 = Page Program Typical time units

(0b:8 µs, 1b:64 µs) = 64 µs = 1b

2Dh

2Bh

C8h

Bits 12:8 = Page Program Typical time

count, (count + 1)*units, count = 01001b,

(typ Program time = count + 1 * units =

10 * 64 µs = 640 µs)

Bits 7:4 = Page size 2^N, N = 9h, = 512B

page

Bits 3:0 = Multiplier from typical time to

maximum for Page or Byte program =

2 * (N + 1), N = 2h = 6x multiplier

Binary Fields:

1-10-01000-0-0000-1-1100-1-01001-1001-

0010

Nibble Format:

1100_1000_0000_0111_0010_1001_1001

_0010

Hex Format: C8_07_29_92

Datasheet

152

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

2Eh

2Fh

30h

2Ch

2Dh

2Eh

ECh

A3h

18h

Bit 31 = Suspend and Resume supported =

0b

Bits 30:29 = Suspend in-progress erase

max latency units (00b: 128 ns, 01b: 1 µs,

10b: 8 µs, 11b: 64 µs) = 8 µs= 10b

Bits 28:24 = Suspend in-progress erase

max latency count = 00101b, max erase

suspend latency = count + 1 * units =

6 * 8 µs = 48 µs

Bits 23:20 = Erase resume to suspend

interval count = 0001b, interval =

count + 1 * 64 µs = 2 * 64 µs = 128 µs

Bits 19:18 = Suspend in-progress program

max latency units (00b: 128 ns, 01b: 1 µs,

10b: 8 µs, 11b: 64 µs) = 8 µs= 10b

Bits 17:13 = Suspend in-progress program

max latency count = 00101b, max erase

suspend latency = count + 1 * units =

6 * 8 µs = 48 µs

Bits 12:9 = Program resume to suspend

interval count = 0001b, interval =

count + 1 * 64 µs = 2 * 64 µs = 128 µs

Bit 8 = RFU = 1b

Bits 7:4 = Prohibited operations during

erase suspend

JEDEC Basic

Flash

= xxx0b: May not initiate a new erase

anywhere (erase nesting not permitted)

+ xx1xb: May not initiate a page program

in the erase suspended sector size

+ x1xxb: May not initiate a read in the

erase suspended sector size + 1xxxb: The

erase and program restrictions in bits 5:4

are sufficient = 1110b

Parameter

Dword-12

31h

2Fh

45h

Bits 3:0 = Prohibited Operations During

Program Suspend

= xxx0b: May not initiate a new erase

anywhere (erase nesting not permitted)

+ xx0xb: May not initiate a new page

program anywhere (program nesting not

permitted)

+ x1xxb: May not initiate a read in the

program suspended page size

+ 1xxxb: The erase and program

restrictions in bits 1:0 are sufficient =

1100b

Binary Fields:

0-10-00101-0001-10-00101-0001-1-1110-

1100

Nibble Format:

0100_0101_0001_1000_1010_0011_1110

_1100

Hex Format: 45_18_A3_EC

Datasheet

153

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

32h

33h

34h

30h

31h

32h

8Ah

85h

7Ah

Bits 31:24 = Erase Suspend Instruction =

75h

JEDEC Basic

Flash

Bits 23:16 = Erase Resume Instruction =

7Ah

Parameter

Dword-13

Bits 15:8 = Program Suspend Instruction =

85h

35h

33h

75h

Bits 7:0 = Program Resume Instruction =

8Ah

36h

37h

38h

34h

35h

36h

F7h

FFh

Bit 31 = Deep Power Down Supported =

not supported = 1

Bits 30:23 = Enter Deep Power Down

Instruction = not supported = FFh

Bits 22:15 = Exit Deep Power Down

Instruction = not supported = FFh

Bits 14:13 = Exit Deep Power Down to next

operation delay units = (00b: 128 ns,

01b: 1 µs, 10b: 8 µs, 11b: 64 µs) = 64 µs =

11b

Bits 12:8 = Exit Deep Power Down to next

operation delay count = 11111b, Exit Deep

Power Down to next operation delay =

(count + 1) * units = not supported

Bits 7:4 = RFU = Fh

JEDEC Basic

Flash

Parameter

Dword-14

Bit 3:2 = Status Register Polling Device

Busy

39h

37h

FFh

= 01b: Legacy status polling supported =

Use legacy polling by reading the Status

Register with 05h instruction and

checking WIP bit[0] (0 = ready; 1 = busy).

Bits 1:0 = RFU = 11b

Binary Fields:

1-11111111-11111111-11-11111-1111-01-

11

Nibble Format:

1111_1111_1111_1111_1111_1111_1111

_0111

Hex Format: FF_FF_FF_F7

Datasheet

154

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

3Ah

3Bh

3Ch

38h

39h

3Ah

00h

F6h

5Dh

Bits 31:24 = RFU = FFh

Bit 23 = Hold and WP Disable = not

supported = 0b

Bits 22:20 = Quad Enable Requirements

= 101b: QE is bit 1 of the status register 2

(SFDP spec calls this Status Register 2,

FL127S calls this

Configuration Register 1).

Status register 1 is read using Read Status

instruction 05h. Status register 2 (FL127S

Configuration Register 1) is read using

instruction 35h. QE is set via Write Status

instruction 01h with two data bytes where

bit 1 of the second byte is one. It is cleared

via Write Status with two data bytes

where bit 1 of the second byte is zero.

Bits 19:16 0-4-4 Mode Entry Method

= xxx1b: Mode Bits[7:0] = A5h Note: QE

must be set prior to using this mode

+ x1xxb: Mode Bits[7:0] = Axh

+ 1xxxb: RFU

= 1101b

JEDEC Basic

Flash

Bits 15:10 = 0-4-4 Mode Exit Method

= xx_xxx1b: Mode Bits[7:0] = 00h will

terminate this mode at the end of the

current read operation

Parameter

Dword-15

3Dh

3Bh

FFh

+ xx_1xxxb: Input Fh (mode bit reset) on

DQ0-DQ3 for 8 clocks. This will terminate

the mode prior to the next read operation.

+ x1_xxxxb: Mode Bit[7:0] != Axh

+ 1x_x1xx: RFU

= 11_1101

Bit 9 = 0-4-4 mode supported = 1

Bits 8:4 = 4-4-4 mode enable sequences

= 0_0000b: 4-4-4 not supported

= 00000b

Bits 3:0 = 4-4-4 mode disable sequences

= 0000b: 4-4-4 not supported

= 0000b

Binary Fields:

11111111-0-101-1101-111101-1-00000-

0000

Nibble Format:

1111_1111_0101_1101_1111_0110_0000

_0000

Hex Format: FF_5D_F6_00

Datasheet

155

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

Bits 31:24 = Enter 4-Byte Addressing

= xxxx_1xxxb: 8-bit volatile bank register

used to define A[30:A24] bits. MSb (bit[7]) is

used to enable/disable 4-byte address

mode. When MSb is set to ‘1’, 4-byte

address mode is active and A[30:24] bits

are don’t care. Read with instruction 16h.

Write instruction is 17h with 1 byte of data.

When MSb is cleared to ‘0’, select the active

128 Mb segment by setting the appropriate

A[30:24] bits and use 3-Byte addressing.

+ xx1x_xxxxb: Supports dedicated 4-Byte

address instruction set. Consult vendor

data sheet for the instruction set definition

or look for 4 Byte Address Parameter Table.

+ 1xxx_xxxxb: Reserved

3Eh

3Fh

40h

3Ch

3Dh

3Eh

F0h

28h

FAh

= 10101000b

Bits 23:14 = Exit 4-Byte Addressing

= xx_xxxx_1xxxb: 8-bit volatile bank

register used to define A[30:A24] bits. MSb

(bit[7]) is used to enable/disable 4-byte

address mode. When MSb is cleared to ‘0’,

3-byte address mode is active and A30:A24

are used to select the active 128 Mb

memory segment. Read with instruction

16h. Write instruction is 17h, data length is

1 byte.

JEDEC Basic

Flash

+ xx_xx1x_xxxxb: Hardware reset

+ xx_x1xx_xxxxb: Software reset (see bits

13:8 in this DWORD)

Parameter

Dword-16

+ xx_1xxx_xxxxb: Power cycle

41h

3Fh

A8h

+ x1_xxxx_xxxxb: Reserved

+ 1x_xxxx_xxxxb: Reserved = 1111101000b

Bits 13:8 = Soft Reset and Rescue Sequence

Support

= x0_1xxxb: issue instruction F0h

+ 1x_xxxxb: exit 0-4-4 mode is required

prior to other reset sequences above if the

device may be operating in this mode. =

101000b

Bit 7 = RFU = 1

Bits 6:0 = Volatile or Nonvolatile Register

and Write Enable Instruction for Status

Register 1

= xx1_xxxxb: Status Register 1 contains a

mix of volatile and nonvolatile bits. The

06h instruction is used to enable writing of

the register.

+ x1x_xxxxb: Reserved

+ 1xx_xxxxb: Reserved

= 1110000b

Binary Fields:

10101000-1111101000-101000-1-1110000

Nibble Format:

1010_1000_1111_1010_0010_1000_1111_

0000

Hex Format: A8_FA_28_F0

Datasheet

156

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

42h

43h

44h

40h

41h

42h

FCh

07h

30h

Bits 31:24 = Read data mask = 10000000b:

Select bit 7 of the data byte for D8h_O

value

Bits 23:22 = Configuration detection

command address length = 00b: No

address

Bits 21:20 = RFU = 11b

Bits 19:16 = Configuration detection

command latency = 0000b: zero latency

Bits 15:8 = Configuration detection

instruction = 07h: Read status register 2

Bits 7:2 = RFU = 111111b

JEDEC

Sector Map

Parameter

Dword-1

Config.

Bit 1 = Command Descriptor = 0

Bit 0 = not the end descriptor = 0

45h

43h

80h

Detect-1

Binary Fields:

10000000-00-11-0000-00000111-111111-

0-0

Nibble Format:

1000_0000_0011_0000_0000_0111_1111

_1100

Hex Format: 80_30_07_FC

46h

47h

48h

44h

45h

46h

JEDEC

Sector Map

Parameter

Dword-2

Config.

FFh

Bits 31:0 = Sector map configuration

detection command address = FFFFh: no

address

49h

47h

FFh

Detect-1

4Ah

4Bh

4Ch

48h

49h

4Ah

FDh

35h

30h

Bits 31:24 = Read data mask = 00000100b:

Select bit 2 of the data byte for TBPARM

value

Bits 23:22 = Configuration detection

command address length = 00b: No

address

Bits 21:20 = RFU = 11b

Bits 19:16 = Configuration detection

command latency = 0000b: zero latency

Bits 15:8 = Configuration detection

instruction = 35h: Read configuration

register 1

JEDEC

Sector Map

Parameter

Dword-3

Config.

Bits 7:2 = RFU = 111111b

Bit 1 = Command Descriptor = 0

Bit 0 = The end descriptor = 1

4Dh

4Bh

04h

Detect-2

Binary Fields:

00000100-00-11-0000-00110101-111111-

0-1

Nibble Format:

0000_0100_0011_0000_0011_0101_1111

_1101

Hex Format: 04_30_35_FD

Datasheet

157

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

4Eh

4Fh

50h

4Ch

4Dh

4Eh

JEDEC

Sector Map

Parameter

Dword-4

Config.

FFh

Bits 31:0 = Sector map configuration

detection command address = FFFFh: no

address

51h

4Fh

FFh

Detect-2

52h

53h

54h

50h

51h

52h

FEh

00h

01h

Bits 31:24 = RFU = FFh

Bits 23:16 = Region count (Dwords - 1) =

01h: Two regions

JEDEC

Sector Map

Parameter

Dword-5

Config-0

Header

Bits 15:8 = Configuration ID = 00h: 4 KB

sectors at bottom with remainder 64 KB

sectors

Bits 7:2 = RFU = 111111b

55h

53h

FFh

Bit 1 = Map Descriptor = 1

Bit 0 = not the end descriptor = 0

56h

57h

58h

54h

55h

56h

F3h

FFh

00h

Bits 31:8 = Region size = 0000FFh:

Region size as count – 1 of 256 Byte units

= 16 x 4 KB sectors = 64 KB

Count = 64KB/256 = 256, value = count – 1

= 256 – 1 = 255 = FFh

Bits 7:4 = RFU = Fh

Erase Type not supported = 0/ supported

= 1

JEDEC

Sector Map

Parameter

Dword-6

Config-0

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 0b

---Erase Type 3 is 256 KB erase and is not

supported in the 4 KB sector region

Bit 1 = Erase Type 2 support = 1b

---Erase Type 2 is 64 KB erase and is

supported in the 4 KB sector region

Bits 0 = Erase Type 1 support = 1b

---Erase Type 1 is 4 KB erase and is

supported in the 4 KB sector region

59h

57h

00h

Region-0

5Ah

5Bh

5Ch

58h

59h

5Ah

F2h

FFh

FEh

Bits 31:8 = Region size = 00FEFFh:

Region size as count – 1 of 256 Byte units

= 255 x 64 KB sectors = 16320 KB

Count = 16320 KB/256 = 65280, value =

count – 1 = 65280 – 1 = 65279 = FEFFh

Bits 4:7 = RFU = Fh

Erase Type not supported = 0 / supported

= 1

JEDEC

Sector Map

Parameter

Dword-7

Config-0

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 0b

---Erase Type 3 is 256 KB erase and is not

supported in the 64 KB sector region

Bit 1 = Erase Type 2 support = 1b

---Erase Type 2 is 64 KB erase and is

supported in the 64 KB sector region

Bit 0 = Erase Type 1 support = 0b

--- Erase Type 1 is 4 KB erase and is not

supported in the 64 KB sector region

5Dh

5Bh

00h

Region-1

Datasheet

158

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

5Eh

5Fh

60h

5Ch

5Dh

5Eh

FEh

01h

Bits 31:24 = RFU = FFh

Bits 23:16 = Region count (Dwords – 1) =

01h: Two regions

JEDEC

Sector Map

Parameter

Dword-8

Config-1

Header

Bits 15:8 = Configuration ID = 01h: 4KB

sectors at top with remainder 64KB

sectors

Bits 7:2 = RFU = 111111b

61h

5Fh

FFh

Bit 1 = Map Descriptor = 1

Bit 0 = not the end descriptor = 0

62h

63h

64h

60h

61h

62h

F2h

FFh

FEh

Bits 31:8 = Region size = 00FEFFh:

Region size as count – 1 of 256 Byte units

= 255 x 64KB sectors = 16320 KB

Count = 16320KB/256 = 65280, value =

count – 1 = 65280 – 1 = 65279 = FEFFh

Bits 4:7 = RFU = Fh

Erase Type not supported = 0/ supported

= 1

JEDEC

Sector Map

Parameter

Dword-9

Config-1

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 0b

---Erase Type 3 is 256 KB erase and is not

supported in the 64 KB sector region

Bit 1 = Erase Type 2 support = 1b

---Erase Type 2 is 64 KB erase and is

supported in the 64 KB sector region

Bit 0 = Erase Type 1 support = 0b

--- Erase Type 1 is 4 KB erase and is not

supported in the 64 KB sector region

65h

63h

00h

Region-0

66h

67h

68h

64h

65h

66h

F3h

FFh

00h

Bits 31:8 = Region size = 0000FFh:

Region size as count – 1 of 256 Byte units

= 16 x 4 KB sectors = 64 KB

Count = 64 KB/256 = 256, value = count – 1

= 256 – 1 = 255 = FFh

Bits 7:4 = RFU = Fh

Erase Type not supported = 0/ supported

= 1

JEDEC

Sector Map

Parameter

Dword-10

Config-1

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 0b

---Erase Type 3 is 256 KB erase and is not

supported in the 4 KB sector region

Bit 1 = Erase Type 2 support = 1b

---Erase Type 2 is 64 KB erase and is

supported in the 4 KB sector region

Bit 0 = Erase Type 1 support = 1b

---Erase Type 1 is 4 KB erase and is

supported in the 4 KB sector region

69h

67h

00h

Region-1

6Ah

6Bh

6Ch

68h

69h

6Ah

FEh

02h

00h

Bits 31:24 = RFU = FFh Bits 23:16 = Region

count (Dwords – 1) = 00h: One region

Bits 15:8 = Configuration ID = 02h: Uniform

256KB sectors

JEDEC

Sector Map

Parameter

Dword-11

Config-2

Bits 7:2 = RFU = 111111b

Bit 1 = Map Descriptor = 1

6Dh

6Bh

FFh

Header

Bit 0 = The end descriptor = 0

Datasheet

159

001-98282 Rev. *K

2022-07-25

128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

6Eh

6Fh

70h

6Ch

6Dh

6Eh

F4h

FFh

Bits 31:8 = Region size = 00FFFFh:

Region size as count – 1 of 256 Byte units

= 16MB/256 = 64K

Count = 65536, value = count – 1 =

65536 – 1 = 65535 = FFFFh

Bits 4:7 = RFU = Fh

Erase Type not supported = 0/ supported

= 1

JEDEC

Sector Map

Parameter

Dword-12

Config-2

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 1b

---Erase Type 3 is 256 KB erase and is

supported in the 256 KB sector region

Bit 1 = Erase Type 2 support = 0b

---Erase Type 2 is 64 KB erase and is not

supported in the 256 KB sector region

Bit 0 = Erase Type 1 support = 0b

--- Erase Type 1 is 4 KB erase and is not

supported in the 256 KB sector region

71h

6Fh

00h

Region-0

72h

73h

74h

70h

71h

72h

FFh

03h

00h

Bits 31:24 = RFU = FFh

JEDEC

Sector Map

Parameter

Dword-13

Config-3

Bits 23:16 = Region count (Dwords – 1) =

00h: One region

Bits 15:8 = Configuration ID = 03h: Uniform

256 KB sectors

Bits 7:2 = RFU = 111111b

Bit 1 = Map Descriptor = 1

Bit 0 = The end descriptor = 1

75h

73h

FFh

Header

76h

77h

78h

74h

75h

76h

F4h

FFh

Bits 31:8 = Region size = 00FFFFh:

Region size as count – 1 of 256 Byte units

= 16 MB/256 = 64K

Count = 65536, value = count – 1 =

65536 – 1 = 65535 = FFFFh

Bits 4:7 = RFU = Fh

Erase Type not supported = 0/ supported

= 1

JEDEC

Sector Map

Parameter

Dword-14

Config-3

Bit 3 = Erase Type 4 support = 0b

---Erase Type 4 is not defined

Bit 2 = Erase Type 3 support = 1b

---Erase Type 3 is 256 KB erase and is

supported in the 256 KB sector region

Bit 1 = Erase Type 2 support = 0b

---Erase Type 2 is 64 KB erase and is not

supported in the 256 KB sector region

Bit 0 = Erase Type 1 support = 0b

--- Erase Type 1 is 4 KB erase and is not

supported in the 256 KB sector region

79h

77h

00h

Region-0

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 67

CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)

CFI parameter

SFDP parameter

relative byte

SFDPDword

name

relative byte

Data

Description

address offset

7Ah

7Bh

7Ch

78h

79h

7Ah

FFh

0Eh

FFh

Supported = 1, Not Supported = 0

Bits 31:20 = RFU = FFFh

Bit 19 = Support for nonvolatile individual

sector lock write command, Instruction =

E3h = 1

Bit 18 = Support for nonvolatile individual

sector lock read command, Instruction =

E2h = 1

Bit 17 = Support for volatile individual

sector lock Write command, Instruction =

E1h = 1

Bit 16 = Support for volatile individual

sector lock Read command, Instruction =

E0h = 1

Bit 15 = Support for (1-4-4) DTR_Read

Command, Instruction = EEh = 0

Bit 14 = Support for (1-2-2) DTR_Read

Command, Instruction = BEh = 0

Bit 13 = Support for (1-1-1) DTR_Read

Command, Instruction = 0Eh = 0

Bit 12 = Support for Erase Command –

Type 4 = 0

JEDEC4Byte

Address

Bit 11 = Support for Erase Command –

Type 3 = 1

Instructions

Parameter

Dword-1

Bit 10 = Support for Erase Command –

Type 2 = 1

7Dh

7Bh

FFh

Bit 9 = Support for Erase Command –

Type 1 = 1

Bit 8 = Support for (1-4-4) Page Program

Command, Instruction = 3Eh =0

Bit 7 = Support for (1-1-4) Page Program

Command, Instruction = 34h = 1

Bit 6 = Support for (1-1-1) Page Program

Command, Instruction = 12h = 1

Bit 5 = Support for (1-4-4) FAST_READ

Command, Instruction = ECh = 1

Bit 4 = Support for (1-1-4) FAST_READ

Command, Instruction = 6Ch = 1

Bit 3 = Support for (1-2-2) FAST_READ

Command, Instruction = BCh = 1

Bit 2 = Support for (1-1-2) FAST_READ

Command, Instruction = 3Ch = 1

Bit 1 = Support for (1-1-1) FAST_READ

Command, Instruction = 0Ch = 1

Bit 0 = Support for (1-1-1) READ

Command, Instruction = 13h = 1

7Eh

7Fh

80h

7Ch

7Dh

7Eh

21h

DCh

Bits 31:24 = FFh = Instruction for Erase

JEDEC4Byte

Address

Type 4: RFU

Bits 23:16 = DCh = Instruction for Erase

Instructions

Parameter

Dword-2

Type 3

Bits 15:8 = DCh = Instruction for Erase Type

2

81h

7Fh

FFh

Bits 7:0 = 21h = Instruction for Erase Type 1

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13.3

Device ID and Common Flash Interface (ID-CFI) ASO Map — Automotive

Only

The CFI Primary Vendor-Specific Extended Query is extended to include Electronic Marking information for device

traceability.

Table 68

Address

Device ID and Common Flash Interface (ID-CFI) map automotive only

Example

# of

Data

Data field

of actual

data

Hex read out of example data

bytes Format

Size of Electronic

Marking

Revision of

Electronic Marking

(SA) + 0180h

(SA) + 0181h

1

Hex

20

1

14h

01h

(SA) + 0182h

(SA) + 018Ah

(SA) + 018Bh Die X Coordinate

(SA) + 018Ch Die Y Coordinate

Fab Lot #

Wafer #

8

1

7

ASCII

Hex

ASCII

LD87270 4Ch, 44h, 38h, 37h, 32h, 37h, 30h, FFh

23

10

15

17h

0Ah

0Fh

(SA) + 018Dh

Class Lot #

BR33150 42h, 52h, 33h, 33h, 31h, 35h, 30h

FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh, FFh,

FFh, FFh, FFh

(SA) + 0194h ReservedforFuture 12

N/A

Fab Lot # + Wafer # + Die X Coordinate + Die Y Coordinate gives a unique ID for each device.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13.4

Registers

The register maps are copied in this section as a quick reference. See “Registers” on page 57 for the full

description of the register contents.

Table 69

Bits

Status Register 1 (SR1)

Function

Field

Default

state

Type

Description

name

1 = Locks state of SRWD, BP, and

Status Register

Write Disable

configuration register bits when WP# is

LOW by ignoring WRR command

7

SRWD

Nonvolatile

0

0 = No protection, even when WP# is LOW

Programming Error

Volatile,

1 = Error occurred

0 = No Error

1= Error occurred

0 = No Error

6

5

P_ERR

E_ERR

0

Occurred

Read only

Erase Error

Occurred

Volatile,

Read only

4

3

BP2

BP1

1 if

Volatile if

CR1[3]=1,

Nonvolatile

if CR1[3] = 0

CR1[3] = 1,

0 when

shipped

from

Protects selected range of sectors (Block)

from Program or Erase

Block Protection

2

BP0

Cypress

1 = Device accepts Write Registers (WRR),

program or erase commands

0 = Device ignores Write Registers (WRR),

program or erase commands

1

WEL

Write Enable Latch

Write in Progress

Volatile

0

This bit is not affected by WRR, only WREN

and WRDI commands affect this bit.

1= Device Busy, a Write Registers (WRR),

program, erase or other operation is in

progress

0 = Ready Device is in standby mode and

can accept commands

Volatile,

Read only

0

WIP

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 70

Bits

Configuration Register (CR1)

Field

Default

state

Function

Type

Description

name

7

6

LC1

0

Selects number of initial read latency

cycles

See Latency Code Tables

Latency Code

Nonvolatile

LC0

0

Configures Start of

Block Protection

1 = BP starts at bottom (Low address)

0 = BP starts at top (High address)

Reserved for Future Use

1 = Volatile

0 = Nonvolatile

5

4

3

TBPROT

RFU

OTP

0

RFU

Configures BP2–0 in

Status Register

BPNV

1 = 4-KB physical sectors at top, (High

address)

Configures Parameter

Sectors location

2

1

TBPARM

QUAD

OTP

0

0 = 4-KB physical sectors at bottom (Low

address)

RFU in uniform sector devices.

1 = Quad

0 = Dual or Serial

Puts the device into

Quad I/O operation

Nonvolatile

Lock current state of

BP2-0 bits in Status

Register, TBPROT and

TBPARM in

Configuration Register,

and OTP regions

1 = Block Protection and OTP locked

0 = Block Protection and OTP un-locked

0

FREEZE

Volatile

0

Table 71

Bits

Status Register 2 (SR2)

Field

Default

state

Function

Type

Description

name

1 = 256 KB Erase (Uniform sectors).

0 = 64 KB Erase (Hybrid 4 KB / 64 KB

sectors).

7

D8h_O

Block Erase Size

OTP

0

1 = Wrap at 512B.

0 = Wrap at 256B.

1 = IO3 alternate function is RESET#.

0 = IO3 alternate function is HOLD#.

6

5

02h_O

Page Buffer Wrap

IO3 Reset

OTP

0

IO3R_O

4

3

2

RFU

Reserved

0

Reserved for Future Use.

Reserved for Future Use

Volatile,

1 = In erase suspend mode.

1

0

ES

PS

Erase Suspend

0

Read only

0 = Not in erase suspend mode.

Volatile,

Read only

1 = In program suspend mode.

0 = Not in program suspend mode.

Program Suspend

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 72

Bits

Bank Address Register (BAR)

Field

Default

state

Function

Type

Description

name

1 = 4-byte (32-bits) addressing required

from command.

0 = 3-byte (24-bits) addressing from

command + Bank Address

Extended Address

Enable

7

EXTADD

Volatile

0b

6 to 2

1

0

RFU

BA25

BA24

Reserved

Bank Address

Volatile

00000b Reserved for Future Use

0

RFU for lower density devices

RFU for lower density device

Table 73

Bits

ASP Register (ASPR)

Field

Default

state

Function

Type

Description

name

RFU

15to9

Reserved

OTP

1

Reserved for Future Use

8

7

6

5

4

3

1

0 = Password Protection Mode

permanently enabled

1 = Password Protection Mode not

permanently enabled

Password Protection

Mode Lock Bit

2

PWDMLB

OTP

1

0 = Persistent Protection Mode

permanently enabled

Persistent Protection

Mode Lock Bit

1

0

PSTMLB

RFU

OTP

1

1 = Persistent Protection Mode not

permanently enabled

Reserved

Reserved for Future Use

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

Table 74

Bits

Password Register (PASS)

Field

Function

Type

Default state

Description

name

Nonvolatile OTP storage of 64-bit

password. The password is no longer

Hidden

Password

63to0

PWD

OTP

FFFFFFFF–FFFFFFFFh readable after the password protection

mode is selected by programming ASP

register bit 2 to 0.

Table 75

Bits

PPB Lock Register (PPBL)

Field

Function

Type

Default state

Description

name

7 to 1

RFU

Reserved Volatile

00h

Reserved for Future Use

Persistent Protection 0 = PPB array protected until next power

Mode = 1 cycle or hardware reset

Password Protection 1 = PPB array may be programmed or

Protect PPB

Volatile

Array

0

PPBLOCK

Mode = 0

Default state

FFh

erased

Table 76

Bits

PPB Access Register (PPBAR)

Field

Function

Type

Description

name

00h = PPB for the sector addressed by the

PPBRD or PPBP command is programmed

to “0”, protecting that sector from

program or erase operations.

FFh = PPB for the sector addressed by the

PPBRD or PPBP command is erased to “1”,

not protecting that sector from program

or erase operations.

Read or

7 to 0

PPB

Program per Nonvolatile

sector PPB

Table 77

Bits

DYB Access Register (DYBAR)

Field

Function

Type

Default state

Description

name

00h = DYB for the sector addressed by the

DYBRD or DYBP command is cleared to

“0”, protecting that sector from program

or erase operations.

FFh = DYB for the sector addressed by the

DYBRD or DYBP command is set to “1”, not

protecting that sector from program or

erase operations.

Read or

Write per

sector DYB

7 to 0

DYB

Volatile

FFh

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Serial flash discoverable parameters (SFDP)

address map

13.5

Initial delivery state

The device is shipped from Infineon with nonvolatile bits set as follows:

• The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).

• The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.

• The SFDP address space contains the values as defined in the description of the SFDP address space.

• The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.

• The Status Register 1 contains 00h (all SR1 bits are cleared to 0’s).

• The Configuration Register 1 contains 00h.

• The Autoboot register contains 00h.

• The Password Register contains FFFFFFFF–FFFFFFFFh

• All PPB bits are 1.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Ordering information

14

Ordering information

The ordering part number is formed by a valid combination of the following:

S25FL 127

S

AB

M

F

I

10

1

Packing type

0 = Tray

1 = Tube

3 = 13” Tape and reel

Model number (package details and RESET#)

00 = SOIC16 footprint with RESET#

10 = SOIC8/WSON footprint

C0 = 5 x 5 ball BGA footprint with RESET#

D0 = 4 x 6 ball BGA footprint with RESET#

=

Temperature range

I = Industrial (–40°C to +85°C)

V = Industrial Plus (–40°C to +105°C)

A = Automotive, AEC-Q100 grade 3 (–40°C to +85°C)

B = Automotive, AEC-Q100 grade 2 (–40°C to +105°C)

Package materials

F = Halogen free, Lead (Pb)-free

[51]

H = Low-Halogen, Lead (Pb)-free

Package type

M = 16-pin SO / 8-pin SO package

N = 8-contact WSON 6 x 5 mm package

B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch

Speed

AB = 108 MHz

Device technology

S = 0.065 µm MIRRORBIT™ Process Technology

Density

127 = 128 Mb

Device family

S25FL

3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory

Note

51.Halogen free definition is in accordance with IEC 61249-2-21 specification.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Ordering information

14.1

Valid combinations

Valid combinations list configurations planned to be supported in volume for this device. Contact your local sales

office to confirm availability of specific valid combinations and to check on newly released combinations.

Table 78

S25FL127S valid combinations

Valid combinations

Baseorderingpart Speed

Package and

Model

Packing

Package marking^[52]

number

option

temperature

number

type

FL127 + S + (Temp) + F + (Model

Number)

FL127 + S + (Temp) + F + (Model

Number)

FL127 + S + (Temp) + H + (Model

Number)

AB

MFI, MFV

00, 10

10

0, 1, 3

S25FL127S

AB

NFI, NFV

BHI, BHV

C0, D0

0, 3

14.2

Valid combinations — automotive grade / AEC-Q100

Table 79 lists configurations that are automotive grade / AEC-Q100 qualified and are planned to be available in

volume. The table will be updated as new combinations are released. Contact your local sales representative to

confirm availability of specific combinations and to check on newly released combinations.

Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.

Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade

products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full

compliance with ISO/TS-16949 requirements.

AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require

ISO/TS-16949 compliance.

Table 79

S25FL127S valid combinations — automotive grade / AEC-Q100^[52]

Valid Combinations

Baseorderingpart Speed

Package and

Temperature

Model

Packing

Type

Package Marking^[52]

number

Option

Number

FL127 + S + (Temp) + F + (Model

Number)

FL127 + S + (Temp) + F + (Model

Number)

FL127 + S + (Temp) + H + (Model

Number)

AB

MFA, MFB

NFA, NFB

BHA, BHB

00, 10

10

0, 1, 3

0, 3

S25FL127S

AB

C0, D0

Note

52.Example, S25FL127SABMFI100 package marking would be FL127SIF10.

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Revision history

Document

Date

Description of changes

revision

**

2012-12-11

Initial release.

Global:

Data sheet designation updated from Advance Information to Preliminary

Performance Summary: Maximum Read Rates table: corrected Dual and

Quad Read ‘Clock Rate’ and ‘Mbytes/s’

Migration Notes: FL Generations Comparison table: corrected Dual Read

Speed and Quad Read Speed for FL127S

DC Characteristics: DC Characteristics table: corrected ICC1 Test Conditions

for Quad

Capacitance Characteristics: Capacitance table: updated note

AC Characteristics: AC Characteristics table: corrected Max value for FSCK,C

dual and quad command

Physical Interface:

8-pin Plastic Small Outline Package (SO) figure: corrected marking

8-Contact USON 6x5 mm, Top View figure: corrected marking

24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View figure: removed VIO

24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View: removed VIO

*A

2013-04-25

Command Set Summary: S25FL127S Command Set (sorted by function)

table: corrected Maximum Frequency for ABRD, DOR, 4DOR, QOR, 4QOR,

DIOR, 4DIOR, QIOR, 4QIOR

Embedded Algorithm Performance Tables:

Added paragraph

Program and Erase Performance table:

- added ‘Erase per Sector’ Parameter

- added note

Software Interface Reference: FL127S Command Set (sorted by instruction)

table: corrected Maximum Frequency for DOR, 4DOR, QOR, 4QOR, DIOR,

4DIOR, QIOR, 4QIOR

Serial Flash Discoverable Parameters (SFDP) Address Map: CFI Alternate

Vendor-Specific Extended Query Parameter 90h – Latency Code table:

corrected Description for 68h

Ordering Information: Valid Combinations table: corrected Package

Marking and Note

Features: Added 16-pin SOIC package

Glossary: Updated description of Page

Signal Descriptions: Changed description of RESET#

Hardware Reset (RESET#): Changed RESET# description from “may be left

unconnected in the host system if not used” to “should be left unconnected

in the host system if not used”

Separate RESET# Input Initiated Hardware (Warm) Reset: Changed RESET#

description from “may be left unconnected” to “should be left unconnected

if not used”

SOIC 16-Lead Package: Added section

Ordering Information: Added 16-pin SOIC package

*B

*C

2013-07-26

2013-09-11

Global: Replaced USON with WSON

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Revision history

Document

Date

Description of changes

revision

Global: Data sheet designation updated from Preliminary to Full Production

Physical Interface: Updated 8-pin Plastic Small Outline Package (SO) figure

Command Set Summary: S25FL127S Command Set (sorted by function)

table: added RSFDP command

*D

*E

2013-11-15

Command Summary: FL127S Command Set (sorted by instruction) table:

added RSFDP command

JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space:

Changed JESD216 to JESD216B

Serial Flash Discoverable Parameters (SFDP) Address Map:

Updated section

Updated SFDP Overview Map table

2015-05-28

SFDP Header Field Definitions:

Updated SFDP Header table

Updated CFI Alternate Vendor-Specific Extended Query Parameter A5h,

JEDEC SFDP table

Replaced “Automotive Temperature Range” with “Industrial Plus

Temperature Range” in all instances across the document.

Updated to Cypress template.

*F

2015-08-24

2016-07-13

Updated Serial flash discoverable parameters (SFDP) address map:

Updated Device ID and Common Flash Interface (ID-CFI) address map:

Updated Field definitions:

Updated Table 67 (Updated entire table).

Updated to new template.

*G

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Revision history

Document

Date

Description of changes

revision

Updated Features:

Added ECC information.

Added Automotive temperature range support.

Updated Overview:

Updated Glossary:

Added ECC definition.

Updated Electrical specifications:

Updated Operating ranges:

Updated Temperature ranges:

Added Automotive temperature range support.

Updated Address space maps:

Updated Registers:

Updated Table 21:

Added ECC Status Register information.

Added ECC Status Register (ECCSR).

Updated Data protection:

Updated Secure silicon region (OTP):

Updated Programming OTP memory space:

Added ECC information.

Updated Commands:

Updated Command set summary:

Updated Command summary sorted by function:

Updated Table 40:

Added ECC Read command information.

Updated Register Access commands:

Added ECC Status Register Read (ECCRD 18h)

Updated Program Flash Array commands:

Added Automatic ECC.

*H

2017-03-24

Updated Software interface reference:

Updated Command summary:

Updated Table 50.

Updated Physical interface:

Updated SOIC 8-lead package:

Updated SOIC 8 physical diagram:

Updated Figure 35.

Updated SOIC 16-lead package:

Updated SOIC 16 physical diagram:

Updated Figure 37.

Updated FAB024 24-ball BGA package:

Updated Physical diagram:

Updated Figure 41.

Updated FAC024 24-ball BGA package:

Updated Physical diagram:

Updated Figure 43.

Updated to new template.

Completing Sunset Review.

Updated Ordering information:

No change in part numbers.

Updated Valid combinations:

Updated Table 78:

*I

2017-06-08

Fixed typo (Replaced “S25FL128S, S25FL256S” with “S25FL127S” in title).

Updated Valid combinations — automotive grade / AEC-Q100:

Updated Table 79:

Fixed typo (Replaced “S25FL128S, S25FL256S” with “S25FL127S” in title).

Datasheet

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128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Revision history

Document

Date

Description of changes

revision

Updated Timing specifications:

Added Thermal resistance.

Updated Address space maps:

Updated Registers:

Updated Configuration Register 1 (CR1):

Updated Table 23.

*J

2019-04-30

Updated Ordering information:

Removed Note “Halogen free definition is in accordance with IEC 61249-2-21

specification.” and its reference.

Updated to new template.

Completing Sunset Review.

Updated Document Title to read as “S25FL127S, 128 Mb (16 MB) FL-S Flash

SPI Multi-I/O, 3.0 V”.

Replaced “Cypress” with “Infineon” in required instances across the

document.

Updated Overview:

Removed “Glossary”.

Removed “Other Resources”.

Updated SPI with multiple input / output (SPI-MIO):

Replaced “Hardware interface” with “SPI with multiple input / output

(SPI-MIO)” in heading.

Updated Signal descriptions:

Updated Chip Select (CS#):

Updated description.

Updated Signal protocols:

Updated Data protection:

Updated description.

*K

2022-07-25

Updated Electrical specifications:

Updated Thermal resistance:

Updated Table 7.

Updated DC characteristics:

Updated Table 10.

Removed “Software interface”.

Updated Address space maps:

Updated Registers:

Updated Configuration Register 1 (CR1):

Updated Table 23.

Updated Commands:

Updated Command set summary:

Updated Command summary sorted by function:

Updated Table 40.

Migrated to Infineon template.

Datasheet

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Please read the Important Notice and Warnings at the end of this document

Trademarks

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IMPORTANT NOTICE

For further information on the product, technology,

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-07-25

Published by

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Go to www.infineon.com/support

authorized

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

001-98282 Rev. *K

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	S25FL127SABBHBC03
厂家：	Infineon
描述：	Quad SPI Flash
文件：	总174页 (文件大小：2659K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S25FL127SABBHBC03 [INFINEON]

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