S25FL512SAGBHEC13_技术文档

S25FL512S

Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Features

• CMOS 3.0 Volt Core with Versatile I/O

• SPI with Multi-I/O

• Density

- 512 Mbits (64 Mbytes)

• SPI

- SPI Clock polarity and phase modes 0 and 3

- Double Data Rate (DDR) option

- Extended Addressing: 32-bit address

- Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families

- Multi I/O Command set and footprint compatible with S25FL-P SPI family

• READ Commands

- Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR

- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected

address

- Common Flash Interface (CFI) data for configuration information.

• Programming (1.5 Mbytes/s)

- 512-byte Page Programming buffer

- Quad-Input Page Programming (QPP) for slow clock systems

- Automatic ECC -internal hardware Error Correction Code generation with single bit error correction

• Erase (0.5 to 0.65 Mbytes/s)

- Uniform 256-kbyte sectors

• Cycling Endurance

- 100 Program-Erase Cycles

• Data Retention

- >20 Year Data Retention

• Security features

- OTP array of 1024 bytes

- Block Protection:

• Status Register bits to control protection against program or erase of a contiguous range of sectors.

• Hardware and software control options

- Advanced Sector Protection (ASP)

• Individual sector protection controlled by boot code or password

• Infineon^®65 nm MirrorBit^™Technology with Eclipse^™Architecture

• Core supply voltage: 2.7V to 3.6V

• I/O supply voltage: 1.65V to 3.6V

- FBGA packages

• Temperature range:

- Military (–55°C to +125°C)

• Packages (Pb-free or Pb)

- BGA-24 6 x 8 mm

• 5 x 5 ball (FAB024) footprint option

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 153

002-19087 Rev. *B

2022-04-11

Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Logic block diagram

CS#

SRAM

SCK

MirrorBit Array

SI/IO0

SO/IO1

Y Decoders

Data Latch

I/O

WP#/IO2

Control

Logic

HOLD#/IO3

Data Path

RESET#

Performance summary

Maximum read rates with the same core and I/O voltage (V_IO= V_CC= 2.7V to 3.6V)

Clock rate

Command

Mbytes/s

(MHz)

50

Read

6.25

16.6

26

Fast Read

Dual Read

Quad Read

133

104

52

Maximum read rates with lower I/O voltage (V_IO= 1.65V to 2.7V, V_CC= 2.7V to 3.6V)

Clock rate

Command

Mbytes/s

(MHz)

50

Read

6.25

8.25

16.5

33

Fast Read

Dual Read

Quad Read

66

Maximum read rates DDR (V_IO= V_CC= 3V to 3.6V)

Command

Clock rate

(MHz)

Mbytes/s

Fast Read DDR

Dual Read DDR

Quad Read DDR

80

20

40

80

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

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Performance summary

Typical program and erase rates

Operation

kbytes/s

1500

Page Programming (512-byte page buffer - Uniform Sector Option)

256-kbyte Logical Sector Erase (Uniform Sector Option)

500

Current consumption

Operation

Serial Read 50 MHz

Serial Read 133 MHz

Quad Read 104 MHz

Program

Current (mA)

22 (max)

35 (max)

61 (max)

100 (max)

0.115 (typ)

Erase

Standby

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

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Table of contents

Features ...........................................................................................................................................1

Logic block diagram ..........................................................................................................................2

Performance summary ......................................................................................................................2

Table of contents...............................................................................................................................4

1 Overview .......................................................................................................................................6

1.1 General description ................................................................................................................................................6

1.2 Migration notes .......................................................................................................................................................7

1.3 Glossary ...................................................................................................................................................................9

Hardware interface..........................................................................................................................10

2 Signal descriptions .......................................................................................................................11

2.1 Input/Output summary ........................................................................................................................................11

2.2 Address and data configuration...........................................................................................................................11

2.3 RESET#...................................................................................................................................................................12

2.4 Serial clock (SCK) ..................................................................................................................................................12

2.5 Chip select (CS#) ...................................................................................................................................................12

2.6 Serial input (SI) / IO0.............................................................................................................................................12

2.7 Serial output (SO) / IO1.........................................................................................................................................13

2.8 Write protect (WP#) / IO2......................................................................................................................................13

2.9 Hold (HOLD#) / IO3................................................................................................................................................13

2.10 Core voltage supply (V_CC) ...................................................................................................................................14

2.11 Versatile I/O power supply (V_IO) .........................................................................................................................14

2.12 Supply and signal ground (V_SS)..........................................................................................................................14

2.13 Not connected (NC) ............................................................................................................................................14

2.14 Reserved for future use (RFU).............................................................................................................................14

2.15 Do not use (DNU).................................................................................................................................................14

2.16 Block diagrams ...................................................................................................................................................15

3 Signal protocols............................................................................................................................16

3.1 SPI clock modes ....................................................................................................................................................16

3.2 Command protocol...............................................................................................................................................17

3.3 Interface states .....................................................................................................................................................22

3.4 Configuration register effects on the interface ...................................................................................................27

3.5 Data protection.....................................................................................................................................................27

4 Electrical specifications.................................................................................................................29

4.1 Absolute maximum ratings ..................................................................................................................................29

4.2 Thermal resistance ...............................................................................................................................................29

4.3 Operating ranges ..................................................................................................................................................29

4.4 Power-up and power-down..................................................................................................................................31

4.5 DC characteristics .................................................................................................................................................33

5 Timing specifications ....................................................................................................................34

5.1 Key to switching waveforms.................................................................................................................................34

5.2 AC test conditions .................................................................................................................................................34

5.3 Reset ......................................................................................................................................................................35

5.4 SDR AC characteristics..........................................................................................................................................38

5.5 DDR AC characteristics .........................................................................................................................................42

6 Physical interface .........................................................................................................................45

6.1 FAB024 24-ball BGA package................................................................................................................................45

Software interface...........................................................................................................................47

7 Address space maps ......................................................................................................................48

7.1 Overview................................................................................................................................................................48

7.2 Flash memory array ..............................................................................................................................................48

7.3 ID-CFI address space.............................................................................................................................................48

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Table of contents

7.4 JEDEC JESD216 Serial flash discoverable parameters (SFDP) space.................................................................49

7.5 OTP address space................................................................................................................................................49

7.6 Registers................................................................................................................................................................50

8 Data protection ............................................................................................................................62

8.1 Secure silicon region (OTP) ..................................................................................................................................62

8.2 Write enable command ........................................................................................................................................62

8.3 Block protection ...................................................................................................................................................63

8.4 Advanced sector protection .................................................................................................................................64

9 Commands ...................................................................................................................................68

9.1 Command set summary .......................................................................................................................................69

9.2 Identification commands .....................................................................................................................................75

9.3 Register access commands ..................................................................................................................................77

9.4 Read memory array commands...........................................................................................................................86

9.5 Program flash array command.s........................................................................................................................101

9.6 Erase flash array commands ..............................................................................................................................105

9.7 One time program array commands..................................................................................................................109

9.8 Advanced sector protection commands ...........................................................................................................110

9.9 Reset commands ................................................................................................................................................115

9.10 Embedded algorithm performance tables ......................................................................................................116

10 Data integrity ........................................................................................................................... 117

10.1 Erase endurance ...............................................................................................................................................117

10.2 Data retention ...................................................................................................................................................117

11 Software interface reference ..................................................................................................... 118

11.1 Command summary .........................................................................................................................................118

11.2 Serial flash discoverable parameters (SFDP) address map............................................................................120

11.3 Device ID and common flash interface (ID-CFI) address map ........................................................................124

11.4 Registers............................................................................................................................................................145

11.5 Initial delivery state ..........................................................................................................................................149

12 Ordering information ................................................................................................................ 150

12.1 Ordering information........................................................................................................................................150

12.2 Valid combinations — Military..........................................................................................................................151

Revision history ............................................................................................................................ 152

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1

Overview

1.1

General description

The Infineon S25FL512S device is a flash non-volatile memory product using:

• MirrorBit^™technology - that stores two data bits in each memory array transistor

• Eclipse architecture - that dramatically improves program and erase performance

• 65 nm process lithography

This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input

and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or

QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family

adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read

data on both edges of the clock.

The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be

programmed in one operation, resulting in faster effective programming and erase than prior generation SPI

program or erase algorithms.

Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the

higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or

exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramati-

cally.

The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a

variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1.2

Migration notes

1.2.1

Features comparison

The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families.

Table 1

FL generations comparison

Parameter

Technology Node

Architecture

Release Date

Density

FL-K

90 nm

Floating Gate

In Production

4 Mb - 128 Mb

x1, x2, x4

FL-P

90 nm

MirrorBit

FL-S

65 nm

MirrorBit Eclipse

In Production

512 Mb

In Production

32 Mb - 256 Mb

x1, x2, x4

Bus Width

x1, x2, x4

Supply Voltage

2.7V - 3.6V

6 MB/s (50 MHz)

13 MB/s (104 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

—

2.7V - 3.6V

5 MB/s (40 MHz)

13 MB/s (104 MHz)

20 MB/s (80 MHz)

40 MB/s (80 MHz)

—

2.7V - 3.6V / 1.65V - 3.6V V_IO

6 MB/s (50 MHz)

17 MB/s (133 MHz)

26 MB/s (104 MHz)

52 MB/s (104 MHz)

20 MB/s (80 MHz)

40 MB/s (80 MHz)

80 MB/s (80 MHz)

512B

Normal Read Speed (SDR)

Fast Read Speed (SDR)

Dual Read Speed (SDR)

Quad Read Speed (SDR)

Fast Read Speed (DDR)

Dual Read Speed (DDR)

Quad Read Speed (DDR)

Program Buffer Size

Erase Sector Size

—

256B

4 kB / 32 kB / 64 kB

4 kB

256B

64 kB / 256 kB

4 kB

256 kB

Parameter Sector Size

—

Sector Erase Time (typ.) 30 ms (4 kB), 150 ms (64 kB)

500 ms (64 kB)

1500 µs (256B)

685 ms (256 kB)

540 µs (512B)

Page Programming Time

(typ.)

700 µs (256B)

OTP

Advanced Sector

Protection

768B (3 x 256B)

No

506B

No

1024B

Yes

Auto Boot Mode

Erase Suspend/Resume

Program

Suspend/Resume

No

Yes

No

Yes

Operating Temperature

–40°C to +85°C

–40°C to +85°C / +105°C

–55°C to +125°C

Notes

1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.

2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).

3. 64 kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.

4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.

5. Refer to individual data sheets for further details.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1.2.2

Known differences from prior generations

Error reporting

1.2.2.1

Prior generation FL memories either do not have error status bits or do not set them if program or erase is

attempted on a protected sector. The FL-S family does have error reporting status bits for program and erase

operations. These can be set when there is an internal failure to program or erase or when there is an attempt to

program or erase a protected sector. In either case the program or erase operation did not complete as requested

by the command.

1.2.2.2

Secure silicon region (OTP)

The size and format (address map) of the One Time Program area is different from prior generations. The method

for protecting each portion of the OTP area is different. For additional details see “Secure silicon region (OTP)”

on page 62.

1.2.2.3

Configuration register freeze bit

The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations.

In the FL-S family it also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and

the Secure Silicon Region (OTP) area.

1.2.2.4

Sector erase commands

The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.

The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.

The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.

1.2.2.5

Deep power down

The Deep Power Down (DPD) function is not supported in FL-S family devices.

The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the

former DPD command, to access a new bank address register. The bank address register allows SPI memory

controllers that do not support more than 24 bits of address, the ability to provide higher order address bits for

commands, as needed to access the larger address space of the 256-Mbit density FL-S device. For additional

information see “Extended address” on page 48.

1.2.2.6

New features

The FL-S family introduces several new features to SPI category memories:

• Extended address for access to higher memory density.

• AutoBoot for simpler access to boot code following power up.

• Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions

when repeating the same type of read command.

• Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock

rate read commands.

• DDR read commands for SIO, DIO, and QIO.

• Automatic ECC for enhanced data integrity.

• Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the

Advanced Sector Protection feature found in several other Infineon parallel interface NOR memory families.

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Overview

1.3

Glossary

Table 2

Glossary

Item

Description

Command

All information transferred between the host system and memory during one period

while CS# is low. This includes the instruction (sometimes called an operation code

or opcode) and any required address, mode bits, latency cycles, or data.

DDP

Two die stacked within the same package to increase the memory capacity of a single

package. Often also referred to as a Multi-Chip Package (MCP).

(Dual Die Package)

DDR

When input and output are latched on every edge of SCK.

(Double Data Rate)

ECC

ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP

array, each of which has its own hidden ECC syndrome to enable error correction on

each group.

Flash

The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM)

that erases large blocks of memory bits in parallel, making the erase operation much

faster than early EEPROM.

High

A signal voltage level ≥ V_IHor a logic level representing a binary one (1).

Instruction

The 8 bit code indicating the function to be performed by a command (sometimes

called an operation code or opcode). The instruction is always the first 8 bits trans-

ferred from host system to the memory in any command.

Low

A signal voltage level ≤ V_ILor a logic level representing a binary zero (0).

LSB

Generally the right most bit, with the lowest order of magnitude value, within a group

of bits of a register or data value.

(Least Significant Bit)

MSB

Generally the left most bit, with the highest order of magnitude value, within a group

of bits of a register or data value.

(Most Significant Bit)

Non-Volatile

OPN

No power is needed to maintain data stored in the memory.

The alphanumeric string specifying the memory device type, density, package, factory

(Ordering Part Number) non-volatile configuration, etc. used to select the desired device.

Page

PCB

512 bytes aligned and length group of data.

Printed Circuit Board.

Register Bit References

Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB:

bit_range_LSB].

SDR

When input is latched on the rising edge and output on the falling edge of SCK.

(Single Data Rate)

Sector

Write

Erase unit size 256 kbytes.

An operation that changes data within volatile or non-volatile registers bits or

non-volatile flash memory. When changing non-volatile data, an erase and repro-

gramming of any unchanged non-volatile data is done, as part of the operation, such

that the non-volatile data is modified by the write operation, in the same way that

volatile data is modified – as a single operation. The non-volatile data appears to the

host system to be updated by the single write command, without the need for

separate commands for erase and reprogram of adjacent, but unaffected data.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Hardware interface

Serial peripheral interface with multiple input / output (SPI-MIO)

Many memory devices connect to their host system with separate parallel control, address, and data signals that

require a large number of signal connections and larger package size. The large number of connections increase

power consumption due to so many signals switching and the larger package increases cost.

The S25FL512S device reduces the number of signals for connection to the host system by serially transferring

all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package,

reduces signal switching power, and either reduces the host connection count or frees host connectors for use

in providing other features.

The S25FL512S device uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports

optional extension commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width

interface is called SPI Multi-I/O or SPI-MIO.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

2

Signal descriptions

2.1

Input/Output summary

Table 3

Signal list

Signal

Type

Description

name

RESET#

Input

Hardware reset: Low = device resets and returns to standby state, ready to receive

a command. The signal has an internal pull-up resistor and may be left uncon-

nected in the host system if not used.

SCK

CS#

SI / IO0

SO / IO1

WP# / IO2

Input

I/O

Serial clock.

Chip select.

Serial input for single bit data commands or IO0 for Dual or Quad commands.

Serial output for single bit data commands. IO1 for Dual or Quad commands.

Write protect when not in Quad mode. IO2 in Quad mode. The signal has an

internal pull-up resistor and may be left unconnected in the host system if not used

for Quad commands.

HOLD# / IO3

I/O

Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O

mode. The signal has an internal pull-up resistor and may be left unconnected in

the host system if not used for Quad commands.

V_CC

V_IO

V_SS

NC

Supply

Unused

Core power supply.

Versatile I/O power supply.

Ground.

Not connected. No device internal signal is connected to the package connector

nor is there any future plan to use the connector for a signal. The connection may

safely be used for routing space for a signal on a Printed Circuit Board (PCB).

However, any signal connected to an NC must not have voltage levels higher than

V_IO.

RFU

Reserved Reserved for future use. No device internal signal is currently connected to the

package connector but there is potential future use of the connector for a signal.

It is recommended to not use RFU connectors for PCB routing channels so that the

PCB may take advantage of future enhanced features in compatible footprint

devices.

DNU

Reserved Do not use. A device internal signal may be connected to the package connector.

The connection may be used by Infineon for test or other purposes and is not

intended for connection to any host system signal. Any DNU signal related function

will be inactive when the signal is at V_IL. The signal has an internal pull-down

resistor and may be left unconnected in the host system or may be tied to V_SS. Do

not use these connections for PCB signal routing channels. Do not connect any

host system signal to this connection.

2.2

Address and data configuration

Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on

the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.

Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will

be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and

IO3.

Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0

and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on

IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

2.3

RESET#

The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a

command. When RESET# is driven to logic low (V_IL) for at least a period of t_RP, the device:

• terminates any operation in progress,

• tristates all outputs,

• resets the volatile bits in the Configuration Register,

• resets the volatile bits in the Status Registers,

• resets the Bank Address Register to zero,

• loads the Program Buffer with all ones,

• reloads all internal configuration information necessary to bring the device to standby mode,

• and resets the internal Control Unit to standby state.

RESET# causes the same initialization process as is performed when power comes up and requires t_PUtime.

RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a

hardware reset should be reinitiated once the device is ready to accept a command sequence.

When RESET# is first asserted Low, the device draws I_CC1(50 MHz value) during t_PU. If RESET# continues to be held

at V_SSthe device draws CMOS standby current (I_SB).

RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.

The RESET# input is not available on all packages options. When not available the RESET# input of the device is

tied to the inactive state, inside the package.

2.4

Serial clock (SCK)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data

input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR

commands, and after every edge in DDR commands.

2.5

Chip select (CS#)

The chip select signal indicates when a command for the device is in process and the other signals are relevant

for the memory device. When the CS# signal is at the logic high state, the device is not selected and all input

signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write

Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the

CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge

on CS# is required prior to the start of any command.

CS# toggle with no CLK and Data is considered as non-valid. The Flash should not be selected (CS# low with no

CLK and Data) when it’s not being addressed. This is considered as a spec violation and can eventually cause the

device to remain in busy state (SR1=0x03) after an embedded operation (program/erase/etc.)

2.6

Serial input (SI) / IO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to

be programmed. Values are latched on the rising edge of serial SCK clock signal.

SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and

data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on

the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal descriptions

2.7

Serial output (SO) / IO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the

serial SCK clock signal.

SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be

programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling

edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

2.8

Write protect (WP#) / IO2

When WP# is driven Low (V_IL), during a WRR command and while the Status Register Write Disable (SRWD) bit of

the Status Register is set to a 1, it is not possible to write to the Status and Configuration Registers. This prevents

any alteration of the Block Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a consequence, all

the data bytes in the memory area that are protected by the Block Protect and TBPROT bits, are also hardware

protected against data modification if WP# is Low during a WRR command.

The WP# function is not available when the Quad mode is enabled (CR[1]=1). The WP# function is replaced by IO2

for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched

on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and

on every edge of SCK, in DDR commands).

WP# has an internal pull-up resistor; when unconnected, WP# is at V_IHand may be left unconnected in the host

system if not used for Quad mode.

2.9

Hold (HOLD#) / IO3

The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the

device or stopping the serial clock.

To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is

recommended that the user keep the CS# input low state during the entire duration of the Hold condition. This

is to ensure that the state of the interface logic remains unchanged from the moment of entering the Hold

condition. If the CS# input is driven to the logic high state while the device is in the Hold condition, the interface

logic of the device will be reset. To restart communication with the device, it is necessary to drive HOLD# to the

logic high state while driving the CS# signal into the logic low state. This prevents the device from going back into

the Hold condition.

The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with SCK

being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state,

the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD# signal to the

logic low state does not terminate any Write, Program or Erase operation that is currently in progress.

During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.

The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK

signal being at the logic low state. If the rising edge does not coincide with the SCK signal being at the logic low

state, the Hold condition ends whenever the SCK signal reaches the logic low state.

The HOLD# function is not available when the Quad mode is enabled (CR1[1] =1). The Hold function is replaced

by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed (values are

latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,

and on every edge of SCK, in DDR commands).

The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for

Quad mode.

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Signal descriptions

CS#

SCK

HOLD#

Hold Condition

Standard Use

Hold Condition

Non-standard Use

Valid Input

Don't Care

B

Valid Input

Don't Care

D

Valid Input

D

SI_or_IO_(during_input)

SO_or_IO_(internal)

SO_or_IO_(external)

A

C

E

B

C

Figure 1

HOLD mode operation

2.10

Core voltage supply (V_CC)

V_CCis the voltage source for all device internal logic. It is the single voltage used for all device internal functions

including read, program, and erase. The voltage may vary from 2.7V to 3.6V.

2.11

Versatile I/O power supply (V_IO)

The Versatile I/O (V_IO) supply is the voltage source for all device input receivers and output drivers and allows the

host system to set the voltage levels that the device tolerates on all inputs and drives on outputs (address,

control, and IO signals). The V_IOrange is 1.65V to V_CC. V_IOcannot be greater than V_CC

.

For example, a V_IOof 1.65V - 3.6V allows for I/O at the 1.8V, 2.5V or 3V levels, driving and receiving signals to and

from other 1.8V, 2.5V or 3V devices on the same data bus. V_IOmay be tied to V_CCso that interface signals operate

at the same voltage as the core of the device. V_IOis not available in all package options, when not available the

V_IOsupply is tied to V_CCinternal to the package.

During the rise of power supplies the V_IOsupply voltage must remain less than or equal to the V_CCsupply voltage.

This supply is not available in all package options. For a backward compatible SO16 footprint, the V_IOsupply is

tied to V_CCinside the package; thus, the IO will function at V_CClevel.

2.12

Supply and signal ground (V_SS)

V_SSis the common voltage drain and ground reference for the device core, input signal receivers, and output

drivers.

2.13

Not connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector

for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).

However, any signal connected to an NC must not have voltage levels higher than V_IO.

2.14

Reserved for future use (RFU)

No device internal signal is currently connected to the package connector but is there potential future use of the

connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take

advantage of future enhanced features in compatible footprint devices.

2.15

Do not use (DNU)

A device internal signal may be connected to the package connector. The connection may be used by Infineon

for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related

function will be inactive when the signal is at V_IL. The signal has an internal pull-down resistor and may be left

unconnected in the host system or may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to these connections.

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Signal descriptions

2.16

Block diagrams

HOLD#

WP#

HOLD#

WP#

SI

SO

SI

SO

SCK

CS2#

CS1#

FL-S

Flash

FL-S

Flash

SPI

Bus Master

Figure 2

Bus master and memory devices on the SPI bus — Single bit data path

HOLD#

WP#

IO1

IO0

SCK

WP#

IO1

IO0

SCK

CS2#

CS1#

FL-S

Flash

FL-S

Flash

SPI

Bus Master

Figure 3

Bus master and memory devices on the SPI bus — Dual bit data path

IO3

IO2

IO3

IO2

IO1

IO0

SCK

CS2#

CS1#

FL-S

Flash

FL-S

Flash

SPI

Bus Master

Figure 4

Bus master and memory devices on the SPI bus — Quad bit data path

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3

Signal protocols

SPI clock modes

3.1

3.1.1

Single data rate (SDR)

The S25FL512S device can be driven by an embedded microcontroller (bus master) in either of the two following

clocking modes.

• Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

• Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the

output data is always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not

transferring any data.

• SCK will stay at logic low state with CPOL = 0, CPHA = 0

• SCK will stay at logic high state with CPOL = 1, CPHA = 1

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

SI

MSB

SO

MSB

Figure 5

SPI SDR modes supported

Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by

showing SCK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with

SCK low at the fall of CS#. In such a case, mode 3 timing simply means clock is high at the fall of CS# so no SCK

rising edge set up or hold time to the falling edge of CS# is needed for mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0 the

beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of

SCK because SCK is already low at the beginning of a command.

3.1.2

Double data rate (DDR)

Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always

latched on the rising edge of clock, the same as in SDR commands. However, the address and input data that

follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is latched on

the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first bit of output

data is driven on the falling edge at the end of the last access latency (dummy) cycle.

SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the

next falling edge of SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling

edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a command.

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CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

Read

Data

Transfer_Phase

Instruction

Inst.7

Address

A 3 1 A 3 0

Mode

Dummy / DLP

M 0

M 6

M 7

A0

SI

Inst.0

SO

D0 D1

DLP7

DLP0

Figure 6

SPI DDR modes supported

3.2

Command protocol

All communication between the host system and S25FL512S memory device is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to

the host serially on the SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be

returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or,

four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1

or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Commands are structured as follows:

• Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by

the host driving the Chip Select (CS#) signal low throughout a command.

• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.

• Each command begins with an 8-bit (byte) instruction. The instruction is always presented only as a single bit

serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising

edge. The instruction selects the type of information transfer or device operation to be performed.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The instruction determines the address space used. The address may be either a

24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands,

or on every SCK edge, in DDR commands.

• The width of all transfers following the instruction are determined by the instruction sent. Following transfers

may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in 2-bit groups

per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the

IO0-IO3 signals. Within the dual or quad groups the least significant bit is on IO0. More significant bits are placed

in significance order on each higher numbered IO signal. Single bits or parallel bit groups are transferred in most

to least significant bit order.

• Some instructions send an instruction modifier called mode bits, following the address, to indicate that the

next command will be of the same type with an implied, rather than an explicit, instruction. The next command

thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to

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send each command when the same command type is repeated in a sequence of commands. The mode bit

transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles

(also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from

the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered

transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising

edge, in SDR commands, or on every SCK edge, in DDR commands.

• If the command returns read data to the host, the device continues sending data transfers until the host takes

the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence. This will

terminate the command.

• At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go

high after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is,

the CS# signal must be driven high when the number of clock cycles after CS# signal was driven low is an exact

multiple of eight cycles. If the CS# signal does not go high exactly at the eight SCK cycle boundary of the

instruction or write data, the command is rejected and not executed.

• All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The

data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address

byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address

increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

3.2.1

Command sequence examples

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 7

Stand alone instruction command

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Data

Figure 8

Single bit wide input command

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CS#

SCK

SI

SO

7 6 5 4 3 2 1 0

Instruction

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data1 Data2

Phase

Figure 9

Single bit wide output command

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 31

Instruction

1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Address

Data 1

Data 2

Figure 10

Single bit wide I/O command without latency

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 31

1 0

Address

7 6 5 4 3 2 1 0

Data 1

Instruction

Dummy Cycles

Figure 11

Single bit wide I/O command with latency

CS#

SCK

IO0

IO1

30 28 26

31 29 27

7 6 5 4 3 2 1 0

Instruction

0

1

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

Address

6 Dummy

Data 1

Data 2

Figure 12

Dual output command

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CS#

SCK

IO0

IO1

7 6 5 4 3 2 1 0 31

1 0 4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

IO2

IO3

Instruction

Address

Data 1 Data 2 Data 3 Data 4 Data 5

...

Phase

Figure 13

Quad output command without latency

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0 30

31

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Instruction

Address

Dummy

Data 1

Data 2

Phase

Figure 14

Dual I/O command

CS#

SCK

IO0

7

6 5

4

3

2

1 0 28

4

5

6

7

0 4

1 5

2 6

3 7

4

5

6

7

0

1

2

3

4 0

5 1

6 2

4

0

1

2

3

4 0

5 1

6 2

IO1

IO2

29

30

31

5

6

7

IO3

7 3

D2

7 3

D4

Instruction

Address Mode

Dummy

D1

D3

Phase

Figure 15

Quad I/O command

CS#

SCK

SI

7

6

5

4

3

2

1

0 3130 0 7 6 5 4 3 2 1 0

SO

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data 1 Data 2

Instruction

Address

Mode

Dummy

Phase

Figure 16

DDR fast read with EHPLC = 00b

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CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

30 28

31 29

0

1

6

7

4

5

2

3

0

1

7 6 5 4

3

2

1 0

6

7

4

5

2

3

0

1

6

7

Instruction

Address

Mode

Dum

DLP

Data 1

Phase

Figure 17

DDR dual I/O read with EHPLC = 01b and DLP

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

2824201612 8 4 0 4 0

7 6 5 4 3 2 1 0 4 0 4 0

7 6 5 4 3 2 1 0 5 1 5 1

7 6 5 4 3 2 1 0 6 2 6 2

7 6 5 4 3 2 1 0 7 3 7 3

2925211713 9 5 1 5 1

302622181410 6 2 6 2

312723191511 7 3 7 3

IO2

IO3

Phase

Instruction

Address

Mode Dummy

DLP

D1 D2

Figure 18

DDR quad I/O read

Additional sequence diagrams, specific to each command, are provided in “Commands” on page 68.

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3.3

Interface states

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 4

Interface states summary (Sheet 1 of 2)

HOLD# WP# SO / SI /

/ IO3 / IO2 IO1 IO0

Interface state

V_CC

V_IO

RESET# SCK

CS#

Power-Off

< V_CC(low)

< V_CC(cut-off)

≤ V_CC

X

Z

X

Low Power

Hardware Data

Protection

Power-On (Cold) Reset

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

X

Z

X

Z

X

Hardware (Warm)

Reset

HL

HH

X

Interface Standby

Instruction Cycle

Hold Cycle

X

HH

HL

X

HT

HH

HL

HH

HV

X

HV

X

HV or

HT

Single Input Cycle

Host to Memory

Transfer

X

HV

Single Latency

(Dummy) Cycle

Single Output Cycle

Memory to Host

Transfer

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

HH

HT

HL

HH

X

Z

X

MV

Dual Input Cycle

Host to Memory

Transfer

Dual Latency

(Dummy) Cycle

Dual Output Cycle

Memory to Host

Transfer

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HH

HT

HL

HH

X

HV

X

HV

X

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

HH

HT

HL

HH

X

MV MV

QPP Address Input

Cycle

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HH

HT

HL

X

HV

Host to Memory

Transfer

Quad Input Cycle

Host to Memory

Transfer

Quad Latency

(Dummy) Cycle

≥ V_IO(min)

≤ V_CC

HV

X

HV

X

HV

X

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HH

HT

HL

X

Quad Output Cycle

Memory to Host

Transfer

≥ V_IO(min)

≤ V_CC

MV

MV MV MV

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Table 4

Interface states summary (Sheet 2 of 2)

HOLD# WP# SO / SI /

/ IO3 / IO2 IO1 IO0

Interface state

V_CC

V_IO

RESET# SCK

CS#

DDR Single Input Cycle

Host to Memory

Transfer

DDR Dual Input Cycle

Host to Memory

Transfer

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HH

HT

HL

X

HV

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HL

X

HV

DDR Quad Input Cycle

Host to Memory

Transfer

≥ V_IO(min)

≤ V_CC

HV

DDR Latency (Dummy)

Cycle

DDR Single Output

Cycle

Memory to Host

Transfer

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

≥ V_IO(min)

≤ V_CC

HH

HT

HL MV or Z MV MV MVor

or Z or Z

Z

X

HL

Z

MV

DDR Dual Output Cycle

Memory to Host

Transfer

DDR Quad Output

Cycle

Memory to Host

Transfer

≥ V_CC(min)

≥ V_IO(min)

≤ V_CC

HH

HT

HL

Z

MV MV

≥ V_IO(min)

≤ V_CC

MV

MV MV MV

Legend:

Z = no driver - floating signal

HL = Host driving V_IL

HH = Host driving V_IH

HV = either HL or HH

X = HL or HH or Z

HT = toggling between HL and HH

ML = Memory driving V_IL

MH = Memory driving V_IH

MV = either ML or MH

3.3.1

Power-off

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

3.3.2

Low power hardware data protection

When V_CCis less than V_CC(cut-off) the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

3.3.3

Power-on (cold) reset

When the core voltage supply remains at or below the V_CC(low) voltage for ≥ t_PDtime, then rises

to ≥ V_{CC (Minimum)}the device will begin its Power-On Reset (POR) process. POR continues until the end of t_PU

.

During t_PUthe device does not react to external input signals nor drive any outputs. Following the end of t_PUthe

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device transitions to the Interface Standby state and can accept commands. For additional information on POR

see “Power-on (cold) reset” on page 35.

3.3.4

Hardware (warm) reset

Some of the device package options provide a RESET# input. When RESET# is driven low for t_RPtime the device

starts the hardware reset process. The process continues for t_RPHtime. Following the end of both t_RPHand the

reset hold time following the rise of RESET# (t_RH) the device transitions to the Interface Standby state and can

accept commands. For additional information on hardware reset see Figure 28.

3.3.5

Interface standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits

for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a

new command.

While in interface standby state the memory device draws standby current (I_SB) if no embedded algorithm is in

progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm

when the entire device returns to standby current draw.

3.3.6

Instruction cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device

captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the

device captures the next lower significance bit of the 8 bit instruction. The host keeps RESET# high, CS# low,

HOLD# high, and drives Write Protect (WP#) signal as needed for the instruction. However, WP# is only relevant

during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder

of the command. The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single

I/O, DDR Dual I/O, or DDR Quad I/O. The expected next interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns

CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface

state in this case is Interface Standby.

3.3.7

Hold

When Quad mode is not enabled (CR[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host keeps

RESET# high, HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a

command is paused, as though SCK were held low. SI / IO0 and SO / IO1 ignore the input level when acting as

inputs and are high impedance when acting as outputs during hold state. Whether these signals are input or

output depends on the command and the point in the command sequence when HOLD# is asserted low.

When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.

When Quad mode is enabled the HOLD# / IO3 signal is used as IO3.

During DDR commands the HOLD# and WP# inputs are ignored.

3.3.8

Single input cycle - Host to memory transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the

memory device. The dual output, and quad output commands send address to the memory using only SI but

return read data using the I/O signals. The host keeps RESET# high, CS# low, HOLD# high, and drives SI as needed

for the command. The memory does not drive the Serial Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or

data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly to

Single, Dual, or Quad Output.

3.3.9

Single latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

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Military 512 Mb (64 MB) FL-S Flash

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Signal protocols

the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and HOLD#

high. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or the host

may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals during the latency

cycles. In dual or quad read commands, the host must stop driving the I/O signals on the falling edge at the end

of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory

does not drive the Serial Output (SO) or I/O signals during the latency cycles.

The next interface state depends on the command structure i.e. the number of latency cycles, and whether the

read is single, dual, or quad width.

3.3.10

Single output cycle - Memory to host transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps

RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory ignores the Serial

Input (SI) signal. The memory drives SO with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the

command.

3.3.11

Dual input cycle - Host to memory transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps

RESET# high, CS# low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0

and SO / IO1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency

cycles needed or Dual Output Cycle if no latency is required.

3.3.12

Dual latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and HOLD#

high. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during these

cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data driven on SI / IO0

and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the falling edge at the

end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory

does not drive the SI / IO0 and SO / IO1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

3.3.13

Dual output cycle - Memory to host transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET#

high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0

and SO / IO1 signals during the dual output cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the

command.

3.3.14

QPP or QOR address input cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The other

IO signals are ignored because the device must be in Quad mode for these commands thus the Hold and Write

Protect features are not active. The host keeps RESET# high, CS# low, and drives IO0.

For QPP the next interface state following the delivery of address is the Quad Input Cycle.

For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or

Quad Output Cycle if no latency is required.

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal protocols

3.3.15

Quad input cycle - Host to memory transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page

Program command transfers four data bits to the memory in each cycle. The host keeps RESET# high, CS# low,

and drives the IO signals.

For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle

if there are latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host

returns CS# high following the delivery of data to be programmed and the interface returns to standby state.

3.3.16

Quad latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low. The host may

drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any data

driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the end of

the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is

sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles.

This prevents driver conflict between host and memory when the signal direction changes. The memory does not

drive the IO signals during the latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

3.3.17

Quad output cycle - Memory to host transfer

The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps RESET#

high, and CS# low. The memory drives data on IO0-IO3 signals during the Quad output cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the

command.

3.3.18

DDR single input cycle - Host to memory transfer

The DDR Fast Read command sends address, and mode bits to the memory only on the IO0 signal. One bit is

transferred on the rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high,

and CS# low. The other IO signals are ignored by the memory.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.19

DDR dual input cycle - Host to memory transfer

The DDR Dual I/O Read command sends address, and mode bits to the memory only on the IO0 and IO1 signals.

Two bits are transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps

RESET# high, and CS# low. The IO2 and IO3 signals are ignored by the memory.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.20

DDR quad input cycle - Host to memory transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits

are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET#

high, and CS# low.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.21

DDR latency cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high and CS# low. The host

may not drive the IO signals during these cycles. So that there is sufficient time for the host drivers to turn off

before the memory begins to drive. This prevents driver conflict between host and memory when the signal

direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern (DLP) during

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Signal protocols

the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so

that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins

driving the DLP. When there are more than 4 cycles of latency the memory does not drive the IO signals until the

last four cycles of latency.

The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle, depending

on the instruction.

3.3.22

DDR single output cycle - Memory to host transfer

The DDR Fast Read command returns bits to the host only on the SO / IO1 signal. One bit is transferred on the

rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The

other IO signals are not driven by the memory.

The next interface state continues to be DDR Single Output Cycle until the host returns CS# to high ending the

command.

3.3.23

DDR dual output cycle - Memory to host transfer

The DDR Dual I/O Read command returns bits to the host only on the IO0 and IO1 signals. Two bits are transferred

on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.

The IO2 and IO3 signals are not driven by the memory.

The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to high ending the

command.

3.3.24

DDR quad output cycle - Memory to host transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the

rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the

command.

3.4

Configuration register effects on the interface

The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code

selects the number of mode bit and latency cycles for each type of instruction.

The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and

allow Quad Page Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected

to allow Read DDR Quad I/O commands.

3.5

Data protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the

hardware design. These are described below. Other software managed protection methods are discussed in the

software section (page 47) of this document.

3.5.1

Power-up

When the core supply voltage is at or below the V_CC(low) voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

Program and erase operations continue to be prevented during the Power-on Reset (POR) because no command

is accepted until the exit from POR to the Interface Standby state.

3.5.2

Low power

When V_CCis less than V_CC(cut-off) the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

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3.5.3

Clock pulse count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count

that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse count is

ignored and no error status is set for the command.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

4

Electrical specifications

4.1

Absolute maximum ratings

Table 5

Absolute maximum ratings

Storage Temperature Plastic Packages

Ambient Temperature with Power Applied

V_CC

–65°C to +150°C

–65°C to +125°C

–0.5V to +4.0V

–0.5V to +(V_IO+ 0.5V)

100 mA

[6]

V_IO

[7]

Input Voltage with Respect to Ground (V_SS

Output Short Circuit Current ^[8]

)

4.2

Table 6

Thermal resistance

Description

Parameter

Test condition

FAB024

Unit

Theta JA

Theta JB

Theta JC

Thermal resistance

Test conditions follow

36

°C/W

(junction to ambient) standard test methods

and procedures for

Thermal resistance

17.6

11

°C/W

measuring thermal

(junction to board)

impedance in accor-

dance with EIA/JESD51.

with Still Air (0 m/s).

Thermal resistance

(junction to case)

4.3

Operating ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

4.3.1

Power supply voltages

Some package options provide access to a separate input and output buffer power supply called V_IO. Packages

which do not provide the separate V_IOconnection, internally connect the device V_IOto V_CC. For these packages

the references to V_IOare then also references to V_CC

.

Table 7

Power supply voltages

V_CC

V_IO

2.7V to 3.6V

1.65V to V_CC+200 mV

Notes

6. V_IOmust always be less than or equal V_CC+ 200 mV.

7. See “Input signal overshoot” on page 30 for allowed maximums during signal transition.

8. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be

greater than one second.

9. Stresses above those listed under “Absolute maximum ratings” on page 29 may cause permanent damage

to the device. This is a stress rating only; functional operation of the device at these or any other conditions

above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to

absolute maximum rating conditions for extended periods may affect device reliability.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

4.3.2

Temperature ranges

Table 8

Temperature ranges

Spec

Parameter

Ambient Temperature

Symbol

Device

Unit

Min

–55

Max

+125

T_A

Military (E)

°C

4.3.3

Input signal overshoot

During DC conditions, input or I/O signals should remain equal to or between V_SSand V_IO. During voltage transi-

tions, inputs or I/Os may overshoot V_SSto –2.0V or overshoot to V_IO+2.0V, for periods up to 20 ns.

20 ns

V_IL

- 2.0V

20 ns

Figure 19

Maximum negative overshoot waveform

20 ns

V_IO+ 2.0V

V_IH

20 ns

Figure 20

Maximum positive overshoot waveform

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

4.4

Power-up and power-down

The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on V_CC

until V_CCreaches the correct value as follows:

)

• V_CC(min) at power-up, and then for a further delay of t_PU

• V_SSat power-down

A simple pull-up resistor (generally of the order of 100 kΩ) on Chip Select (CS#) can usually be used to insure safe

and proper power-up and power-down.

The device ignores all instructions until a time delay of t_PUhas elapsed after the moment that V_CCrises above the

minimum V_CCthreshold. See Figure 21. However, correct operation of the device is not guaranteed if V_CCreturns

below V_CC(min) during t_PU. No command should be sent to the device until the end of t_PU

.

After power-up (t_PU), the device is in Standby mode (not Deep Power Down mode), draws CMOS standby current

(I_SB), and the WEL bit is reset.

During power-down or voltage drops below V_CC(cut-off), the voltage must drop below V_CC(low) for a period of

t_PDfor the part to initialize correctly on power-up. See Figure 22. If during a voltage drop the V_CCstays above V_CC

(cut-off) the part will stay initialized and will work correctly when V_CCis again above V_CC(min). In the event

Power-on Reset (POR) did not complete correctly after power up, the assertion of the RESET# signal or receiving

a software reset command (RESET) will restart the POR process.

Normal precautions must be taken for supply rail decoupling to stabilize the V_CCsupply at the device. Each device

in a system should have the V_CCrail decoupled by a suitable capacitor close to the package supply connection

(this capacitor is generally of the order of 0.1 µf).

Table 9

Symbol

_CC(min)

_CC(cut-off)

Power-up / Power-down voltage and timing

Parameter

V_CC(minimum operation voltage)

V_CC(Cut 0ff where re-initialization is needed)

V_CC(low voltage for initialization to occur)

V_CC(Low voltage for initialization to occur at embedded)

Min

2.7

2.4

1.6

2.3

Max

Unit

V

V_CC(low)

t_PU

t_PD

V_CC(min) to Read operation

V_CC(low) time

300

µs

15.0

V_CC

(max)

V_CC

(min)

V_CC

t_PU

Full Device Access

Time

Figure 21

Power-up

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

V_CC

(max)

V_CC

No Device Access Allowed

(min)

V_CC

t_PU

Device Access

Allowed

(cut-off)

V_CC

(low)

V_CC

t_PD

Time

Figure 22

Power-down and voltage drop

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Electrical specifications

4.5

DC characteristics

Applicable within operating ranges.

Table 10

Symbol

DC characteristics

Parameter

Input Low Voltage

Input High Voltage

Output Low

Voltage

Output High

Voltage

Input Leakage

Current

Output Leakage

Current

Active Power

Supply Current

(READ)

Test conditions

Min

-0.5

0.7 x V_IO

Typ ^[10]

Max

Unit

V_IL

V_IH

V_OL

0.2 x V_IO

V_IO+0.4

0.15 x V_IO

V

I_OL= 1.6 mA, V_CC= V_CCmin

I_OH= –0.1 mA

V_OH

I_LI

0.85 x V_IO

V

V_CC= V_CCMax, V_IN= V_IHor V_IL

±2

µA

mA

I_LO

I_CC1

Serial SDR@50 MHz

Serial SDR@133 MHz

Quad SDR @ 80 MHz

Quad SDR @104 MHz

Quad DDR @ 66 MHz

Quad DDR @80 MHz

Outputs unconnected during read

data return^[11]

22

35

50

61

75

90

I_CC2

I_CC3

I_CC4

I_CC5

I_SB

Active Power

CS# = V_IO

100

300

mA

µA

Supply Current

(Page Program)

Active Power

Supply Current

(WRR)

Active Power

Supply Current

(SE)

Active Power

Supply Current

(BE)

Standby Current RESET#, CS# = V_IO; SI, SCK = V_IOor

V_SS

115

4.5.1

Active power and standby power modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device

is disabled, but may still be in an Active Power mode until all program, erase, and write operations have

completed. The device then goes into the Standby Power mode, and power consumption drops to I_SB

.

Notes

10.Typical values are at T_AI= 25°C and V_CC= V_IO= 3V.

11.Output switching current is not included.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

5

Timing specifications

5.1

Key to switching waveforms

High Impedance

Any change permitted

Valid at logic high or low

Input

Symbol

Output

Logic High Logic Low

High Impedance

Valid at logic high or low

Changing, state unknown

Figure 23

Waveform element meanings

Input Levels

_IO+ 0.4V

Output Levels

0.85 x V

V

IO

0.7 x V

0.5 x V

0.2 x V

IO

Timing Reference Level

0.15 x V

IO

- 0.5V

Figure 24

Input, output, and timing reference levels

5.2

AC test conditions

Device

Under

Test

C

L

Figure 25

Test setup

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

Table 11

Symbol

C_L

AC measurement conditions

Parameter

Min

Max

Unit

pF

Load Capacitance

30

15 ^[15]

Input Rise and Fall

Times

2.4

ns

Input Pulse Voltage

0.2 x V_IOto 0.8 V_IO

0.5 V_IO

V

Input Timing Ref

Voltage

Output Timing Ref

Voltage

0.5 V_IO

V

5.2.1

Capacitance characteristics

Table 12

Capacitance

Parameter

Test conditions

Min

Max

Unit

C_IN

C_OUT

Input Capacitance (applies to SCK, CS#,

RESET#)

Output Capacitance (applies to All I/O)

1 MHz, T_A= 25°C

8

pF

1 MHz, T_A= 25°C

8

pF

5.3

Reset

Power-on (cold) reset

5.3.1

The device executes a Power-On Reset (POR) process until a time delay of t_PUhas elapsed after the moment that

V_CCrises above the minimum V_CCthreshold. See Figure 21, Table 9, and Table 13. The device must not be

selected (CS# to go high with V_IO) during power-up (t_PU), i.e. no commands may be sent to the device until the

end of t_PU. RESET# is ignored during POR. If RESET# is low during POR and remains low through and beyond the

end of t_PU, CS# must remain high until t_RHafter RESET# returns high. RESET# must return high for greater than

t_RSbefore returning low to initiate a hardware reset.

VCC

VIO

tPU

If RESET# is low at tPU end

CS# must be high at tPU end

RESET#

tRH

CS#

Figure 26

Notes

Reset low at the end of POR

12.Output High-Z is defined as the point where data is no longer driven.

13.Input slew rate: 1.5 V/ns.

14.AC characteristics tables assume clock and data signals have the same slew rate (slope).

15.DDR Operation.

16.For more information on capacitance, please consult the IBIS models.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

VCC

VIO

tPU

RESET#

If RESET# is high at tPU end

tPU

CS# may stay high or go low at tPU end

CS#

Figure 27

Reset high at the end of POR

VCC

VIO

tPU

tRS

RESET#

CS#

Figure 28

POR followed by hardware reset

5.3.2

Hardware (warm) reset

When the RESET# input transitions from V_IHto V_ILthe device will reset register states in the same manner as

power-on reset but, does not go through the full reset process that is performed during POR. The hardware reset

process requires a period of t_RPHto complete. If the POR process did not complete correctly for any reason during

power-up (t_PU), RESET# going low will initiate the full POR process instead of the hardware reset process and will

require t_PUto complete the POR process.

The RESET# input provides a hardware method of resetting the flash memory device to standby state.

• RESET# must be high for t_RSfollowing t_PUor t_RPH, before going low again to initiate a hardware reset.

• When RESET# is driven low for at least a minimum period of time (t_RP), the device terminates any operation in

progress, tri-states all outputs, and ignores all read/write commands for the duration of t_RPH. The device resets

the interface to standby state.

• If CS# is low at the time RESET# is asserted, CS# must return high during t_RPHbefore it can be asserted low again

after t_RH

.

• Hardware Reset is only offered in 16-lead SOIC and BGA packages.

tRP

Any prior reset

tRPH

RESET#

CS#

tRH

tRS

tRPH

Figure 29

Hardware reset

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

Table 13

Hardware reset parameters

Parameter

Description

Limit

Time

Unit

t_RS

Reset Setup - Prior Reset end and RESET# high

before RESET# low

Min

50

ns

t_RPH

t_RP

t_RH

Reset Pulse Hold - RESET# low to CS# low

RESET# Pulse Width

Reset Hold - RESET# high before CS# low

Min

35

200

50

µs

ns

Notes

17.RESET# Low is optional and ignored during Power-up (t_PU). If Reset# is asserted during the end of t_PU, the

device will remain in the reset state and t_RHwill determine when CS# may go Low.

18.Sum of t_RPand t_RHmust be equal to or greater than t_RPH.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

5.4

SDR AC characteristics

Table 14

Symbol

F_{SCK, R}

AC characteristics (Single die package, V_IO= V_CC2.7V to 3.6V)

Parameter

Min

DC

Typ

Max

50

133

Unit

MHz

SCK Clock Frequency for READ and 4READ instructions

F_{SCK, C}

SCK Clock Frequency for single commands as shown in

DC

Table 42 ^[22]

F_{SCK, C}

SCK Clock Frequency for the following dual and quad

commands: DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR,

QIOR, 4QIOR

DC

104

MHz

F_{SCK, QPP}SCK Clock Frequency for the QPP, 4QPP commands

P_SCKSCK Clock Period

_WH, t_CHClock High Time ^[23]

_WL, t_CLClock Low Time ^[23]

DC

1/ F_SCK

45% P_SCK

0.1

80

∞

t

ns

V/ns

ns

t

_CRT, t_CLCHClock Rise Time (slew rate)

_CFT, t_CHCLClock Fall Time (slew rate)

0.1

10

50

t_CS

CS# High Time (Read Instructions)

CS# High Time (Program/Erase)

t_CSS

t_CSH

t_SU

t_HD

t_V

CS# Active Setup Time (relative to SCK)

CS# Active Hold Time (relative to SCK)

Data in Setup Time

Data in Hold Time

Clock Low to Output Valid

3

2

ns

3000^[24]

8.0 ^[20]

7.65 ^[21]

6.5 ^[22]

t_HO

t_DIS

Output Hold Time

Output Disable Time

WP# Setup Time

WP# Hold Time

HOLD# Active Setup Time (relative to SCK)

HOLD# Active Hold Time (relative to SCK)

HOLD# Non Active Setup Time (relative to SCK)

HOLD# Non Active Hold Time (relative to SCK)

HOLD# enable to Output Invalid

HOLD# disable to Output Valid

2

0

ns

8

t_WPS

t_WPH

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_HZ

20 ^[19]

100 ^[19]

3

8

t_LZ

Notes

19.Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

20.Full V_CCrange (2.7 - 3.6V) and CL = 30 pF.

21.Regulated V_CCrange (3.0 - 3.6V) and CL = 30 pF.

22.Regulated V_CCrange (3.0 - 3.6V) and CL = 15 pF.

23.±10% duty cycle is supported for frequencies ≤ 50 MHz.

24.Maximum value only applies during Program/Erase Suspend/Resume commands.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

Table 15

Symbol

F_{SCK, R}

AC characteristics (Single die package, V_IO1.65V to 2.7V, V_CC2.7V to 3.6V)

Parameter

Min

Typ

Max

Unit

MHz

SCK Clock Frequency for READ, 4READ

instructions

DC

50

F_{SCK, C}

P_SCK

SCK Clock Frequency for all others ^[27]

SCK Clock Period

DC

1/ F_SCK

45% P_SCK

0.1

66

∞

MHz

t

_WH, t_CHClock High Time ^[28]

t_WL, t_CLClock Low Time ^[28]

ns

V/ns

ns

t

_CRT, t_CLCHClock Rise Time (slew rate)

_CFT, t_CHCLClock Fall Time (slew rate)

0.1

10

50

t_CS

CS# High Time (Read Instructions)

CS# High Time (Program/Erase)

t_CSS

t_CSH

t_SU

t_HD

t_V

CS# Active Setup Time (relative to SCK)

CS# Active Hold Time (relative to SCK)

Data in Setup Time

Data in Hold Time

Clock Low to Output Valid

10

3

5

ns

3000 ^[29]

4

14.5 ^[26]

12.0 ^[27]

t_HO

t_DIS

Output Hold Time

Output Disable Time

WP# Setup Time

WP# Hold Time

HOLD# Active Setup Time (relative to SCK)

HOLD# Active Hold Time (relative to SCK)

HOLD# Non Active Setup Time (relative to

SCK)

2

0

ns

14

t_WPS

t_WPH

t_HLCH

t_CHHH

t_HHCH

20 ^[25]

100 ^[25]

5

t_CHHL

HOLD# Non Active Hold Time (relative to

SCK)

5

ns

t_HZ

t_LZ

HOLD# enable to Output Invalid

HOLD# disable to Output Valid

14

ns

Notes

25.Only applicable as a constraint for WRR instruction when SRWD is set to a 1.

26.CL = 30 pF.

27.CL = 15 pF.

28.±10% duty cycle is supported for frequencies ≤ 50 MHz.

29.Maximum value only applies during Program/Erase Suspend/Resume commands.

Datasheet

39 of 153

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2022-04-11

Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

5.4.1

Clock timing

P_SCK

tCH

tCL

V_{IH min}

V_{IO / 2}

V_{IL max}

tCFT

tCRT

Figure 30

Clock timing

5.4.2

Input / output timing

tCS

CS#

SCK

tCSH

tCSS

tSU

tCSS

tHD

SI

MSB IN

LSB IN

SO

Figure 31

SPI single bit input timing

tCS

CS#

SCK

SI

tLZ

tHO

tV

LSB OUT

tDIS

SO

MSB OUT

Figure 32

SPI single bit output timing

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

tCS

CS#

tCSS

tCSH

tCSS

SCK

tSU

tHD

tLZ

tHO

tV

tDIS

MSB IN

LSB IN

MSB OUT.

LSB OUT

IO

Figure 33

SPI SDR MIO timing

CS#

SCK

tCHHH

tHLCH

tHHCH

tCHHH

tCHHL

HOLD#

Hold Condition

Standard Use

Hold Condition

Non-standard Use

SI_or_IO_(during_input)

tHZ

tLZ

tHZ

tLZ

SO_or_IO_(during_output)

A

B

C

D

E

Figure 34

Hold timing

CS#

tWPS

WP#

SCK

tWPH

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

WRR Instruction

Input Data

Figure 35

WP# input timing

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

5.5

DDR AC characteristics

Table 16

AC characteristics DDR operation

66 MHz

Typ

80 MHz

Typ

Symbol

Parameter

Unit

Min

Max

Min

Max

F_{SCK, R}SCK Clock Frequency for

DDR READ instruction

DC

66

DC

80

MHz

P_{SCK, R}SCK Clock Period for DDR

READ instruction

15

∞

12.5

∞

ns

t_WH, t_CHClock High Time

45% P_SCK

10

45% P_SCK

10

ns

t

_WL, t_CLClock Low Time

t_CS

CS# High Time (Read

Instructions)

t_CSSCS# Active Setup Time

(relative to SCK)

t_CSHCS# Active Hold Time

(relative to SCK)

3

ns

t_SU

t_HD

t_V

t_HO

t_DIS

t_LZ

IO in Setup Time

IO in Hold Time

Clock Low to Output Valid

Output Hold Time

Output Disable Time

Clock to Output Low

Impedance

2

3000 ^[31]

6.5 ^[30]

1.5

3000 ^[31]

6.5 ^[30]

ns

1.5

0

1.5

0

8

t_{O_SKEW}First Output to last Output

data valid time

600

ps

Notes

30.Regulated V_CCrange (3.0 - 3.6V) and CL =15 pF.

31.Maximum value only applies during Program/Erase Suspend/Resume commands.

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

5.5.1

DDR input timing

tCS

CS#

SCK

tCSH

tCSS

tHD

tSU

tHD

tSU

SI_or_IO

SO

MSB IN

LSB IN

Figure 36

SPI DDR input timing

5.5.2

DDR output timing

tCS

CS#

SCK

SI

tLZ

tHO

tV

tDIS

SO_or_IO

MSB

LSB

Figure 37

SPI DDR output timing

Datasheet

43 of 153

002-19087 Rev. *B

2022-04-11

Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Timing specifications

P_SCK

tCL

tCH

SCK

tV

tO_SKEW

tOTT

Slow

D1

Slow

D2

IO0

IO1

IO2

Fast

D1

Fast

D2

IO3

D1

Valid

D2

Valid

IO_valid

tDV

Figure 38

SPI DDR data valid window

Notes

32.t_CLHis the shorter duration of t_CLor t_CH

.

33.t_{O_SKEW}is the maximum difference (delta) between the minimum and maximum t_V(output valid) across all

IO signals.

34.t_OTTis the maximum Output Transition Time from one valid data value to the next valid data value on each IO.

35.t_OTTis dependent on system level considerations including:

a. Memory device output impedance (drive strength).

b. System level parasitics on the IOs (primarily bus capacitance).

c. Host memory controller input V_IHand V_ILlevels at which 0 to 1 and 1 to 0 transitions are recognized.

d. As an example, assuming that the above considerations result a memory output slew rate of 2V/ns and a 3V

transition (from 1 to 0 or 0 to 1) is required by the host, the t_OTTwould be:

t_OTT= 3V/(2V/ns) = 1.5 ns

e. t_OTTis not a specification tested by Infineon, it is system dependent and must be derived by the system

designer based on the above considerations.

36.The minimum data valid window (t_DV) can be calculated as follows:

a. As an example, assuming:

i. 80 MHz clock frequency = 12.5 ns clock period

ii. DDR operations are specified to have a duty cycle of 45% or higher

iii. t_CLH= 0.45*PSCK = 0.45x12.5 ns = 5.625 ns

iv. t_{O_SKEW}= 600 ps

v. t_OTT= 1.5 ns

b. t_DV= t_CLH- t_{O_SKEW}- t_OTT

c. t_DV= 5.625 ns - 600 ps - 1.5 ns = 3.525 ns

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

6

Physical interface

Table 17

Model specific connections

VIO / RFU

Versatile I/O or RFU — Some device models bond this connector to the device I/O power

supply, other models bond the device I/O supply to Vcc within the package leaving this

package connector unconnected.

RESET# / RFU

RESET# or RFU — Some device models bond this connector to the device RESET#

signal, other models bond the RESET# signal to Vcc within the package leaving this

package connector unconnected.

6.1

FAB024 24-ball BGA package

6.1.1

Connection diagram

1

2

3

4

5

A

B

C

D

E

NC

VSS

RESET#/

RFU

NC

DNU

NC

SCK

CS#

VCC

RFU WP#/IO2

SO/IO1 SI/IO0 HOLD#/IO3 NC

NC

VIO/RFU

NC

Figure 39

24-ball BGA, 5 x 5 ball footprint (FAB024), top view

Notes

37.Refer to Table 3 for signal descriptions.

38.Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use

either package.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Physical interface

6.1.2

FAB024 physical diagram

NOTES:

DIMENSIONS

SYMBOL

MIN.

NOM.

MAX.

1.

2.

3.

DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

ALL DIMENSIONS ARE IN MILLIMETERS.

A

A1

D

1.20

-

0.20

BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

8.00 BSC

4.

5.

e REPRESENTS THE SOLDER BALL GRID PITCH.

E

6.00 BSC

4.00 BSC

5

D1

E1

MD

ME

N

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

5

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

24

0.40

b

0.35

0.45

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE

POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

eE

eD

SD

SE

1.00 BSC

0.00 BSC

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND

"SE" = eE/2.

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

8.

9.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALLIZED MARK INDENTATION OR OTHER MEANS.

Figure 40

FAB024 — 24-ball BGA (8 x 6 mm) package

6.1.3

Special handling instructions for FBGA packages

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Software interface

This section discusses the features and behaviors most relevant to host system software that interacts with the

S25FL512S memory device.

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

7

Address space maps

Overview

7.1

7.1.1

Extended address

The S25FL512S device supports 32-bit addresses to enable higher density devices than allowed by previous

generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access

only 16 Mbytes (128 Mbits) of maximum density. A 32-bit byte resolution address allows direct addressing of up

to a 4 Gbytes (32 Gbits) of address space.

Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit

addresses are enabled in three ways:

• Bank address register — a software (command) loadable internal register that supplies the high order bits of

address when legacy 24-bit addresses are in use.

• Extended address mode — a bank address register bit that changes all legacy commands to expect 32 bits of

address supplied from the host system.

• New commands — that perform both legacy and new functions, which expect 32-bit address.

The default condition at power-up and after reset, is the Bank address register loaded with zeros and the

extended address mode set for 24-bit addresses. This enables legacy software compatible access to the first 128

Mbits of a device.

7.1.2

Multiple address spaces

Many commands operate on the main flash memory array. Some commands operate on address spaces separate

from the main flash array. Each separate address space uses the full 32-bit address but may only define a small

portion of the available address space.

7.2

Flash memory array

The main flash array is divided into erase units called sectors. The sectors are organized as uniform 256-kbyte

sectors.

Table 18

S25FL512S sector and memory address map, uniform 256-kbyte sectors

Address range

Sector size (kbyte)

Sector count

Sector range

Notes

(8-bit)

256

SA00

00000000h-0003FFF

Fh

Sector Starting

Address

—

:

Sector Ending

Address

SA255

03FC0000h-03FFFFF

Fh

Note: This is a condensed table that uses a sector as a reference. There are address ranges that are not explicitly

listed. All 256-kB sectors have the pattern XXXX0000h-XXXXFFFFh.

7.3

ID-CFI address space

The RDIDJ command (9Fh) reads information from a separate flash memory address space for device identifi-

cation (ID) and Common Flash Interface (CFI) information. See “Device ID and common flash interface (ID-CFI)

address map” on page 124 for the tables defining the contents of the ID-CFI address space. The ID-CFI address

space is programmed by Infineon and read-only for the host system.

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

7.4

JEDEC JESD216 Serial flash discoverable parameters (SFDP) space.

The RSFDP command (5Ah) reads information from a separate Flash memory address space for device identifi-

cation, feature, and configuration information, in accord with the JEDEC JESD216B standard for Serial Flash

Discoverable Parameters. The ID-CFI address space is incorporated as one of the SFDP parameters.

See “Serial flash discoverable parameters (SFDP) address map” on page 120 for the table defining the

contents of the SFDP address space. The SFDP address space is programmed by Infineon and is read-only for the

host system

7.5

OTP address space

Each S25FL512S memory device has a 1024-byte One Time Program (OTP) address space that is separate from

the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

In the 32-byte region starting at address zero:

• The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able

to program these bytes.

• The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently

protect each region from programming. The bytes are erased when shipped from Infineon. After an OTP region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the OTP Lock Bytes.

• The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU

bytes may be programmed by the host system but it must be understood that a future device may use those

bits for protection of a larger OTP space. The bytes are erased when shipped from Infineon.

The remaining regions are erased when shipped from Infineon, and are available for programming of additional

permanent data.

Refer to Figure 41 for a pictorial representation of the OTP memory space.

The OTP memory space is intended for increased system security. OTP values, such as the random number

programmed by Infineon, can be used to “mate” a flash component with the system CPU/ASIC to prevent device

substitution.

The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when

set to 1. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent

further OTP memory space programming during the remainder of normal power-on system operation.

32 Byte OTP Region 31

32 Byte OTP Region 30

32 Byte OTP Region 29

.

When programmed to

“0” each lock bit

protects its related 32

byte region from any

further programming

.

32 Byte OTP Region 3

32 Byte OTP Region 2

32 Byte OTP Region 1

32 Byte OTP Region 0

...

Lock Bits 31 to 0

Reserved

Lock Bytes

16 Byte Random Number

Contents of Region 0

{

Byte 1F

Byte 10

Byte 0

Figure 41

OTP address space

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

Table 19

OTP address map

Initial delivery state

(Hex)

Region

Byte address range (Hex)

Contents

Region 0

000

Least Significant Byte of

Spansion Programmed

Random Number

Spansion Programmed

Random Number

...

00F

Most Significant Byte of

Spansion Programmed

Random Number

010 to 013

Region Locking Bits

Byte 10 [bit 0] locks region

0 from programming

when = 0

All bytes = FF

...

Byte 13 [bit 7] locks region

31 from programming

when = 0

014 to 01F

020 to 03F

040 to 05F

...

Reserved for Future Use

(RFU)

All bytes = FF

Region 1

Region 2

...

Available for User

Programming

Available for User

Programming

Available for User

Programming

Available for User

Programming

Region 31

3E0 to 3FF

7.6

Registers

Registers are small groups of memory cells used to configure how the S25FL512-S memory device operates or to

report the status of device operations. The registers are accessed by specific commands. The commands (and

hexadecimal instruction codes) used for each register are noted in each register description. The individual

register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for each bit is noted in each

register description. The default state shown for each bit refers to the state after power-on reset, hardware reset,

or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when

the device is shipped from Infineon. Non-volatile bits have the same cycling (erase and program) endurance as

the main flash array.

Table 20

Register descriptions

Register

Abbreviation

SR1[7:0]

CR1[7:0]

Type

Volatile

RFU

Bit location

Status Register 1

Configuration Register 1

Status Register 2

7:0

SR2[7:0]

AutoBoot Register

Bank Address Register

ECC Status Register

ASP Register

ABRD[31:0]

BRAC[7:0]

ECCSR[7:0]

ASPR[15:1]

Non-volatile

Volatile

OTP

31:0

7:0

15:1

Datasheet

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002-19087 Rev. *B

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

Table 20

Register descriptions

Register

Abbreviation

ASPR[0]

PASS[63:0]

PPBL[7:1]

PPBL[0]

Type

RFU

Non-volatile OTP

Volatile

Bit location

ASP Register

0

63:0

7:1

0

Password Register

PPB Lock Register

Volatile

Read Only

PPB Access Register

DYB Access Register

SPI DDR Data Learning Registers

PPBAR[7:0]

DYBAR[7:0]

NVDLR[7:0]

VDLR[7:0]

Non-volatile

Volatile

Non-volatile

Volatile

7:0

7.6.1

Status register 1 (SR1)

Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h),

Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).

Table 21

Status register-1 (SR1)

Field

Bits

Function

Type

Default state

Description

name

7

SRWD

Status

Register Write

Disable

Non-Volatile

0

1 = Locks state of SRWD, BP, and configuration

register bits when WP# is low by ignoring WRR

command

0 = No protection, even when WP# is low

6

5

P_ERR Programming

Error

Volatile,

0

1 = Error occurred.

0 = No Error

Read only

Occurred

E_ERR

Erase Error

Occurred

Volatile,

Read only

1 = Error occurred

0 = No Error

4

3

2

BP2

BP1

BP0

Block

Volatile if

CR1[3]=1,

1 if CR1[3]=1, Protects selected range of sectors (Block)

Protection

0 when

from Program or Erase

Non-Volatile shipped from

if CR1[3]=0

Volatile

Infineon

0

1

WEL

Write Enable

Latch

1 = Device accepts Write Registers (WRR),

program or erase commands

0 = Device ignores Write Registers (WRR),

program or erase commands

This bit is not affected by WRR, only WREN and

WRDI commands affect this bit

0

WIP

Write in

Progress

Volatile,

Read only

0

1 = Device Busy, a Write Registers (WRR),

program, erase or other operation is in

progress

0 = Ready Device is in standby mode and can

accept commands

The Status Register contains both status and control bits:

Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit

is set to 1 and the WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the Status Register

become read-only bits and the Write Registers (WRR) command is no longer accepted for execution. If WP# is high

the SRWD bit and BP bits may be changed by the WRR command. If SRWD is 0, WP# has no effect and the SRWD

Datasheet

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Address space maps

bit and BP bits may be changed by the WRR command. The SRWD bit has the same non-volatile endurance as the

main flash array.

Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure

indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program

operation. This bit will also be set when the user attempts to program within a protected main memory sector or

locked OTP region. When the Program Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register

(CLSR) command. This is a read-only bit and is not affected by the WRR command.

Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When

the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation. This bit will also be

set when the user attempts to erase an individual protected main memory sector. The Bulk Erase command will

not set E_ERR if a protected sector is found during the command execution. When the Erase Error bit is set to a 1

this bit can be reset to 0 with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected

by the WRR command.

Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected

against program and erase commands. The BP bits are either volatile or non-volatile, depending on the state of

the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to 1, the

relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed

only when the BP bits are cleared to 0’s. See “Block protection” on page 63 for a description of how the BP bit

values select the memory array area protected. The BP bits have the same non-volatile endurance as the main

flash array.

Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to 1 to enable program, write, or erase operations as

a means to provide protection against inadvertent changes to memory or register values. The Write Enable

(WREN) command execution sets the Write Enable Latch to a 1 to allow any program, erase, or write commands

to execute afterwards. The Write Disable (WRDI) command can be used to set the Write Enable Latch to a 0 to

prevent all program, erase, and write commands from execution. The WEL bit is cleared to 0 at the end of any

successful program, write, or erase operation. Following a failed operation the WEL bit may remain set and

should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence,

hardware reset, or software reset, the Write Enable Latch is set to a 0 The WRR command does not affect this bit.

Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation,

or any other operation, during which a new operation command will be ignored. When the bit is set to a 1 the

device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2), Erase Suspend (ERSP),

Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands may be

accepted. ERSP and PGSP will only be accepted if memory array erase or program operations are in progress. The

status register E_ERR and P_ERR bits are updated while WIP = 1. When P_ERR or E_ERR bits are set to one, the

WIP bit will remain set to one indicating the device remains busy and unable to receive new operation commands.

A Clear Status Register (CLSR) command must be received to return the device to standby mode. When the WIP

bit is cleared to 0 no operation is in progress. This is a read-only bit.

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7.6.2

Configuration register 1 (CR1)

Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration

Register bits can be changed using the WRR command with sixteen input cycles.

The configuration register controls certain interface and data protection functions.

Table 22

Bits

Configuration register (CR1)

Default

state

Field name

Function

Type

Description

7

6

LC1

LC0

Latency Code

Non-Volatile

0

Selects number of initial read

latency cycles

See Latency Code Tables

5

TBPROT

Configures Start of Block

Protection

OTP

0

1 = BP starts at bottom (Low

address)

0 = BP starts at top (High

address)

4

3

RFU

BPNV

RFU

OTP

0

Reserved for Future Use

1 = Volatile

0 = Non-Volatile

Configures BP2-0 in Status

Register

2

1

RFU

QUAD

RFU

0

Reserved for Future Use

1 = Quad

0 = Dual or Serial

Puts the device into Quad I/O Non-Volatile

operation

0

FREEZE

Lock current state of BP2-0

bits in Status Register,

TBPROT in Configuration

Register, and OTP regions

Volatile

0

1 = Block Protection and OTP

locked

0 = Block Protection and OTP

un-locked

Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end

of address and the start of read data output for all read commands.

Some read commands send mode bits following the address to indicate that the next command will be of the

same type with an implied, rather than an explicit, instruction. The next command thus does not provide an

instruction byte, only a new address and mode bits. This reduces the time needed to send each command when

the same command type is repeated in a sequence of commands.

Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array

before data can be returned to the host system. Some read commands require additional latency cycles as the

SCK frequency is increased.

The following latency code tables provide different latency settings that are configured by Infineon. The High

Performance versus the Enhanced High Performance settings are selected by the ordering part number.

Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported

at the frequency shown. Read is supported only up to 50 MHz but the same latency value is assigned in each

latency code and the command may be used when the device is operated at ≤ 50 MHz with any latency code

setting. Similarly, only the Fast Read command is supported up to 133 MHz but the same 10b latency code is used

for Fast Read up to 133 MHz and for the other dual and quad read commands up to 104 MHz. It is not necessary

to change the latency code from a higher to a lower frequency when operating at lower frequencies where a

particular command is supported. The latency code values for a higher frequency can be used for accesses at

lower frequencies.

The High Performance settings provide latency options that are the same or faster than alternate source SPI

memories. These settings provide mode bits only for the Quad I/O Read command.

The Enhanced High Performance settings similarly provide latency options the same or faster than additional

alternate source SPI memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR

Dual I/O Read commands.

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Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start

of read data, if there are 5 or more dummy cycles. See “Read memory array commands” on page 86 for more

information on the DLP.

Table 23

Latency codes for SDR high performance

Read

(03h, 13h)

Dum-

Fast Read

(0Bh, 0Ch)

Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read

Freq.

(3Bh, 3Ch)

(6Bh, 6Ch)

Dum-

(BBh, BCh)

(EBh, ECh)

LC

(MHz)

Dum-

Mode

my

0

my

0

my

0

my

1

≤ 50 11

≤ 80 00

≤ 90 01

≤104 10

≤133 10

0

-

0

-

0

-

0

-

0

-

4

5

6

-

2

-

8

4

-

8

4

-

8

5

-

Table 24

Latency codes for DDR high performance

DDR Fast Read

(0Dh, 0Eh)

DDR Dual I/O Read

(BDh, BEh)

Read DDR Quad I/O

(EDh, EEh)

Freq.

LC

(MHz)

Mode

Dummy

Mode

Dummy

Mode

Dummy

≤ 50

≤ 66

11

00

01

10

0

4

5

6

7

0

4

6

7

8

1

3

6

7

8

Table 25

Latency codes for SDR enhanced high performance

Read Quad

Out

(6Bh, 6Ch)

Read

Fast Read

(0Bh, 0Ch)

Read Dual Out

(3Bh, 3Ch)

Dual I/O Read Quad I/O Read

Freq.

LC

(03h, 13h)

(BBh, BCh)

(EBh, ECh)

(MHz)

Dum-

Mode

my

0

my

1

≤ 50 11

≤ 80 00

≤ 90 01

≤104 10

≤133 10

0

-

0

-

0

-

0

8

-

0

-

0

8

-

4

-

0

1

2

-

2

-

8

4

5

-

8

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Table 26

Latency codes for DDR enhanced high performance

DDR Fast Read

(0Dh, 0Eh)

DDR Dual I/O Read

(BDh, BEh)

Read DDR Quad I/O

(EDh, EEh)

Freq.

LC

(MHz)

Mode

Dummy

Mode

Dummy

Mode

Dummy

≤ 50

≤ 66

≤ 80

11

00

01

10

00

01

10

4

1

2

4

5

2

4

5

2

4

5

6

4

5

6

1

3

6

7

8

6

7

8

Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2,

BP1, and BP0 in the Status Register. As described in the status register section, the BP2-0 bits allow the user to

optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is

set to a 0 the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT is

set to a 1 the Block Protection is defined to start from the bottom (zero address) of the array. The TBPROT bit is

OTP and set to a 0 when shipped from Infineon. If TBPROT is programmed to 1, an attempt to change it back to

0 will fail and set the Program Error bit (P_ERR in SR1[6]).

The desired state of TBPROT must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPROT must not be

programmed after programming or erasing is done in the main flash array.

CR1[4]: Reserved for Future Use

Block Protection Non-Volatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the Status

Register are volatile or non-volatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to 000 when

shipped from Infineon. When BPNV is set to a 0 the BP2-0 bits in the Status Register are non-volatile. When BPNV

is set to a 1 the BP2-0 bits in the Status Register are volatile and will be reset to binary 111 after POR, hardware

reset, or command reset. If BPNV is programmed to 1, an attempt to change it back to 0 will fail and set the

Program Error bit (P_ERR in SR1[6]).

CR1[2]: Reserved for Future Use.

Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit - Quad

mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not monitored for their

normal functions and are internally set to high (inactive). The commands for Serial, Dual Output, and Dual I/O

Read still function normally but, there is no need to drive WP# and Hold# inputs for those commands when

switching between commands using different data path widths. The QUAD bit must be set to one when using

Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program commands. The QUAD bit is

non-volatile.

Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits in

Status Register, the TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This

prevents writing, programming, or erasing these areas. As long as the FREEZE bit remains cleared to logic 0 the

other bits of the Configuration Register, including FREEZE, are writable, and the OTP address space is program-

mable. Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to

power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit. The FREEZE bit is

Note

39.When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides

5 or more dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving

before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01

for DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning Pattern (DLP) for DDR is used.

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volatile and the default state of FREEZE after power-on is 0. The FREEZE bit can be set in parallel with updating

other values in CR1 by a single WRR command.

7.6.3

Status register 2 (SR2)

Related Commands: Read Status Register 2 (RDSR2 07h).

Table 27

Bits

Status register-2 (SR2)

Field name Function

Default

state

Type

Description

7

6

5

4

3

2

1

RFU

ES

Reserved

0

Reserved for Future Use

Erase

Suspend

Volatile, Read

only

1 = In erase suspend mode

0 = Not in erase suspend mode

0

PS

Program

Suspend

Volatile, Read

only

0

1 = In program suspend mode

0 = Not in program suspend mode

Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend

mode. This is a status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in erase suspend

mode. When Erase Suspend bit is cleared to 0, the device is not in erase suspend mode. Refer to Erase Suspend

and Resume Commands (75h) (7Ah) for details about the Erase Suspend/Resume commands.

Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program

Suspend mode. This is a status bit that cannot be written. When Program Suspend bit is set to 1, the device is in

program suspend mode. When the Program Suspend bit is cleared to 0, the device is not in program suspend

mode. Refer to “Program suspend (PGSP 85h) and resume (PGRS 8Ah)” on page 104 for details.

7.6.4

AutoBoot register

Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).

The AutoBoot Register provides a means to automatically read boot code as part of the power on reset, hardware

reset, or software reset process.

Table 28

Bits

AutoBoot register

Default

state

Field name

Function

Type

Description

31 to 9

ABSA

AutoBoot Start Non-Volatile 000000h 512 byte boundary address for the

Address

start of boot code access

8 to 1

0

ABSD

ABE

AutoBoot Start Non-Volatile

Delay

00h

0

Number of initial delay cycles

between CS# going low and the first

bit of boot code being transferred

AutoBoot Enable Non-Volatile

1 = AutoBoot is enabled

0 = AutoBoot is not enabled

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7.6.5

Bank address register

Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h)

and Bank Register Write (BRWR 17h).

The Bank Address register supplies additional high order bits of the main flash array byte boundary address for

legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of

address (above A23) for all 3-byte address commands when EXTADD=0. The Bank Address is not used when

EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.

Table 29

Bank address register (BAR)

Field

Default

state

Bits

Function

Type

Description

name

7

EXTADD

Extended

Address Enable

Volatile

0b

1 = 4-byte (32-bits) addressing required from

command.

0 = 3-byte (24-bits) addressing from command +

Bank Address

6 to 2

1

0

RFU

BA25

BA24

Reserved

Bank Address

Volatile

00000b Reserved for Future Use

0

A25 for 512 Mb device

A24 for 512 Mb device

Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By default

(power up reset, hardware reset, and software reset), it is cleared to 0 for 3 bytes (24 bits) of address. When set to

1, the legacy commands will require 4 bytes (32 bits) for the address field. This is a volatile bit.

7.6.6

ECC status register (ECCSR)

Related Commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable non-volatile bits. All

defined bits are volatile read only status. The default state of these bits are set by hardware. See “Automatic

ECC” on page 101.

The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read

command is written followed by an ECC unit address. The contents of the status register then indicates, for the

selected ECC unit, whether there is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes

of data, or that ECC is disabled for that ECC unit.

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Table 30

Bits

ECC status register (ECCSR)

Field

Default

state

Function

name

Type

Description

7 to 3

2

RFU

EECC

Reserved

Error in ECC

0

Reserved for Future Use

Volatile, Read

only

1 = Single Bit Error found in the ECC unit

eight bit error correction code

0 = No error.

1

0

EECCD Error in ECC unit Volatile, Read

0

1 = Single Bit Error corrected in ECC

unit data.

data

only

0 = No error.

ECCDI

ECC Disabled

Volatile, Read

only

1 = ECC is disabled in the selected ECC

unit.

0 = ECC is enabled in the selected ECC

unit.

ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC

unit data. ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures

and ECC is enabled.

ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to

another. These bits should be treated as “don’t care” and ignored by any software reading status.

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7.6.7

ASP register (ASPR)

Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).

The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector

Protection (ASP) features.

Table 31

ASP register (ASPR)

Default

state

Bits Field name

Function

Type

Description

Reserved for Future Use

15 to 9

RFU

Reserved

OTP

1

[40]

8

7

6

5

4

3

2

Reserved for Future Use

[40]

1

[40]

RFU

PWDMLB

Password

Protection

Mode Lock Bit

1

0 = Password Protection Mode permanently

enabled.

1 = Password Protection Mode not permanently

enabled.

1

0

PSTMLB

RFU

Persistent

Protection

Mode Lock Bit

OTP

0 = Persistent Protection Mode permanently

enabled.

1 = Persistent Protection Mode not permanently

enabled.

Reserved

Reserved for Future Use

Reserved for Future Use (RFU) ASPR[15:3, 0].

Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection

Mode is permanently selected.

Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection

Mode is permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to

zero.

7.6.8

Password register (PASS)

Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).

Table 32

Bits

Password register (PASS)

Field

Function

Type

Default state

Description

name

63 to 0

PWD

Hidden

Password

OTP

FFFFFFFF-FFFFF Non-volatile OTP storage of 64-bit password. The

FFFh

password is no longer readable after the password

protection mode is selected by programming ASP

register bit 2 to zero.

Note

40.Default value depends on ordering part number, see “Initial delivery state” on page 149.

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7.6.9

PPB lock register (PPBL)

Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)

Table 33

Bits

PPB lock register (PPBL)

Field

Function

Type

Default state

Description

name

7 to 1

0

RFU

Reserved

Volatile

00h

Reserved for Future Use

PPBLOCK Protect PPB Volatile

Array

Persistent Protection

Mode = 1

Password Protection

Mode = 0

0 = PPB array protected until next

power cycle or hardware reset

1 = PPB array may be programmed or

erased.

7.6.10

PPB access register (PPBAR)

Related Commands: PPB Read (PPBRD E2h)

Table 34

Bits

PPB access register (PPBAR)

Field

Default

state

Function

Type

Description

name

7 to 0

PPB

Read or

Program per

sector PPB

Non-volatile

FFh

00h = PPB for the sector addressed by the PPBRD

or PPBP command is programmed to 0,

protecting that sector from program or erase

operations.

FFh = PPB for the sector addressed by the PPBRD

or PPBP command is erased to 1, not protecting

that sector from program or erase operations.

7.6.11

DYB access register (DYBAR)

Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).

Table 35

Bits

DYB access register (DYBAR)

Field

Default

state

Function

Type

Description

name

7 to 0

DYB

Read or

Write per

sector DYB

Volatile

FFh

00h = DYB for the sector addressed by the DYBRD or

DYBP command is cleared to 0, protecting that sector

from program or erase operations.

FFh = DYB for the sector addressed by the DYBRD or

DYBP command is set to 1, not protecting that sector

from program or erase operations.

7.6.12

SPI DDR data learning registers

Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read

(DLPRD 41h).

The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit

Volatile Data Learning Register (VDLR). When shipped from Infineon, the NVDLR value is 00h. Once programmed,

the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the

VDLR. The VDLR can be written to at any time, but on reset or power cycles the data pattern will revert back to

what is in the NVDLR. During the learning phase described in the SPI DDR modes, the DLP will come from the

VDLR. Each IO will output the same DLP value for every clock edge. For example, if the DLP is 34h (or binary

00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock edge all I/O’s will

output 0, the 3rd will output 1, etc.

When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR

commands.

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Table 36

Bits

Non-volatile data learning register (NVDLR)

Field

Default

state

Function

Type

Description

name

7 to 0

NVDLP Non-Volatile OTP

00h

OTP value that may be transferred to the host during

DDR read command latency (dummy) cycles to provide

a training pattern to help the host more accurately

center the data capture point in the received data bits.

Data

Learning

Pattern

Table 37

Bits

Volatile data learning register (NVDLR)

Field

Default

state

Function

Type

Description

name

7 to 0

VDLP

VolatileData Volatile Takes the Volatile copy of the NVDLP used to enable and deliver

Learning

Pattern

value of the Data Learning Pattern (DLP) to the outputs. The

NVDLR VDLP may be changed by the host during system

duringPOR operation.

or Reset

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Data protection

8

Data protection

8.1

Secure silicon region (OTP)

The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array.

The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with

the system CPU/ASIC to prevent device substitution. See “OTP address space” on page 49, “One time program

array commands” on page 109, and “OTP read (OTPR 4Bh)” on page 109.

8.1.1

Reading OTP memory space

The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB OTP

address range will yield indeterminate data.

8.1.2

Programming OTP memory space

The protocol of the OTP programming command is the same as Page Program. The OTP Program command can

be issued multiple times to any given OTP address, but this address space can never be erased.

Automatic ECC is programmed on the first programming operation to each 16-byte region. Programming within

a 16-byte region more than once disables the ECC. It is recommended to program each 16-byte portion of each

32-byte region once so that ECC remains enabled to provide the best data integrity.

The valid address range for OTP Program is depicted in Figure 41. OTP Program operations outside the valid OTP

address range will be ignored and the WEL in SR1 will remain high (set to 1). OTP Program operations while

FREEZE = 1 will fail with P_ERR in SR1 set to 1.

8.1.3

Infineon programmed random number

Infineon standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF)

with a 128-bit random number using the Linear Congruential Random Number Method. The seed value for the

algorithm is a random number concatenated with the day and time of tester insertion.

8.1.4

Lock bytes

The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest

address region related to the byte. The next higher address byte similarly protects the next higher 8 regions. The

LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest address region. In other

words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the lowest address region from

further programming. See “OTP address space” on page 49.

8.2

Write enable command

The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The

WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during

power-up, hardware reset, or after the device completes the following commands:

• Reset

• Page Program (PP)

• Sector Erase (SE)

• Bulk Erase (BE)

• Write Disable (WRDI)

• Write Registers (WRR)

• Quad-input Page Programming (QPP)

• OTP Byte Programming (OTPP)

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Data protection

8.3

Block protection

The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register

TBPROT bit can be used to protect an address range of the main flash array from program and erase operations.

The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range

is selected by the TBPROT bit of the configuration register.

Table 38

Upper array start of protection (TBPROT = 0)

Status Register Content

Protected Memory (kbytes)

Protected Fraction of Memory

FL512S

512 Mb

Array

BP2

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

Upper 64th

Upper 32nd

Upper 16th

Upper 8th

Upper 4th

Upper Half

All Sectors

1024

2048

4096

8192

16384

32768

65536

Table 39

Lower array start of protection (TBPROT = 1)

Status Register Content

Protected Memory (kbytes)

Protected Fraction of Memory

FL512S

512 Mb

Array

BP2

BP1

BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

0

Lower 64th

Lower 32nd

Lower 16th

Lower 8th

Lower 4th

Lower Half

All Sectors

1024

2048

4096

8192

16384

32768

65536

When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used

to protect sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection

are used on the same sector the logical OR of ASP and Block Protection related to the sector is used. Recommen-

dation: ASP and Block Protection should not be used concurrently. Use one or the other, but not both.

8.3.1

Freeze bit

Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and

the TBPROT bit in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once the FREEZE

bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the

FREEZE bit is cleared to logic 0 the status register BP bits and the TBPROT bit of the Configuration Register are

writable. The FREEZE bit also protects the entire OTP memory space from programming when set to 1. Any

attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no error status is set.

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8.3.2

Write protect signal

The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide hardware

input signal controlled protection. When WP# is Low and SRWD is set to 1 the Status and Configuration register

is protected from alteration. This prevents disabling or changing the protection defined by the Block Protect bits.

8.4

Advanced sector protection

Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods

used to disable or enable programming or erase operations, individually, in any or all sectors. An overview of

these methods is shown in Figure 42.

Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each

sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. Refer to “Block

protection” on page 63 for full details of the BP2-0 bits.

ASP Register

One Time Programmable

Password Method Persistent Method

(ASPR[2]=0)

(ASPR[1]=0)

6.) Password Method requires a

password to set PPB Lock to “1”

to enable program or erase of

PPB bits

7.) Persistent Method only allows

PPB Lock to be cleared to “0” to

prevent program or erase of PPB

bits. Power off or hardware reset

required to set PPB Lock to “1”

64-

bit Password

(One Time Protect)

4.) PPB Lock bit is volatile and

defaults to “1” (persistent

mode).or “0” (password mode)

upon reset

PBB Lock Bit

“0” = PPBs locked

“1”=PPBs unlocked

5.) PPB Lock = “0” locks all PPBs

to their current state

Persistent

Protection Bits

(PPB)

Dynamic

Protection Bits

(DYB)

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

PPB 1

PPB 2

DYB 0

DYB 1

DYB 2

Sector N-2

Sector N-1

Sector N

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

3.) DYB are volatile bits

1.) N = Highest Address Sector,

a sector is protected if its PPB =”0”

or its DYB = “0”

PPB are programmed individually

but erased as a group

2.)

Figure 42

Advanced sector protection overview

Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When

either bit is 0, the sector is protected from program and erase operations.

The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for

managing the state of the PPB Lock bit, Persistent Protection and Password Protection.

The Persistent Protection method sets the PPB Lock bit to 1 during POR, or Hardware Reset so that the PPB bits

are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB. There is

no command in the Persistent Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will

remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows boot code the

option of changing sector protection by programming or erasing the PPB, then protecting the PPB from further

change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This is sometimes called

Boot-code controlled sector protection.

The Password method clears the PPB Lock bit to 0 during POR, or Hardware Reset to protect the PPB. A 64-bit

password may be permanently programmed and hidden for the password method. A command can be used to

provide a password for comparison with the hidden password. If the password matches, the PPB Lock bit is set

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to 1 to unprotect the PPB. A command can be used to clear the PPB Lock bit to 0. This method requires use of a

password to control PPB protection.

The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so

as to permanently select the method used.

8.4.1

ASP register

The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features.

See Table 31.

As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unpro-

tected, when power is applied. The device programmer or host system must then choose which sector protection

method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits, locks the part

permanently in the selected mode:

• ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.

• ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.

• ASPR[2:1] = 01 = Password Protection Mode permanently selected.

• ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure.

ASP register programming rules:

• If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock

Bits.

• Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from

programming and no further changes to the ASP register is allowed.

The programming time of the ASP Register is the same as the typical page programming time. The system can

determine the status of the ASP register programming operation by reading the WIP bit in the Status Register.

See “Status register 1 (SR1)” on page 51 for information on WIP.

After selecting a sector protection method, each sector can operate in each of the following states:

• Dynamically Locked — A sector is protected and can be changed by a simple command.

• Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is 0.

• Unlocked — The sector is unprotected and can be changed by a simple command.

8.4.2

Persistent protection bits

The Persistent Protection Bits (PPB) are located in a separate non-volatile flash array. One of the PPB bits is

related to each sector. When a PPB is 0, its related sector is protected from program and erase operations. The

PPB are programmed individually but must be erased as a group, similar to the way individual words may be

programmed in the main array but an entire sector must be erased at the same time. The PPB have the same

program and erase endurance as the main flash memory array. Preprogramming and verification prior to erasure

are handled by the device.

Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector

erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status register.

Reading of a PPB bit requires the initial access time of the device.

Notes:

Each PPB is individually programmed to 0 and all are erased to 1 in parallel.

If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming

or erasing the PPB.

The state of the PPB for a given sector can be verified by using the PPB Read command.

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8.4.3

Dynamic protection bits

Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only

control the protection for sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is cleared

to 0 or set to 1, thus placing each sector in the protected or unprotected state respectively. This feature allows

software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of

protection when changes are needed. The DYBs can be set or cleared as often as needed as they are volatile bits.

8.4.4

PPB lock bit (PPBL[0])

The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs and when set to

1, it allows the PPBs to be changed.

The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only after all

the PPBs are configured to the desired settings.

In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0, no

software command sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the

PPB Lock bit.

In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB Lock

bit can only be set to 1 by the Password Unlock command.

8.4.5

Sector protection states summary

Each sector can be in one of the following protection states:

• Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection

state defaults to unprotected after a power cycle, software reset, or hardware reset.

• Dynamically Locked — A sector is protected and protection can be changed by a simple command. The

protection state is not saved across a power cycle or reset.

• Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to 1.

The protection state is non-volatile and saved across a power cycle or reset. Changing the protection state

requires programming and or erase of the PPB bits

Table 40

Sector protection states

Protection bit values

PPB lock PPB

Sector state

DYB

1

0

1

0

1

0

Unprotected – PPB and DYB are changeable

Protected – PPB and DYB are changeable

0

1

0

1

0

1

0

Protected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB not changeable, DYB is changeable

8.4.6

Persistent protection mode

The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits

are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR

command can clear the PPB Lock bit to 0 to protect the PPB. There is no command to set the PPB Lock bit

therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.

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8.4.7

Password protection mode

Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by

requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password requirement, after power

up and hardware reset, the PPB Lock bit is cleared to 0 to ensure protection at power-up. Successful execution

of the Password Unlock command by entering the entire password clears the PPB Lock bit, allowing for sector

PPB modifications.

Password Protection Notes:

• Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to prevent

reading the password.

• The Password Program Command is only capable of programming ‘0’s. Programming a 1 after a cell is

programmed as a 0 results in the cell left as a 0 with no programming error set.

• The password is all 1’s when shipped from Infineon. It is located in its own memory space and is accessible

through the use of the Password Program and Password Read commands.

• All 64-bit password combinations are valid as a password.

• The Password Mode, once programmed, prevents reading the 64-bit password and further password

programming. All further program and read commands to the password region are disabled and these

commands are ignored. There is no means to verify what the password is after the Password Mode Lock Bit is

selected. Password verification is only allowed before selecting the Password Protection mode.

• The Protection Mode Lock Bits are not erasable.

• The exact password must be entered in order for the unlocking function to occur. If the password unlock

command provided password does not match the hidden internal password, the unlock operation fails in the

same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the WIP Bit

remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the

lack of a valid password.

• The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it

take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an

attempt to correctly match a password. The Read Status Register 1 command may be used to read the WIP bit

to determine when the device has completed the password unlock command or is ready to accept a new

password command. When a valid password is provided the password unlock command does not insert the

100 µs delay before returning the WIP bit to zero.

• If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.

• ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced

to the boot sector address. ECC status is shown in that sector while read protection mode is active.

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Commands

9

Commands

All communication between the host system and the S25FL512S memory device is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be

performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred serially

between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to

the host serially on SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be

returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or,

four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1

or, four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Commands are structured as follows:

• Each command begins with an eight bit (byte) instruction.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.

• The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data infor-

mation to be done one, two, or four bits in parallel. This enables a trade off between the number of signal

connections (IO bus width) and the speed of information transfer. If the host system can support a two or four

bit wide IO bus the memory performance can be increased by using the instructions that provide parallel two

bit (dual) or parallel four bit (quad) transfers.

• The width of all transfers following the instruction are determined by the instruction sent.

• All sIngle bits or parallel bit groups are transferred in most to least significant bit order.

• Some instructions send instruction modifier (mode) bits following the address to indicate that the next

command will be of the same type with an implied, rather than an explicit, instruction. The next command thus

does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send

each command when the same command type is repeated in a sequence of commands.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Read latency may be zero to several SCK cycles (also referred to as dummy cycles).

• All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted

into the device with the most significant byte first. All data is transferred with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions. While a program, erase, or write operation is in progress, it is recommended to check that the

Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to ensure the new command can

be accepted.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

• Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces

of the host system and the memory device generally handle the details of signal relationships and timing. For

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Commands

this reason, signal relationships and timing are not covered in detail within this software interface focused

section of the document. Instead, the focus is on the logical sequence of bits transferred in each command

rather than the signal timing and relationships. Following are some general signal relationship descriptions to

keep in mind. For additional information on the bit level format and signal timing relationships of commands,

see “Command protocol” on page 17.

- The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide

transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately

drive the IO0-IO3 signals during Dual and Quad transfers.

- All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK.

CS# is kept low throughout a command and when CS# is returned high the command ends. Generally, CS#

remains low for eight bit transfer multiples to transfer byte granularity information. Some commands will not

be accepted if CS# is returned high not at an 8 bit boundary.

9.1

Command set summary

Extended addressing

9.1.1

To accommodate addressing above 128 Mb, there are three options:

1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.

Instruction name

4FAST_READ

4READ

Description

Read Fast (4-byte Address)

Read (4-byte Address)

Code (Hex)

0C

13

3C

6C

BC

EC

0E

BE

4DOR

4QOR

4DIOR

4QIOR

4DDRFR

4DDRDIOR

Read Dual Out (4-byte Address)

Read Quad Out (4-byte Address)

Dual I/O Read (4-byte Address)

Quad I/O Read (4-byte Address)

Read DDR Fast (4-byte Address)

DDR Dual I/O Read (4-byte

Address)

4DDRQIOR

DDR Quad I/O Read (4-byte

Address)

EE

4PP

4QPP

Page Program (4-byte Address)

Quad Page Program (4-byte

Address)

12

34

4SE

Erase 256 kB (4-byte Address)

DC

2. For backward compatibility to the 3-byte address instructions, the standard instructions can be used in

conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0

(following power up and hardware reset), to enable 3-byte (24-bit) addressing. When set to 1, the legacy

commands are changed to require 4 bytes (32 bits) for the address field. The following instructions can be used

in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes of address field.

Instruction name

READ

Description

Read (3-byte Address)

Read Fast (3-byte Address)

Read Dual Out (3-byte Address)

Read Quad Out (3-byte Address)

Code (Hex)

03

0B

3B

6B

FAST_READ

DOR

QOR

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Commands

Instruction name

Description

Code (Hex)

DIOR

QIOR

DDRFR

DDRDIOR

Dual I/O Read (3-byte Address)

Quad I/O Read (3-byte Address)

Read DDR Fast (3-byte Address)

BB

EB

0D

BD

DDR Dual I/O Read (3-byte

Address)

DDRQIOR

DDR Quad I/O Read (3-byte

Address)

ED

PP

QPP

Page Program (3-byte Address)

Quad Page Program (3-byte

Address)

02

32

SE

Erase 256 kB (3-byte Address)

D8

3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction

with the Bank Address Register:

a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory, The standard

3-byte address selects an address within the bank selected by the Bank Address Register.

i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of memory.

ii. This applies to read, erase, and program commands.

b. The Bank Register provides the high order (4th) byte of address, which is used to address the available

memory at addresses greater than 16 Mbytes.

c. Bank Register bits are volatile.

i. On power up, the default is Bank0 (the lowest address 16 Mbytes).

d. For Read, the device will continuously transfer out data until the end of the array.

i. There is no bank to bank delay.

ii. The Bank Address Register is not updated.

iii. The Bank Address Register value is used only for the initial address of an access.

Table 41

Bank address map

Bank Address Register Bits

Bank

Memory Array Address Range (Hex)

Bit 1

Bit 0

0

1

0

1

0

1

0

1

2

3

00000000

01000000

02000000

03000000

00FFFFFF

01FFFFFF

02FFFFFF

03FFFFFF

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Commands

Table 42

Function

S25FL512S command set (sorted by function)

Maximum

frequency

(MHz)

Command

name

Instruction

value (Hex)

Command description

Read Device READ_ID

Read Electronic Manufacturer Signature

90

133

Identifi-

cation

(REMS)

RDID

Read ID (JEDEC Manufacturer ID and JEDEC CFI)

Read Electronic Signature

Read Serial Flash Discoverable Parameters

Read Status Register-1

9F

AB

5A

05

07

35

01

04

06

30

18

14

133

50

RES

RSFDP

RDSR1

RDSR2

RDCR

WRR

133

Register

Access

Read Status Register-2

Read Configuration Register-1

Write Register (Status-1, Configuration-1)

Write Disable

Write Enable

Clear Status Register-1 - Erase/Prog. Fail Reset

ECC Read (4-byte address

WRDI

WREN

CLSR

ECCRD

ABRD

AutoBoot Register Read

133

(QUAD=0)

104

(QUAD=1)

ABWR

BRRD

BRWR

BRAC

AutoBoot Register Write

Bank Register Read

Bank Register Write

Bank Register Access

(Legacy Command formerly used for Deep Power

Down)

15

16

17

B9

133

DLPRD

PNVDLR

WVDLR

Data Learning Pattern Read

Program NV Data Learning Register

Write Volatile Data Learning Register

41

43

4A

133

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Commands

Table 42

Function

S25FL512S command set (sorted by function) ^(continued)

Maximum

frequency

(MHz)

Command

name

Instruction

value (Hex)

Command description

Read Flash

Array

READ

4READ

Read (3- or 4-byte address)

Read (4-byte address)

03

13

0B

0C

0D

0E

3B

3C

6B

6C

BB

BC

BD

BE

EB

EC

ED

EE

02

12

32

38

50

133

80

FAST_READ Fast Read (3- or 4-byte address)

4FAST_READ Fast Read (4-byte address)

DDRFR

4DDRFR

DOR

DDR Fast Read (3- or 4-byte address)

DDR Fast Read (4-byte address)

Read Dual Out (3- or 4-byte address)

Read Dual Out (4-byte address)

Read Quad Out (3- or 4-byte address)

Read Quad Out (4-byte address)

Dual I/O Read (3- or 4-byte address)

Dual I/O Read (4-byte address)

DDR Dual I/O Read (3- or 4-byte address)

DDR Dual I/O Read (4-byte address)

Quad I/O Read (3- or 4-byte address)

Quad I/O Read (4-byte address)

DDR Quad I/O Read (3- or 4-byte address)

DDR Quad I/O Read (4-byte address)

Page Program (3- or 4-byte address)

Page Program (4-byte address)

80

104

80

4DOR

QOR

4QOR

DIOR

4DIOR

DDRDIOR

4DDRDIOR

QIOR

4QIOR

DDRQIOR

4DDRQIOR

PP

80

104

80

Program

Flash Array

133

80

4PP

QPP

Quad Page Program (3- or 4-byte address)

Quad Page Program - Alternate instruction (3- or

4-byte address)

80

4QPP

PGSP

PGRS

Quad Page Program (4-byte address)

Program Suspend

Program Resume

34

85

8A

60

C7

D8

DC

75

7A

42

4B

80

133

Erase Flash BE

Bulk Erase

Array

BE

SE

4SE

ERSP

ERRS

OTPP

OTPR

Bulk Erase (alternate command)

Erase 256 kB (3- or 4-byte address)

Erase 256 kB (4-byte address)

Erase Suspend

Erase Resume

OTP Program

One Time

Program

Array

OTP Read

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Commands

Table 42

Function

S25FL512S command set (sorted by function) ^(continued)

Maximum

frequency

(MHz)

Command

name

Instruction

value (Hex)

Command description

Advanced

Sector

DYBRD

DYBWR

PPBRD

PPBP

PPBE

ASPRD

ASPP

PLBRD

PLBWR

PASSRD

PASSP

PASSU

RESET

MBR

DYB Read

DYB Write

PPB Read

PPB Program

PPB Erase

ASP Read

ASP Program

PPB Lock Bit Read

PPB Lock Bit Write

Password Read

Password Program

Password Unlock

Software Reset

Mode Bit Reset

Reserved for Multi-I/O-High Perf Mode (MPM)

E0

E1

E2

E3

E4

2B

2F

A7

A6

E7

E8

E9

F0

FF

A3

133

Protection

Reset

Reserved for MPM

Future Use

RFU

Reserved-18 Reserved

Reserved-E5 Reserved

Reserved-E6 Reserved

18

E5

E6

9.1.2

Read device identification

There are multiple commands to read information about the device manufacturer, device type, and device

features. SPI memories from different vendors have used different commands and formats for reading infor-

mation about the memories. The S25FL512S device supports the three most common device information

commands.

9.1.3

Register read or write

There are multiple registers for reporting embedded operation status or controlling device configuration

options. There are commands for reading or writing these registers. Registers contain both volatile and

non-volatile bits. Non-volatile bits in registers are automatically erased and programmed as a single (write)

operation.

9.1.3.1

Monitoring operation status

The host system can determine when a write, program, erase, suspend or other embedded operation is complete

by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command

provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register

indicate whether the most recent program or erase command has not completed successfully. When P_ERR or

E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy. Under this

condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid commands. A Clear

Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby

state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or

Software Reset (RESET) may be used to return the device to standby state.

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9.1.3.2

Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing,

interface address length, and some aspects of data protection.

9.1.4

Read flash array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incre-

mentally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte address

reaches the maximum address of the memory array, the read will continue at address zero of the array.

There are several different read commands to specify different access latency and data path widths. Double Data

Rate (DDR) commands also define the address and data bit relationship to both SCK edges:

• The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning

a single bit per SCK falling edge on the SO signal. This command has zero latency between the address and the

returning data but is limited to a maximum SCK rate of 50 MHz.

• Other read commands have a latency period between the address and returning data but can operate at higher

SCK frequencies. The latency depends on the configuration register latency code.

• The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data

returning a single bit per SCK falling edge on the SO signal and may operate up to 133 MHz.

• Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0 signal with

read data returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.

• Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data

returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.

• Fast (Single), Dual, or Quad Double Data Rate read commands provide address one bit, two bits or four bits per

every SCK edge with read data returning one bit, two bits, or four bits of data per every SCK edge on the IO0-IO3

signals. Double Data Rate (DDR) operation is only supported for core and I/O voltages of 3 to 3.6V.

9.1.5

Program flash array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page

Program command accepts from 1 byte up to 512 consecutive bytes of data (page) to be programmed in one

operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing bits from

0 to 1 requires an erase operation.

9.1.6

Erase flash array

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1.

A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually

programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.

9.1.7

OTP, block protection, and advanced sector protection

There are commands to read and program a separate One Time Programmable (OTP) array for permanent data

such as a serial number. There are commands to control a contiguous group (block) of flash memory array sectors

that are protected from program and erase operations. There are commands to control which individual flash

memory array sectors are protected from program and erase operations.

9.1.8

Reset

There is a command to reset to the default conditions present after power on to the device. There is a command

to reset (exit from) the Enhanced Performance Read Modes.

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9.1.9

Reserved

Some instructions are reserved for future use. In this generation of the S25FL512S some of these command

instructions may be unused and not affect device operation, some may have undefined results.

Some commands are reserved to ensure that a legacy or alternate source device command is allowed without

affect. This allows legacy software to issue some commands that are not relevant for the current generation

S25FL512S device with the assurance these commands do not cause some unexpected action.

Some commands are reserved for use in special versions of the FL-S not addressed by this document or for a

future generation. This allows new host memory controller designs to plan the flexibility to issue these command

instructions. The command format is defined if known at the time this document revision is published.

9.2

Identification commands

9.2.1

Read identification - REMS (Read_ID or REMS 90h)

The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also referred to

as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The command is initiated by shifting on SI the instruction code “90h” followed by a 24-bit address of 00000h.

Following this, the Manufacturer ID and the Device ID are shifted out on SO starting at the falling edge of SCK after

address. The Manufacturer ID and the Device ID are always shifted out with the MSB first. If the 24-bit address is

set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and

Device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition

on CS# input. The maximum clock frequency for the READ_ID command is

133 MHz.

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 23

Instruction (90h)

1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Manufacturer ID Device ID

Address

Figure 43

Table 43

READ_ID (90h) command sequence

Read_ID values

Device

S25FL512S

Manufacturer ID (hex)

Device ID (hex)

19

01

9.2.2

Read identification (RDID 9Fh)

The Read Identification (RDID) command provides read access to manufacturer identification, device identifi-

cation, and Common Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The

CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by Infineon.

The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a

vendor-specified software flash management program (driver) to be used for entire families of flash devices.

Software support can then be device-independent, JEDEC manufacturer ID independent, forward and

backward-compatible for the specified flash device families. System vendors can standardize their flash drivers

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for long-term software compatibility by using the CFI values to configure a family driver from the CFI information

of the device in use.

Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on

execution of the program, erase, or write cycle that is in progress.

The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of

manufacturer identification, two bytes of device identification, extended device identification, and CFI infor-

mation will be shifted sequentially out on SO. As a whole this information is referred to as ID-CFI. See “ID-CFI

address space” on page 48 for the detail description of the ID-CFI contents.

Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The

RDID command sequence is terminated by driving CS# to the logic high state anytime during data output.

The maximum clock frequency for the RDID command is 133 MHz.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Data 1

Data N

Figure 44

Read identification (RDID 9Fh) command sequence

9.2.3

Read electronic signature (RES) (ABh):

The RES command is used to read a single byte Electronic Signature from SO. RES is only supported for backward

compatibility and should not be used for new software designs. New software designs should instead make use

of the RDID command.

The RES instruction is shifted in followed by three dummy bytes onto SI. After the last bit of the three dummy

bytes are shifted into the device, a byte of Electronic Signature will be shifted out of SO. Each bit is shifted out by

the falling edge of SCK. The maximum clock frequency for the RES command is 50 MHz.

The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles.

The RES command sequence is terminated by driving CS# to the logic high state anytime during data output.

CS#

SCK

SI

SO

7 6 5 4 3 2 1 0 23

Instruction (ABh)

1 0

7 6 5 4 3 2 1 0

Device ID

Phase

Dummy

Figure 45

Table 44

Read electronic signature (RES ABh) command sequence

RES values

Device

Device ID (hex)

S25FL512S

19

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9.2.4

Read serial flash discoverable parameters (RSFDP 5Ah)

The command is initiated by shifting on SI the instruction code ‘5Ah’, followed by a 24-bit address of 000000h,

followed by eight dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK

after the eight dummy cycles. The SFDP bytes are always shifted out with the MSB first. If the 24-bit address is set

to any other value, the selected location in the SFDP space is the starting point of the data read. This enables

random access to any parameter in the SFDP space. The maximum clock frequency for the RSFDP command is

133 MHz.

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 23

1 0

Address

7 6 5 4

3

2 1 0

Instruction

Dummy Cycles

Data 1

Figure 46

RSFDP command sequence

9.3

Register access commands

Read status register-1 (RDSR1 05h):

9.3.1

The Read Status Register-1 (RDSR1) command allows the Status Register-1 contents to be read from SO. The

Status Register-1 contents may be read at any time, even while a program, erase, or write operation is in progress.

It is possible to read the Status Register-1 continuously by providing multiples of eight clock cycles. The status is

updated for each eight cycle read. The maximum clock frequency for the RDSR1 (05h) command is 133 MHz.

CS#

SCK

SI

SO

7 6 5 4 3 2 1 0

Instruction

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Status Updated Status

Phase

Figure 47

Read status register-1 (RDSR1 05h) command sequence

9.3.2

Read status register-2 (RDSR2 07h):

The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. The Status

Register-2 contents may be read at any time, even while a program, erase, or write operation is in progress. It is

possible to read the Status Register-2 continuously by providing multiples of eight clock cycles. The status is

updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is 133 MHz.

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CS#

SCK

SI

SO

7 6 5 4 3 2 1 0

Instruction

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Status Updated Status

Phase

Figure 48

Read status register-2 (RDSR2 07h) command sequence

9.3.3

Read configuration register (RDCR 35h)

The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read from

SO. It is possible to read the Configuration Register continuously by providing multiples of eight clock cycles. The

Configuration Register contents may be read at any time, even while a program, erase, or write operation is in

progress.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Register Read

Repeat Register Read

Figure 49

Read configuration register (RDCR 35h) command sequence

9.3.4

Bank register read (BRRD 16h)

The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The

instruction is first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the

Bank Register continuously by providing multiples of eight clock cycles. The maximum operating clock frequency

for the BRRD command is 133 MHz.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Instruction

Register Read

Repeat Register Read

Phase

Figure 50

Read bank register (BRRD 16h) command

9.3.5

Bank register write (BRWR 17h)

The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address Register

(BAR). The command is also used to write the Extended address control bit (EXTADD) that is also in BAR[7]. BAR

provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes), when using 3-byte

address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of

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the addressing method and is not changing data in the flash memory, this command does not require the WREN

command to precede it.

The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length.

The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration Registers.

Any bank address bit reserved for the future should always be written as a 0.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Data

Figure 51

Bank register write (BRWR 17h) command

9.3.6

Bank register access (BRAC B9h)

The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but they are

both commands that are not present in legacy SPI memory devices. Host system SPI memory controller inter-

faces may not be able to easily support such new commands. The Bank Register Access (BRAC) command uses

the same command code and format as the Deep Power Down (DPD) command that is available in legacy SPI

memories. The FL-S family does not support a DPD feature but assigns this legacy command code to the BRAC

command to enable write access to the Bank Address Register for legacy systems that are able to send the legacy

DPD (B9h) command.

When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write

Register (WRR) command as a write to the lower address bits of the BAR. A WREN command is not used between

the BRAC and WRR commands. Only the lower two bits of the first data byte following the WRR command code

are used to load BAR[1:0]. The upper bits of that byte and the content of the optional WRR command second data

byte are ignored. Following the WRR command the access to BAR is closed and the device interface returns to the

standby state. The combined BRAC followed by WRR command sequence has no affect on the value of the ExtAdd

bit (BAR[7]).

Commands other than WRR may immediately follow BRAC and execute normally. However, any command other

than WRR, or any other sequence in which CS# goes low and returns high, following a BRAC command, will close

the access to BAR and return to the normal interpretation of a WRR command as a write to Status Register-1 and

the Configuration Register.

The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase suspend

states. This command sequence is illegal when the device is performing an embedded algorithm or when the

program (P_ERR) or erase (E_ERR) status bits are set to 1.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 52

BRAC (B9h) command sequence

9.3.7

Write registers (WRR 01h):

The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configu-

ration Register. Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN)

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command must be received. After the Write Enable (WREN) command has been decoded successfully, the device

will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The Status

Register is one data byte in length.

The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation.

Any Status or Configuration Register bit reserved for the future must be written as a 0.

CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the

Write Registers (WRR) command is not executed. If CS# is driven high after the eighth cycle then only the Status

Register-1 is written; otherwise, after the sixteenth cycle both the Status and Configuration Registers are written.

When the configuration register QUAD bit CR[1] is 1, only the WRR command format with 16 data bits may be used.

As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While

the Write Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed Write Registers (WRR)

operation, and is a 0 when it is completed. When the Write Registers (WRR) operation is completed, the Write

Enable Latch (WEL) is set to a 0. The WRR command must be executed under continuous power. The maximum

clock frequency for the WRR command is 133 MHz.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Status Register-1

Figure 53

Write registers (WRR 01h) command sequence – 8 data bits

CS#

SCK

SI

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Figure 54

Write registers (WRR 01h) command sequence – 16 data bits

The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and

BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR) command also

allows the user to set the Status Register Write Disable (SRWD) bit to a 1 or a 0. The Status Register Write Disable

(SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.

When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is

possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to the logic high

or logic low state.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be

considered, depending on the state of Write Protect (WP#):

• If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration

Registers provided that the Write Enable Latch (WEL) bit has previously been set to a “1” by initiating a Write

Enable (WREN) command.

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• If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and Config-

uration Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write Enable (WREN)

command. Attempts to write to the Status and Configuration Registers are rejected, and are not accepted for

execution. As a consequence, all the data bytes in the memory area that are protected by the Block Protect

(BP2, BP1, BP0) bits of the Status Register, are also hardware protected by WP#.

The WP# hardware protection can be provided:

• by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic low

state;

• or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable

(SRWD) bit to a 1.

The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state.

If WP# is permanently tied high, hardware protection of the BP bits can never be activated.

Table 45

WP#

Block protection modes

Memory content

SRWD

Mode

Write protection of registers

Unprotected

bit

Protected area

area

1

0

1

0

Software Status and Configuration Registers are

Protected

Ready to accept

Page Program,

Protected Writable (if WREN command has set the against Page

WEL bit). The values in the SRWD, BP2, Program, Quad Quad Input

BP1, and BP0 bits and those in the

Input Program, Program and

Configuration Register can be changed Sector Erase, and Sector Erase

Bulk Erase

Protected

commands

Ready to accept

Page Program or

0

1

Hardware Status and Configuration Registers are

Protected Hardware Write Protected. The values in against Page

the SRWD, BP2, BP1, and BP0 bits and

those in the Configuration Register

cannot be changed

Program, Sector Erase commands

Erase, and Bulk

Erase

The WRR command has an alternate function of loading the Bank Address Register if the command immediately

follows a BRAC command. See “Bank register access (BRAC B9h)” on page 79.

Notes

41.The Status Register originally shows 00h when the device is first shipped from Infineon to the customer.

42.Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP#

becomes IO2; therefore, it cannot be utilized.

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Commands

9.3.8

Write enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1[1]) to a 1.

The Write Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to enable write,

program and erase commands.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI.

Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on

SI, the write enable operation will not be executed.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 55

Write enable (WREN 06h) command sequence

9.3.9

Write disable (WRDI 04h)

The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register-1 (SR1[1]) to a 0.

The Write Enable Latch (WEL) bit may be set to a 0 by issuing the Write Disable (WRDI) command to disable Page

Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR), OTP Program (OTPP), and other

commands, that require WEL be set to 1 for execution. The WRDI command can be used by the user to protect

memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The WRDI

command is ignored during an embedded operation while WIP bit =1.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI.

Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on

SI, the write disable operation will not be executed.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 56

Write disable (WRDI 04h) command sequence

9.3.10

Clear status register (CLSR 30h)

The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It is not

necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will be accepted

even when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set.

The WEL bit will be unchanged after this command is executed.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 57

Clear status register (CLSR 30h) command sequence

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9.3.11

ECC status register read (ECCRD 18h)

To read the ECC Status Register, the command is followed by the ECC unit (16 Bytes) address, the four least

significant bits (LSB) of address must be set to zero. This is followed by the number of dummy cycles selected by

the read latency value in CR2V[3:0]. Then the 8-bit contents of the ECC Register, for the ECC unit selected, are

shifted out on SO 16 times, once for each byte in the ECC Unit. If CS# remains low the next ECC unit status is sent

through SO/IO1 16 times, once for each byte in the ECC Unit, this continues until CS# goes high. The maximum

operating clock frequency for the ECC READ command is 133 MHz. See “Automatic ECC” on page 101 for details

on ECC unit.

CS#

0

7

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCK

32-Bit

Instruction

Dummy Byte

Address

SI

6

5

4

3

2

1

0

31 30 29

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 1

DATA OUT 2

High Impedance

SO

7

6

5

4

3

2

1

0

7

MSB

Figure 58

ECC status register read command sequence

9.3.12

AutoBoot

SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And,

in order to read boot code from an SPI device, the host memory controller or processor must supply the read

command from a hardwired state machine or from some host processor internal ROM code.

Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to

start reading boot code.

The AutoBoot feature allows the host memory controller to take boot code from an S25FL512S device immedi-

ately after the end of reset, without having to send a read command. This saves 32 or more cycles and simplifies

the logic needed to initiate the reading of boot code.

• As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically

starts a read access from a pre-specified address. At the time the reset process is completed, the device is ready

to deliver code from the starting address. The host memory controller only needs to drive CS# signal from high

to low and begin toggling the SCK signal. The S25FL512S device will delay code output for a pre-specified

number of clock cycles before code streams out.

- The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by

the host.

- The host cannot send commands during this time.

- If ABSD = 0, the maximum SCK frequency is 50 MHz.

- If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the QUAD bit is

set to 1.

• The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address

(ABSA) field of the AutoBoot Register which specifies a 512 byte boundary aligned location; the default address

is 00000000h.

- Data will continuously shift out until CS# returns high.

• At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to standard

SPI mode; able to accept normal command operations.

- A minimum of one byte must be transferred.

- AutoBoot mode will not initiate again until another power cycle or a reset occurs.

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• An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.

The AutoBoot register bits are non-volatile and provide:

- The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the ABSA field

is 23 bits for devices up to 32-Gbit.

- The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.

- The AutoBoot Enable.

If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the same

manner as a Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same manner as a

Read command.

CS#

SCK

SI

SO

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Wait States (ABSD)

Data 1

Data N

Phase

Figure 59

AutoBoot sequence (CR1[1]=0)

CS#

SCK

IO0

IO1

4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

IO2

IO3

Phase

Data 1 Data 2 Data 3 Data 4 Data 5

...

Wait States (ABSD)

Figure 60

AutoBoot sequence (CR1[1]=1)

9.3.13

AutoBoot register read (ABRD 14h)

The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO,

least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register contin-

uously by providing multiples of 32 clock cycles. If the QUAD bit CR1[1] is cleared to 0, the maximum operating

clock frequency for ABRD command is 133 MHz. If the QUAD bit CR1[1] is set to 1, the maximum operating clock

frequency for ABRD command is 104 MHz.

CS#

SCK

SI

SO

7 6 5 4 3 2 1 0

Instruction

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data1 DataN

Phase

Figure 61

AutoBoot register read (ABRD 14h) Command

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9.3.14

AutoBoot register write (ABWR 15h)

Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by

the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,

most significant bit of each byte first. The ABWR data is 32 bits in length.

The ABWR command has status reported in Status Register-1 as both an erase and a programming operation. An

E_ERR or a P_ERR may be set depending on whether the erase or programming phase of updating the register

fails.

CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR command

is not executed. As soon as CS# is driven to the logic high state, the self-timed ABWR operation is initiated. While

the ABWR operation is in progress, Status Register-1 may be read to check the value of the Write-In Progress (WIP)

bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ABWR operation, and is a 0. when it is completed.

When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for

the ABWR command is 133 MHz.

CS#

SCK

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

SO

Phase

Instruction

Input Data 1

Figure 62

AutoBoot register write (ABWR) Command

9.3.15

Program NVDLR (PNVDLR 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command

must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded success-

fully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PNVDLR

command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation is

initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle, and is a 0.

when it is completed. The PNVDLR operation can report a program error in the P_ERR bit of the status register.

When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to a 0 The maximum clock

frequency for the PNVDLR command is 133 MHz.

CS#

SCK

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SO

Phase

Instruction

Input Data

Figure 63

Program NVDLR (PNVDLR 43h) command sequence

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9.3.16

Write VDLR (WVDLR 4Ah)

Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must

be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully,

the device will set the Write Enable Latch (WEL) to enable WVDLR operation.

The WVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WVDLR

command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with

no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Data

Figure 64

Write VDLR (WVDLR 4Ah) command sequence

9.3.17

Data learning pattern read (DLPRD 41h)

The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously

by providing multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command

is 133 MHz.

CS#

SCK

SI

7

6

5

4

3

2

1

0

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Data 1

Data N

Figure 65

DLP Read (DLPRD 41h) command sequence

9.4

Read memory array commands

Read commands for the main flash array provide many options for prior generation SPI compatibility or

enhanced performance SPI:

• Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate

commands (SDR).

• Some SDR commands transfer address one bit per rising edge of SCK and return data 1, 2, or 4 bits of data per

rising edge of SCK. These are called Read or Fast Read for 1-bit data; Dual Output Read for 2-bit data, and Quad

Output for 4-bit data.

• Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual

I/O for 2 bit and Quad I/O for 4 bit.

• Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called

Double Data Rate (DDR) commands.

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• There are DDR commands for 1, 2, or 4 bits of address or data per SCK edge. These are called Fast DDR for 1-bit,

Dual I/O DDR for 2-bit, and Quad I/O DDR for 4-bit per edge transfer.

All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The

instruction is followed by either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address

or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For FL-S devices at

256 Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the

memory array. These device have a bank address register that is used with 3-byte address commands to supply

the high order address bits beyond the address from the host system. The default bank address is zero.

Commands are provided to load and read the bank address register. These devices may also be configured to

take a 4-byte address from the host system with the traditional 3-byte address commands. The 4-byte address

mode for traditional commands is activated by setting the External Address (EXTADD) bit in the bank address

register to 1.

The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent

following the address bits. The mode bits indicate whether the command following the end of the current read

will be another read of the same type, without an instruction at the beginning of the read. These mode bits give

the option to eliminate the instruction cycles when doing a series of Quad I/O read accesses.

A device ordering option provides an enhanced high performance option by adding a similar mode bit scheme

to the DDR Fast Read, Dual I/O, and Dual I/O DDR commands, in addition to the Quad I/O command.

Some commands require delay cycles following the address or mode bits to allow time to access the memory

array. The delay cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus

any data provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high

impedance during the dummy cycles. When MIO commands are used the host must stop driving the IO signals

(outputs are high impedance) before the end of last dummy cycle. When DDR commands are used the host must

not drive the I/O signals during any dummy cycle. The number of dummy cycles varies with the SCK frequency or

performance option selected via the Configuration Register 1 (CR1) Latency Code (LC). Dummy cycles are

measured from SCK falling edge to next SCK falling edge. SPI outputs are traditionally driven to a new value on

the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the memory on the same

falling edge of SCK that the host stops driving address or mode bits.

The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all

data outputs, in the dummy cycles immediately before the start of data. The DLP can help the host memory

controller determine the phase shift from SCK to data edges so that the memory controller can capture data at

the center of the data eye.

When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more dummy cycles

should be selected to allow additional time for the host to stop driving before the memory starts driving data, to

minimize I/O driver conflict. When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more

dummy cycles should be selected to allow 1 cycle of additional time for the host to stop driving before the

memory starts driving the 4 cycle DLP.

Each read command ends when CS# is returned High at any point during data return. CS# must not be returned

High during the mode or dummy cycles before data returns as this may cause mode bits to be captured incor-

rectly; making it indeterminate as to whether the device remains in enhanced high performance read mode.

9.4.1

Read (Read 03h or 4READ 13h)

The instruction

• 03h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• 03h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• 13h is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency

for the READ command is 50 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

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Commands

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 A

Instruction

1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data 1 Data N

Address

Figure 66

Read command sequence (READ 03h or 13h)

9.4.2

Fast read (FAST_READ 0Bh or 4FAST_READ 0Ch):

The instruction

• 0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• 0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• 0Ch is followed by a 4-byte address (A31-A0)

The address is followed by zero or eight dummy cycles depending on the latency code set in the Configuration

Register. The dummy cycles allow the device internal circuits additional time for accessing the initial address

location. During the dummy cycles the data value on SO is “don’t care” and may be high impedance. Then the

memory contents, at the address given, are shifted out on SO.

The maximum operating clock frequency for FAST READ command is 133 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

SI

SO

Phase

7 6 5 4 3 2 1 0 A

1 0

Address

7 6 5 4 3 2 1 0

Data 1

Instruction

Dummy Cycles

Figure 67

Fast read (FAST_READ 0Bh or 0Ch) command sequence with read latency

CS#

SCK

SI

SO

7 6 5 4 3 2 1 0 A

Instruction

1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data 1 Data N

Phase

Address

Figure 68

Fast read command (FAST_READ 0Bh or 0Ch) sequence without read latency

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Commands

9.4.3

Dual output read (DOR 3Bh or 4DOR 3Ch)

The instruction

• 3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• 3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• 3Ch is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO).

Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output Read

commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI before data

begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s internal circuitry

enough time to read from the initial address. During the dummy cycles, the data value on SI is a “don’t care” and

may be high impedance. The number of dummy cycles is determined by the frequency of SCK (refer to Table 25).

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS#

SCK

IO0

IO1

23 22 21

7 6 5 4 3 2 1 0

Instruction

0

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

Address 8 Dummy Cycles

Data 1

Data 2

Figure 69

Dual output read command sequence (3-byte address, 3Bh [ExtAdd=0], LC=10b)

CS#

SCK

IO0

IO1

31 30 29

7 6 5 4 3 2 1 0

Instruction

0

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

Address 8 Dummy Cycles Data1

Data2

Figure 70

Dual output read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd=1, LC=10b])

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Commands

CS#

SCK

IO0

IO1

31 30 29

7 6 5 4 3 2 1 0

Instruction

0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

Address Data1

Data2

Figure 71

Dual output read command sequence (4-byte address, 3Ch or 3Bh [ExtAdd=1, LC=11b])

9.4.4

Quad output read (QOR 6Bh or 4QOR 6Ch)

The instruction

• 6Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• 6Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• 6Ch is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each nibble (4

bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output Read

Mode, there may be dummy cycles required after the last address bit is shifted into SI before data begins shifting

out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to set

up for the initial address. During the dummy cycles, the data value on IO0-IO3 is a “don’t care” and may be high

impedance. The number of dummy cycles is determined by the frequency of SCK (refer to Table 25).

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

The QUAD bit of Configuration Register must be set (CR Bit1=1) to enable the Quad mode capability.

CS#

SCK

IO0

IO1

7 6 5 4 3 2 1 0 A 1 0

4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

D1 D2 D3 D4 D5

IO2

IO3

Phase

Address

Instruction

Dummy

Figure 72

Quad output read (QOR 6Bh or 4QOR 6Ch) command sequence with read latency

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Commands

CS#

SCK

IO0

IO1

IO2

7

6

5

4

3

2

1

0

A

1

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

IO3

7

Instruction

Address

Data 1 Data 2 Data 3 Data 4 Data 5

Phase

...

Figure 73

Quad output read (QOR 6Bh or 4QOR 6Ch) command sequence without read latency

9.4.5

Dual I/O read (DIOR BBh or 4DIOR BCh)

The instruction

• BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• BCh is followed by a 4-byte address (A31-A0)

The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the

Dual Output Read command but takes input of the address two bits per SCK rising edge. In some applications,

the reduced address input time might allow for code execution in place (XIP) i.e. directly from the memory device.

The maximum operating clock frequency for Dual I/O Read is 104 MHz.

For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and SO

before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the latency

code table used for this command, either the High Performance LC (HPLC) table or the Enhanced High Perfor-

mance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each Dual I/O Read command

starts with the 8 bit instruction, followed by address, followed by a latency period.

This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial

address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The

number of dummy cycles is determined by the frequency of SCK (Table 25). The number of dummy cycles is set

by the LC bits in the Configuration Register (CR1).

The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate the 8-bit

instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following

command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8-bit

instruction, followed by address, followed by four cycles of mode bits, followed by a latency period. If the mode

bit pattern is Axh the next command is assumed to be an additional Dual I/O Read command that does not

provide instruction bits. That command starts with address, followed by mode bits, followed by latency.

The Enhanced High Performance feature removes the need for the instruction sequence and greatly improves

code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read

command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the

Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the device remains

in Dual I/O Enhanced High Performance Read Mode and the next address can be entered (after CS# is raised high

and then asserted low) without the BBh or BCh instruction, as shown in “Quad I/O read (QIOR EBh or 4QIOR

ECh):” on page 93; thus, eliminating eight cycles for the command sequence. The following sequences will

release the device from Dual I/O Enhanced High Performance Read mode; after which, the device can accept

standard SPI commands:

1. During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any value other than

Axh, then the next time CS# is raised high the device will be released from Dual

I/O Read Enhanced High Performance Read mode.

During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1) are

not set for a valid instruction sequence, then the device will be released from Dual I/O Enhanced High Perfor-

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Commands

mance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency time to

access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).

It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock.

At higher clock speeds the time available to turn off the host outputs before the memory device begins to drive

(bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention, for the host

system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t care” mode

cycles or during any dummy cycles.

Following the latency period the memory content, at the address given, is shifted out two bits at a time through

IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

CS#

SCK

IO0

IO1

22 20 18

23 21 19

Address

7 6 5 4 3 2 1 0

0

1

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

4 Dummy

Instruction

Data 1

Data 2

Figure 74

Dual I/O read command sequence (3-byte address, BBh [ExtAdd=0], HPLC=00b)

CS#

SCK

IO0

IO1

30 28 26

31 29 27

7 6 5 4 3 2 1 0

Instruction

0

1

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Phase

Address

6 Dummy

Data 1

Data 2

Figure 75

Dual I/O read command sequence (4-byte address, BBh [ExtAdd=1], HPLC=10b)

CS#

SCK

IO0

IO1

7 6 5 4 3 2 1 0 30

31

2 0 6 4 2

3 1 7 5 3

Mode

0

1

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Instruction

Address

Dum

Data 1

Data 2

Phase

Figure 76

Dual I/O read command sequence (4-byte address, BCh or BBh [ExtAdd=1], EHPLC=10b)

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Commands

CS#

SCK

IO0

IO1

6

7

4

5

2

3

0

1

30

31

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

Data N

Address

Mode

Dum

Data 1

Data 2

Phase

Figure 77

Continuous dual I/O read command sequence (4-byte address, BCh or BBh [ExtAdd=1], EH-

PLC=10b)

9.4.6

Quad I/O read (QIOR EBh or 4QIOR ECh):

The instruction

• EBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• ECh is followed by a 4-byte address (A31-A0)

The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad

Output Read command but allows input of the address bits four bits per serial SCK clock. In some applications,

the reduced instruction overhead might allow for code execution (XIP) directly from the S25FL512S device. The

QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad capability of the S25FL512S

device.

The maximum operating clock frequency for Quad I/O Read is 104 MHz.

For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data

begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry

enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3 are “don’t care”

and may be high impedance. The number of dummy cycles is determined by the frequency of SCK and the latency

code table (refer to Table 25). There are different ordering part numbers that select the latency code table used

for this command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC)

table. The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). However, both

latency code tables use the same latency values for the Quad I/O Read command.

Following the latency period, the memory contents at the address given, is shifted out four bits at a time through

IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through

the setting of the Mode bits (after the address sequence, as shown in Figure 78 or Figure 80). This added feature

removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits

7-4) of the Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the

first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal

Axh, then the device remains in Quad I/O High Performance Read Mode and the next address can be entered (after

CS# is raised high and then asserted low) without requiring the EBh or ECh instruction, as shown in Figure 79 or

Figure 81; thus, eliminating eight cycles for the command sequence. The following sequences will release the

device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:

1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next

time CS# is raised high the device will be released from Quad I/O High Performance Read mode.

During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0-IO3) are not

set for a valid instruction sequence, then the device will be released from Quad I/O High Performance Read mode.

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Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal

circuitry latency time to access the initial address after the last address cycle that is clocked into IO0-IO3.

It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out

clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins to

drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal contention,

for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the last “don’t care”

mode cycle or during any dummy cycles.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7

6 5

4

3

2

1 0 20

4

5

6

7

0 4

1 5

2 6

3 7

0

1

2

3

4

5

6

7

0

1

2

3

4 0

5 1

6 2

7 3

D2

4

5

6

7

0

1

2

3

4 0

5 1

6 2

7 3

D4

21

22

23

Instruction

Address

Mode

Dummy

D1

D3

Figure 78

Quad I/O read command sequence (3-byte address, EBh [ExtAdd=0], LC=00b)

CS#

SCK

IO0

IO1

IO2

IO3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

20

21

22

23

4

5

6

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

6

7

4

5

2

3

0

1

7

DN-1

D N

Address

Mode

Dummy

D1

D 2

D 3

D 4

Phase

Figure 79

Continuous quad I/O read command sequence (3-byte address), LC=00b

CS#

SCK

IO0

IO1

IO2

IO3

7

6 5

4

3

2

1 0 28

4

5

6

0 4

1 5

2 6

3 7

0

1

2

3

4

5

6

7

0

1

2

3

4 0

5 1

6 2

7 3

D 2

4

5

6

7

0

1

2

3

4 0

5 1

6 2

7 3

D 4

29

30

31

7

Instruction

Address

Mode

Dummy

D 1

D 3

Phase

Figure 80

Quad I/O read command sequence(4-byte address, ECh or EBh [ExtAdd=1], LC=00b)

CS#

SCK

IO0

IO1

IO2

IO3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

28

29

30

31

4

5

6

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

6

7

4

5

2

3

0

1

7

DN-1

D N

Address

Mode

Dummy

D 1

D 2

D 3

D 4

Phase

Figure 81

Continuous quad I/O read command sequence (4-byte address), LC=00b

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9.4.7

DDR fast read (DDRFR 0Dh, 4DDRFR 0Eh)

The instruction

• 0Dh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• 0Dh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• 0Eh is followed by a 4-byte address (A31-A0)

The DDR Fast Read command improves throughput by transferring address and data on both the falling and

rising edge of SCK. It is similar to the Fast Read command but allows transfer of address and data on every edge

of the clock.

The maximum operating clock frequency for DDR Fast Read command is 80 MHz.

For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI before

data begins shifting out of SO. There are different ordering part numbers that select the latency code table used

for this command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC)

table. The HPLC table does not provide cycles for mode bits so each DDR Fast Read command starts with the 8-bit

instruction, followed by address, followed by a latency period.

This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial

address. During the dummy cycles, the data value on SI is “don’t care” and may be high impedance. The number

of dummy cycles is determined by the frequency of SCK (Table 25). The number of dummy cycles is set by the LC

bits in the Configuration Register (CR1).

Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each clock

edge through SO. Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate the

8-bit instruction after the first DDR Fast Read command sends a mode bit pattern of complementary first and

second Nibbles, e.g. A5h, 5Ah, 0Fh, etc., that indicates the following command will also be a DDR Fast Read

command. The first DDR Fast Read command in a series starts with the 8-bit instruction, followed by address,

followed by four cycles of mode bits, followed by a latency period. If the mode bit pattern is complementary the

next command is assumed to be an additional DDR Fast Read command that does not provide instruction bits.

That command starts with address, followed by mode bits, followed by latency.

When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read instruc-

tions. This is controlled through the setting of the Mode bits (after the address sequence, as shown in Figure 82

and Figure 84. This added feature removes the need for the eight bit SDR instruction sequence to reduce initial

access time (improves XIP performance). The Mode bits control the length of the next DDR Fast Read operation

through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble

(IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) then the next address can be entered (after CS# is

raised high and then asserted low) without requiring the 0Dh or 0Eh instruction, as shown in Figure 83 and

Figure 85, thus, eliminating eight cycles from the command sequence. The following sequences will release the

device from this continuous DDR Fast Read mode; after which, the device can accept standard SPI commands:

1. During the DDR Fast Read Command Sequence, if the Mode bits are not complementary the next time CS# is

raised high the device will be released from the continuous DDR Fast Read mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (SI) are not set

for a valid instruction sequence, then the device will be released from DDR Fast Read mode.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

The HOLD function is not valid during any part of a Fast DDR Command.

Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of

34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4 device, both

IOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover both DC and AC data

transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks)

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followed by a high going transition (001) and the complementary low going transition (110). The two AC transition

scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and

the complementary low going transition (010). The DC transitions will typically occur with a starting point closer

to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many

cases the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the

ending of the data valid period. These transitions will allow the host controller to identify the beginning and

ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be

chosen. See “SPI DDR data learning registers” on page 60 for more details.

CS#

SCK

SI

SO

7

6

5

4

3

2

1

0

2322

0 7 6 5 4 3 2 1 0

7

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Phase

Instruction

Address

Mode

Dummy

Data 1

Data 2

Figure 82

DDR fast read initial access (3-byte address, 0Dh [ExtAdd=0, EHPLC=11b])

CS#

SCK

IO0

23

1

0

7

6

5

4

3

2

1

0

IO1

7

6

5

4

3

2

1

0

7

6

Phase

Address

Mode

Dum

Data 1

D2

Figure 83

Continuous DDR fast read subsequent access (3-byte address [ExtAdd=0, EHPLC=11b])

CS#

SCK

31

SI

SO

7

6

5

4

3

2

1

0

1 0 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6

DLP Data 1 D2

Phase

Instruction

Address

Mode

Figure 84

DDR fast read initial access (4-byte address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b)^[43]

CS#

SCK

SI

SO

31

1 0 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6

DLP Data 1 D2

Address

Mode

Phase

Figure 85

Continuous DDR fast read subsequent access (4-byte address [ExtAdd=1], EHPLC=01b)^[43]

Note

43.Example DLP of 34h (or 00110100).

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

SI

SO

3.

7

6

5

4

3

2

1

0

1 0

7 6 5 4 3 2 1 0 7 6

Data 1 D2

Address

Instruction

Dummy

Phase

Figure 86

DDR fast read subsequent access (4-byte address, HPLC=01b)

9.4.8

DDR dual I/O read (BDh, BEh)

The instruction

• BDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• BDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• BEh is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out, in a DDR fashion, two bits at a time on each clock

edge through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the rising and falling edge of

the SCK signal.

The DDR Dual I/O Read command improves throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar

to the Dual I/O Read command but transfers two address, mode, or data bits on every edge of the clock. In some

applications, the reduced instruction overhead might allow for code execution (XIP) directly from the S25FL512S

device.

The maximum operating clock frequency for DDR Dual I/O Read command is 80 MHz.

For DDR Dual I/O Read commands, there is a latency required after the last address bits are shifted into IO0 and

IO1, before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the

latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced High

Performance LC (EHPLC) table. The number of latency (dummy) clocks is determined by the frequency of SCK

(refer to Table 24 or Table 26). The number of dummy cycles is set by the LC bits in the Configuration Register

(CR1).

The HPLC table does not provide cycles for mode bits so each Dual I/O command starts with the 8 bit instruction,

followed by address, followed by a latency period. This latency period allows the device’s internal circuitry

enough time to access the initial address. During these latency cycles, the data value on SI (IO0) and SO (IO1) are

“don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must

not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the host so that

the memory device can drive the DLP during the dummy cycles.

The EHPLC table does provide cycles for mode bits so a series of Dual I/O DDR commands may eliminate the 8 bit

instruction after the first command sends a complementary mode bit pattern, as shown in Figure 87 and

Figure 89. This added feature removes the need for the eight bit SDR instruction sequence and dramatically

reduces initial access times (improves XIP performance). The Mode bits control the length of the next DDR Dual

I/O Read operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble

(IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to

Continuous DDR Dual I/O Read Mode and the next address can be entered (after CS# is raised high and then

asserted low) without requiring the BDh or BEh instruction, as shown in Figure 88, and thus, eliminating eight

cycles from the command sequence. The following sequences will release the device from Continuous DDR Dual

I/O Read mode; after which, the device can accept standard SPI commands:

1. During the DDR Dual I/O Read Command Sequence, if the Mode bits are not complementary the next time CS#

is raised high and then asserted low the device will be released from DDR Dual I/O Read mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1)

are not set for a valid instruction sequence, then the device will be released from DDR Dual I/O Read mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

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Commands

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. The

HOLD function is not valid during Dual I/O DDR commands.

Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is a

data learning pattern (DLP) that is used by the host controller to optimize data capture at higher frequencies. The

preamble DLP drives the IO bus for the four clock cycles immediately before data is output. The host must be sure

to stop driving the IO bus prior to the time that the memory starts outputting the preamble.

The preamble is intended to give the host controller an indication about the round trip time from when the host

drives a clock edge to when the corresponding data value returns from the memory device. The host controller

will skew the data capture point during the preamble period to optimize timing margins and then use the same

skew time to capture the data during the rest of the read operation. The optimized capture point will be deter-

mined during the preamble period of every read operation. This optimization strategy is intended to compensate

for both the PVT (process, voltage, temperature) of both the memory device and the host controller as well as

any system level delays caused by flight time on the PCB.

Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of

34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4 device, both

SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover both DC and AC

data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half

clocks) followed by a high going transition (001) and the complementary low going transition (110). The two AC

transition scenarios include data low for a short period of time (one half clock) followed by a high going transition

(101) and the complementary low going transition (010). The DC transitions will typically occur with a starting

point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC)

levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC transitions

will bound the ending of the data valid period. These transitions will allow the host controller to identify the

beginning and ending of the valid data eye. Once the data eye has been characterized the optimal data capture

point can be chosen. See “SPI DDR data learning registers” on page 60 for more details.

CS#

SCK

IO0

IO1

7

6

5

4

3

2

1

0

30 28

31 29

0

1

6

7

4

5

2

3

0

1

7 6 5 4

3

2

1 0

6

7

4

5

2

3

0

1

6

7

Phase

Instruction

Address

Mode

Dum

DLP

Data 1

Figure 87

DDR dual I/O read initial access (4-byte address, BEh or BDh [ExtAdd=1], EHPLC= 01b)

CS#

SCK

IO0

IO1

30

31

2

3

0

1

6

7

4

5

2

3

0

1

7

6

4

5

DLP

3

2 1

0

6

7

4

5

2

3

0

1

6

7

Dummy

Address

Mode

Data 1

D2

Phase

Figure 88

Continuous DDR dual I/O read subsequent access (4-byte address, EHPLC= 01b)

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Military 512 Mb (64 MB) FL-S Flash

SPI Multi-I/O, 3.0 V

Commands

CS#

SCK

IO0

IO1

30

31

7

6

5

4

3

2

1

0

2 0

3 1

6 4 2 0 6

7 5 3 1 7

Data 1 D2

Instruction

Address

Dummy

Phase

Figure 89

DDR dual I/O read (4-byte address, BEh or BDh [ExtAdd=1], HPLC=00b)

9.4.9

DDR quad I/O read (EDh, EEh)

The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3. It is similar to the Quad

I/O Read command but allows input of the address four bits on every edge of the clock. In some applications, the

reduced instruction overhead might allow for code execution (XIP) directly from the S25FL512S device. The QUAD

bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad capability.

The instruction

• EDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

• EDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

• EEh is followed by a 4-byte address (A31-A0)

The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR

fashion, with four bits at a time on each clock edge through IO0-IO3.

The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz.

For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the IO0-IO3

signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal

circuitry enough time to access the initial address. During these latency cycles, the data value on IO0-IO3 are

“don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must

not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the host so that

the memory device can drive the DLP during the dummy cycles.

There are different ordering part numbers that select the latency code table used for this command, either the

High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of dummy

cycles is determined by the frequency of SCK (refer to Table 24). The number of dummy cycles is set by the LC

bits in the Configuration Register (CR1).

Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8 bit

instruction after the first command sends a complementary mode bit pattern, as shown in Figure 90 and

Figure 92. This feature removes the need for the eight bit SDR instruction sequence and dramatically reduces

initial access times (improves XIP performance). The Mode bits control the length of the next Read DDR Quad I/O

operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and

lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous

Read DDR Quad I/O Mode and the next address can be entered (after CS# is raised high and then asserted low)

without requiring the EDh or EEh instruction, as shown in Figure 92 and Figure 93 thus, eliminating eight cycles

from the command sequence. The following sequences will release the device from Continuous Read DDR Quad

I/O mode; after which, the device can accept standard SPI commands:

1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS#

is raised high and then asserted low the device will be released from Read DDR Quad I/O mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0, IO1, IO2,

and IO3) are not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O

mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the

next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore

be read out with one single read instruction and address 000000h provided. When the highest address is reached,

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Commands

the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued

indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. The

HOLD function is not valid during Quad I/O DDR commands.

Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a pattern

that is used by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus

for the four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior

to the time that the memory starts outputting the preamble.