S25HL02GTDZBHB050 [INFINEON]
SEMPER™ NOR Flash;
| 型号： | S25HL02GTDZBHB050 |
| 厂家： | 
Infineon |
| 描述： | SEMPER™ NOR Flash |
| 文件： | 总9页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
2-Gb (DDP), 4-Gb (QDP), HS-T (1.8-V),
HL-T (3.0-V) Semper™ Flash with Quad SPI
S25HS02GT / S25HS04GT / S25HL02GT / S25HL04GT 2-Gb (DDP), 4-Gb (QDP), HS-T (1.8-V), HL-T (3.0-V) Semper™ Flash with Quad SPI
Device Overview
Protection Features
Architecture
❐ Legacy Block Protection for memory array and device con-
Cypress 45-nm MirrorBit® technology that stores two data
bits in each memory array cell
figuration
❐ Advanced Sector Protection for individual memory array
sector based protection
Multi-Chip Package (MCP)
❐ 02GT Dual Die Package (DDP) 2 1 Gb die
❐ 04GT Quad Die Package (QDP) 4 1 Gb die
Hardware Reset through CS# Signaling method (JEDEC) /
individual RESET# pin / DQ3_RESET# pin
Sector Architecture options
Identification
❐ Uniform - Address space consists of all 256 KB Sectors
❐ Hybrid
• Configuration 1: Address space consists of thirty-two 4 KB
sectors grouped either on the top or the bottom while the
remaining sectors are all 256 KB
• Configuration 2: Address space consists of thirty-two 4 KB
sectors at the top and bottom while the remaining sectors
are all 256 KB
Serial Flash Discoverable Parameters (SFDP) describing
device functions and features
Device Identification, Manufacturer Identification, and Unique
Identification
Data Integrity
Page Programming buffer of 256 or 512 bytes
02GT DDP, 04GT QDP Devices
❐ Minimum 2,560,000 Program-Erase Cycles for the Main
array
OTP Secure Silicon array of 1024 bytes (32 32 bytes)
All Devices
Interface
❐ Minimum 300,000 Program-Erase Cycles for the 4 KB
Sectors
Quad SPI
❐ Supports 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S,
4S-4D-4D protocols
❐ Minimum 25 Years Data Retention
❐ SDR option runs up to 83 MBps (166 MHz clock speed)
❐ DDR option runs up to 102 MBps (102 MHz clock speed)
Supply Voltage
1.7 V to 2.0 V (HS-T)
2.7 V to 3.6 V (HL-T)
Dual SPI
❐ Supports 1S-2S-2S protocol
❐ SDR option runs up to 41.5 MBps (166 MHz clock speed)
Grade / Temperature Range
SPI
❐ Supports 1S-1S-1S protocol
❐ SDR option runs up to 21 MBps (166 MHz clock speed)
Industrial (40 °C to +85 °C)
Industrial Plus (40 °C to +105 °C)
Automotive AEC-Q100 Grade 3 (40 °C to +85 °C)
Automotive AEC-Q100 Grade 2 (40 °C to +105 °C)
Automotive AEC-Q100 Grade 1 (40 °C to +125 °C)
Highlights
Safety Features
❐ Functional Safety with the Industry’s first ISO26262 ASIL B
compliant and ASIL D ready NOR flash
❐ EnduraFlex Architecture provides High-Endurance and
Long Retention Partitions
Packages
❐ Data Integrity CRC detects errors in memory array
❐ SafeBoot reports device initialization failures, detects config-
uration corruption and provides recovery options
02GT DDP, 04GT QDP Devices:
❐ 24-ball BGA 8 8 mm
❐ Built-in Error Correcting Code (ECC) corrects Single-bit Error
and detects Double-bit Error (SECDED) on memory array
data
❐ Sector Erase Status indicator for power loss during erase
Cypress Semiconductor Corporation
Document Number: 002-28767 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 11, 2019
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
Performance Summary
Table 1. Maximum Read Rates
Initial Access Latency
Transaction
Clock Rate (MHz)
MBps
(Cycles)
SPI Read
0
9
50
6.25
20.75
41.50
83.00
102.00
SPI Fast Read
Dual Read SDR
Quad Read SDR
Quad Read DDR
166
166
166
102
7
10
7
Table 2. Typical Program and Erase Rates
Operation
Page Programming 256 Bytes page buffer (4 KB Sector / 256 KB Sector)
Page Programming 512 Bytes page buffer (4 KB Sector / 256 KB Sector)
256 KB Sector Erase
KBps
595 / 533
753 / 898
331
4 KB Sector Erase
95
Table 3. Typical Current Consumption DDP Device
Operation
SDR Read 50 MHz
Current (mA)
31
SDR Read 166 MHz
DDR Read 102 MHz
Program
96
105
50
Erase
50
Standby (HS-T)
0.022
0.028
0.0026
0.0044
Standby (HL-T)
Deep Power Down (HS-T)
Deep Power Down (HL-T)
Table 4. Typical Current Consumption QDP Device
Operation
SDR Read 50 MHz
Current (mA)
31
SDR Read 166 MHz
DDR Read 102 MHz
Program
96
105
50
Erase
50
Standby (HS-T)
0.044
0.054
0.0052
0.0088
Standby (HL-T)
Deep Power Down (HS-T)
Deep Power Down (HL-T)
Document Number: 002-28767 Rev. **
Page 2 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
Pinout and Signal Description
Figure 1. 24-Ball BGA Pinout Configuration
1
2
3
4
5
DNU
DNU
RESET#
DNU
DNU
DNU
DNU
DNU
A
B
C
D
E
DNU
DNU
DNU
DNU
CK
VSS
VCC
DQ2 /
WP#
CS#
DNU
DQ1 /
SO
DQ3 /
RESET#
DQ0 / SI
DNU
DNU
DNU
Top View
Table 5. Signal Description
Mandatory/
Symbol
Type
Description
Optional
CS#
Input
Chip Select (CS#). All bus transactions are initiated with a HIGH to LOW transition on
CS# and terminated with a LOW to HIGH transition on CS#. Driving CS# LOW enables
the device, placing it in the active mode. When CS# is driven HIGH, the device enters
Standby mode, unless an internal embedded operation is in progress. All other input pins
are ignored and the output pins are put in high impedance state. On parts where the pin
configuration offers a dedicated RESET# pin, it remains active when CS# is HIGH.
Mandatory
CK
Input
Mandatory Clock (CK). Clock provides the timing of the serial interface. Transactions are latched on
the rising edge of the clock. In SDR protocol, command, address and data inputs are
latched on the rising edge of the clock, while data is output on the falling edge of the clock.
In DDR protocol, command, address and data inputs are latched on both edges of the
clock, and data is output on both edges of the clock.
DQ0 / SI
Input/Output Mandatory Serial Input (SI) for single SPI protocol
DQ0 Input/ Output for Dual or Quad SPI protocol
DQ1 / SO Input/Output Mandatory Serial Output (SO) for single SPI protocol
DQ1 Input/ Output for Dual or Quad SPI protocol
DQ2 / WP# Input/Output
(weak Pull-up)
Optional Write Protect (WP#) for single and dual SPI protocol
DQ2 Input/ Output for Quad SPI protocol
The signal has an internal pull-up resistor and can be left unconnected in the host system
if not used for Quad transactions or write protection. If write protection is enabled, the host
system is required to drive WP# HIGH or LOW during write register transactions.
DQ3 /
Input/Output
Optional RESET# for single and dual SPI protocol. This signal can be configured as RESET# when
CS# is HIGH or Quad SPI protocol is disabled.
RESET# (weak Pull-up)
DQ3 Input/ Output for Quad SPI protocol
The signal has an internal pull-up resistor and can be left unconnected in the host system
if not used for Quad SPI transactions or RESET#
RESET#
VCC
Input
Optional Hardware Reset (RESET#). When LOW, the device will self initialize and return to the
array read state. DQ[3:0] are placed into the high impedance state when RESET# is LOW.
RESET# includes a weak pull-up, meaning, if RESET# is left unconnected it will be pulled
up to the HIGH state on its own.
(weak Pull-up)
Power Supply Mandatory Core Power Supply
Document Number: 002-28767 Rev. **
Page 3 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
Table 5. Signal Description (continued)
Mandatory/
Optional
Symbol
Type
Description
VSS
Ground
Supply
Mandatory Core Ground
Do Not Use
DNU
-
-
General Description
The Cypress Semper Flash with Quad SPI family of products are high-speed CMOS, MirrorBitNOR flash devices. Semper Flash
is designed for Functional Safety with development according to ISO 26262 standard to achieve ASIL-B compliance and ASIL-D
readiness.
Semper Flash with Quad SPI devices support traditional SPI single bit serial input and output, optional two bit (Dual I/O or DIO) as
well as four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) protocols. In addition, there are DDR read transactions for
QIO and QPI that transfer address and read data on both edges of the clock.
Read operations from the device are burst oriented. Read transactions can be configured to use either a wrapped or linear burst.
Wrapped bursts read from a single page whereas linear bursts can read the whole memory array.
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (HIGH) to a logic 0 (LOW). Only an erase operation
can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete sector (4 KB or 256 KB).
Semper Flash provides a flexible sector architecture. The address space can be configured as either a uniform 256 KB sector array,
or a hybrid configuration 1 where thirty-two 4 KB sectors are either grouped at the top or at the bottom while the reaming sectors are
all 256 KB, or a hybrid configuration 2 where the thirty-two 4 KB sectors at the top and the bottom while the remaining sectors are all
256 KB.
The Page Programming Buffer used during a single programming operation is configurable to either 256 bytes or 512 bytes. The 512
byte option provides the highest programming throughput.
This device is an MCP with DDP or QDP stacked die, with the control signals for all dies tied together internally in the package.
Figure 2. Logic Block Diagram Monolithic Device
Power Management
Address Register
Embedded
Microcontroller
ECC
(SECDED)
Control Logic
CK
CS#
MirrorBit
EnduraFlex
Memory Array
RESET#
DQ0 / SI
Program Buffer
Read Buffer
Input/Output
Drivers
DQ1 / SO
DQ2 / WP#
DQ3 / RESET#
Data Integrity
Check
Secure Silicon Region
SFDP and IDs
Clock
Registers
Reset Control
Document Number: 002-28767 Rev. **
Page 4 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
Figure 3. MCP Diagram
VCC
VCC
DDP
QDP
DQ0 / SI
DQ0 / SI
VCC
VSS
DQ0 / SI
DQ1 / SO
DQ0 / SI
VCC
VSS
DQ1 / SO
DQ1 / SO
DQ1 / SO
DQ2 / WP#
DQ2 / WP#
DQ3 / RESET#
DQ2 / WP#
DQ3 / RESET#
DQ2 / WP#
DQ3 / RESET#
DQ3 / RESET#
DIE # 4
DIE # 2
RESET#
CK
RESET#
CK
RESET#
CK
RESET#
CK
CS#
CS#
CS#
CS#
DQ0 / SI
VCC
VSS
DQ0 / SI
VCC
VSS
DQ1 / SO
DQ1 / SO
DQ2 / WP#
DQ2 / WP#
DQ3 / RESET#
DQ3 / RESET#
DIE # 3
DIE # 1
RESET#
CK
RESET#
CK
CS#
CS#
DQ0 / SI
VCC
VSS
VSS
DQ1 / SO
DQ2 / WP#
DQ3 / RESET#
DIE # 2
RESET#
CK
CS#
DQ0 / SI
VCC
VSS
DQ1 / SO
DQ2 / WP#
DQ3 / RESET#
DIE # 1
RESET#
CK
CS#
VSS
The Semper Flash with Quad SPI family consists of multiple densities with, 1.8V and 3.0V core voltage options.
The device control logic is subdivided into two parallel operating sections: the Host Interface Controller (HIC) and the Embedded
Algorithm Controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs as needed to complete read,
program and write data transfers with the host system. The HIC delivers data from the currently entered address map on read transfers;
places write transfer address and data information into the EAC command memory, and notifies the EAC of power transition, and write
transfers. The EAC interrogates the command memory, after a program or write transfer, for legal command sequences and performs
the related Embedded Algorithms.
Changing the nonvolatile data in the memory array requires a sequence of operations that are part of Embedded Algorithms (EA).
The algorithms are managed entirely by the internal EAC. The main algorithms perform programming and erase of the main flash
array data. The host system writes command codes to the flash device. The EAC receives the command, performs all the necessary
steps to complete the transaction, and provides status information during the progress of an EA.
Executing code directly from Flash memory is often called Execute-In-Place (XIP). By using XIP with Semper Flash devices at the
higher clock rates with Quad or DDR Quad SPI transactions, the data transfer rate can match or exceed traditional parallel or
asynchronous NOR flash memories while reducing signal count dramatically.
EnduraFlex Architecture provides system designers the ability to customize the NOR Flash endurance and retention for their specific
application. The host defines partitions for high endurance or long retention, providing up to 1+ million cycles or 25 years of data
retention.
The Semper Flash with Quad SPI device supports error detection and correction by generating an embedded Hamming error
correction code during memory array programming. This ECC code is then used for single-bit and double-bit error detection and
single-bit correction during read.
Document Number: 002-28767 Rev. **
Page 5 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
The Semper Flash with Quad SPI device has built-in diagnostic features providing the host system with the device status:
■ Program and Erase Operation: Reporting of program or erase success, failure, and suspend status
■ Error Detection and Correction: 1-bit and/or 2-bit error status with address trapping and error count
■ Data Integrity Check: Error detection over memory array contents
■ SafeBoot: Reporting of proper flash device initialization and configuration corruption recovery
■ Sector Erase Status: Reporting of erase success or failure status per sector
■ Sector Erase Counter: Counts the number of erase cycles per sector
Ordering Information
Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S
25
H
L
02G
T
FA
B
H
I
05
3
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
05 = 8 8 mm package, stacked 1 Gb die
07 = 6 8 mm package, stacked 512 Mb die
Grade / Temperature Range
I = Industrial (–40 °C to + 85 °C)
V = Industrial Plus (–40 °C to + 105 °C)
A = Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
B = Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
M = Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
Package Materials
H = Low-Halogen, Lead (Pb)-free
Package Type
B = 24-ball 5 5 BGA, 1.00 mm pitch
Speed
DP = 133 MHz SDR / 66 MHz DDR
FA = 166 MHz SDR / 102 MHz DDR
Device Technology
T = 45-nm MirrorBit Process Technology
Density
02G = 2 Gb
04G = 4 Gb
Voltage
L = 3.0V
S = 1.8V
Family
H = High Performance Serial
Series
25 = Quad SPI
Prefix
S = Cypress
Register for the Semper Access Program and get access to datasheets, application notes, models, software and evaluation Kits
Document Number: 002-28767 Rev. **
Page 6 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
Document History Page
Document Title: S25HS02GT / S25HS04GT / S25HL02GT / S25HL04GT, 2-Gb (DDP), 4-Gb (QDP), HS-T (1.8-V), HL-T (3.0-V)
Semper™ Flash with Quad SPI
Document Number: 002-28767
Submission
Revision
ECN
Description of Change
Date
**
6717413
11/11/2019 Initial release of Summary Datasheet.
Document Number: 002-28767 Rev. **
Page 7 of 8
S25HS02GT / S25HS04GT
S25HL02GT / S25HL04GT
SUMMARY
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© Cypress Semiconductor Corporation, 2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware
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solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
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CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
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medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-28767 Rev. **
Revised November 11, 2019
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