S26KS128SDPBHA020_技术文档

S26KL512S, S26KS512S, S26KL256S, S26KS256S,

S26KL128S, S26KS128S

512 Mb (64 MB)/256 Mb (32 MB)/

128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Features

• 3.0 V I/O, 11 bus signals

- Single ended clock

• 1.8 V I/O, 12 bus signals

- Differential clock (CK, CK#)

• Chip Select (CS#)

• 8-bit data bus (DQ[7:0])

• Read-write data strobe (RWDS)

- HYPERFLASH™ memories use RWDS only as a Read Data Strobe

• Up to 333 MBps sustained read throughput

• DDR – two data transfers per clock

• 166-MHz clock rate (333 MBps) at 1.8 V V_CC

• 100-MHz clock rate (200 MBps) at 3.0 V V_CC

• 96-ns initial random read access time

- Initial random access read latency: 5 to 16 clock cycles

• Sequential burst transactions

• Configurable burst characteristics

- Wrapped burst lengths:

• 16 bytes (8 clocks)

• 32 bytes (16 clocks)

• 64 bytes (32 clocks)

- Linear burst

- Hybrid option: one wrapped burst followed by linear burst

- Wrapped or linear burst type selected in each transaction

- Configurable output drive strength

• Low power modes

- Active clock stop during read: 12 mA, no wake-up required

- Standby: 25 µA (typical), no wake-up required

- Deep Power-Down: 8 µA (typical)

• 300 µs wake-up required

• INT# output to generate external interrupt

- Busy to Ready transition

- ECC detection

• RSTO# output to generate system level power-on reset

- User configurable RSTO# LOW period

• 512-byte program buffer

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Features

• Sector erase

- Uniform 256-KB sectors

- Optional eight 4-KB parameter sectors (32 KB total)

• Advanced sector protection

- Volatile and non-volatile protection methods for each sector

• Separate 1024-byte one-time program array

• Operating temperature

- Industrial (–40°C to +85°C)

- Industrial Plus (–40°C to +105°C)

- Extended (–40°C to +125°C)

- Automotive, AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive, AEC-Q100 grade 2 (–40°C to +105°C)

- Automotive, AEC-Q100 grade 1 (–40°C to +125°C)

• ISO/TS16949 and AEC Q100 Certified

• Endurance

- 100,000 program/erase cycles

• Retention

- 20 year data retention

• Erase and program current

- Max peak < 100 mA

• Packaging options

- 24-ball FBGA

• Additional features

- ECC 1-bit correction, 2-bit detection

- CRC

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Performance summary

Read access timings

Maximum clock rate at 1.8 V V_CC/V_CC

Maximum clock rate at 3.0 V V_CC/V_CC

Q

166 MHz

100 MHz

96 ns

Maximum access time, (t_ACC

)

Maximum CS# access time to first word @ 166 MHz

118 ns

Typical program / erase times

Single word programming (2B = 16b)

Write buffer programming (512B = 4096b)

Sector erase time (256 KB = 2 Mb)

500 µs (~4 KBps)

475 µs (~1 MBps)

930 ms (~282 KBps)

Typical current consumption

Burst read (Continuous read at 166 MHz)

Power-on reset

80 mA

Sector erase current

60 mA

Write buffer programming current

Standby (CS# = HIGH)

60 mA

25 µA

30 µA (512 Mb)

4 µA (all other densities)

Deep power-down (CS# = HIGH, 85°C)

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Table of contents

Features ...........................................................................................................................................1

Performance summary ......................................................................................................................3

Table of contents...............................................................................................................................4

1 General description.........................................................................................................................5

1.1 DDR center aligned read strobe (DCARS) functionality ........................................................................................7

1.2 Error detection and correction functionality ........................................................................................................7

2 Connection diagram......................................................................................................................10

2.1 FBGA 24-ball 5 × 5 array footprint ........................................................................................................................10

3 Signal description.........................................................................................................................11

4 HYPERBUS™ protocol ....................................................................................................................13

4.1 Command / address bit assignments ..................................................................................................................14

4.2 Read operations....................................................................................................................................................15

4.3 HYPERFLASH™ Read with DCARS timing .............................................................................................................19

4.4 Write operations ...................................................................................................................................................20

5 Address space maps ......................................................................................................................22

5.1 Flash memory array ..............................................................................................................................................23

5.2 Device ID and CFI (ID-CFI) ASO .............................................................................................................................25

6 Embedded operations ...................................................................................................................27

6.1 Embedded algorithm controller (EAC).................................................................................................................27

6.2 Program and erase summary...............................................................................................................................28

6.3 Data protection.....................................................................................................................................................60

7 Device ID and Common Flash Interface (ID-CFI) ASO map .................................................................71

7.1 Device ID and Common Flash Interface (ID-CFI) ASO map — standard .............................................................71

7.2 Device ID and Common Flash Interface (ID-CFI) ASO Map — automotive grade / AEC-Q100 ...........................76

8 Software interface reference .........................................................................................................77

8.1 Command summary .............................................................................................................................................77

9 Data integrity ...............................................................................................................................91

9.1 Endurance .............................................................................................................................................................91

9.2 Data retention .......................................................................................................................................................91

10 Hardware interface .....................................................................................................................92

11 Electrical specifications...............................................................................................................93

11.1 Absolute maximum ratings ................................................................................................................................93

11.2 Thermal resistance .............................................................................................................................................94

11.3 Latchup characteristics ......................................................................................................................................94

11.4 Operating ranges ................................................................................................................................................95

11.5 DC characteristics (CMOS compatible) ..............................................................................................................96

11.6 Power-up and power-down................................................................................................................................99

11.7 Power-off with Hardware Data Protection ......................................................................................................104

11.8 Power Conservation modes .............................................................................................................................104

12 Timing specifications ................................................................................................................ 106

12.1 AC test conditions .............................................................................................................................................106

12.2 AC characteristics..............................................................................................................................................107

13 Embedded algorithm performance ............................................................................................. 113

14 Ordering information ................................................................................................................ 115

14.1 Ordering part numbers.....................................................................................................................................115

14.2 Valid combinations — standard .......................................................................................................................116

14.3 Valid combinations — automotive grade / AEC-Q100.....................................................................................118

15 Package diagram ...................................................................................................................... 120

15.1 Fortified ball grid array 24-ball 6 × 8 × 1.0 mm (VAA024).................................................................................120

Revision history ............................................................................................................................ 121

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

General description

1

General description

The HYPERFLASH™ family of products are high-speed CMOS, MIRRORBIT™NOR flash devices with the

HYPERBUS™ low signal count DDR interface, that achieves high speed read throughput. The DDR protocol

transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HYPERFLASH™

consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERFLASH™ core and two

corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals.

Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock

input signals are used for signal capture by the HYPERFLASH™ device when receiving command/address/data

information on the DQ signals. The read data strobe (RWDS) is an output from the HYPERFLASH™ device that

indicates when data is being transferred from the memory to the host. RWDS is referenced to the rising and falling

edges of CK during the data transfer portion of read operations.

Command/address/write-data values are center aligned with the clock edges and read-data values are edge

aligned with the transitions of RWDS.

Read and write operations to the HYPERFLASH™ device are burst oriented. Read transactions can be specified to

use either a wrapped or linear burst. During wrapped operation, accesses start at a selected location and

continue for a configured number of locations in a group wrap sequence. During linear operation accesses start

at a selected location and continue in a sequential manner until the read operation is terminated, when CS#

returns HIGH. Write transactions transfer one or more 16-bit values.

Mandatory Signals

CONTROL

LOGIC

X

C

O

M

A

X

CS#

CK

X

D

E

C

D

E

R

S

D

E

C

D

E

R

S

D

E

C

D

E

R

S

E

Memory

CK#

DQ[7:0]

Memory

Ar ay

C

X

MIRRORBIT

Array

D

N

D

ADDR

MEMORY ARRAY

RWDS

E

R

S

Optional Signals

D

E

C

O

D

E

R

RESET#

RSTO#

INT#

Sense Amplifiers

SENSE AMPLIFIERS

Y

Y DECODERS

Data Latch

PSC

PSC#

ADDR

ADDRESS

REGISTER

RWDS

GENERATOR

Figure 1

Logic block diagram

The HYPERFLASH™ family consists of multiple densities, 1.8 V/3.0 V core and I/O, non-volatile, synchronous flash

memory devices. These devices have an 8-bit (1-byte) wide DDR data bus and use only word-wide (16-bit data)

address boundaries. Read operations provide 16 bits of data during each clock cycle (8 bits on each clock edge).

Write operations take 16 bits of data from each clock cycle (8 bits on each clock edge).

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

General description

Each random read accesses a 32-byte length and aligned set of data called a page. Each page consists of a pair

of 16-byte aligned groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries.

A read access requires two clock cycles to define the target half-page address and the burst type, then an

additional initial latency. During the initial latency period the third clock cycle will specify the starting address

within the target half-page. After the initial data value has been output, additional data can be read from the page

on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst mode, while a

page is being burst out, the device will automatically fetch the next sequential page from the MIRRORBIT™ flash

memory array. This simultaneous burst output while fetching from the array allows for a linear sequential burst

operation that can provide a sustained output of 333 MBps data rate [1-byte (8-bit data bus) * 2 (Data on both clock

edges) * 166 MHz = 333 MBps].

Table 1

S26KS and S26KL address map

Type

Count

Addresses

A2–A0

A7–A0

A16–A3

A16–A8

Notes

16 bytes

512 bytes

Word address within a half-page (16 byte)

8 (word addresses)

256 (word addresses)

8192 (half-pages)

512 (lines)

Word address within write buffer line (512 byte)

Half-pages (16 bytes) within erase sector (256 KB)

Write buffer lines (512 bytes) within erase sector (256 KB)

–

256 (512 Mb)

128 (256 Mb)

64 (128 Mb)

Total number of erase sectors (256 KB)

Amax–A17

–

The device control logic is subdivided into two parallel operating sections: the host interface controller (HIC) and

the embedded algorithm controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs

as needed to complete read and write data transfers with the host system (HYPERFLASH™ master). The HIC

delivers data from the currently entered address map on read transfers; places write transfer address and data

information into the EAC command memory; notifies the EAC of power transition, and write transfers. The EAC

looks in the command memory, after a write transfer, for legal command sequences and performs the related

Embedded Algorithms (EA).

Changing the non-volatile data in the memory array requires a complex sequence of operations that are called

EA’s. The algorithms are managed entirely by the internal EAC. The main algorithms perform programming and

erase of the main flash array data. The host system writes command codes to the flash device address space. The

EAC receives the command, performs all the necessary steps to complete the command, and provides status

information during the progress of an EA.

The erased state of each memory bit is a logic ‘1’. Programming changes a logic ‘1’ (HIGH) to a logic ‘0’ (LOW).

Only an erase operation is able to change a ‘0’ to a ‘1’. An erase operation must be performed on an entire 256-KB

(or 4-KB for parameter sectors) aligned group of data called a sector. When shipped from Infineon, all sectors are

erased.

Programming is done via a 512-byte write buffer. It is possible to write from one to 256 words, anywhere within

the write buffer before starting a programming operation. Within the flash memory array, each 512-byte aligned

group of data is called a line. A programming operation transfers data from the volatile write buffer to a

non-volatile memory array line. The operation is called write buffer programming.

The write buffer is filled with 1s after reset or the completion of any operation using the write buffer. Any locations

not written to a ‘0’ by a Write to Buffer command are by default still filled with 1s. Any 1s in the write buffer do

not affect data in the memory array during a programming operation.

In addition to the mandatory signals (CS#, CK, CK#, DQ [7:0], RWDS) dedicated to the HYPERBUS™, the device also

includes optional signals (RESET#, INT#, RSTO#, and phase shifted clocks PSC/PSC#).

When RESET# transitions from LOW to HIGH the device returns to the default state that occurs after an internal

power-on reset (POR).

The INT# output can provide an interrupt to the HYPERFLASH™ master to indicate when the HYPERFLASH™

transitions from busy to ready at the end of a program or erase operation.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

General description

The RSTO# is an open-drain output used to indicate when a POR is occurring within the device and can be used

as a system level reset signal. Upon completion of the internal POR, the RSTO# signal will transition from LOW to

HIGH impedance after a user defined timeout period has expired. Upon transition to the HIGH impedance state,

the external pull-up resistance will pull RSTO# HIGH and the device immediately is placed into the Standby state.

PSC/PSC# are differential phase shifted clock inputs used as a reference for RWDS edges instead of CK/CK#. Refer

to “DDR center aligned read strobe (DCARS) functionality” on page 7 for more details.

1.1

DDR center aligned read strobe (DCARS) functionality

The HYPERFLASH™ memories offer a configurable feature that enables independent skewing (phase shifting) of

the RWDS signal with respect to the read data outputs.

When the DCARS feature is enabled, a second differential phase shifted clock input PSC/PSC# is used as the

reference for RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase shifted

90° to place the RWDS edges centered within the DQ signals valid data window. However, other degrees of phase

shift between CK/CK# and PSC/PSC# may be used to optimize the position of RWDS edges within the DQ signals

valid data window so that RWDS provides the desired amount of data setup and hold time in relation to RWDS

edges.

PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven LOW and HIGH respectively or,

both may be driven LOW during write transactions.

1.2

Error detection and correction functionality

Error correction code (ECC)

1.2.1

HYPERFLASH™ memories provide embedded hamming ECC generation during flash memory array

programming, with error detection and correction during read.

As each 16-byte aligned half-page of data, loaded into the write buffer, is transferred to the 512-byte flash

memory array line, an ECC for each half-page ECC unit is also programmed in to a portion of the memory array

not visible to the host system software.

The ECC information is checked during each half-page flash array read operation. Any one bit error within the

half-page will be corrected by the ECC logic during the access of each half-page.

The ECC information for each half-page can be written once after each erase of the sector containing each

half-page. Programming within the same half-page more than once will disable error detection and correction

within that half-page.

Word programming and write buffer programming, more than once within a half-page, is supported for legacy

software compatibility. However, for the best data integrity, it is recommended to not use word programming or

write buffer programming to program within a half-page, more than once. Multiple writes to the same half page

without an erase will disable the ECC functionality since the ECC syndrome becomes invalid. For applications

requiring multiple programming operations within the same half-page, it is recommended to add system

software error detection and correction, to enhance the data integrity of half-pages that are programmed more

than once.

There is a mode that may be enabled for two bit error detection. When this mode is enabled, any one bit error in

a half-page is corrected and any two bit error is detected and reported. In this mode, the ability to write to the

same half-page more than once, after an erase, is disabled. In this mode, attempting to program more than once

in the same half-page will result in programming operation failure status.

ECC errors may be detected by reading an ECC status register, enabling an interrupt, or enabling the RWDS to

stop when an uncorrectable error is encountered - to create a bus error before data is transferred to the

HYPERBUS™ master.

A register is provided to capture the address location of the ECC error.

A counter is provided to count ECC corrections or uncorrectable errors.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

General description

1.2.2

Cyclic redundancy check

A group of commands are provided to perform a hardware accelerated CRC calculation over a user defined

address range. The calculation is another type of embedded operation similar to programming or erase, in which

the device is busy while the calculation is in progress. The CRC operation uses a 32-bit polynomial able to detect

up to a 32-bit long group of error bits.

A command is used to enter the CRC address space overlay (ASO) where the desired address range is loaded to

start the CRC calculation. While entered in the CRC ASO the status of the CRC operation may be checked,

suspended to read from the memory array, resumed, and the resulting check-value read. Refer to “Address

space maps” on page 22 for more details.

1.2.2.1

CRC check-value calculation

The check-value calculation command sequence causes the device to perform a CRC calculation over a user

defined address range. The CRC calculation is achieved with the polynomial described in Figure 2.

The check-value generation sequence is started by entering the CRC ASO. The next step is to load the beginning

address into the CRC Start Address Register identifying the beginning of the address range that will be covered

by the CRC calculation. Next, the ending address is loaded into the CRC End Address Register, this step starts the

CRC calculation. The CRC process calculates the check-value on the data contained at the starting address

through the ending address.

During the calculation period, the device goes into the Busy state (SR[7] = 0). Once the check-value calculation

has completed, the device returns to the Ready state (SR[7] = 1) and the calculated check-value is available in the

check-value Low Result Register and the check-value High Result Register. The check-value Low Result Register

contains check-value bits 0–15 and can be read from address 0 while the device is in the CRC ASO. The

check-value High Result Register contains bits 16–31 and can be read from address 1 while the device is in the

CRC ASO. The check-value Low Result Register and the check-value High Result Register are loaded with 0s once

the CRC calculation process is initiated.

The check-value calculation can only be initiated when the device is in Standby state and once started can be

suspended with the CRC Suspend sequence to read data from the array. During the suspended state, the CRC

Suspend Status Bit (CRCSSB) in the Status Register will be set (SR[8] = 1). Once suspended, the host can read the

Status Register, read data from the array and can resume the CRC calculation by using the CRC Resume command

sequence. Once initiated, the CRC ASO can be terminated with the ASO Exit Command or a Hardware Reset to

return the device to read array mode. The check-value calculation cannot be performed while another ASO is

active. A hardware reset will clear the value in the CRC Start Address Register, CRC End Address Register,

check-value High Result Register, and the check-value Low Result Register.

The Ending Address (EA) should be at least two addresses higher than the Starting Address (SA). If EA < SA + 2, the

check-value calculation will abort and the device will return to the ready state (SR[7] = 1). SR[3] will be set (1) to

indicate the aborted condition. If EA < SA + 2, the check-value High Result Register and the check-value Low

Result Register will hold indeterminate data.

CRC-32C Polynomial = X³²+ X²⁸+ X²⁷+ X²⁶+ X²⁵+ X²³+ X²²+ X²⁰+ X¹⁹+ X¹⁸+ X¹⁴+ X¹³+ X¹¹+ X¹⁰+ X⁹+ X⁸+ X⁶+ 1

Figure 2

CRC-32 polynomial

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

General description

Enter CRC ASO

Load CRC Starting

Address

Load CRC Ending

Address

Read Status Register

Busy ?

SR[7]=0

No

Yes

Read Checkvalue

Result Register

Exit CRC ASO

Figure 3

Check-value calculation sequence

The read data ordering used in calculating the check-value from the CRC-32 polynomial is shown in Figure 4.

32-Bit Read data

Lower Order Word – Data from Address (n)

Higher Order Word – Data from Address (n+1)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CRC-32 Polynomial Data Ordering

Figure 4

Read data ordering

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Connection diagram

2

Connection diagram

2.1

FBGA 24-ball 5 × 5 array footprint

HYPERFLASH™ devices are provided in fortified ball grid array (FBGA), 1 mm pitch, 24-ball, 5 × 5 ball array

footprint, with 6 mm × 8 mm body. The package height is device dependent and may be either 1 mm or 1.2 mm.

Refer to “Ordering information” on page 115 for more details. Refer to the device datasheet ordering part

number valid combinations section for the package in use.

Figure 5

24-ball FBGA, 6 × 8 mm, 5 × 5 ball footprint, top view^{[1, 2, 3]}

Notes

1. B1 (CK#) is RFU on the 3.0 V device (model 02).

2. B5 (PSC) and C5 (PSC#) are RFU on standard 3.0 V and 1.8 V devices (model 02). C5 (PSC#) is RFU on 3 V DCARS

device (model 03).

3. DNU — Do not Use. This pin/ball is connected internally and must be left unconnected.

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Signal description

3

Signal description

RESET#

V

CC

V

Q

CC

CS#

CK

DQ[7:0]

RWDS

CK#

PSC

PSC#

INT#

RSTO#

V

SS

V

Q

SS

Figure 6

HYPERFLASH™ interface

Datasheet

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HYPERBUS™, 3.0 V/1.8 V

Signal description

Table 2

Symbol

Signal description

Type

M / O

Description

Chip Select. HYPERFLASH™ bus transactions are initiated with a HIGH to LOW

transition. HYPERFLASH™ bus transactions are terminated with a LOW to HIGH

transition.

CS#

Input

M

Differential Clock. Command / address / data information is input or output

with respect to the crossing of the CK and CK# signals. CK# is only used on the

1.8 V devices and may be left open or connected to CK on 3 V devices.

CK, CK#

Input

M

Read Write Data Strobe. Output data during read transactions are edge aligned

RWDS

Output

M

with RWDS.

Input /

Output

Data Input / Output. Command / address / data information is transferred on

these DQs during read and write transactions.

DQ[7..0]

Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS

signal with respect to the CK/CK# inputs. PSC# is only used on the 1.8 V device.

PSC and PSC# may be driven HIGH and LOW respectively or both may be driven

LOW during write transactions.

INT Output. When LOW, the device is indicating that an internal event has

occurred. This signal is intended to be used as a system level interrupt for the

device to indicate that an on-chip event has occurred. INT# is an open-drain

output.

Hardware Reset. When LOW, the device will self initialize and return to the array

read state. RWDS and DQ[7:0] are placed into the High-Z state when RESET# is

LOW. RESET# includes a weak pull-up, if RESET# is left unconnected it will be

pulled up to the HIGH state.

PSC, PSC#

INT#

Input

O

Output

(open

drain)

RESET#

Input

RSTO# Output. RSTO# is an open-drain output used to indicate when a POR is

occurring within the device and can be used as a system level reset signal. Upon

completion of the internal POR the RSTO# signal will transition from LOW to

HIGH impedance after a user defined timeout period has elapsed. Upon

transition to the HIGH impedance state the external pull-up resistance will pull

RSTO# HIGH and the device immediately is placed into the Standby state.

Output

(open

drain)

RSTO#

V_CC

O

Power

Supply

P/G Power.

Power

V_CC

V_SS

Q

P/G Input / Output Power.

P/G Ground.

Supply

Power

Supply

Power

Supply

Q

P/G Input / Output Ground.

Note

4. M = Mandatory; O = Optional; P/G = Power / Ground.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

4

HYPERBUS™ protocol

All bus transactions can be classified as either read or write. A bus transaction is started with CS# going LOW with

CK = LOW and CK# = HIGH. The transaction to be performed is presented to the HYPERFLASH™ device during the

first three clock cycles in a DDR manner using all six clock edges. These first three clocks transfer three words of

command / address (CA0, CA1, CA2) information to define the transaction characteristics:

• Read or write transaction.

• Whether the transaction will be to the memory array or to register space.

- Although the HYPERBUS™ protocol provides for slave devices that have both memory and register address

spaces, HYPERFLASH™ memories described in this specification do not differentiate between memory and

registers as separate address spaces. There is a single address space selected by any transaction, independent

of whether the transaction indicates the target location is in memory space or register space. Write

transactions always place the transaction address and data into a a command register set (buffer). Read

transactions return data from the memory array or from a register address space window that has been

temporarily overlaid within the single address space by the execution of commands. The single address space

with register space overlays methodology is backward compatible with legacy parallel NOR flash memory

program and erase software drivers.

• Whether a transaction will use a linear or wrapped burst sequence.

- HYPERFLASH™ write transactions do not support burst sequence and ignore the burst type indication. Write

command transactions transfer a single word per write. Only the word program command write data transfer

may be done with a linear burst at up to 50 MHz.

• The target half-page address (row and upper order column address).

• The target word (within half-page) address (lower order column address).

Once the transaction has been defined, a number of idle clock cycles are used to satisfy any read latency

requirements before data is transferred. Once the target data has been transferred, the HYPERBUS™ master host

completes the transaction by driving CS# HIGH with CK = LOW and CK# = HIGH. Data is transferred as 16-bit values

with the first eight bits (15–8) transferred on a HIGH going CK (write data or CA bits) or RWDS edge (read data) and

the second eight bits (7–0) being transferred on the LOW going CK or RWDS edge. Data transfers during read or

write operations can be ended at any time by bringing CS# HIGH when CK = LOW and CK# = HIGH. Read data is

edge aligned with RWDS transitions and Write data is center aligned with clock edges.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

4.1

Command / address bit assignments

Table 3

Command / Address bit assignments

Bit name

CA Bit#

Bit function

Identifies the transaction as a read or write.

1 = Read operation

47

R/W#

0 = Write operation

Target space is defined in CA46.

Indicates whether the read or write operation accesses the memory

or register spaces.

0 = Memory space

1 = Register space

46

45

Target

The register space is intended to be used by volatile memory and

peripheral devices. The HYPERFLASH™ devices will not take

advantage of this feature and this bit should be set to ‘0’ during read

or write transactions.

Indicates whether the burst will be linear or wrapped.

0 = Wrapped Burst

1 = Linear Burst

Burst type

Reserved

44–39 (1 Gb)

44–38 (512 Mb)

44–37 (128 Mb)

Reserved for future address expansion.

Reserved bits should be set to ‘0’ by the host controller.

38–16 (1 Gb)

37–16 (512 Mb)

36–16 (128 Mb)

Row and upper

column address

Half page component of target address.

Reserved for future column address expansion.

15–3

2–0

Reserved

Reserved bits should be set to ‘0’ by the host controller.

Lower column

address

Lower column component of the target address: System word

address bits A2–0 selecting the starting word within a half-page.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

4.2

Read operations

CA0 indicates that a read operation is to be performed and also indicates the burst type (wrapped or linear). Read

operations begin the internal array access as soon as the half-page address has been presented in CA0 and CA1.

CA2 identifies the target word address within the chosen half-page. The host then continues clocking for a

number of cycles defined by the latency count setting in the Configuration Register. Once these latency clocks

have been completed, the memory starts to simultaneously transition the read write data strobe (RWDS) and

begins outputting the target data. New data is output in an edge aligned fashion upon every transition of RWDS.

Data will continue to be output as long as the host continues to transition the clock (CK and CK#). Wrapped bursts

will continue to wrap within the burst length and linear burst will output data in a sequential manner across page

boundaries. A hybrid burst provides one initial wrapped burst followed by linear burst, as described in “Hybrid

Burst” on page 68. Wrapped reads can be performed from the main array, the CFI tables in “Device ID and

Common Flash Interface (ID-CFI) ASO map” on page 71 and the secure silicon region (see “Hybrid Burst” on

page 68). Read transfers can be ended at any time by bringing CS# HIGH when CK = LOW and CK# = HIGH.

When a linear burst reaches the last address in the array, if the burst continues, the address counter will wrap

around and roll back to address 000000h, allowing the read sequence to be continued indefinitely. The entire

memory can therefore be read out with one single read instruction.

The 16-byte and 32-byte wrapped bursts do not cross page boundaries and do not incur inter-page boundary

crossing latencies. For a 64-byte wrapped burst read, a latency may occur during the target address to next page

boundary crossing, depending on the starting address (see Table 22).

CS#

Initial Access

CK# , CK

5 cycle latency

RWDS

Dn

A

Dn

B

Dn+1 Dn+1

DQ[7:0]

47:40 39:32 31:24 23:16 15:8

7:0

A

B

Command-Address

RWDS and Data

are edge aligned

Memory drives DQ[7:0]

and RWDS

Host drives DQ[7:0] and Memory drives RWDS

Figure 7

Read operation^{[5, 6, 7, 8]}

Notes

5. Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new transaction

is initiated.

6. Read access from the flash array starts once CA[23:16] is captured.

7. The read latency is defined by the read latency value in the Volatile Configuration Register (or the Non-volatile

Configuration Register).

8. In this example of a read operation, the latency count was set to five clocks.

Datasheet

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001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

Table 4

Maximum operating frequency for latency code options

Latency code

Latency clocks

Maximum operating frequency (MHz)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

5

6

7

8

52

62

72

83

9

10

11

12

13

14

15

16

93

104

114

125

135

145

156

166

NA

Reserved

12Clock

9 Words Data

Initial Latency

CS#

CK

3 Clock Initial Page

Crossing Latency

RWDS

A0 02 46 8A 80 07

dd dd dd dd

dd dd dd dd dd dd

dd

dd dd dd dd

DQ[7-0

]

Read from

Address =123457h

Address Address

123457 123458

Address Address Address

12345D 12345E 12345F

Address

123460

Address

123461

Figure 8

Read transaction crossing a page boundary^{[12, 13, 14, 15, 16]}

Notes

9. Default NVCR latency setting when the device is shipped from the factory is 16 clocks.

10.The latency code is the value loaded into (Non) Volatile Configuration Register bits xVCR[7:4].

11.Maximum operating frequency assumed to be using a device with t_ACC= 96 ns.

12.Read operation starting at device address 123457h.

13.Latency code loaded into the Configuration Register is 0111b which results in 12 latency clocks.

14.Page boundary crossing requires three clocks in this case. 12 clock initial latency minus 9 clocks (words) of

initial data.

15.CK# is not shown but is the complement of the CK signal.

16.CA45 = 1 for a linear read burst.

Datasheet

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

Table 5

First page boundary crossing during linear read (Latency count = 11 clocks)

Clock cycle

Target

address

0

1

2

3

...

12

13

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

14

D1

D2

D3

D4

D6

D7

D8

D9

15

D2

D3

D4

D5

D6

D7

D8

D9

16

D3

D4

D5

D6

D7

D8

D9

17

D4

D5

D6

D7

D8

D9

18

D5

D6

D7

D8

D9

19

D6

D7

D8

D9

20

D7

D8

D9

21

D8

D9

22

23

24

25

26

27

28

29

30

0

1

D9

D10 D11 D12 D13 D14 D15 D16 D17

D10 D11 D12 D13 D14 D15 D16 D17 D18

2

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19

3

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20

4

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21

5

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22

6

D10 D11 D12 D13 D14 D15

X

D16 D17 D18 D19 D20 D21 D22

7

D10 D11 D12 D13 D14 D15

X

Bus turnaround +

initial latency

8

CA0 CA1 CA2

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25

9

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26

10

11

12

13

14

15

16

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27

D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28

D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29

D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30

D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D24 D25 D26 D27 D28 D29 D30

X

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33

—

1

2

...

11

—

Latency Count

Table 6

First page boundary crossing during linear read (Latency count = 16 clocks)

Clock cycle after CS# goes LOW

Target

address

0

1

2

3

...

17

18

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

19

D1

D2

D3

D4

D6

D7

D8

D9

20

D2

D3

D4

D5

D6

D7

D8

D9

21

D3

D4

D5

D6

D7

D8

D9

22

D4

D5

D6

D7

D8

D9

23

D5

D6

D7

D8

D9

24

D6

D7

D8

D9

25

D7

D8

D9

26

D8

D9

27

28

29

30

31

32

33

34

35

0

1

D9

D10 D11 D12 D13 D14 D15 D16 D17

D10 D11 D12 D13 D14 D15

X

D16 D17

2

D10 D11 D12 D13 D14 D15

X

3

D10 D11 D12 D13 D14 D15

X

4

D10 D11 D12 D13 D14 D15

X

5

D10 D11 D12 D13 D14 D15

X

6

D10 D11 D12 D13 D14 D15

X

7

D10 D11 D12 D13 D14 D15

X

Bus turnaround +

initial latency

8

CA0 CA1 CA2

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25

9

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D24 D25

10

11

12

13

14

15

16

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

D15 D16 D17 D18 D19 D20 D21 D22 D23

X

D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33

—

1

2

...

16

—

Latency count

Datasheet

17

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

To calculate latency when crossing a page boundary, use the following formula:

if ((PS - LTCY) < ADDR & (SP -1))

{

((ADDR & (SP -1)) - PS + LTCY)

}

else

{0}

where:

PS = page size = 16 words

SP = sub-page size = 8 words

LTCY = late nc y

ADDR = target address

Datasheet

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001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

4.3

HYPERFLASH™ Read with DCARS timing

The illustrations and parameters in this section are only those needed to define the DCARS feature and show the

relationship between the phase shifted clock, RWDS, and data.

t_CSHI

CS#

t_CSH

t_CSS

t_ACC= Access time

4 cycle latency

CK, CK#

PSC, PSC#

RWDS

t_DSV

t_PSCRWDS

t_DSZ

t_IS

t_IH

t_DQLZ

t_CKD

t_OZ

Dn

A

Dn

B

Dn+1

A

Dn+1

B

47:40 39:32 31:24 23:16 15:8

7:0

DQ[7:0]

RWDS aligned

by PSC

Command-Address

Memory drives DQ[7:0]

and RWDS

Host drives DQ[7:0] and Memory drives RWDS

Figure 9

HYPERFLASH™ Read DCARS timing diagram^{[17, 18, 19, 20]}

Notes

17.Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new

transaction is initiated.

18.CK# and PSC# are optional and shown as dashed line waveforms.

19.The memory drives RWDS during read transactions.

20.This example demonstrates a latency code setting of four clocks and no additional initial latency required.

Datasheet

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

4.4

Write operations

A write operation starts with the first three clock cycles providing the CAx (command / address) information

indicating the transaction characteristics. The burst type bit CA[45) is ‘don’t care’ because the HYPERFLASH™

device only supports a single write transaction of 16b or a continuous linear write burst that is only supported

when loading data during a Word Program command. Immediately following the CA information the host is able

to transfer the write data on the DQ bus. The first byte (A) of data is presented on the rising edge of CK and the

second byte (B) is presented on the falling edge of CK. Write data is center aligned with the CK/CK# inputs. Write

transfers can be ended at any time by bringing CS# HIGH when CK = LOW and CK# = HIGH.

CS#

CK# / CK

RWDS

47:40

39:32

31:24

23:16

15:8

7:0

DN A

DN B

DQ[7:0]

Command-Address

Host drives DQ[7:0] with Command-Address and Write Data

Write_Data

Figure 10

Write operation^{[21, 22, 23]}

Write

CS#

CK

Address=555h, Data=00AAh

Address=2AAh, Data=0055h

00 00 00 AA 00 05 00 AA

00 00 00 55 00 02 00 55

DQ[7-0]

Write

CS#

CK

Address=555h, Data=0080h

Address=555h, Data=00AAh

00 00 00 AA 00 05 00 80

00 00 00 AA 00 05 00 AA

DQ[7-0]

Write

CS#

CK

Address=2AAh, Data=0055h

Address=sector, Data=0030h

00 00 00 55 00 02 00 55

00 0E 00 00 00 00 00 30

DQ[7-0]

Figure 11

Notes

Write transaction usage example: Erase operation command sequence^{[24, 25, 26, 27]}

21.Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new

transaction is initiated.

22.RWDS will be driven LOW as long as CS# is LOW.

23.Write operations are limited to a transaction of a single word (16b) or a linear write burst supported only

when loading data during a Word Program command.This example demonstrates a latency code setting of

four clocks and no additional initial latency required.

24.See Figure 17 for the Erase Operation command sequence flowchart.

25.Erase operation to the sector starting at 0700000h.

26.CK# is not shown but is the complement of the CK signal.

27.RWDS is not shown and is not used during Write transactions.

Datasheet

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001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

HYPERBUS™ protocol

Write

CS#

CK

Address=555h, Data=00AAh

Address=2AAh, Data=0055h

00 00 00 AA 00 05 00 AA

00 00 00 55 00 02 00 55

DQ [7-0]

Write

SA, Buffer Program Command

Address=4xxxxh, Data=0025h

SA, Word Count

Address=4xxxxh, Data=0001h

CS#

CK

00 00 8x xx 00 0x 00 25

00 00 8x xx 00 0x 00 01

DQ [7-0]

Write

Target Address + 0, Data 0

Address=45678h, Data=2345h

Target Address + 1, Data 1

Address=45679h, Data=9876h

CS#

CK

00 00 8A CF 00 00 23 45

00 00 8A CF 00 01 98 76

DQ [7-0]

Write

SA, Buffer Program Confirm

Address=4xxxxh, Data=0029h

CS#

CK

00 00 8x xx 00 0x 00 29

DQ [7-0]

Figure 12

Write transaction usage example: Write Buffer Program command sequence^{[28, 29, 30, 31]}

Write

Read

Address=555h, Data=0070h

Address=000h, SR Data=hh80h

CS#

CK

5 Clock Latency

RWDS

DQ[7-0]

00 00 00 AA 00 05 00 70

80 00 00 00 00 00

hh

SR

Figure 13

Status Read transaction example^[30]

Notes

28.See Figure 15 for the Write Buffer Program Operation command sequence flowchart.

29.Program 2345h into address 45678h, and 9876h into address 45679h.

30.CK# is not shown but is the complement of the CK signal.

31.RWDS is not shown and is not used during Write transactions.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Address space maps

5

Address space maps

Although the HYPERBUS™ protocol provides for slave devices that have both memory and register address

spaces, HYPERFLASH™ memories described in this specification do not differentiate between memory and

registers as separate address spaces. There is a single address space selected by any transaction, independent

of whether the HYPERBUS™ transaction indicates the target location is in memory space or register space of the

selected device.

Write transactions always place the transaction address and data into a a command register set (buffer).

Read transactions return data from the memory array or from a register address space window that has been

temporarily overlaid within the single address space by the execution of commands. The single address range

with register space overlays methodology is backward compatible with legacy parallel NOR flash memory

program and erase software drivers.

There are several separate address spaces that may appear within the address range of the flash memory device.

One address space is visible (entered) at any given time.

• Flash memory array: The main non-volatile memory array used for storage of data that may be randomly

accessed by read operations.

• ID/CFI: A flash memory array used for Infineon factory programmed device characteristics information. This

area contains the device identification (ID) and common flash interface (CFI) information tables.

• Secure silicon region (SSR): A 1024-byte one-time programmable non-volatile memory array used for Infineon

factory programmed permanent data, and customer programmable permanent data.

• Persistent protection bits (PPB): A non-volatile memory array with one bit for each sector. When programmed,

each bit protects the related sector from erasure and programming.

• PPB lock bit: A volatile register bit used to enable or disable programming and erase of the PPB bits.

• Password: An OTP non-volatile array used to store a 64-bit password used to enable changing the state of the

PPB lock bit when using password mode sector protection.

• Dynamic protection bits (DYB): A volatile array with one bit for each Sector. When set, each bit protects the

related sector from erasure and programming.

• ECC status: Read the address of ECC corrected data and total ECC error count.

• CRC: Read the CRC check-value.

• Status or Peripheral Registers: Register access used to display EA status and read or write other registers.

The flash memory array is the primary and default address space but, it may be overlaid by one other address

space, at any one time. Each alternate address space is called an ASO.

Each ASO replaces (overlays) either the sector selected by the command that enters the ASO or the entire flash

device address range, depending on the ASO Entry command. If only one sector is overlaid by an ASO the

remaining sectors of the memory array remain readable. Any address range not defined by a particular ASO

address map, is reserved for future use. Unless otherwise stated all read accesses outside of an ASO address map

returns non-valid (undefined) data. The locations will display actively driven data but their meaning is not

defined.

There are multiple address map modes that determine what appears in the flash device address space at any

given time:

• Read Mode

• Status Register (SR) Mode

• ASO Mode

• Peripheral Register Mode

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Address space maps

In Read Mode, the entire flash memory array may be directly read by the host system memory controller. The

memory device EAC, puts the device in Read Mode during power-on, after a hardware reset, after a command

reset, or after an EA is suspended. Read accesses and commands are accepted in Read Mode. A subset of

commands is accepted in Read Mode when an EA is suspended.

While in any mode, the Status Register read command may be issued to cause the Status Register ASO to appear

at every word address in the device address space. In this Status Register ASO Mode, the device interface waits

for a read access and, any write access is ignored. The next read access to the device accesses the content of the

Status Register, exits the Status Register ASO, and returns to the previous (calling) mode in which the Status

Register read command was received.

Similarly, commands that read and write other registers use Peripheral Register Mode, in which the register

appears in a temporary ASO that is automatically exited after the read or write of the command selected register.

The read or write occurs in the last cycle of the Register Access command sequence.

In EA Mode the EAC is performing an EA, such as programming or erasing a non-volatile memory array. While in

EA Mode, none of the flash memory array is readable. While in EA Mode, only the Program / Erase Suspend

command or the Status Register Read command will be accepted. All other commands are ignored. Thus, no

other ASO may be entered from the EA Mode.

In ASO Mode, one of the remaining overlay address spaces is entered (overlaid on the flash memory array address

map). Only one ASO may be entered at any one time. Commands to the device affect the currently entered ASO.

Only certain commands are valid for each ASO. These are listed in each ASO related section of Table 41.

The following ASOs have non-volatile data that may be programmed to change 1s to 0s:

• Secure silicon region

• ASP Configuration Register (ASPR)

• Persistent protection bits (PPB)

• Password

• Only the PPB ASO has nonvolatile data that may be erased to change 0s to 1s.

When a program or erase command is issued while one of the non-volatile ASOs is entered, the EA operates on

the ASO. The ASO is not readable while the EA is active. When the EA is completed the ASO remains entered and

is again readable. Suspend and Resume commands are ignored during an EA operating on any of these ASOs.

The Peripheral Register Mode is used to manage the POR Timer, Interrupt Configuration Register, Interrupt Status

Register, Volatile Configuration Register, and the Non-volatile Configuration Register.

5.1

Flash memory array

The S26KL/S26KS family has a uniform sector architecture with a sector size of 256 KB. The following tables show

the sector architecture of the devices.

A user configuration option is available to overlay either the first sector (SA00) or last sector (SAmax) with eight

4-KB parameter-sectors. The parameter-sector address map showing how the lowest or highest sector is

partitioned is shown in the following memory address map tables. The parameter-sectors can be erased and

programmed in the normal manner using the standard erase and program command sequences targeting the

appropriate parameter-sector addresses. Note that the smaller parameter-sectors need to include A[16:11] as

part of the address identifying the target parameter-sector during erase and program command sequences.

Configuring the first or last uniform sector to include the parameter sectors is accomplished with the Non-volatile

Configuration Register.

Note The following tables have been condensed to show sector related information for an entire device on a

single page. Sectors and their address ranges that are not explicitly listed (such as SA001–SA510) have sector

starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 256-KB

sectors have the pattern XX00000h–XX1FFFFh.

Datasheet

23

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Address space maps

Table 7

S26KL512S and S26KS512S sector and memory address map

Sector

count

Sector

range

Sector size (KB)

Address range (16-bit)

Notes

SA00

:

0000000h–001FFFFh

Sector starting address

256

:

–

SA255

1FE0000h–1FFFFFFh

Sector ending address

Table 8

S26KL256S and S26KS256S sector and memory address map

Sector

count

Sector

range

Sector size (KB)

Address range (16-bit)

Notes

SA00

:

0000000h–001FFFFh

Sector starting address

256

128

:

–

SA127

0FE0000h–0FFFFFFh

Sector ending address

Table 9

S26KL128S and S26KS128S sector and memory address map

Sector

count

Sector

range

Sector size (KB)

Address range (16-bit)

Notes

SA00

:

0000000h–001FFFFh

Sector starting address

256

64

:

–

SA63

07E0000h–07FFFFFh

Sector ending address

Table 10

Main array sector 0 overlaid with eight 4-KB parameter-sectors

Main array Parameter-sector

Address size

Address range (16-bit)

Notes

sector size

number

0

1

2

3

4

5

6

7

4 KB

0000000h–00007FFh

0000800h–0000FFFh

0001000h–00017FFh

0001800h–0001FFFh

0002000h–00027FFh

0002800h–0002FFFh

0003000h–00037FFh

0003800h–0003FFFh

Start of parameter-sector 0

Parameter-sector 1

Parameter-sector 2

Parameter-sector 3

Parameter-sector 4

Parameter-sector 5

Parameter-sector 6

End of parameter-sector 7

256 KB

Exposed portion of

main array sector 0

Mapped to exposed portion

of main array sector 0

224 KB

0004000h–001FFFFh

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Address space maps

Table 11

Last sector overlaid with eight 4-KB parameter-sectors

Main array Parameter-sector

Address size

Address range (16-bit)

Notes

sector size

number

Expose portion of

main array last

sector

Mapped to exposed portion

of main array sector (last)

224 KB

xx00000h–xx1BFFFh

0

1

2

3

4

5

6

7

4 KB

xx1C000h–xx1C7FFh

xx1C800h–xx1CFFFh

xx1D000h–xx1D7FFh

xx1D800h–xx1DFFFh

xx1E000h–xx1E7FFh

xx1E800h–xx1EFFFh

xx1F000h–xx1F7FFh

xx1F800h–xx1FFFFh

Start of parameter-sector 0

Parameter-sector 1

Parameter-sector 2

Parameter-sector 3

Parameter-sector 4

Parameter-sector 5

Parameter-sector 6

End of parameter-sector 7

256 KB

5.2

Device ID and CFI (ID-CFI) ASO

There are two traditional methods for systems to identify the type of flash memory installed in the system. One

is device identification (ID). The other method is called common flash interface (CFI).

For ID, a command is used to enable an address space overlay where up to 16 word locations can be read to get

JEDEC manufacturer identification (ID), device ID, and some configuration and protection status information

from the flash memory. The system can use the manufacturer and device IDs to select the appropriate driver

software to use with the flash device.

CFI also uses a command to enable an ASO where an extendable table of standard information about how the

flash memory is organized and operates can be read. With this method the driver software does not have to be

written with the specifics of each possible memory device in mind. Instead the driver software is written in a more

general way to handle many different devices but adjusts the driver behavior based on the information in the CFI

table.

Traditionally these two address spaces have used separate commands and were separate overlays. However, the

mapping of these two address spaces are non-overlapping and so can be combined in to a single address space

and appear together in a single overlay. Either of the traditional commands used to access (enter) the Autoselect

(ID) or CFI overlay will cause the now combined ID-CFI address map to appear.

The ID-CFI address map appears within, and overlays the flash memory array data of the sector selected by the

address used in the ID-CFI enter command. While the ID-CFI ASO is entered the content of all other sectors is

undefined.

The ID-CFI address map starts at location zero of the selected sector. Locations above the maximum defined

address of the ID-CFI ASO to the maximum address of the selected sector have undefined data. The ID-CFI enter

commands use the same address and data values used on previous generation memories to access the JEDEC

manufacturer ID (Autoselect) and CFI information, respectively.

Table 12

ID-CFI address map overview

Word address

Description

Device ID (traditional autoselect values)

CFI data structure

Read / Write

Read only

(SA) + 0000h to 000Fh

(SA) + 0010h to 0079h

(SA) + 007Ah to 00FFh

Undefined

For the complete address map, see Table 35.

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Address space maps

5.2.1

Device ID

The JEDEC standard JEP106T defines the manufacturer ID for a compliant memory. Common industry usage

defined a method and format for reading the manufacturer ID and a device specific ID from a memory device. The

manufacturer and device ID information is primarily intended for programming equipment to automatically

match a device with the corresponding programming algorithm. Infineon has added additional fields within this

32-byte address space.

The original industry format was structured to work with any memory data bus width (for example: ×8, ×16, ×32).

The ID code values are traditionally byte wide but are located at bus width address boundaries such that

incrementing the device address inputs will read successive byte, word, or double word locations with the ID

codes always located in the least significant byte location of the data bus. Because the device data bus is word

wide, each code byte is located in the lower half of each word location. The original industry format made the

high order byte always zero. Infineon has modified the format to use both bytes in some words of the address

space. For the detail description of the device ID address map, see Table 35.

5.2.2

Common flash memory interface

The JEDEC CFI specification (JESD68.01) defines a standardized data structure that may be read from a flash

memory device, which allows vendor-specified software algorithms to be used for entire families of devices. The

data structure contains information for system configuration such as various electrical and timing parameters,

and special functions supported by the device. Software support can then be device-independent, device

ID-independent, and forward-and-backward-compatible for entire flash device families.

The system can read CFI information at the addresses within the selected sector as shown in “Device ID and

Common Flash Interface (ID-CFI) ASO map” on page 71.

Similar to the device ID information, CFI information is structured to work with any memory data bus width (for

example: ×8, ×16, ×32). The code values are always byte wide but are located at data bus width address

boundaries such that incrementing the device address reads successive byte, word, or double word locations

with the codes always located in the least significant byte location of the data bus. Because the data bus is word

wide, each code byte is located in the lower half of each word location and the high order byte is always zero.

For further information, refer to the CFI Specification, Version 1.5 (or later), and the JEDEC publications JEP137-A

and JESD68.01.

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Embedded operations

6

Embedded operations

6.1

Embedded algorithm controller (EAC)

The EAC takes commands from the host system for programming and erasing the flash memory arrays and

performs all the complex operations needed to change the nonvolatile memory state. This frees the host system

from any need to manage the program and erase processes.

There are five EAC operation categories:

• Deep Power-Down (DPD)

• Standby (Read Mode)

• Address space switching

• Embedded algorithms (EA)

• Advanced sector protection (ASP) management

6.1.1

Deep power-down

In the DPD mode, current consumption is driven to the lowest level. The DPD Mode must be entered while the

device is in the Standby state while not in an ASO.

6.1.2

EAC Standby

In the Standby state, current consumption is greatly reduced. The EAC enters its Standby state when no

command is being processed and no EA is in progress. If the device is deselected (CS# = HIGH) during an EA, the

device still draws active current until the operation is completed (I_CC3). I_CC4in “DC characteristics (CMOS

compatible)” on page 96 represents the standby current specification when both the Host Interface and EAC are

in their Standby state.

6.1.3

Address space switching

Writing specific address and data sequences (command sequences) switch the memory device address space

from the flash memory array to one of the ASO’s.

EA’s operate on the information visible in the currently active (entered) ASO. The system continues to have access

to the ASO until the system issues an ASO Exit command, performs a hardware reset, or until power is removed

from the device. An ASO Exit Command switches from an ASO back to the flash memory array address space. The

commands accepted when a particular ASO is entered are listed between the ASO Enter and Exit commands in

the command definitions table. See “Command summary” on page 77 for address and data requirements for

all command sequences.

6.1.4

Embedded algorithms (EA)

Changing the non-volatile data in the memory array requires a complex sequence of operations that are called

EA’s. The algorithms are managed entirely by the device’s internal EAC. The main algorithms perform

programming and erase of the main array data and the ASO’s. The host system writes command codes to the

flash device address space. The EAC receives the commands, performs all the necessary steps to complete the

command, and provides status information during the progress of an EA.

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Embedded operations

6.2

Program and erase summary

Flash data bits are erased in parallel in a large group called a sector. The erase operation places each data bit in

the sector in the logical 1 state (HIGH). Flash data bits may be individually programmed from the erased 1 state

to the programmed logical 0 (LOW) state. A data bit of ‘0’ cannot be programmed back to ‘1’. A succeeding read

shows that the data is still ‘0’. Only erase operations can convert ‘0’ to ‘1’. Programming the same word location

more than once with different 0 bits will result in the logical AND of the previous data and the new data being

programmed.

The duration of program and erase operations is shown in “Embedded algorithm performance” on page 113.

Program and erase operations may be suspended.

• An erase operation may be suspended to allow either programming or reading of another sector (not in the

erase sector) in the erase operation. No other erase operation can be started during an erase suspend.

• A program operation may be suspended to allow reading ofanother location (not in the line being programmed).

• No other program or erase operation may be started during a suspended program operation; program or erase

commands will be ignored during a suspended program operation.

• After an intervening program operation or read access is complete the suspended erase or program operation

may be resumed.

• Program and Erase operations may be interrupted as often as necessary but in order for a program or erase

operation to progress to completion there must be some periods of time between resume and the next suspend

commands greater than or equal to t_PRSor t_ERSin “Embedded algorithm performance” on page 113.

• When an EA is complete, the EAC returns to the operation state and address space from which the EA was started

(Erase Suspend or EAC Standby).

The system can determine the status of a program or erase operation by reading the Status Register (“Error

types and clearing procedures” on page 55).

Any commands written to the device during the embedded program algorithm are ignored except the Program

Suspend, and Status Read command.

Any commands written to the device during the embedded erase algorithm are ignored except Erase Suspend

and Status Read command.

A hardware reset immediately terminates any in progress program / erase operation and returns to Read Mode

after t_RPHtime. The terminated operation should be reinitiated once the device has returned to the Standby

state, to ensure data integrity.

For performance and reliability reasons programming is internally done on 16-byte half-pages, using an aligned

16-byte address range.

I_CC3in “DC characteristics (CMOS compatible)” on page 96 represents the active current specification for a

write (Embedded Algorithm) operation.

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Embedded operations

6.2.1

Program granularity

The S26KL/S26KS supports two methods of programming, word or write buffer programming.

Word programming examines the data word supplied by the command and programs 0’s in the addressed

memory array word to match the 0’s in the command data word.

Write buffer programming examines the write buffer and programs 0’s in the addressed memory array line to

match the 0’s in the write buffer. The write buffer does not need to be completely filled with data. It is allowed to

program as little as a single bit, several bits, a single word, a few words, a half-page, multiple half-pages, or the

entire buffer as one programming operation. Use of the write buffer method reduces host system overhead in

writing program commands and reduces memory device internal overhead in programming operations to make

write buffer programming more efficient and thus faster than programming individual words with the Word

Programming command.

Each half-page can be programmed by either method. Half-pages programmed by different methods may be

mixed within a Line.

Word programming and write buffer programming, more than once within a half-page, is supported for legacy

software compatibility. However, using word programming or write buffer programming more than once within

a half-page without an erase will disable the device’s ECC functionality for that half-page. For applications

requiring multiple programming operations within the same half-page, it is recommended to add system

software error detection and correction, to enhance the data integrity of half-pages.

Note If 2-bit ECC is enabled, multiple word programming or write buffer programming within the same page will

result in a program error.

Future silicon process generations of HYPERFLASH™ may no longer support multiple program operations, within

the same half-page, without an erase operation on the sector containing the half-page. Planning for software

migration to future generations should adopt data structures and data management methods that can support

only one programming operation, per half-page, per erase.

6.2.2

Incremental programming

The same word location or half-page may be programmed more than once, by either the word or write buffer

programming methods, to incrementally change 1’s to 0’s. However as noted in “Program granularity” on

page 29 incremental programming affects ECC syndrome bits and causes the device to disable ECC for that

half-page.

Note If 2-bit ECC is enabled, multiple word programming or write buffer programming within the same page will

result in a program error.

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Embedded operations

6.2.3

Program methods

Word programming

6.2.3.1

Word programming is used to program a single word or a group of words anywhere in the flash memory arrays.

The minimum Word Programming command sequence requires four command write transactions. The program

command sequence is initiated by issuing two unlock command write transactions (transactions one and two),

followed by the Program Set-Up command (transaction three). The program address and data are written next

(transaction four), which in turn initiates the embedded programming algorithm. The system is not required to

provide further controls or timing. The device automatically generates the program pulses and verifies the

programmed cell margin internally. When the embedded programming algorithm is complete, the EAC then

returns to its Standby State.

The four transaction Word Programming command sequence described earlier is used to program a single

(16-bit) word (two bytes). Multiple sequential words can be programmed with the Word Programming sequence

by using the burst write capability. The Unlock and Program command sequence is identical to a single Word

Programming sequence but during the data / address transaction multiple sequential data values are loaded

during a single assertion of CS#. The data presented is programmed into sequential addresses starting with the

target address identified in the command-address phase of the burst write transaction. A maximum of 256 words

(512 bytes) can be programmed as long as an aligned 256-word (512-byte) address boundary is not crossed.

The system can determine the status of the program operation by reading the Status Register. Refer to “Error

types and clearing procedures” on page 55.

Any commands other than Program Suspend and Status Register Read written to the device during the

embedded program algorithm are ignored.

Note that a hardware reset (RESET# = V_IL) or power loss immediately terminates the programming operation and

returns the device to Read Mode after t_RPHtime. The termination may leave the area being programmed in an

intermediate state with invalid or unstable data values. Once the device has completed the hardware reset

operation, the program command sequence may be reinitiated with the same data to complete the

programming operation, to ensure the data is fully programmed. However, to ensure the best data integrity, the

sector in which the program operation was terminated must be erased and re-programed.

The Word Programming command may also be used when the SSR ASO is entered.

A modified version of the Word Programming command, without unlock write cycles, is used for programming

when entered into the ASP Configuration Register (ASPR), Password, and PPB ASOs. The same command is used

to change volatile bits when entered in to the PPB Lock, and DYB ASOs. See Table 41 for Program Command

sequences.

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Embedded operations

START

Write Program

Command Sequence

Read Status Register

Embedded

Program

Algorithm in

Progress

No

Done ?

Yes

Last Address ?

Increment Address

Yes

Programming

Completed

Figure 14

Word program operation

6.2.3.2

Write buffer programming

A write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (Line).

Thus, a full write buffer programming operation must be aligned on a line boundary. Programming operations of

less than a full 512 bytes may start on any word boundary but may not cross a line boundary. At the start of a write

buffer programming operation all bit locations in the buffer are all 1’s (FFFFh words) thus any locations not

loaded will retain the existing data. See Table 1 for information on address map.

Write buffer programming allows up to 512 bytes to be programmed in one operation. It is possible to program

from 1 bit up to 512 bytes in each write buffer programming operation. It is strongly recommended that a multiple

of 16-byte half-pages be written and each half-page written only once. For the very best performance,

programming should be done in full lines of 512 bytes aligned on 512-byte boundaries.

Write buffer programming is supported only in the flash memory array or the SSR ASO.

The write buffer programming operation is initiated by first writing two unlock cycles. This is followed by a third

write cycle of the Write to Buffer command with the sector address (SA), in which programming is to occur. Next,

the system writes the number of word locations minus one. This tells the device how many write buffer addresses

will be loaded with data and therefore when to expect the Program Buffer to Flash Confirm command. The sector

address provided in both the Write to Buffer command and the Write Word Count command must match. The

sector to be programmed must be unlocked (unprotected). If a programming operation is attempted to a locked

sector, the operation will be aborted and the failure will be indicated in the Status Register (see Table 17).

The system then writes the starting address and data word. This starting address is the first address and data pair

to be programmed, and selects the starting word address within the write buffer line. The sector address must

match the Write to Buffer command Sector Address or the operation will abort and return to the initiating state.

All subsequent single word address and data pair write transactions must be in sequential order. All write buffer

addresses must be within the same line. If the system attempts to load data outside this range, the operation will

abort and return to the initiating state. Note that linear burst sequence is not supported while loading the data

words.

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Embedded operations

The word counter decrements for each data word loaded. Note that while counting down the data writes, every

write is considered to be data being loaded into the write buffer. No commands are possible during the write

buffer loading period. The only way to stop loading the write buffer is to write with an address that is outside the

line of the programming operation. This invalid address will immediately abort the Write to Buffer command

sequence and set the write buffer abort status bit (SR[3]).

Once the specified number of write buffer locations has been loaded, the system must then write the Program

Buffer to Flash command at the SA. The device then goes busy. The embedded program algorithm automatically

programs and verifies the data for the correct data pattern. The system is not required to provide any controls or

timings during these operations. If an incorrect number of write buffer locations have been loaded the operation

will abort and return to the initiating state. The abort occurs as well when anything other than the Program Buffer

to Flash is written when that command is expected at the end of the word count number of data words.

The write-buffer embedded programming operation can be suspended using the Program Suspend command.

When the embedded program algorithm is complete, the EAC then returns to the EAC Standby or Erase Suspend

Standby state where the programming operation was started.

The system can determine the status of the program operation by using the Status Register (see Table 17). See

Figure 15 for a diagram of the programming operation.

The write buffer programming sequence will be aborted under the following conditions:

• Load a word count value greater than the buffer size (255).

• Write an address that is outside the line provided in the Write to Buffer command.

• The Program Buffer to Flash command is not issued after the write word count number of data words is loaded.

When any of the conditions that cause an abort of write buffer command occur the abort will happen immediately

after the offending condition, and will indicate a program fail in the Status Register at bit location 4 (PSB = 1) due

to write buffer abort bit location 3 (WBASB = 1). The next successful program operation will clear the failure status

or a Clear Status Register may be issued to clear the PSB status bit.

The write buffer programming sequence can be terminated by the following: Hardware reset or power cycle.

However, using either of these methods may leave the area being programmed in an intermediate state with

invalid or unstable data values. In this case the same area will need to be reprogrammed with the same data or

erased to ensure data values are properly programmed or erased. To ensure the best data integrity, the sector in

which the program operation was terminated must be erased and re-programmed.

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Embedded operations

Write “Write to Buffer”

command Sector Address

Write “Word Count”

to program - 1 (WC)

Sector Address

Write Starting Address/Data

Yes

WC = 0?

Write to a different

Sector Address

No

Yes

ABORT Write to

Write to Buffer ABORTED.

Must write “Write-to-Buffer

ABORT RESET”

command sequence to

return to READ mode.

Buffer Operation?

No

Note [33]

Write next Address/Data pair

WC = WC - 1

Write Program Buffer to Flash

Confirm, Sector Address

Read Status Register

Yes

DRB

SR[7] = 0?

No

PSB

SR[4] = 0?

No

Program Fail

Program Successful

WBASB

Yes

SR[3] = 1?

No

Yes

SLSB

SR[1] = 0?

No

Program aborted during

Write to Buffer command

Sector Locked Error

Program Fail

Figure 15

Write buffer programming operation with Status Register^{[32, 33]}

Notes

32.See Table 41 for the command sequence as required for write buffer programming.

33.When the SA is specified, any address in the selected sector is acceptable. However, when loading

write-buffer address locations with data, all addresses must fall within the selected line.

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Embedded operations

Table 13

Write buffer programming command sequence

Sequence Address Data

Comment

Issue Unlock Command 1

Issue Unlock Command 2

555h

2AAh

AAh

55h

Issue Write to Buffer Command at Sector

Address

SA

0025h

WC

Issue Number of Locations at Sector

Address

WC = number of words to program minus 1.

Example:

WC of 0 = 1 word to program

WC of 1 = 2 words to program

Starting

address

Selects a Line and loads first Address / Data

Pair.

All addresses must be within the selected Line

boundaries, and have to be loaded in

sequential order.

Load Starting Address / Data Pair

PD

Load Next Address / Data Pair

WBL

All addresses must be within the selected Line

boundaries, and have to be loaded in

sequential order.

This command must follow the last write buffer

location loaded, or the operation will ABORT.

Load Last Address / Data Pair

WBL

SA

PD

Issue Write Buffer Program Confirm at

Sector Address

0029h

Device goes Busy

Legend:

SA = Sector Address (Non-Sector Address bits are ‘don’t care’. Any address within the sector is sufficient.)

WBL = Write Buffer Location (Must be within the boundaries of the line specified by the Starting Address.)

WC = Word Count

PD = Program Data

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Embedded operations

6.2.4

Program Suspend / Program Resume commands

The Program Suspend command allows the system to interrupt an embedded programming operation so that

data can be read from any non-suspended Line. When the Program Suspend command is written during a

programming process, the device halts the programming operation within t_PSL(program suspend latency) and

updates the status bits. Addresses are ‘don’t care’ when writing the Program Suspend command.

After the programming operation has been suspended, the system can read array data from any non-suspended

line. The Program Suspend command may also be issued during a programming operation while an erase is

suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend.

After the Program Resume command is written, the device reverts to programming and the status bits are

updated. The system can determine the status of the program operation by reading the Status Register. Refer to

“Error types and clearing procedures” on page 55 for information on these status bits.

Accesses and commands that are valid during Program Suspend are:

• Read to any other non-erase-suspended sector

• Read to any other non-program-suspended line

• Status Read command

• Exit ASO or Command Set Exit

• Program Resume command

• Load Interrupt Configuration Register

• Load Interrupt Status Register

The system must write the Program Resume command to exit the Program Suspend Mode and continue the

programming operation. Further writes of the Program Resume command are ignored. Another Program

Suspend command can be written after the device has resumed programming.

Program operations can be interrupted as often as necessary but in order for a program operation to progress to

completion there must be some periods of time between resume and the Next Suspend command greater than

or equal to t_PRSin “Embedded algorithm controller (EAC)” on page 27.

Program Suspend and Resume is not supported while entered in an ASO. While in Program Suspend Entry into

ASO is not supported.

6.2.5

Blank Check

The Blank Check command will confirm if the selected flash memory array sector is fully erased. The Blank Check

command does not allow for reads to the array during the Blank Check. Reads to the array while this command

is executing will return unknown data.

To initiate a Blank Check on a sector, write 33h to address 555h in the sector, while the EAC is in the Standby state.

The Blank Check command may not be written while the device is actively programming or erasing or suspended.

Use the Status Register read to confirm if the device is still busy and when complete if the sector is blank or not.

Bit 7 of the Status Register will show if the device is performing a Blank Check (similar to an erase operation).

Bit 5 of the Status Register will be cleared to ‘0’ if the sector is erased and set to ‘1’ if not erased.

As soon as any bit is found to not be erased, the device will halt the operation and report the results.

Once the Blank Check is completed, the EAC will return to the Standby state.

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Embedded operations

6.2.6

Evaluate Erase Status

The Evaluate Erase Status (EES) command verifies that the last erase operation on the addressed sector was

completed successfully. If the selected sector was successfully erased the sector erase status bit in the Status

Register (SR[0]) is set to ‘1’. If the selected sector was not completely erased SR[0] is cleared to ‘0’. See Figure 16

for details.

The EES command can be used to detect erase operations that failed due to loss of power, reset, or failure during

an erase operation.

The EES command requires t_EESto complete and updates the sector erase status bit in the Status Register (SR[0]).

The device ready bit in the Status Register (SR[7]) may be read using the Read Status Register (70h) command to

determine when the EES command has finished. Once the device ready bit in the Status Register indicates that

the device has returned to the ready (1) state, the sector erase status bit (SR[0]) indicates whether the target

sector was successfully erased. If a sector is found not erased with SR[0] = 0, the sector must be erased again to

ensure reliable storage of data in the sector.

Write Evalulate Erase

Status Command (D0h)

to target sector (SA)

Read Status Register

Busy ?

SR[7]=0

No

Yes

Prior Erase

Corrupted ?

SR[0]=1

Yes

No

Prior Erase

Unsuccessful

Prior Erase Successful

Figure 16

Evaluate Erase Status software sequence

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Embedded operations

6.2.7

Erase methods

Chip Erase

6.2.7.1

The Chip Erase function erases the entire flash memory array. The device does not require the system to

preprogram prior to erase. The embedded erase algorithm automatically programs and verifies the entire

memory for an all 0 data pattern prior to electrical erase. After a successful chip erase, all locations within the

device contain FFFFh. The system is not required to provide any controls or timings during these operations. The

Chip Erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the Chip Erase command, which in turn invokes the

embedded erase algorithm.

When the embedded erase algorithm is complete, the EAC returns to the Standby state. Note that while the

embedded erase operation is in progress, the system cannot read valid data from the array. The system can

determine the status of the erase operation by reading the Status Register. Refer to “Error types and clearing

procedures” on page 55 for information on these status bits. Once the chip erase operation has begun, only a

Status Read, Hardware Reset, or Power cycle are valid. All other commands are ignored. However, a Hardware

Reset or Power Cycle immediately terminates the erase operation and returns to Read Mode after t_RPHtime. If a

chip erase operation is terminated, the Chip Erase command sequence must be reinitiated once the device has

returned to the Standby state to ensure data integrity.

Sectors protected by the ASP DYB and PPB bits will not be erased. See “Software interface reference” on

page 77. If a sector is protected during Chip Erase, Chip Erase will skip the protected sector and continue with

next sector erase. The Status Register erase status bit and sector lock bit are not set to ‘1’ by a failed erase on a

protected sector.

6.2.7.2

Sector Erase

The Sector Erase function erases one sector in the memory array. The device does not require the system to

preprogram prior to erase. The embedded erase algorithm automatically programs and verifies the entire sector

for an all 0 data pattern prior to electrical erase. After a successful sector erase, all locations within the erased

sector contain FFFFh. The system is not required to provide any controls or timings during these operations. The

Sector Erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the address of the sector to be erased, and the Sector Erase

command.

The system can determine the status of the erase operation by reading the Status Register. Refer to “Error types

and clearing procedures” on page 55 for information on these status bits.

Once the sector erase operation has begun, the Status Register Read and Erase Suspend commands are valid. All

other commands are ignored by the embedded algorithm controller. However, note that a Hardware Reset

immediately terminates the erase operation and returns to Read Mode after t_RPHtime. If a sector erase operation

is terminated, the Sector Erase command sequence must be reinitiated once the device has reset operation to

ensure data integrity.

See “Embedded algorithm controller (EAC)” on page 27 for parameters and timing diagrams.

Sectors protected by the ASP DYB and PPB bits will not be erased. See “Software interface reference” on

page 77. If an erase operation is attempted to a locked sector the operation will be aborted and the failure will

be indicated in the Status Register (see Table 17).

Datasheet

37

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Command Cycle 1

Command Cycle 2

Command Cycle 3

Address 2AAh, Data 55h

Specify first sector for erasure

Sector Address, Data 30h

Perform Write Operation

Status Algorithm

Status may be obtained by Status Register Polling.

Yes

Done?

No

Erase Error?

Yes

No

Error condition (Exceeded Timing Limits)

PASS. Device returns

to reading array.

FAIL. Write reset command

to return to reading array.

Figure 17

Sector Erase operation

Datasheet

38

001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.8

Erase Suspend / Erase Resume

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from,

or program data to, the flash memory array. This command is valid only during sector erase or program

operation. The Erase Suspend command is ignored if written during the chip erase operation.

When the Erase Suspend command is written during the sector erase operation, the device requires a maximum

of t_ESL(erase suspend latency) to suspend the erase operation and update the status bits.

After the erase operation has been suspended, the part enters the Erase-Suspend Mode. The system can read

data from or program data to the flash memory array. Reading at any address within erase-suspended sectors

produces undetermined data. The system can determine if a sector is actively erasing or is erase-suspended by

reading the Status Register. Refer to “Error types and clearing procedures” on page 55 for information on these

status bits.

After an erase-suspended program operation is complete, the EAC returns to the Erase-Suspend state. The

system can determine the status of the program operation by reading the Status Register, just as in the standard

program operation.

If a program failure occurs during erase suspend the Status Register Clear or Software Reset commands will

return the device to the erase suspended state. Erase will need to be resumed and completed before again trying

to program the memory array.

Accesses and commands that are valid during Erase Suspend are:

• Read to any other non-suspended sector

• Program to any other non-suspended sector

• Status Read command

• Exit ASO or Command Set Exit

• Erase Resume command

• SSR Entry

• SSR Read

• SSR Program

To resume the sector erase operation, the system must write the Erase Resume command. The device will revert

to erasing and the status bits will be updated. Further writes of the Resume command are ignored. Another Erase

Suspend command can be written after the chip has resumed erasing.

Note that the DYB ASO can not be entered while the device is in the Erase Suspend state.

Datasheet

39

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.9

Volatile and Non-volatile Register summary

Non-volatile Configuration Registers

6.2.9.1

Table 14

Symbol

Non-volatile Configuration Registers

Width

(bits)

NV

Default

value

Name

Reference

type

“Non-volatile Configuration Register

Non-volatile

NVCR

PASS

16

64

P/E

8EBBh and Volatile Configuration Register” on

Configuration Register

page 43

FFFFFFFF

Password Protection

Register

“Password Protection Mode” on

page 66

OTP

FFFF

FFFFh

Persistent Protection

Bits

ASP Configuration

Register

1-bit per

sector

“Persistent Protection Bits (PPB)” on

PPB

P/E

OTP

1

page 63

“ASP Configuration Register” on

page 65

“Power-on (Cold) Reset (POR)” on

page 101

ASPR

16

FEFFh

PORTime Power-On Reset Time

FFFFh

6.2.9.2

Volatile Configuration Registers

Table 15

Symbol

Volatile Configuration Registers

Width

(bits)

Default

Name

Reference

Value

Volatile Configuration

Register 0

“Non-volatile Configuration Register and

Volatile Configuration Register” on page 43

VCR

16

NVCR

Dynamic Protection

Bits

PPB Lock Bit

Interrupt Configuration

Register

1-bit per

sector

DYB

PPBL

ICR

1

“Dynamic Protection Bits (DYB)” on page 63

1

ASPR[2] “PPB Lock” on page 63

FFFFh “INT# Output” on page 69

16

CRC Start Address

Register

CRC End Address

Register

CRCS

CRCE

26 (1 Gb) 3FFFFFFh “CRC check-value calculation” on page 8

Datasheet

40

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.10

Volatile Results and Status Registers

Table 16

Volatile Results and Status Registers

Name

Width (bits)

Default value

Reference

Sector Lock Status

Status Register

Interrupt Status Register

ECC Status Register

3-bit per sector

NA

xx80h

FFFBh

NA

See Note 85 for Table 41.

16

Table 17

Table 34

–

Error Lower Address Trap

Register

Error Upper Address Trap

Register

Read Check-Value Low

Result Register

Read Check-Value High

Result Register

16

NA

Table 41

“CRC Value Register” on

page 50

“CRC Value Register” on

page 50

6.2.11

Status and Configuration Register definitions

Status Register mode

6.2.11.1

The status of EA’s are provided by a single 16-bit Status Register. The Status Register Read command is issued

followed by one read access of the Status Register information. The contents of the Status Register is aliased

(overlaid) in all locations of the device address space. The overlay is in effect for one read access, specifically the

next read access that follows the Status Register Read command. After the one Status Register access, the Status

Register ASO is exited.

The Status Register contains bits related to the results — success or failure — of the most recently initiated EA’s:

• Erase Status (bit 5),

• Program Status (bit 4),

• Write Buffer Abort (bit 3),

• Sector Locked Status (bit 1),

• Sector Erase Status Bit (bit 0).

and, bits related to the current state of any in process EA:

• Device Busy (bit 7),

• Erase Suspended (bit 6),

• Program Suspended (bit 2),

• CRC Calculation Suspended (bit 8)

The current state bits indicate whether an EA is in process, suspended, or completed.

The upper 7 bits (bits 15:9) are reserved. These have an undefined HIGH or LOW value that can change from one

status read to another. These bits should be treated as ‘don’t care’ and ignored by any software reading status.

The Clear Status Register command and the Software Reset command will clear to ‘0’ the results related bits of

the Status Register (bits 5, 4, 3, 1, and 0) but will not affect the current state bits.

Datasheet

41

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 17

Status Register

Bit description

Reserved

Bit

Reset

status

Busy

Bit name

Ready status

number

status

[15:9]

X

0

1

0

Invalid

0

X

0 = No CRC in Suspension

1 = CRC in Suspension

1

0 = No Erase in Suspension

1 = Erase in Suspension

[8]

CRC Suspend Status Bit CRCSSB

[7]

Device Ready Bit

DRB

Erase Suspend Status

Bit

[6]

ESSB

Invalid

0 = Erase Successful

1 = Erase Fail

0 = Program Successful

1 = Program Fail

[5]

[4]

Erase Status Bit

ESB

PSB

0

Invalid

Program Status Bit

0 = Program Not Aborted

Write Buffer Abort

Status Bit

[3]

[2]

[1]

WBASB

PSSB

0

Invalid 1 = Program Aborted during Write

to Buffer Command

Program Suspend

Status Bit

0 = No Program in Suspension

1 = Program in Suspension

Invalid

0 = Sector Not Locked during

Invalid Operation

Sector Lock Status Bit

SLSB

1 = Sector Locked Error

0 = Sector Erase Status Command

Result = previous erase did not

complete successfully

[0]

Sector Erase Status Bit

ESTAT

0

Invalid

1 = Sector Erase Status Command

Result = previous erase completed

successfully

Notes

34.Bits 15 through 9 are reserved for future use and may display as ‘0’ or ‘1’. These bits should be ignored

(masked) when checking status.

35.Bit 7 is ‘1’ when there is no EA in progress in the device.

36.Bit 8 and bits 6 through 0 are valid only if Bit 7 is ‘1’.

37.All bits are put in their reset status by cold reset or warm reset.

38.Bits 5, 4, 3, 1, and 0 are cleared to ‘0’ by the Clear Status Register command or Software Reset command.

39.Upon issuing the Erase Suspend command, the user must continue to read status until DRB becomes ‘1’.

40.ESSB is cleared to ‘0’ by the Erase Resume command.

41.ESB reflects success or failure of the most recent erase operation.

42.PSB reflects success or failure of the most recent program operation.

43.During Erase Suspend, programming to the suspended sector, will cause program failure and set the

Program status bit to ‘1’.

44.During Erase Suspend, an erase operation will cause an erase failure and set the Erase status bit to ‘1’.

45.During Program Suspend, a programming operation will cause a program failure and set the Program

status bit to ‘1’.

46.During Program Suspend, an erase operation will cause an erase failure and set the Erase status bit to ‘1’.

47.Upon issuing the Program Suspend command, the user must continue to read status until DRB becomes ‘1’.

48.PSSB is cleared to ‘0’ by the Program Resume command.

49.SLSB indicates that a program or erase operation failed because the target memory region was locked.

50.SLSB reflects the status of the most recent program or erase operation.

51.CRCSSB – During a suspended CRC calculation only read operations from the array are allowed.

Datasheet

42

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.12

Non-volatile Configuration Register and Volatile Configuration Register

The Non-volatile Configuration Register (NVCR) and the Volatile Configuration Register (VCR) are used to define

the operating conditions for the HYPERFLASH™ bus. Configurable characteristics include:

1. Wrapped burst length (16-byte, 32-byte, or 64-byte wrapped burst).

a.16-byte and 32-byte wrapped bursts behave in the legacy manner, 64-byte wrapped burst behave as shown

in Table 22.

2. Read latency (5 to 16 clocks to allow for initial read latency).

3. Output driver drive strength.

4. Whether the 4-KB parameter-sectors are used and how they are mapped into the address map.

5. SSR Freeze bit to lock the secure silicon region.

6. xVCR Freeze bit to lock the Volatile Configuration Register and the Non-volatile Configuration Register.

The contents of the VCR and NVCR can be loaded and read back as described in Table 41. The HYPERFLASH™

device uses the contents of the NVCR to define bus characteristics upon power-up or after a hardware reset. If the

host system loads the VCR, the bus characteristics will be defined by the contents of the VCR (Figure 18). The

NVCR is intended to hold a default setting to allow alignment with the host controller settings during boot

operation. The VCR will often be updated with optimized settings during the boot process. The source for bus

characteristics will shift from the NVCR (after power-up or hard reset) to the VCR once the VCR is loaded. Once

the VCR is loaded only a power-up or hard reset will return bus characteristics back to the NVCR settings. When

unlocked the VCR can be altered at any time while the device is idle.

The number of times the NVCR can be erased and reprogrammed is defined by the NVCR spec. To assure

consistent bus configuration during and after NVCR programming, the VCR should be used to define bus

operating characteristics when programming the NVCR.

Datasheet

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001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 18

xVCR Bit

VCR and NVCR Configuration Register bit assignments

Function

Reserved

Settings (Binary)

xVCR[15]

1 = Reserved (default)

xVCR[14:12]

Drive strength

See Table 19.

0 = VCR or NVCR locked (No programming or erasing of NVCR, no changes

to VCR)

xVCR[11]

xVCR[10]

xVCR freeze

SSR freeze

1 = VCR and NVCR unlocked (Factory default)

0 = Secure silicon region locked (Programming not allowed)

1 = Secure silicon region unlocked (Factory default)

00 = Parameter-sectors and read password sectors mapped into lowest

addresses

01 = Parameter-sectors and read password sectors mapped into highest

Parameter-sector addresses

xVCR[9:8]

xVCR[7:4]

mapping

10 = Uniform sectors with read password sector mapped into lowest

addresses. (factory default)

11 = Uniform sectors with read password sector mapped into highest

addresses

0000 = 5 clock latency

0001 = 6 clock latency

0010 = 7 clock latency

0011 = 8 clock latency

0100 = 9 clock latency

...

Read latency

1011 = 16 clock latency (factory default)

See Table 4.

xVCR[3]

xVCR[2]

Reserved

1 = Reserved (default)

0 = RWDS will stall (remain LOW) upon dual error detect (default)

1 = RWDS will not be stalled upon dual error detect

RWDS stall control

00 = Reserved

01 = 64 bytes

xVCR[1:0]

Burst length

10 = 16 bytes

11 = 32 bytes (factory default)

Note

52.The placement of the Configuration Register bits are the same in both the Non-volatile and Volatile

Configuration Registers.

Datasheet

44

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 19

Drive strength code

xVCR[14:12]

Typical impedance 1.8 V V_CC

Q

Typical impedance 3 V V_CC

Q

Unit

000 (default)

001

27

117

68

45

34

27

24

20

71

40

27

20

16

14

12

010

011

Ohms

100

101

110

111

Non-Volatile

Configuration Register

Volatile

Configuration Register

Set

Clear

Load Volatile Configuration Register

Power-On Reset

Hardware Reset

CR Select Multiplexer

DIR

DIR=0=NVCR

DIR=1=VCR

Device Configuration

Figure 18

Table 20

Configuration control^{[54, 55, 56]}

VCR and NVCR freeze bits immediately after power-up or hardware reset

NVCR[11] bit

VCR[11] bit

NVCR

VCR

1

0

1

0

1

0

Programmable / erasable

Temporarily locked

Programmable / erasable

Permanently locked

Settable / clearable

Temporarily locked

Settable / clearable^{[57, 59]}

Permanently locked^[60]

Notes

53.Typical impedance measured at nominal V_CCQ, 25 °C.

54.A software reset will not change the state of the CR Select Multiplexer.

55.Programming or erasure of the NVCR does not impact the contents of the VCR that has been previously

loaded.

56.If the VCR has not been loaded, programming of the NVCR will be result in the VCR being loaded with the new

NVCR value.

57.Programming / Erasing the NVCR will not impact behavior until after the next POR or hardware reset.

58.Loading the VCR will impact behavior immediately.

59.This state occurs after NVCR[11] = VCR[11] = 1 and the NVCR[11] bit is programmed. The state will only exist

until the next POR or hardware reset. Thereafter NVCR[11] = VCR[11] = 0.

60.This state occurs after POR or hardware reset when NVCR[11] was previously programmed.

Datasheet

45

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 21

Example Burst sequences

Wrap

Start

VCR / NVCR

[1:0]

CA[45] boundary

(Bytes)

address

(Hex)

Address sequence (Hex) (Words)

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12,

13, 14, 15, 16, 17, 18, ...

XX

1

Linear

XXXXXX03

10

11

0

16

32

XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01, ...

XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ...

XXXXXX0A 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...

XXXXXX1E 1E, 1F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, ...

03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12,

01

0

64

XXXXXX03

13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ...

2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D,

3E, 3F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, , ...

XXXXXX2E

Datasheet

46

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.12.1

CRC Value Register

The volatile CRC register (CRCR) stores the results of the CRC process that calculates the check-value on the data

contained at the starting address through the ending address.

Table 24

CRC Value Register bit assignments

Bit position CRC Value Low Result Register

CRC Value High Result Register

[15]

[14]

[13]

[12]

[11]

[10]

[9]

[8]

[7]

[6]

[5]

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R31

R30

R29

R28

R27

R26

R25

R24

R23

R22

R21

R20

R19

R18

R17

R16

[4]

[3]

[2]

[1]

R4

R3

R2

R1

[0]

R0

Note

61.CRC value is a Volatile Register.

Datasheet

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.13

ASO entry and exit

ID-CFI ASO

6.2.13.1

The system can access the ID-CFI ASO by issuing the ID-CFI Entry command sequence during Read Mode. This

entry command uses the Sector Address (SA) in the command to determine which sector will be overlaid. See the

detail descriptions in Table 41, Table 12, “Device ID” on page 26, and “Common flash memory interface” on

page 26.

The ID-CFI ASO allows the following activities:

• Read ID-CFI ASO, using the same SA as used in the Entry command.

• ASO Exit.

The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Low Level Driver

User Guide for general information on Cypress flash memory software development guidelines.

/* Example: CFI Entry command */

*( (UINT16 *)base_addr + 0x555 ) = 0x0098; /* write CFI entry command */

/* Example: CFI Exit command */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* write cfi exit command */

6.2.13.2

Status Register ASO

When the Status Register read command is issued, the current status is captured by the register and the ASO is

entered. The first read access in the Status Register ASO exits the ASO and returns to the address space map in

use when the Status Register read command was issued. No other command should be sent before reading the

status to exit the Status Register ASO. The contents of the Status Register is only output as the first data value of

a burst read, indeterminate data will be output during subsequent clock cycles.

6.2.13.3

Secure Silicon Region ASO

The system can access the Secure Silicon Region by issuing the Secure Silicon Region Entry command sequence

during Read Mode. This entry command uses the SA in the command to determine which sector will be overlaid.

The Secure Silicon Region ASO allows the following activities:

• Read Secure Silicon Region, using the same SA as used in the entry command. Reads within the overlaid SA but

outside of the SSR will return indeterminate data.

• Reads to a SA outside of the Secure Silicon Region will retrieve array data. A read from the array will not cause

an exit from the SSR ASO.

• Program the customer Secure Silicon Region using the Word or Write Buffer Programming commands.

• ASO Exit using legacy Secure Silicon Exit command for backward software compatibility.

• ASO Exit using the common exit command for all ASO – alternative for a consistent exit method.

Datasheet

51

001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.13.4

ASP Configuration Register (ASPR) ASO

The system can access the ASP Configuration Register by issuing the ASP Configuration Register entry command

sequence during Read Mode. This entry command does not use a sector address from the entry command. The

ASP Configuration Register appears at word location 0 in the device address space. All other locations in the

device address space are undefined.

The ASP Configuration Register ASO allows the following activities:

• Read ASP Configuration Register, using device address location 0.

• Program the customer ASP Configuration Register using a modified Word Programming command.

• ASO Exit using legacy Command Set Exit command for backward software compatibility.

• ASO Exit using the common exit command for all ASO – alternative for a consistent exit method.

6.2.13.5

Password ASO

The system can access the Password ASO by issuing the Password entry command sequence during Read Mode.

This entry command does not use a sector address from the entry command. The Password appears at word

locations 0 to 3 in the device address space. All other locations in the device address space are undefined.

The Password ASO allows the following activities:

• Read Password, using device address location 0 to 3.

• Program the Password using a modified Word Programming command.

• Unlock the PPB Lock Bit with the Password Unlock command.

• ASO Exit using legacy Command Set Exit command for backward software compatibility.

• ASO Exit using the common exit command for all ASO – alternative for a consistent exit method.

6.2.13.6

PPB ASO

The system can access the PPB ASO by issuing the PPB Entry command sequence during Read Mode. This entry

command does not use a sector address from the entry command. The PPB bit for a sector appears in bit 0 of all

word locations in the sector.

The PPB ASO allows the following activities:

• Read PPB protection status of a sector in bit 0 of any word in the sector.

• Program the PPB bit using a modified Word Programming command.

• Erase all PPB bits with the PPB Erase command.

• ASO Exit using legacy Command Set Exit command for backward software compatibility.

• ASO Exit using the Common Exit command for all ASO – alternative for a consistent exit method.

6.2.13.7

PPB Lock ASO

The system can access the PPB Lock ASO by issuing the PPB Lock Entry command sequence during Read Mode.

This entry command does not use a sector address from the entry command. The global PPB lock bit appears in

bit 0 of all word locations in the device.

The PPB Lock ASO allows the following activities:

• Read PPB Lock protection status in bit 0 of any word in the device address space.

• Clear the PPB Lock bit using a modified Word Programming command.

• ASO Exit using legacy Command Set Exit command for backward software compatibility.

• ASO Exit using the Common Exit command for all ASO – alternative for a consistent exit method.

Datasheet

52

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.13.8

Dynamic Protection Bits (DYB) ASO

The system can access the DYB ASO by issuing the DYB entry command sequence during Read Mode. This entry

command does not use a sector address from the entry command. The DYB bit for a sector appears in bit 0 of all

word locations in the sector.

The DYB ASO allows the following activities:

• Read DYB protection status of a sector in bit 0 of any word in the sector

• Set the DYB bit using a modified Word Programming command

• Clear the DYB bit using a modified Word Programming command

• ASO Exit using legacy Command Set Exit command for backward software compatibility

• ASO Exit using the Common Exit command for all ASO – alternative for a consistent exit method

6.2.13.9

ECC Status ASO

The ECC Status ASO displays the status of any error correction action when reading a half-page of the flash

memory array. A single word of status is displayed at any word location within a half-page.

The system can access the ECC Status ASO by issuing the ECC Status entry command sequence during Read

Mode. This entry command does not use a sector address from the entry command. The ECC status bits for a

half-page appears in bits 4, 3, 2, 1, and 0 of all word locations in the addressed half-page.

The ECC Status ASO allows the following activities:

• Read the ECC Status Register value for the addressed half-page

• Read the Error-Detect Upper and Lower Address Trap Registers

• Read the ECC Error Counter Register

• ASO Exit

6.2.13.10 CRC ASO

Entering the CRC ASO enables the CRC related commands and reading of the CRC calculation result check-value.

While the CRC calculation is not suspended the CRC ASO overlays the entire flash memory array. When the CRC

calculation is suspended the flash memory array is visible for reading. Only reading of the memory array is

supported while entered in the CRC ASO and the CRC calculation is suspended. The CRC ASO allows the following

activities:

• Load CRC beginning location

• Load CRC ending location

• CRC calculation suspend

• Flash array read during suspend

• CRC calculation resume

• Read check-value result

• Exit the CRC ASO

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.13.11 Software (command) Reset / ASO exit

Software Reset is part of the command set (see Table 41) that also returns the EAC to Standby state and must be

used for the following conditions:

• Exit ID/CFI Mode

• Clear timeout bit (DQ5) for data polling when timeout occurs

Software Reset does not affect EA Mode. Reset commands are ignored once programming or erasure has begun,

until the operation is complete. Software Reset does not affect outputs; it serves primarily to return to Read Mode

from an ASO Mode or from a failed program or erase operation.

Software Reset may cause a return to Read Mode from undefined states that might result from invalid command

sequences. However, a Hardware Reset may be required to return to normal operation from some undefined

states.

There is no Software Reset latency requirement. The reset command is executed during the t_WPHperiod.

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HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.14

Error types and clearing procedures

There are three types of errors reported by the embedded operation status methods. Depending on the error

type, the status reported and procedure for clearing the error status is different. The following is the clearing of

error status:

• If an ASO was entered before the error the device remains entered in the ASO awaiting ASO read or a command

write.

• If an erase was suspended before the error the device returns to the erase suspended state awaiting flash array

read or a command write.

• Otherwise, the device will be in Standby state awaiting flash array read or a command write.

6.2.14.1

Embedded operation error (and invalid password)

If an error occurs during an embedded operation (program, erase, blank check, or password unlock) the

embedded algorithm controller remains active. The Status Register shows ready (SR[7] = 1) with valid status bits

indicating the reason for the error. The embedded algorithm controller remains active until the error status is

detected by the host system status monitoring and the error status is cleared.

During embedded algorithm error status the Status Register will show the following:

• SR[7] = 1; Valid status displayed

• SR[6] = X; May or may not be erase suspended during the EA error

• SR[5] = 1 on erase or blank check error, else = 0

• SR[4] = 1 on program error or invalid password, else = 0

• SR[3] = X; Treat as ‘don’t care’ (masked)

• SR[2] = 0; No Program in suspension

• SR[1] = 0

• SR[0] = X; Treat as ‘don’t care’ (masked)

When the embedded algorithm error status is detected, it is necessary to clear the error status in order to return

to normal operation, ready for a new read or command write. The error status can be cleared by writing:

• Reset command

• Status Register Clear command

Commands that are accepted during embedded algorithm error status are:

• Status Register Read

• Reset command

• Status Register Clear command

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.2.14.2

Protection error

If an embedded algorithm attempts to change data within a protected area (program, or erase of a protected

sector or OTP area) the device (EAC) goes busy for a period of 20 to 100 µs then returns to normal operation.

Protection mechanisms include DYB, PPB, and locks. During the busy period the Status Register shows not ready

with invalid status bits (SR[7] = 0). If a programming or erase operation is attempted to a locked region the

operation will be aborted and the failure will be indicated in the Status Register (see Table 17).

Commands that are accepted during the protection error status busy period are:

• Status Register Read

When the busy period ends the device returns to normal operation, and the Status Register shows ready with

valid status bits. The device is ready for flash array read or write of a new command.

After the protection error status busy period the Status Register will show the following:

• SR[7] = 1; valid status displayed

• SR[6] = X; may or may not be erase suspended after the protection error busy period

• SR[5] = 1 on erase error, else = 0

• SR[4] = 1 on program or password unlock error, else = 0

• SR[3] = X; treat as ‘don’t care’ (masked)

• SR[2] = 0; no program in suspension

• SR[1] = 1; error due to attempting to change a protected location

• SR[0] = X; treat as ‘don’t care’ (masked)

Commands that are accepted after the protection error status busy period are:

• Any command

For cases where the program status bit is set a further program operation will immediately clear SR[4]. For cases

where the erase status bit is set a further erase operation will immediately clear SR[6].

6.2.14.3

Write buffer abort

If an error occurs during a Write to Buffer command the device (EAC) remains busy. The Status Register shows

ready with valid status bits. The device remains busy until the error status is detected by the host system status

monitoring and the error status is cleared.

During embedded algorithm error status the Status Register will show the following:

• SR[7] = 1; valid status displayed

• SR[6] = X; m]ay or may not be erase suspended during the WBA error status

• SR[5] = 0; erase successful

• SR[4] = 1; programming related error, else = 0

• SR[3] = 1; write buffer abort

• SR[2] = 0; no Program in suspension

• SR[1] = 0; sector not locked during operation

• SR[0] = X; treat as ‘don’t care’ (masked)

When the WBA error status is detected, it is necessary to clear the error status in order to return to normal

operation, ready for a new read or command write. The error status can be cleared by writing:

• Write Buffer Abort Reset command

- Clears the status register and returns to normal operation

• Status Register Clear command

Datasheet

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Commands that are accepted during embedded algorithm error status are:

• Status Register Read

- Reads the status register and returns to WBA busy state

• Write Buffer Abort Reset command

• Status Register Clear command

During an embedded algorithm, read transactions not associated with a Status Register Read will toggle RWDS

and return indeterminate data.

6.2.14.4

ECC error

There are three methods for reporting to the host system when ECC errors are detected.

• There is an ECC Status ASO that provides the status of any error detection or correction action taken when

reading a half-page location within the ASO.

• The Interrupt (INT#) output may be enabled to indicate when either a one or two bit error is detected as a

half-page is read.

• A mode may be enabled to cause the read write data strobe (RWDS) to stop toggling (stall) when reading a

half-page containing a two bit error. The stall condition can be detected by the HYPERBUS™ master as a bus

error when RWDS does not transition for more than 32 clock cycles.

ECC Status Register (ECCSR)

ECCSR does not have user programmable non-volatile bits, all defined bits are volatile read only status. The

status of ECC in each half-page ECC unit is provided by the 16-bit ECC Status Register (ECCSR). The ECC Register

Read command is written followed by an ECC unit address. The contents of the Status Register then indicates,

for the selected ECC unit, whether there is an error in the ECC, the ECC unit data, or that ECC is disabled for that

ECC unit. Results regarding 2-bit ECC detection (ECCSR[4]) and 1-bit ECC correction (ECCSR[3]) are global and not

dependent on any specific ECC unit address.

Table 25

Bits

ECC Status Register bit assignments

Field

Default

state

Function

Type

Description

name

[15:5]

RFU

Reserved

Volatile, read only

0

Reserved for Future Use

1 = 2-bit ECC detection occurred since last

ECC Status ASO exit

0 = No 2-bit ECC detection occurred since

last ECC Status ASO exit

[4]

2BD 2-bit ECC detection Volatile, read only

0

1 = ECC correction performed since last

ECC Status ASO exit

1-bit ECC

[3]

[2]

CB

Volatile, read only

0

correction

0 = No ECC correction performed since

last ECC Status ASO exit

1 = Single bit error found in the ECC unit

error correction code

0 = No error

EECC

Error in ECC

1 = Single bit error correction in ECC unit

Error in ECC unit

data

[1]

[0]

EECCD

ECCD1

Volatile, read only

0

data

0 = No error

1 = ECC is disabled in selected ECC unit

0 = ECC is enabled in selected ECC unit

ECC disabled

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

ECCSR[0] = 1 indicates the ECC is disabled in the ECC unit.

ECCSR[1] = 1 indicates an error was corrected in the ECC unit data.

ECCSR[2] = 1 indicates an error was corrected in the ECC syndrome.

The default state of 0 for ECCSR[2:0] bits indicates no failures and ECC is enabled.

ECCSR[3] = 1 indicates that an ECC correction has been performed since the last ECC Status ASO exit. An ECC

Status ASO exit resets the ECCSR[3] value to the 0 state. Note that the ECC results for the current ECC Status Read

may impact the ECCSR[3] bit.

ECCSR[4] = 1 indicates that a 2-bit ECC detection has occurred since the last ECC Status Register ASO exit. An ECC

Status ASO exit resets the ECCSR[4] value to the 0 state. Note that the ECCSR[3:1] bits are not valid if a 2-bit ECC

event has occurred. If a 2-bit ECC detection has occurred the address accessed when the error was detected is

trapped in a pair of registers. Note that the ECC results for the current ECC Status Read may impact the ECCSR[4]

bit.

The ECCSR[15:5] bits are reserved. These have undefined HIGH or LOW values that can change from one ECC

status read to another. These bits should be treated as ‘don’t care’ and ignored by any software reading ECC

status.

The ECCSR is returned to the default state (0s) with a Hardware Reset or when the ECC Status ASO is exited with

a Software-Reset / ASO-Exit command.

Address Trap Register (ATR)

A register is provided to capture the half-page address where an ECC error is first encountered during a read of

the flash array. The 512-Mbit HYPERFLASH™ density devices only record the address where a two-bit error is

encountered. All other HYPERFLASH™ devices may use the ASPR[13] configuration bit to enable the Address Trap

Register to capture both 1-bit and 2-bit error locations. The Address Trap Register has a valid address when the

ECC Status Register (ECCSR) bit 3 or 4 =1.

The Error Lower Address Register and Error Upper Address Register contain the address that was accessed when

the error is detected. The failing bits may not be located at the exact address indicated in the registers but will

be located within the aligned 16-byte half-page where the error was detected. If errors are found in multiple

half-pages during a single read operation the address of the first failing half-page address is captured in the Error

Lower / Upper Address Registers. Only the address of the first enabled error type (2-bit or either 1-bit or 2-bit as

selected in ASPR[13]) encountered after POR, hardware reset, or exit from the ECC ASO is captured. Each ECC ASO

exit clears the address trap register and ECCSR[4:3] bits.

When two-bit error detection is not enabled and the same half-page is programmed more than once, ECC error

detection for that half-page is disabled so, no error can be recognized to trap the address.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 26

Density

Error Upper / Lower Address Trap Register bit assignments

Error Lower Address

Error Upper Address Register

Register

All

128 Mb

256 Mb

0

512 Mb

0

[15]

[14]

[13]

[12]

[11]

[10]

[9]

A15

A14

A13

A12

A11

A10

A9

0

[8]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

A8

A7

A6

A5

A4

A3

0

A24

A23

A22

A21

A20

A19

A18

A17

A16

A23

A22

A21

A20

A19

A18

A17

A16

A22

A21

A20

A19

A18

A17

A16

[0]

0

Error detection counter

The 512 Mb density HYPERFLASH™ devices do not support this feature. In HYPERFLASH™ devices other than the

512 Mbit density, a counter is provided to keep track of the number of 1-bit or 2-bit errors that occur as half-pages

are read from the flash array. Only errors recognized in the main array (no active ASO) will cause the error

detection counter to increment. The counter does not increment while the ECC ASO is entered.

The error detection counter is not cleared when the ECC ASO is exited. The counter will be set to ‘0’ on POR,

Hardware Reset or with the Counter Clear command sequence. The Counter Read and Counter Clear command

sequences operate only while in the ECC Status ASO. The 16-bit error detection counter will not increment past

FFFFh. If the error count has increased since the last ECC ASO exit, the ECC Address Trap Register holds the valid

address of the first ECC error found after the ECC ASO exit.

Note that during continuous read operations when a 2-bit error is detected and RWDS stops toggling (stalls), the

clock may continue toggling and the memory device will continue incrementing the data address and placing

new data on the DQ signals; any additional half-pages with errors that are encountered will be counted until CS#

is brought back HIGH.

During a burst read transaction only one error is counted for each half-page found with an error. Each read

transaction will cause a new read of the target half-page. If multiple read transactions access the same half-page

containing an error, the error counter will increment each time that half-page is read.

When two-bit error detection is not enabled and the same half-page is programmed more than once, ECC error

detection for that half-page is disabled so, no error can be recognized or counted.

RWDS Stall

The RWDS Stall Control bit in xVCR[2] can be used to enable RWDS stall when a two bit error is encountered. If

enabled (xVCR[2] = 0), upon DED, the RWDS will be driven LOW. RWDS will remain in the LOW state as long as CS#

remains asserted, normal RWDS functionality resumes as soon as CS# returns HIGH. If the RWDS stall control bit

is in the disabled state (xVCR[2] = 1) RWDS behavior is not impacted.

Datasheet

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001-99198 Rev. *O

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3

Data protection

6.3.1

Secure silicon region (SSR)

Each device has a 1024-byte one-time programmable SSR address space that is separate from the flash memory

array. The SSR area is divided into 32, individually lockable, 32-byte aligned and length regions.

In the 32-byte region starting at address zero:

• The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able

to program these bytes. Attempting to program 0s into these locations will fail and generate a Program Status

Error (SR[4] = 1).

• The next 4 higher address bytes (SSR lock bytes) are used to provide one bit per SSR region to permanently

protect each region from programming. The bytes are erased when shipped from Infineon. After an SSR region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the SSR lock bytes.

• The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU

bytes may be programmed by the host system but it must be understood that a future device may use those

bits for protection of a larger SSR space. The bytes are erased when shipped from Infineon.

The remaining regions are erased when shipped from Infineon, and are available for programming of additional

permanent data.

Refer to Figure 19 for a pictorial representation of the SSR memory space.

The SSR memory space is intended for increased system security. SSR values, such as the random number

programmed by Infineon, can be used to ‘mate’ a flash component with the system CPU / ASIC to prevent device

substitution.

The Configuration Register SSR Freeze (xVCR[10]) bit protects the entire SSR memory space from programming

when cleared (or programmed for NVCR) to ‘0’. This allows trusted boot code to control programming of SSR

regions then set the freeze bit to prevent further SSR memory space programming during the remainder of

normal power-on system operation.

6.3.1.1

Reading the secure silicon region memory space

Reading the SSR region is performed once the SSR ASO is entered using the SSR entry sequence. The SSR is

mapped to a specific sector identified during the SSR Entry command sequence. SSR Read operations within the

sector identified during the SSR Entry command sequence but outside the valid 8-KB SSR address range will yield

indeterminate data. Reads to sectors not overlaid by the SSR ASO will retrieve array data. A SSR Exit sequence

will return the device to the array read ASO.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.1.2

Programming secure silicon region memory space

Programming the SSR memory is performed once the SSR ASO is entered using the SSR Entry sequence. The

protocol of the SSR programming command is the same as normal array programming. The SSR programing

sequences can be issued multiple times to any given SSR address, but this address space can never be erased.

The valid address range for SSR program is depicted in Figure 19. SSR program operations outside the valid SSR

address range will ignore address A9 and higher and will alias into the valid SSR address range. SSR program

operations while Freeze = 0 will fail with no indication of the failure. The SSR address space is not protected by

the selection of an ASP Protection Mode. The Freeze SSR bit (xVCR.10) may be used to protect the SSR address

space. A SSR Exit sequence will return the device to the Read Mode.

32-byte OTP Region 31

32-byte OTP Region 30

32-byte OTP Region 29

When programmed to 0, each

lock bit protects its related 32

byte OTP region from any further

programming

.

32-byte OTP Region 3

32-byte OTP Region 2

32-byte OTP Region 1

32-byte OTP Region 0

Region 0 Expanded View

...

Reserved

16-byte Random Number

Lock Bits 31 to 0

Byte 0h

Byte 10h

Byte 1Fh

Figure 19

SSR address space

Table 27

Region

SSR address map

Byte address range

(Hex)

Contents

Initial delivery state (Hex)

Least significant byte of Infineon

programmed random number

0000h

...

Infineon programmed random

number

...

Most significant byte of Infineon

programmed random number

000Fh

Region locking bits

Byte 10 [bit 0] locks region 0 from

programming when = 0

...

Byte 13 [bit 7] locks region 31from

programming when = 0

Region 0

0010h–0013h

All bytes = FFh

0014h–001Fh

0020h–003Fh

0040h–005Fh

...

Reserved for Future Use (RFU)

Available for user programming

All bytes = FFh

Region 1

Region 2

...

Region 31

03E0h–03FFh

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.2

Advanced sector protection (ASP)

Advanced sector protection (ASP) is a set of independent hardware and software methods used to disable or

enable programming or erase operations, individually, in any or all sectors. This section describes the various

methods of protecting data stored in the memory array. An overview of these methods is shown in Figure 20.

ASP Configuration Register

(One-Time Programmable)

Password Protection

Persistent Protection

Method Lock Bit

(ASPR[2]=0)

(ASPR[1]=0)

Password Register (64b)

(One-Time Protect)

1. Bit is volatile, POR setting depends on protection method:

Persistent Protection Method defaults to 1.

1, 2, 3

PPB Lock Bit

0 = PPBs Locked

Password Protection Method defaults to 0.

2. Clearing to 0 locks all PPBs to their current state.

3. Once cleared to 0, requires power cycle to unlock.

1 = PPBs Unlocked

Persistent Protection Bits

Dynamic Protection Bits

Memory Array

(PPB) ^{5, 6}

PPB 0

(DYB) ^{7, 8, 9}

DYB 0

Sector 0

Sector 1

Sector 2

PPB 1

PPB 2

DYB 1

DYB 2

Sector N-2

Sector N-1

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

Sector N ⁴

4. N = Highest Address Sector.

5. 0 = Sector Protected (Programmed)

1 = Sector Unprotected (Erased)

6. PPBs set (programmed) individually, but cleared

(erased) collectively.

7. 0 = Sector Protected

1 = Sector Unprotected

8. Protect effective only if corresponding PPB is 1

(unprotected).

9. Volatile Bits: default to set (unprotected) upon power-up.

Figure 20

Advanced sector protection overview

Every flash memory array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it.

When either bit is ‘0’, the associated sector is protected from program and erase operations.

The PPB bits are protected from program and erase when the PPB lock bit is ‘0’. There are two methods for

managing the state of the PPB lock bit, Persistent Protection and Password Protection.

The Persistent Protection method sets the PPB lock bit to ‘1’ during POR or hardware reset so that the PPB bits

are unprotected by a device reset. Software reset does not affect the PPB lock bit. There is a command to clear

the PPB lock bit to ‘0’ to protect the PPB. There is no command in the Persistent Protection method to set the

PPB lock bit therefore the PPB lock bit will remain at ‘0’ until the next power-off or hardware reset. The Persistent

Protection method allows boot code the option of changing sector protection by programming or erasing the

PPB, then protecting the PPB from further change for the remainder of normal system operation by clearing (to

‘0’) the PPB lock bit. This is sometimes called Boot-Code Controlled Sector Protection.

The Password method clears the PPB lock bit to ‘0’ during POR or hardware reset to protect the PPB. A 64-bit

password may be permanently programmed and hidden for the Password method. A command can be used to

provide a password for comparison with the hidden password. If the password matches the PPB lock bit is set to

‘1’ to unprotect the PPB. A command can be used to clear the PPB lock bit to ‘0’. This method requires use of a

password to control PPB Protection.

The selection of the PPB Lock Management method is made by programming OTP bits in the ASP Configuration

Register so as to permanently select the method used.

The PPB bits are erased so that all flash memory array sectors are unprotected when shipped from Infineon.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.3

PPB Lock

The persistent protection lock bit is a volatile bit for protecting all PPB bits. When cleared to ‘0’, it locks all PPBs

and when set to ‘1’, it allows the PPBs to be changed. There is only one PPB lock bit per device.

The PPB Lock command is used to clear the bit to ‘0’. The PPB lock bit must be cleared to ‘0’ only after all the

PPBs are configured to the desired settings.

In Persistent Protection Mode, the PPB lock bit is set to ‘1’ during POR or a hardware reset. When cleared with the

PPB Lock Bit Clear sequence, no software command sequence can set the PPB lock bit, only another hardware

reset or power-up can set the PPB lock bit.

In the Password Protection Mode, the PPB lock bit is cleared to ‘0’ during POR or a hardware reset. The PPB lock

bit can only set to ‘1’ by the Password Unlock command sequence. The PPB lock bit can be cleared back to ‘0’

with the PPB Lock Bit Clear sequence.

6.3.4

Persistent Protection Bits (PPB)

The Persistent Protection Bits (PPB) are located in a separate non-volatile flash array. One of the PPB bits is

assigned to each sector. When a PPB is programmed to ‘0’, its related sector is protected from program and erase

operations. The PPB are programmed individually but must be erased as a group, similar to the way individual

words may be programmed in the main array but an entire sector must be erased at the same time.

Pre-programming and verification prior to erasure are handled by the EAC.

Programming a PPB bit requires the typical word programming time. During a PPB bit programming operation

or PPB bit erasing, the Status Register can be accessed to determine when the operation has completed. Erasing

all the PPBs requires typical sector erase time.

If the PPB lock bit is ‘0’, the PPB Program or Erase command does not execute and times-out without

programming or erasing the PPB. If an program or erase operation is attempted to the PPB bits when the PPB

lock bit is ‘0’, the operation will be aborted and the failure will be indicated in the Status Register (see Table 17).

The protection state of a PPB for a given sector can be verified by writing a PPB Status Read command when

entered in the PPB ASO.

6.3.5

Dynamic Protection Bits (DYB)

Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only

control protection for sectors that have their PPBs cleared. By issuing the DYB Set or Clear command sequences,

the DYB are set to ‘0’ or cleared to ‘1’, thus placing each sector in the protected or unprotected state respectively.

This feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy

removal of protection when changes are needed.

The DYB can be set to ‘0’ or cleared to ‘1’ as often as needed.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.6

Sector Protection States summary

Each sector can be in one of the following protection states:

• Unlocked – The sector is unprotected and protection can be changed by a simple command. The protection

state defaults to unprotected after a power cycle or hardware reset.

• Dynamically Locked – A sector is protected and protection can be changed by a simple command. The protection

state is not saved across a power cycle or hardware reset.

• Persistently Locked – A sector is protected and protection can only be changed if the PPB lock bit is set to ‘1’.

The protection state is non-volatile and saved across a power cycle or hardware reset. Changing the protection

state requires programming or erase of the PPB bits.

Table 28

Sector protection states

Protection bit values

Sector state

PPB lock bit

PPB

1

0

1

0

DYB

1

0

1

0

1

0

1

0

1

0

Unprotected – PPB and DYB are changeable

Protected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB not changeable, DYB is changeable

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.7

ASP Configuration Register

The ASP Configuration Register (ASPR) holds the non-volatile OTP bits for controlling security management.

Table 29

Bit

ASP Configuration Register

Default value

Name

[15:14]

1

Reserved

1-bit Address Trap Enable (not available on the 512-Mb device)

ASPR[13] = 0: Address Trap Register will trap both 1-bit and 2-bit errors

ASPR[13] = 1: Address Trap Register only traps 2-bit errors (legacy

functionality)

Reserved

Hybrid Burst Type Enable

ASPR[11] = 0: Hybrid – One Wrapped burst sequence followed by linear

burst

ASPR[11] = 1: Legacy – Wrapped burst sequence only

[13]

[12]

[11]

[10]

[9]

1

Reserved

DED / ECC On-Off Bit

ASPR[9] = 0: ECC On-Off Bit Disabled, Dual Error Detect Enabled

ASPR[9] = 1: ECC On-Off Bit Enabled, Dual Error Detect Disabled (default)

[8]

[7]

[6]

0

X

1

Reserved

Read Password Mode Enable

ASPR[5] = 0: Read Password Mode Permanently Enabled

ASPR[5] = 1: Read Password Mode Disabled (default from factory)

[5]

1

[4]

[3]

1

Reserved

Persistent / Password Protection Mode Lock Bits

ASPR[2:1] = 00: Not allowed

[2:1]

[0]

1

ASPR[2:1] = 01: Password Mode Permanently Enabled, ASPR Frozen

ASPR[2:1] = 10: Persistent Mode Permanently Enabled, ASPR Frozen

ASPR[2:1] = 11: Persistent Mode Temporarily Enabled (default from factory)

Reserved

As shipped from the factory, all devices default to the Persistent Protection method, with all sectors unprotected,

when power is applied. The device programmer or host system can then choose which sector protection method

to use. Programming either of the following two, one-time programmable, non-volatile bits, locks the part

permanently in that mode:

• Persistent Protection Mode Lock Bit (ASPR[1])

• Password Protection Mode Lock Bit (ASPR[2])

If both lock bits (ASPR[2] and ASPR[1]) are selected to be programmed at the same time, the operation will abort

and Status Register bits SR[4] and SR[1] will be set to indicate the failure. Once the Password Mode Lock Bit is

programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the protection scheme

are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently

disabled. Programming attempts to the ASPR after either ASPR[2] or ASPR[1] have been programmed will be

aborted and Status Register bits SR[4] and SR[1] will be set to indicate the failure.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

If the Password Mode is chosen, the password must be programmed prior to setting the corresponding Lock

Register Bit. The four-word password must be programmed in order in a 0-1-2-3 sequence, other programming

sequences will result in undefined behavior. After the Password Protection Mode Lock Bit is programmed, a

power cycle, hardware reset, or PPB Lock Bit Set command is required to set the PPB lock bit to ‘0’ to protect the

PPB array.

The programming time of the ASP Configuration Register is the same as the typical word programming time.

During a ASP Configuration Register programming EA. The system can also determine the status of the ASPR

programming by reading the Status Register. See “Error types and clearing procedures” on page 55 for

information on these status bits.

6.3.8

Persistent Protection Mode

The Persistent Protection method sets the PPB lock bit to ‘1’ during POR or hardware reset so that the PPB bits

are unprotected by a device reset. There is a command to clear the PPB lock bit to ‘0’ to protect the PPB. There

is no command in the Persistent Protection method to set the PPB lock bit to ‘1’ therefore the PPB lock bit will

remain at ‘0’ until the next power-off or hardware reset.

6.3.9

Password Protection Mode

Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by

requiring a 64-bit password for setting the PPB lock bit. In addition to this password requirement, after power-up

or hardware reset, the PPB lock bit is cleared to ‘0’ to ensure protection at power-up. Successful execution of the

Password Unlock command by entering the entire password sets the PPB lock bit to ‘1’, allowing for sector PPB

modifications.

Password Protection Notes:

• The Password Program Command is only capable of programming 0’s.

• The password is all 1’s when shipped from Infineon. It is located in its own memory space and is accessible

through the use of the Password Program and Password Read commands.

• All 64-bit password combinations are valid as a password.

• Once the Password is programmed and verified, the Password Protection Mode Locking Bit must be

programmed (to ‘0’) in order to prevent reading the password.

• The Password Protection Mode Lock Bit, once programmed (to ‘0’), prevents reading the 64-bit password on

the data bus and further password programming. All further program and read commands to the password

region are disabled and these commands are ignored. Attempted programming of a protected Password will

set the Sector Lock Status Bit (SR[1]) and the Program Status Bit (SR[4]). If a further programming operation is

attempted on either the Password or the Password Protection Mode Lock Bit the operation will be aborted and

the failure will be indicated in the Status Register (see Table 17). There is no means to verify what the password

is after the Password Protection Mode Lock Bit is programmed. Password verification is only allowed before

selecting the Password Protection Mode.

• The Password Mode Lock Bit is not erasable.

• For the unlocking function to occur, the password portion can be entered in any order as long as the entire 64-bit

password is entered. If the Password Unlock command provided password does not match the hidden internal

password, the unlock operation fails in the same manner as a programming operation on a protected sector.

The Status Register will return to the ready state with the Program Status Bit set to ‘1’ indicating a failed

programming operation due to a locked sector. In this case it is a failure to change the state of the PPB lock bit

because it is still protected by the lack of a valid password.

• The device requires approximately t_PSWD= 100 µs for setting the PPB lock bit after the valid 64-bit password is

given to the device.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

• The Password Unlock command cannot be accepted any faster than once every t_PSWD(see Table 64). This makes

it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in

an attempt to correctly match a password. The EA status checking methods may be used to determine when

the EAC is ready to accept a new password command.

• If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB lock bit.

6.3.10

Read Password Protection Mode

The Read Password Mode can replace the default “Password Protection Mode” on page 66. The Read Password

Mode is enabled to replace the default PPB Password Protection Mode when the user programs ASPR[5] = 0. The

Read Password Mode is not active until the password is programmed and ASPR[2] is programmed to ‘0’.

The Read Password Protection Mode enables protecting the flash memory array from read, program and erase.

Only the lowest or highest (256-KB) sector address range, selected by the Non-volatile Configuration Register bits

xVCR[9:8], remains readable until a successful Password Unlock command is completed. Note that reads from

the read-protected portion of the array will alias back to the readable sector.

In this mode the PPB lock bit is used to control the high order bits of address. When the PPB lock bit is ‘1’, the

address bits operate normally. When the PPB lock bit is ‘0’, the address bits that select a main array sector address

range are forced either to 0s (xVCR[9:8] = 00 or 10) or to 1s (xVCR[9:8] = 01 or 11) to select the lowest or highest

address flash memory array address range per the table below. When xVCR[9:8] = 00 or 10, the bottom (zero

address) 256 KB of the array is readable. When xVCR[9:8] = 01 or 10, the top (maximum address) 256 KB of the

array is readable.

Table 30

ASPR bit

2

ASP Configuration Register selection of Persistent and Password Protection Modes

Default value

Name

1

Persistent / Password Protection Mode Lock Bits

ASPR[2:1] = 00: Not allowed

ASPR[2:1] = 01: Password Mode Permanently Enabled

ASPR[2:1] = 10: Persistent Mode Permanently Enabled

ASPR[2:1] = 11: Persistent Mode Temporarily Enabled (default from factory)

1

Table 31

xVCR bit

xVCR mapping of boot block address range

Default value

Name

00 - Map Parameter-Sectors and Read Password Sectors mapped into lowest

addresses.

01 - Map Parameter-Sectors and Read Password Sectors mapped into highest

addresses.

xVCR[9:8]

11

10 - Uniform Sectors with Read Password Sector mapped into lowest

addresses.

11 - Uniform Sectors with Read Password Sector mapped into highest

addresses.

The PPB bits are protected from program and erase when the PPB lock bit is ‘0’ and may be programmed or

erased when the PPB lock bit is ‘1’.

The PPB lock bit is set to ‘0’ by POR or hardware reset, same as in PPB Password Protection Mode.

Read Password Protection Notes

• When the Read Password OPN option is ordered, the user can program the ASPR[5] bit to ‘0’ and use Read

Password, or not, as desired.

• The command sequence for programming, reading, and locking of the Password for Read Password Method is

the same as the default for the PPB Password Method.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

• When the Read Password Mode and Password Protection Mode are enabled (i.e. ASPR[2] and ASPR[5] are

programmed to ‘0’), then all addresses are redirected to the boot sector until the password unlocking sequence

is properly entered, with the correct password. At which time, the Read Password Mode is disabled and all

addressing will select the proper location.

• If a system hardware reset occurs, then the Read Password Mode is re-enabled.

• ASPR[5] is used to select between Read Password versus PPB Password options. If ASPR[5] = 0 then the device

is ready for Read Password. However, Read Password is not enabled until ASPR[2] = 0. At which point, all

addresses select only within the top or bottom sectors, until the device is unlocked with the proper unlocking

sequence and password. When ASPR[2] = 1 the addresses select normally. This allows users to program in code,

test it, provide a password, and then lock it by programming ASPR[2] = 0.

• The Read Password command sequence return undefined results if sent when Read Password Protection is in

use. The PPB lock bit may only be returned to ‘0’ by a Hardware Reset, POR or the PPB Lock Bit Clear command

sequence.

• Only the ID Read command, Password Unlock command and array reads are valid during Read Password Mode

while the PPB lock bit = 0. Other commands are disabled until the password is supplied to enable reading of the

entire device and normal command operation.

• When Read Password Protection Mode is active (ASPR[5] = 0, ASPR[2] = 0, PPB Lock Bit = 0), reading of the main

array is allowed but forced to have only the boot sector visible via the forcing of memory sector address to 0 or

1s. Reading the DYB, or PPB address space returns undefined data.

• Programming memory spaces or writing registers is not allowed when Read Password Protection Mode is active.

RESET operates normally, and bus protocol may be modified by resetting mode bits.

6.3.11

Hybrid Burst

An additional type of burst that combines one wrapped burst followed by linear burst, is supported by all

members of the HYPERFLASH™ family.

The beginning of a hybrid burst will wrap once within the target address wrapped burst length group, before

switching to linear burst of data beyond the end of the initial wrapped burst length group. Hybrid burst is

supported for 16-byte and 32-byte but not 64-byte wrapped burst length groups.

Table 32

Bit

ASPR bit assignment for hybrid burst type enable

Default value

Name

Hybrid Burst Type Enable

0 = Hybrid - One Wrapped burst sequence followed by linear burst

1 = Legacy - Wrapped burst sequence only

[11]

1

Example burst sequences for 32-byte, and 16-byte hybrid burst reads:

1. 32-byte example (wrap within 32-byte boundary before transitioning to linear burst)

a. 06-07-08-09-0A-0B-0C-0D-0E-0F-00-01-02-03-04-05-10-11

a. 0E-0F-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-10-11

2. 16-byte example (wrap within 16-byte boundary before transitioning to linear burst)

a. 06-07-00-01-02-03-04-05-08-09

b. 03-04-05-06-07-00-01-02-08-09

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

6.3.12

INT# Output

The INT# pin is an open-drain output used to indicate to the host system that an event has occurred within the

flash device. The user can select to transition the INT# output pin to the active (LOW) state when:

• Transitioning from the Busy to the Ready state

• 2-bit ECC error is detected

• Transitioning from the Busy to the Ready state

The interrupt sources are enabled by the Interrupt Configuration Register.

Operation is controlled with the Interrupt Configuration Register where the INT# output (normally HIGH) is

enabled. The Interrupt Configuration Register determines when an internal event is enabled to trigger a HIGH to

LOW transition on the INT# output pin. The Interrupt Status Register indicates what enabled internal event(s)

have occurred since the last time the Interrupt Status Register has been cleared. If enabled, the INT# output pin

will then transition from HIGH to LOW upon the occurrence of an enabled event. Once the host recognizes that

INT# has transitioned to the LOW state the Interrupt Status Register can be read to determine which internal

event was responsible.

The INT# output can be forced to transition back to the HIGH impedance state (returned HIGH by an external

pull-up resistance) using three methods:

• Disable the INT# output by loading ‘1’ into bit 15 of the Interrupt Configuration Register. The Interrupt Status

Register will be cleared upon loading ICR[15] with ‘1’.

• Disabletheeventchannel responsiblefor causingthe outputtotransitionLowbyloading‘1’intotheappropriate

event enable bit in the Interrupt Configuration Register. The associated bit in the Interrupt Status Register will

be cleared upon loading ‘1’ into the corresponding bit in the ICR.

• Reset the appropriate bit (by writing ‘1’) in the Interrupt Status Register bit that indicates which internal event

occurred to cause the output to go LOW. All Interrupt Status Register bits that are LOW and are also enabled in

the Interrupt Configuration Register must be reset before the INT# output will return HIGH.

The INT# output will also be returned to the default (disabled, HIGH-Z) state with a Hardware Reset

(RESET# = LOW) or a power-on reset. Hardware reset and power-on reset disable all interrupts by setting the

Interrupt Configuration Register back to the default (all interrupts disabled) state.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Embedded operations

Table 33

Interrupt Configuration Register

POR RESET#

Bits Function

Type

default default

Description

state

1 = INT# output disabled (HIGH or Open-Drain)

0 = INT# output enabled, internal events will cause a HIGH

to LOW transition

INT#

Output

Enable

[15]

1

[14] Reserved

[13:5] Reserved

1

Reserved

Reserved for Future Use

1 = Ready/Busy transitions will not transition the INT#

output

0 = A Busy to Ready transition will cause a HIGH to LOW

transition on the INT# output

Reserved for future use

[4]

READY

1

Volatile,

Read / Write

[3] Reserved

[2] Reserved

1

1 = 2-bit error detection will not transition the INT# output

0 = 2-bit error detection will cause a HIGH to LOW

transition on the INT# output

1 = 1-bit error detection will not transition the INT# output

0 = 1-bit error detection will cause a HIGH to LOW

transition on the INT# output

2-bit Error

[1]

1

Detect

1-bit Error

Detect

[0]

Table 34

Bits

Interrupt Status Register

POR RESET#

default default

Function

Type

Description

Reserved for Future Use

1 = A Busy to Ready transition has not occurred

0 = A Busy to Ready transition has occurred

Reserved for future use

1 = POR has not occurred

0 = POR has occurred

state

1

[15:5]

[4]

Reserved

READY

1

0

1

3]

Reserved

Volatile,

Read / Write

POR

Detect

[2]^{[65, 66]}

1 = 2-bit error detection has not occurred

0 = 2-bit error detection has occurred

1 = 1-bit error detection has not occurred

0 = 1-bit error detection has occurred

2-bit Error

Detect

[1]

[0]

1

1-bit Error

Detect

Notes

62.Both POR and hardware reset results in all interrupt channels being disabled.

63.Hardware reset results in all ISR bits being set to ‘1’.

64.POR results in the ISR POR Detect bit (ISR[2]) being cleared to ‘0’, all other bits to be set to ‘1’.

65.ISR[2] is cleared (to ‘0’) during POR and is only set (to ‘1’) with a hardware reset (RESET# = 0) or with a write

to the ISR.

66.The INT# output state is not affected by the value of ISR[2].

67.Writing to the ISR can only flip bits from the ‘0’ to the ‘1’ state. Only an interrupt occurrence flips an ISR bit

from the ‘1’ to the ‘0’ state.

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

7

Device ID and Common Flash Interface (ID-CFI) ASO map

7.1

Device ID and Common Flash Interface (ID-CFI) ASO map — standard

The device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID and basic feature

set information for the device. For additional information, see “ID-CFI ASO” on page 51.

Table 35

Word address

(SA) + 0000h

ID (Autoselect) address map

Data

Description

0001h

007Eh

Infineon Manufacturer ID

Device ID

(SA) + 0001h

(SA) + 0002h

(SA) + 0003h

(SA) + 0004h

(SA) + 0005h

(SA) + 0006h

(SA) + 0007h

(SA) + 0008h

(SA) + 0009h

(SA) + 000Ah

(SA) + 000Bh

Reserved

RFU

Lower Software bits

Bit 0 - Status Register support:

1 = Status Register supported

0 = Status Register not supported

Bit 1 - DQ Polling support:

1 = DQ Bits Polling supported

0 = DQ Bits Polling not supported

(SA) + 000Ch

0005h

Bit 3–2 - Command Set support:

11 = Reserved

10 = Reserved

01 = HYPERFLASH™ Command Set

00 = Classic Command Set

Bits 4–F – Reserved = 0

Upper Software bits

(SA) + 000Dh

(SA) + 000Eh

(SA) + 000Fh

Reserved

0070h = 512 Mb @ 1.8 V

006Fh = 512 Mb @ 3.0 V

0072h = 256 Mb @ 1.8 V

0071h = 256 Mb @ 3.0 V

Device ID

0074h = 128 Mb @ 1.8 V

0073h = 128 Mb @ 3.0 V

0000h

Device ID

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

Table 36

CFI query identification string

Word address

Data

Description

(SA) + 0010h

(SA) + 0011h

(SA) + 0012h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

(SA) + 0013h

(SA) + 0014h

0002h

0000h

Primary OEM Command Set

(SA) + 0015h

(SA) + 0016h

0040h

0000h

Address for Primary Extended table

Alternate OEM Command Set

(00h = none exists)

(SA) + 0017h

(SA) + 0018h

0000h

Address for alternate OEM Extended table

(00h = none exists)

(SA) + 0019h

(SA) + 001Ah

0000h

Table 37

Word address

(SA) + 001Bh

CFI system interface string

Data

Description

0017h for V_CC= 1.8 V

0027h for V_CC= 3.0 V

V_CCMin. (erase / program) (D7–D4: volts, D3–D0: 100 millivolts)

0019h for V_CC= 1.8 V

0036h for V_CC= 3.0 V

(SA) + 001Ch

V_CCMax. (erase / program) (D7–D4: volts, D3–D0: 100 millivolts)

V_PPMin. voltage (00h = no V_PPpin present)

(SA) + 001Dh

(SA) + 001Eh

(SA) + 001Fh

0000h

0009h

V

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single word write 2^Nµs

Typical timeout for max

multi-byte program, 2^Nµs

(00h = Not supported)

(SA) + 0020h

(SA) + 0021h

(SA) + 0022h

0009h

000Ah

0012h (512 Mb)

Typical timeout per individual block erase 2^Nms

0011h (256 Mb) Typical timeout for full chip erase 2^Nms (00h = Not supported)

0010h (128 Mb)

(SA) + 0023h

(SA) + 0024h

(SA) + 0025h

0002h

Max. timeout for single word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical

(00h = Not supported)

(SA) + 0026h

0002h

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

Table 38

CFI device geometry definition

Word address

Data

Description

001Ah (512 Mb)

(SA) + 0027h

0019h (256 Mb) Device Size = 2^Nbyte

0018h (128 Mb)

(SA) + 0028h

(SA) + 0029h

(SA) + 002Ah

(SA) + 002Bh

0000h

0009h

0000h

Flash Device Interface Description 0 = ×8-only, 1 = ×16-only, 2 = ×8 /

×16 capable

Max. number of byte in multi-byte write = 2^N

(00 = Not supported)

Number of Erase Block Regions within device

1 = Uniform Device, 2 = Boot Device

(SA) + 002Ch

0001h

(SA) + 002Dh

(SA) + 002Eh

(SA) + 002Fh

(SA) + 0030h

(SA) + 0031h

(SA) + 0032h

(SA) + 0033h

(SA) + 0034h

(SA) + 0035h

(SA) + 0036h

(SA) + 0037h

(SA) + 0038h

(SA) + 0039h

(SA) + 003Ah

(SA) + 003Bh

(SA) + 003Ch

Erase Block Region 1 information (refer to JEDEC JESD68-01 or

JEP137 specifications)

See description 00FFh, 0000h, 0000h, 0004h = 512 Mb (256 × 2-Mb blocks)

007Fh, 0000h, 0000h, 0004h = 256 Mb (128 × 2-Mb blocks)

003Fh, 0000h, 0000h, 0004h = 128 Mb (64 × 2-Mb blocks)

0000h

Erase Block Region 2 information (refer to JEDEC JESD68-01 or

JEP137 specifications)

Erase Block Region 3 information (refer to JEDEC JESD68-01 or

JEP137 specifications)

Erase Block Region 4 information (refer to JEDEC JESD68-01 or

JEP137 specifications)

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

Table 39

Word address

(SA) + 0040h

CFI primary vendor-specific extended query

Data

0050h

0052h

0049h

0031h

0035h

Description

(SA) + 0041h

(SA) + 0042h

(SA) + 0043h

(SA) + 0044h

Query-unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1–0)

00b = Required, 01b = Not required

Process Technology (Bits 5–2)

0000b = 0.23 µm floating gate

0001b = 0.17 µm floating gate

0010b = 0.23 µm MIRRORBIT™

0011b = 0.13 µm floating gate

0100b = 0.11 µm MIRRORBIT™

0101b = 0.09 µm floating gate

0110b = 0.09 µm MIRRORBIT™

0111b = 0.065 µm MIRRORBIT™ Eclipse

1000b = 0.065 µm MIRRORBIT™

1001b = 0.045 µm MIRRORBIT™

Erase Suspend

(SA) + 0045h

001Ch

0 = Not supported

1 = Read only

(SA) + 0046h

0002h

2 = Read and Write

Sector Protect

(SA) + 0047h

(SA) + 0048h

0001h

0000h

00 = Not supported

X = Number of sectors in smallest group

Temporary Sector Unprotect

00 = Not supported

01 = Supported

Sector Protect / Unprotect Scheme

04 = High Voltage method

05 = Software Command Locking method

08 = Advanced Sector Protection method

Simultaneous operation

00 = Not supported

X = Number of banks

Burst Mode type

00 = Not supported

(SA) + 0049h

0008h

(SA) + 004Ah

(SA) + 004Bh

0000h

0001h

01 = Supported

Datasheet

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512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

Table 39

CFI primary vendor-specific extended query (Continued)

Word address

Data

Description

Page Read Mode type

00 = Not supported

(SA) + 004Ch

0000h

01 = 4 Word Page

02 = 8 Word Page

03 =16 Word Page

ACC (Acceleration) supply minimum

00 = Not supported

D7–D4: Volt

D3–D0: 100 mV

ACC (Acceleration) supply maximum

00 = Not supported

(SA) + 004Dh

(SA) + 004Eh

0000h

D7–D4: Volt

D3–D0: 100 mV

WP# Protection

00h = Flash device without WP Protect (No boot)

01h = Eight 8-KB Sectors at top and bottom with WP (Dual boot)

02h = Bottom Boot Device with WP Protect (Bottom boot)

03h = Top Boot Device with WP Protect (Top boot)

04h = Uniform, bottom WP Protect (Uniform bottom boot)

05h = Uniform, top WP Protect (Uniform top boot)

06h = WP Protect for all sectors

07h = Uniform, top or bottom WP Protect

Program Suspend

(SA) + 004Fh

(SA) + 0050h

0000h

0001h

00 = Not supported

01 = Supported

Unlock Bypass

(SA) +0051h

(SA) + 0052h

0000h

000Ah

00 = Not supported

01 = Supported

Secure silicon sector (Customer OTP Area = 1024B) Size 2^N(bytes)

Software features

Bit 0: Status Register polling (1 = Supported, 0 = Not supported)

Bit 1: DQ polling (1 = Supported, 0 = Not supported)

Bit 2: New Program Suspend / Resume commands (1 = Supported, 0 = Not

supported)

Bit 3: Word Programming (1 = Supported, 0 = Not supported)

Bit 4: Bit-Field Programming (1 = Supported, 0 = Not supported)

Bit 5: Autodetect Programming (1 = Supported, 0 = Not supported)

Bit 6: RFU

(SA) + 0053h

008Dh

Bit 7: Multiple Writes per line (1 = Supported, 0 = Not supported)

Page size = 2^Nbytes

Erase Suspend Timeout maximum < 2^N(µs)

Program Suspend Timeout maximum < 2^N(µs)

(SA) + 0054h

(SA) + 0055h

(SA) + 0056h

0005h

0006h

Datasheet

75

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Device ID and Common Flash Interface (ID-CFI)

ASO map

Table 39

Word address

(SA) + 0057h to

CFI primary vendor-specific extended query (Continued)

Data

Description

FFFFh

Reserved for Future Use

(SA) + 0077h

Embedded Hardware Reset Timeout maximum < 2^N(µs)

Reset with Reset Pin

Non-Embedded Hardware Reset Timeout maximum < 2^N(µs)

Power-On Reset

(SA) + 0078h

0006h

0009h

(SA) + 0079h

7.2

Device ID and Common Flash Interface (ID-CFI) ASO Map — automotive

grade / AEC-Q100

The CFI primary vendor-specific extended query for automotive grade / AEC-Q100 is extended to include

Electronic Marking information for device traceability (see Table 40).

Table 40

Word address

Device ID and Common Flash Interface (ID-CFI) ASO map^[68]

Number of

bytes

Data

Example of actual Hex Read Out of

Data field

format

of data

example data

Size of Electronic

Marking

Revision of

Electronic Marking

(SA) + 0080h

(SA) + 0081h

1

Hex

19

0013h

1

0001h

004Ch, 0044h,

0038h, 0037h,

0032h, 0037h,

0030h

(SA) + 0082h

Fab Lot #

7

ASCII

LD87270

(SA) + 0089h

(SA) + 008Ah

(SA) + 008Bh

Wafer #

Die X coordinate

Die Y coordinate

1

Hex

23

10

15

0017h

000Ah

000Fh

0042h, 0052h,

0033h, 0033h,

0031h, 0035h,

0030h

(SA) + 008Ch

(SA) + 0093h

Class Lot #

7

ASCII

NA

BR33150

NA

Reserved for Future

13

Undefined

Note

68.Fab Lot # + Wafer # + Die X coordinate + Die Y coordinate provides unique ID for each device.

Datasheet

76

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Software interface reference

8

Software interface reference

8.1

Command summary

Table 41

Command definitions

[69, 70, 71, 72]

Bus cycles

Addr

Command sequence

Cycles

First

Addr

Second

Third

Fourth

Fifth

Sixth

Seventh

Data

RD

F0

Addr

Data

Addr

Data

Addr Data

Addr Data Addr Data

[72]

Read

Reset / ASO Exit

1

2

1

3

4

RA

[73, 82]

XXX

555

[84]

Status Register Read

70

XXX

RD

Status Register Clear

71

Enter Deep Power-Down

Program Power-On Reset Timer Register

AA

2AA

55

XXX

555

B9

34

AA

XXX

PORTime

Notes

69.All values are in hexadecimal. All addresses reference 16-bit words.

70.Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing

ID / Device ID), Indicator Bits, Secure Silicon Region Read, SSR Lock Read, and 2nd cycle of Status Register

Read.

71.Data bits DQ15–DQ8 are ‘don’t care’ in command sequences, except for RD, PD, WC and PWD.

72.Address bits A_MAX–A11 are ‘don’t care’ for unlock and command cycles, unless SA or PA required. (A_MAXis the

highest address pin.)

73.No unlock or command cycles required when reading array data.

74.The Reset command is required to return to reading array data when device is in the ID-CFI (Autoselect)

Mode, or if DQ5 goes HIGH (while the device is providing status data).

75.Command is valid when device is ready to read array data or when device is in ID-CFI (Autoselect) Mode.

76.The system can read and program / program suspend in non-erasing sectors, or enter the ID-CFI ASO, when

in the Erase Suspend Mode. The Erase Suspend command is valid only during a sector erase operation.

77.The Erase Resume / Program Resume command is valid only during the Erase Suspend / Program Suspend

Modes.

78.Issue this command sequence to return to READ Mode after detecting device is in a Write-to-Buffer-Abort

state. Note that the full command sequence is required if resetting out of ABORT.

79.The Exit command returns the device to reading the array.

80.For PWDx, only one portion of the password can be programmed per each ‘A0’ command. Portions of the

password must be programmed in sequential order (PWD0–PWD3).

81.All ASP Register bits are one-time programmable. The program state = 0 and the erase state = 1. Both the

Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at

the same time or the ASPR Register Bits Program operation aborts and returns the device to Read Mode.

ASPR Register bits that are reserved for future use are undefined and may be 0’s or 1’s.

82.If any of the Entry commands was issued, an Exit command must be issued to reset the device into Read

Mode.

83.Bit 0 = 0 indicates the Protected State, Bit 0 = 1 indicates the Unprotected State. Bits 1 through 15 are all 1s.

The sector address for DYB set, DYB clear, or PPB Program command may be any location within the sector;

the lower order bits of the sector address are ‘don’t care’.

84.Data out during a Status Register Read transaction, DYB Read, PPB Read, SA Protection Read, Password

Read, POR Timer Read, ICR Read, ISR Read, VCR Read, NVCR Read, FIDR Read, ASPR Read, PPBL Read

Register Read transactions is only valid during the first word output by the device. Subsequent data values

output if CK/CK# continue to toggle while CS# remains LOW are undefined.

85.Data out during a SA Protection Status Read indicates whether the indicated sector is protected in bits 0–2.

Bit 0 – Indicates whether the indicated sector is protected (0 = protected, 1 = unprotected).

Bit 1 – Protected using the sector’s DYB bit (0 = protected, 1 = unprotected).

Bit 2 – Protected using the sector’s PPB bit (0 = protected, 1 = unprotected).

Bits 3 through 15 are all 1s.

86.The smaller parameter-sectors need to include A[16:11] as part of the address identifying the target

parameter-sector during erase and program command sequences.

87.Both the ID (Autoselect) Entry and the CFI Entry allows access to the same ID/CFI data set. All data contained

in within the ID/CFI data set is available after using either the ID or CFI Entry sequences.

Datasheet

77

001-99198 Rev. *O

2022-10-26

512 Mb (64 MB)/256 Mb (32 MB)/128 Mb (16 MB) HYPERFLASH™ Family

HYPERBUS™, 3.0 V/1.8 V

Software interface reference

Table 41

Command definitions (Continued)

[69, 70, 71, 72]

Bus cycles

Command sequence

Cycles

First

Addr

Second

Third

Addr

Fourth

Fifth

Sixth

Seventh

Data

AA

Addr

Data

3C

36

Addr

XXX

Data

RD

Addr Data

Addr Data Addr Data

Read Power-On Reset Timer Register

Load Interrupt Configuration Register

Read Interrupt Configuration Register

Load Interrupt Status Register

4

555

2AA

55

555

PORTime

ICR

AA

55

RD

AA

55

C4

37

ICR

AA

55

ISR

RD

Read Interrupt Status Register

AA

55

C5

38

ISR

Load Volatile Configuration Register

Read Volatile Configuration Register

AA

55

VCR

RD

AA

55

C7