S27KS0642GABHB023 [INFINEON]
64MBit 1.8 V Automotive (105°C) HyperBus HYPERRAM Gen 2.0 in 24 FBGA;
| 型号： | S27KS0642GABHB023 |
| 厂家： | 
Infineon |
| 描述： | 64MBit 1.8 V Automotive (105°C) HyperBus HYPERRAM Gen 2.0 in 24 FBGA |
| 文件： | 总59页 (文件大小：1270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S27KL0642, S27KS0642
64Mb HYPERRAM™ self-refresh DRAM
(PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Features
• Interface
- HYPERBUS™ interface
- 1.8 V / 3.0 V interface support
• Single-ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals
- Chip select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as Read data strobe
• Input during write transactions as Write data mask
- Optional DDR center-aligned read strobe (DCARS)
• During read transactions RWDS is offset by a second clock, phase shifted from CK
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• Performance, power, and packages
- 200 MHz maximum clock rate
- DDR - transfers data on both edges of the clock
- Data throughput up to 400 MBps (3,200 Mbps)
- Configurable burst characteristics:
• Linear burst
- Wrapped burst lengths:
• 16 bytes (8 clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
• 128 bytes (64 clocks)
- Hybrid option - one wrapped burst followed by linear burst
• Configurable output drive strength
• Power modes
- Hybrid Sleep mode
- Deep power-down
• Array refresh
- Partial memory array (1/8, 1/4, 1/2, and so on)
- Full
• Package
- 24-ball FBGA
• Operating temperature range
- Industrial (I): -40°C to +85°C
- Industrial Plus (V): -40°C to +105°C
- Automotive, AEC-Q100 grade 3: -40°C to +85°C
- Automotive, AEC-Q100 grade 2: -40°C to +105°C
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 59
002-24692 Rev. *I
2022-04-29
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Performance summary
• Technology
- 38-nm DRAM
Performance summary
Read transaction timings
Unit
200 MHz
35 ns
Maximum clock rate at 1.8 V VCC/VCC
Q
Q
Maximum clock rate at 3.0 V VCC/VCC
Maximum access time (tACC
)
Maximum current consumption
Burst read or write (Linear burst at 200 MHz, 1.8 V)
Burst read or write (Linear burst at 200 MHz, 3.0 V)
Standby (CS# = VCC = 3.6 V, 105°C)
Unit
25 mA
30 mA
360 µA
15 µA
330 µA
12 µA
Deep power down (CS# = VCC = 3.6 V, 105°C)
Standby (CS# = VCC = 2.0 V, 105°C)
Deep power down (CS# = VCC = 2.0 V, 105°C)
Logic block diagram
CS#
Memory
CK/CK#
RWDS
Control
Y Decoders
Data Latch
I/O
Logic
DQ[7:0]
RESET#
Data Path
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Table of contents
Table of contents
Features ...........................................................................................................................................1
Performance summary ......................................................................................................................2
Logic block diagram ..........................................................................................................................2
Table of contents...............................................................................................................................3
1 General description.........................................................................................................................5
1.1 HYPERBUS™ interface.............................................................................................................................................5
2 Product overview ...........................................................................................................................8
2.1 HYPERBUS™ interface.............................................................................................................................................8
3 Signal description...........................................................................................................................9
3.1 Input/output summary...........................................................................................................................................9
4 HYPERBUS™ transaction details .....................................................................................................10
4.1 Command/address bit assignments....................................................................................................................10
4.2 Read transactions .................................................................................................................................................15
4.3 Write transactions (Memory array write).............................................................................................................16
4.4 Write transactions without initial latency (Register write).................................................................................18
5 Memory space ..............................................................................................................................19
5.1 HYPERBUS™ interface...........................................................................................................................................19
6 Register space ..............................................................................................................................20
6.1 HYPERBUS™ interface...........................................................................................................................................20
6.2 Device Identification Registers ............................................................................................................................................................ 20
6.2.1 Density and row boundaries .............................................................................................................................21
6.3 Register space access ...........................................................................................................................................22
6.3.1 Configuration Register 0....................................................................................................................................22
6.3.2 Wrapped burst ...................................................................................................................................................24
6.3.3 Configuration Register 1....................................................................................................................................27
7 Interface states ............................................................................................................................29
8 Power conservation modes............................................................................................................30
8.1 Interface standby..................................................................................................................................................30
8.2 Active clock stop ...................................................................................................................................................30
8.3 Hybrid sleep ..........................................................................................................................................................30
8.4 Deep power-down ................................................................................................................................................31
9 Electrical specifications.................................................................................................................32
9.1 Absolute maximum ratings[45]............................................................................................................................32
9.2 Input signal overshoot..........................................................................................................................................32
9.3 Latch-up characteristics.......................................................................................................................................33
9.4 Operating ranges ..................................................................................................................................................33
9.4.1 Temperature ranges ..........................................................................................................................................33
9.4.2 Power supply voltages......................................................................................................................................................................... 33
9.5 DC characteristics .................................................................................................................................................34
9.5.1 Capacitance characteristics .............................................................................................................................................................. 38
9.6 Power-up initialization .........................................................................................................................................39
9.7 Power-down..........................................................................................................................................................40
9.8 Hardware reset......................................................................................................................................................41
10 Timing specifications ..................................................................................................................42
10.1 Key to switching waveforms...............................................................................................................................42
10.2 AC test conditions ...............................................................................................................................................42
10.3 Timing reference levels.......................................................................................................................................43
10.4 CLK characteristics .............................................................................................................................................44
10.5 AC characteristics................................................................................................................................................46
10.5.1 Read transactions................................................................................................................................................................................ 46
10.5.2 Write transactions............................................................................................................................................48
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Table of contents
11 Physical interface .......................................................................................................................49
11.1 FBGA 24-ball 5 x 5 array footprint ......................................................................................................................49
12 Package diagram ........................................................................................................................50
13 DDR center-aligned read strobe (DCARS) functionality ...................................................................51
13.1 HYPERRAM™ products with DCARS signal descriptions....................................................................................51
13.2 HYPERRAM™ products with DCARS — FBGA 24-ball, 5 ´ 5 array footprint.......................................................53
13.3 HYPERRAM™ memory with DCARS timing .........................................................................................................53
14 Ordering information ..................................................................................................................55
14.1 Ordering part number.........................................................................................................................................55
14.2 Valid combinations .............................................................................................................................................56
14.3 Valid combinations — Automotive grade / AEC-Q100.......................................................................................57
Revision history ..............................................................................................................................58
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
General description
1
General description
The Infineon® 64Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with HYPERBUS™ interface. The
DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the
refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™
interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears
to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more
accurately described as Pseudo Static RAM (PSRAM).
Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host
limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The
host must confine the duration of transactions and allow additional initial access latency, at the beginning of a
new transaction, if the memory indicates a refresh operation is needed.
1.1
HYPERBUS™ interface
HYPERBUS™ is a low signal count, DDR interface, that achieves high-speed read and write throughput. The DDR
protocol transfers two data bytes per clock cycle on the DQ[7:0] input/output signals. A read or write transaction
on HYPERBUS™ consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERRAM™ array
with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs
are LV-CMOS compatible. Device are available as 1.8 V VCC/(VCCQ or 3.0 V VCC/VCCQ (nominal) for array (VCC) and
I/O buffer (VCCQ) supplies, through different Ordering part numbers (OPN).
Command, address, and data information is transferred over the eight HYPERBUS™ DQ[7:0] signals. The clock
(CK#, CK) is used for information capture by a HYPERBUS™ slave device when receiving command, address, or
data on the DQ signals. Command or address values are center-aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-address (CA) signals, followed by the start of
clock transitions to transfer six CA bytes, followed by initial access latency and either read or write data transfers,
until CS# is deasserted.
CS#
tRWR=Read Write Recovery
t ACC = Access
Latency Count
CK#,CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 1
Read transaction, single initial latency count
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
General description
The RWDS is a bidirectional signal that indicates:
• When data will start to transfer from a HYPERRAM™ device to the master device in read transactions (initial read
latency)
• When data is being transferred from a HYPERRAM™ device to the master device during read transactions (as a
source synchronous read data strobe)
• When data may start to transfer from the master device to a HYPERRAM™ device in write transactions (initial
write latency)
• Data masking during write data transfers
During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HYPERRAM™ device
to indicate whether additional initial access latency is needed in the transaction.
During read data transfers, RWDS is a read data strobe with data values edge-aligned with the transitions of
RWDS.
CS#
tRWR=Read Write Recovery
Additional Latency
Latency Count 1
tACC = Access
CK#, CK
RWDS
Latency Count 2
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
Dn
A
Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
B
A
B
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 2
Read transaction, additional latency count
During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS HIGH (invalid
and prevented from changing the byte location in a memory) or not masked with RWDS LOW (valid and written
to a memory). Data masking may be used by the host to byte align write data within a memory or to enable
merging of multiple non-word aligned writes in a single burst write. During write transactions, data is
center-aligned with clock transitions.
CS#
tRWR =Read Write Recovery
tACC= Access
Latency Count
CK#,CK
CK and Data
are center aligned
High = 2x Latency Count
RWDS
Low = 1x Latency Count
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16
15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 3
Write transaction, single initial latency count
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle.
Each individual read or write transaction can use either a wrapped or linear burst sequence.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
General description
16 word group alignment boundaries
Linear Burst
5h 6h 7h 8h 9h Ah Bh
Dh Eh Fh 10h 11h 12h 13h
4h
Ch
Ch
Initial address = 4h
Wrapped Burst
1h 2h 3h
5h 6h 7h 8h 9h Ah Bh
4h
Dh Eh Fh
0h
Figure 4
Linear versus wrapped burst sequence
During wrapped transactions, accesses start at a selected location and continue to the end of a configured word
group aligned boundary, then wrap to the beginning location in the group, then continue back to the starting
location. Wrapped bursts are generally used for critical word first cache line fill read transactions. During linear
transactions, accesses start at a selected location and continue in a sequential manner until the transaction is
terminated when CS# returns HIGH. Linear transactions are generally used for large contiguous data transfers
such as graphic images. Since each transaction command selects the type of burst sequence for that transaction,
wrapped and linear bursts transactions can be dynamically intermixed as needed.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Product overview
2
Product overview
The 64 Mb HYPERRAM™ device is 1.8 V or 3.0 V array and I/O, synchronous self-refresh DRAM. The HYPERRAM
device provides a HYPERBUS™ slave interface to the host system. The HYPERBUS™ interface has an 8-bit (1 byte)
wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read transactions provide 16 bits
of data during each clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data from each clock
cycle (8 bits on each clock edge).
RESET#
V
CC
V
Q
CC
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
Q
SS
Figure 5
HYPERBUS™ interface[1]
2.1
HYPERBUS™ interface
Read and write transactions require two clock cycles to define the target row address and burst type, then an
initial access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional
latency for a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the HIGH
state. During the CA period, the third clock cycle will specify the target word address within the target row. During
a read (or write) transaction, after the initial data value has been output (or input), additional data can be read
from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When configured
in linear burst mode, the device will automatically fetch the next sequential row from the memory array to
support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data
transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data rate of
400 MBps [1 byte (8 bit data bus) * 2 (data clock edges) * 200 MHz = 400 MBps].
Note
1. CK# is used in differential clock mode, but optional.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Signal description
3
Signal description
3.1
Input/output summary
HYPERRAM™ signals are shown in Table 1. Active low signal names have a hash symbol (#) suffix.
Table 1
Symbol
I/O summary[3]
Type
Description
Chip Select. Bus transactions are initiated with a HIGH to LOW transition.
Bus transactions are terminated with a LOW to HIGH transition. The master
device has a separate CS# for each slave.
CS#
Master output,
slave input
Differential Clock. Command, address, and data information is output
with respect to the crossing of the CK and CK# signals. Use of differential
clock is optional.
CK, CK#[2]
DQ[7:0]
Single ended clock. CK# is not used, only a single ended CK is used. The
clock is not required to be free-running.
Data Input/Output. Command, Address, and Data information is
transferred on these signals during read and write transactions.
Read-write Data Strobe. During the Command/address portion of all bus
transactions, RWDS is a slave output and indicates whether additional
initial latency is required. Slave output during read data transfer, data is
edge-aligned with RWDS. Slave input during data transfer in write
transactions to function as a data mask.
Input/output
RWDS
(HIGH = Additional latency, LOW = No additional latency).
Hardware Reset. When LOW, the slave device will self initialize and return
to the standby state. RWDS and DQ[7:0] are placed into the HIGH-Z state
when Reset# is LOW. The slave Reset# input includes a weak pull-up, if
Reset# is left unconnected it will be pulled up to the HIGH state.
Master output,
slave input,
internal pull-up
RESET#
VCC
Array power.
VCC
Q
Input/output power.
Array ground.
Power supply
No connect
VSS
VSSQ
Input/output ground.
Reserved for Future Use. May or may not be connected internally, the
signal/ball location should be left unconnected and unused by PCB routing
channel for future compatibility. The signal/ball may be used by a signal in
the future.
RFU
Notes
2. CK# is used in Differential clock mode, but optional connection. Tie the CK# input pin to either VCCQ or VSS
if not connected to the host controller, but do not leave it floating.
Q
3. Optional Center-Aligned Read Strobe (DCARS) pinout and pin description are outlined in
“DDR center-aligned read strobe (DCARS) functionality” on page 51.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
4
HYPERBUS™ transaction details
4.1
Command/address bit assignments
All HYPERRAM™ bus transactions can be classified as either read or write. A bus transaction is started with CS#
going LOW with clock in idle state (CK = LOW and CK# = HIGH). The first three clock cycles transfer three words of
command/address (CA0, CA1, CA2) information to define the transaction characteristics. The command/address
words are presented with DDR timing, using the first six clock edges.
The following characteristics are defined by the command/address information:
• Read or write transaction
• Address space: Memory array space or register space
- Register space is used to access Device Identification (ID) registers and Configuration Registers (CR) that iden-
tify the device characteristics and determine the slave specific behavior of read and write transfers on the
HYPERBUS™ interface.
• Whether a transaction will use a linear or wrapped burst sequence.
• The target row (and half-page) address (upper order address)
• The target column (word within half-page) address (lower order address)
CS#
CK , CK#
DQ[7:0]
CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8]
CA2[7:0]
Figure 6
Table 2
Command/address (CA) sequence[4-7]
CA bit assignment to DQ signals
Signal
CA0[47:40]
CA[47]
CA[46]
CA[45]
CA[44]
CA[43]
CA[42]
CA[41]
CA[40]
CA0[39:32]
CA[39]
CA[38]
CA[37]
CA[36]
CA[35]
CA[34]
CA[33]
CA[32]
CA1[31:24]
CA[31]
CA[30]
CA[29]
CA[28]
CA[27]
CA[26]
CA[25]
CA[24]
CA1[23:16]
CA[23]
CA[22]
CA[21]
CA[20]
CA[19]
CA[18]
CA[17]
CA[16]
CA2[15:8]
CA2[7:0]
CA[7]
CA[6]
CA[5]
CA[4]
CA[3]
CA[2]
CA[1]
CA[0]
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
CA[15]
CA[14]
CA[13]
CA[12]
CA[11]
CA[10]
CA[9]
CA[8]
Notes
4. Figure 6 shows the initial three clock cycles of all transactions on the HYPERBUS™.
5. CK# of differential clock is shown as dashed line waveform.
6. CA information is “center-aligned” with the clock during both read and write transactions.
7. Data bits in each byte are always in HIGH to LOW order with bit 7 on DQ7 and bit 0 on DQ0.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
Table 3
CA bit#
Command/address bit assignments[8-11]
Bit name
Bit function
Identifies the transaction as a read or write.
R/W# = 1 indicates a read transaction
R/W# = 0 indicates a write transaction
47
R/W#
Indicates whether the read or write transaction accesses the memory or register
space.
Address space
(AS)
46
AS = 0 indicates memory space
AS = 1 indicates the register space
The register space is used to access device ID and Configuration Registers.
Indicates whether the burst will be linear or wrapped.
Burst type = 0 indicates wrapped burst
Burst type = 1 indicates linear burst
45
Burst type
Row and upper column component of the target address: System word address
bits A31-A3. Any upper Row address bits not used by a particular device density
should be set to 0 by the host controller master interface. The size of Rows and
therefore the address bit boundary between row and column address is slave
device dependent.
Row and upper
column address
44-16
Reserved for future column address expansion.
15-3
2-0
Reserved
Reserved bits are don’t care in current HYPERBUS™ devices but should be set to
0 by the host controller master interface for future compatibility.
Lower column Lower column component of the target address. System word address bits
address A2-A0 selecting the starting word within a half-page.
Notes
8. A row is a group of words relevant to the internal memory array structure. The number of Rows is also used
in the calculation of a distributed refresh interval for HYPERRAM™ memory.
9. The Column address selects the burst transaction starting word location within a Row. The Column address
is split into an upper and lower portion. The upper portion selects an 8-word (16-byte) half-page and the
lower portion selects the word within a half-page where a read or write transaction burst starts.
10. The initial read access time starts when the row and upper column (half-page) address bits are captured by
a slave interface. Continuous linear read burst is enabled by memory devices internally interleaving access
to 16 byte half-pages.
11. HYPERBUS™ protocol address space limit, assuming:
29 Row and upper column address bits
3 Lower column address bits
Each address selects a word wide (16 bit = 2 byte) data value
29 + 3 = 32 address bits = 4G addresses supporting 8GB (64Gb) maximum address space
future expansion of the column address can allow for 29 row and upper column + 16 lower column address
bits = 35 tera-word = 70 tera-byte address space.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
CS#
CK , CK#
RWDS
DQ[7:0]
DnA
DnB
Dn+1A
Dn+1B
Dn+2A
Figure 7
Data placement during a read transaction[12-16]
Data placement during memory read/write is dependent upon the host. The device will output data (read) as it
was written in (write). Hence both Big endian and Little endian are supported for the memory array.
Data placement during register read/write is Big endian.
Notes
12. Figure 7 shows a portion of a read transaction on the HYPERBUS. CK# of differential clock is shown as
dashed line waveform.
13. Data is “edge-aligned” with the RWDS serving as a read data strobe during read transactions.
14. Data is always transferred in full word increments (word granularity transfers).
15. Word address increments in each clock cycle. Byte A is between RWDS rising and falling edges and is followed
by byte B between RWDS falling and rising edges, of each word.
16. Data bits in each byte are always in HIGH to LOW order with bit 7 on DQ7 and bit 0 on DQ0.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
Table 4
Data bit placement during read or write transaction
Address
space
Byte
Byte
Word data bit
DQ
Bit order
order
position
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
B
A
B
When data is being accessed in memory space:
The first byte of each word read or written is the “A”
byte and the second is the “B” byte.
The bits of the word within the A and B bytes depend on
how the data was written. If the word lower address bits
7-0 are written in the A byte position and bits 15-8 are
written into the B byte position, or vice versa, they will
be read back in the same order.
8
Big-
Memory
endian
7
6
5
Memory space can be stored and read in either
little-endian or big-endian order.
4
3
2
1
0
7
6
5
4
3
When data is being accessed in memory space:
The first byte of each word read or written is the “A”
byte and the second is the “B” byte.
2
The bits of the word within the A and B bytes depend on
how the data was written. If the word lower address bits
7-0 are written in the A byte position and bits 15-8 are
written into the B byte position, or vice versa, they will
be read back in the same order.
1
0
Little-
Memory
endian
15
14
13
12
11
10
9
Memory space can be stored and read in either
little-endian or big-endian order.
8
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
Table 4
Data bit placement during read or write transaction (Continued)
Address
space
Byte
Byte
Word data bit
DQ
Bit order
order
position
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When data is being accessed in register space:
During a Read transaction on the HYPERBUS™ two
bytes are transferred on each clock cycle. The upper
order byte A (word[15:8]) is transferred between the
rising and falling edges of RWDS (edge-aligned). The
lower order byte B (word[7:0]) is transferred between
the falling and rising edges of RWDS.
A
8
Register
Big-endian
7
During a write, the upper order byte A (word[15:8]) is
transferred on the CK rising edge and the lower order
byte B (word[7:0]) is transferred on the CK falling edge.
Therefore, register space is always read and written in
big-endian order because registers have device
6
5
4
B
dependent fixed bit location and meaning definitions.
3
2
1
0
CS#
CK , CK#
RWDS
DQ[7:0]
DnA
DnB
Dn+1A
Dn+1B
Dn+2A
Figure 8
Data placement during a write transaction[17-20]
Notes
17. Figure 8 shows a portion of a Write transaction on the HYPERBUS™.
18. Data is “center-aligned” with the clock during a write transaction.
19. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last
byte is shown to illustrate an unaligned 3 byte write of data.
20. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are
always written in this case. RWDS may be driven LOW or left HIGH-Z by the slave in this case.
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HYPERBUS™ transaction details
4.2
Read transactions
The HYPERBUS™ master begins a transaction by driving CS# LOW while clock is idle. The clock then begins
toggling while CA words are transferred.
In CA0, CA[47] = 1 indicates that a Read transaction is to be performed. CA[46] = 0 indicates the memory space is
being read or CA[46] = 1 indicates the register space is being read. CA[45] indicates the burst type (wrapped or
linear). Read transactions can begin the internal array access as soon as the row and upper column address has
been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within the chosen
row.
The HYPERBUS™ master then continues clocking for a number of cycles defined by the latency count setting in
Configuration Register 0. The initial latency count required for a particular clock frequency is based on RWDS. If
RWDS is LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an
additional latency count is inserted. Once these latency clocks have been completed the memory starts to simul-
taneously transition the RWDS and output the target data.
New data is output edge-aligned with every transition of RWDS. Data will continue to be output as long as the
host continues to transition the clock while CS# is LOW. Note that burst transactions should not be so long as to
prevent the memory from doing distributed refreshes.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential
manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the
burst beyond the last address will provide data from the beginning of the address range. Read transfers can be
ended at any time by bringing CS# HIGH when the clock is idle.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
CS#
Additional Latency
tRWR= Read Write Recovery
tACC = Access
CK#, CK
High = 2x Latency Count
Low = 1x Latency Count
RWDS
RWDS and Data
are edge aligned
Latency Count 1
Latency Count 2
Dn Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
A
B
A
B
Memory drives DQ[7:0]
and RWDS
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Figure 9
Notes
Read transaction with additional initial latency[21-28]
21. Figure 8 shows a portion of a Write transaction on the HYPERBUS™.
22. Data is “center-aligned” with the clock during a write transaction.
23. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last
byte is shown to illustrate an unaligned 3 byte write of data.
24. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are
always written in this case. RWDS may be driven LOW or left HIGH-Z by the slave in this case.
25. The read latency is defined by the initial latency value in a configuration register.
26. In this read transaction example the initial latency count was set to four clocks.
27. In this read transaction a RWDS HIGH indication during CA delays output of target data by an additional four
clocks.
28. The memory device drives RWDS during read transactions.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
CS#
tRWR =Read Write Recovery
tACC = Initial Acces
CK, CK#
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
4 cycle latency
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Addres
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 10
Read transaction without additional initial latency[29]
4.3
Write transactions (Memory array write)
The HYPERBUS™ master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins
toggling while CA words are transferred.
In CA0, CA[47] = 0 indicates that a Write transaction is to be performed. CA[46] = 0 indicates the memory space is
being written. CA[45] indicates the burst type (wrapped or linear). Write transactions can begin the internal array
access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2
(CA(15:0]) identifies the target word address within the chosen row.
The HYPERBUS™ master then continues clocking for a number of cycles defined by the latency count setting in
Configuration Register 0. The initial latency count required for a particular clock frequency is based on RWDS. If
RWDS is LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an
additional latency count is inserted.
Once these latency clocks have been completed, the HYPERBUS™ master starts to output the target data. Write
data is center-aligned with the clock edges. The first byte of data in each word is captured by the memory on the
rising edge of CK and the second byte is captured on the falling edge of CK.
During the CA clock cycles, RWDS is driven by the memory.
During the write data transfers, RWDS is driven by the host master interface as a data mask. When data is being
written and RWDS is HIGH, the byte will be masked and the array will not be altered. When data is being written
and RWDS is LOW, the data will be placed into the array. Because the master is driving RWDS during write data
transfers, neither the master nor the HYPERRAM™ device are able to indicate a need for latency within the data
transfer portion of a write transaction. The acceptable write data burst length setting is also shown in
Configuration Register 0.
Data will continue to be transferred as long as the HYPERBUS™ master continues to transition the clock while CS#
is LOW. Note that burst transactions should not be so long as to prevent the memory from doing distributed
refreshes. Legacy format wrapped bursts will continue to wrap within the burst length. Hybrid wrap will wrap
once then switch to linear burst starting at the next wrap boundary. Linear burst accepts data in a sequential
manner across page boundaries. Write transfers can be ended at any time by bringing CS# HIGH when the clock
is idle.
When a linear burst write reaches the last address in the memory array space, continuing the burst will write to
the beginning of the address range.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
Note
29. RWDS is LOW during the CA cycles. In this Read Transaction, there is a single initial latency count for read
data access because, this read transaction does not begin at a time when additional latency is required by
the slave.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
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HYPERBUS™ transaction details
CS#
Additional Latency
tRWR = Read Write Recovery
tACC = Initial Access
Latency Count 2
CK, CK#
High = 2x Latency Count
Low = 1x Latency Count
RWDS
CK and Data
are center aligned
Latency Count 1
Dn Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8 7:0
DQ[7:0]
A
B
A
B
Host drives DQ[7:0]
and RWDS
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Figure 11
Write transaction with additional initial latency[30-36]
CS#
tRWR=Read Write Recovery
tACC = Access
CK#, CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
CK and Data
are center aligned
Latency Count
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 12
Write transaction without additional initial latency[32-36]
Notes
30. Transactions must be initiated with CK = LOW and CK# = HIGH.
31. CS# must return HIGH before a new transaction is initiated.
32. During CA, RWDS is driven by the memory and indicates whether additional latency cycles are required.
33. In this example, RWDS indicates that additional initial latency cycles are required.
34. At the end of CA cycles the memory stops driving RWDS to allow the host HYPERBUS™ master to begin driving
RWDS. The master must drive RWDS to a valid LOW before the end of the initial latency to provide a data
mask preamble period to the slave.
35. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or
loaded into the array.
36. The figure shows RWDS masking byte Dn A and byte Dn+1 B to perform an unaligned word write to bytes
Dn B and Dn+1 A.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
HYPERBUS™ transaction details
4.4
Write transactions without initial latency (Register write)
A write transaction starts with the first three clock cycles providing the command/address information indicating
the transaction characteristics. CA0 may indicate that a Write transaction is to be performed and also indicates
the address space and burst type (wrapped or linear).
Writes without initial latency are used for register space writes. HYPERRAM™ device write transactions with zero
latency mean that the CA cycles are followed by write data transfers. Writes with zero initial latency, do not have
a turn around period for RWDS. The HYPERRAM™ device will always drive RWDS during the CA period to indicate
whether extended latency is required for a transaction that has initial latency. However, the RWDS is driven
before the HYPERRAM™ device has received the first byte of CA i.e., before the HYPERRAM™ device knows whether
the transaction is a read or write to register space. In the case of a write with zero latency, the RWDS state during
the CA period does not affect the initial latency of zero. Since master write data immediately follows the CA period
in this case, the HYPERRAM™ device may continue to drive RWDS LOW or may take RWDS to High-Z during write
data transfer. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not
use RWDS as a data mask function. All bytes of write data are written (full word writes).
The first byte of data in each word is presented on the rising edge of CK and the second byte is presented on the
falling edge of CK. Write data is center-aligned with the clock inputs. Write transfers can be ended at any time by
bringing CS# HIGH when clock is idle. The clock is not required to be free-running.
CS#
CK#, CK
High: 2X latency count*
Low: 1X latency count*
RWDS
CA
[47:40]
CA
[39:32]
CA
[31:24]
CA
[23:16]
CA
[15:8]
CA
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - address
(Host drives DQ[7:0], Memory drives RWDS)
Write data
Figure 13
Write operation without initial latency[37]
Note
37. Latency count is not applicable for Register write. The RWDS driven LOW or HIGH during CA cycle should be
ignored by the host and the host must continue register write with zero latency.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Memory space
5
Memory space
5.1
Table 5
HYPERBUS™ interface
Memory space address map (Word based - 16 bits)
System word
Unit type
Count
CA bits
Notes
address bits
Rows within 64 Mb
device
8192 (rows)
A21 - A9
34 - 22
–
512 (word addresses)
1 KB
Row
1 (row)
A8 - A3
A2 - A0
21 - 16
2 - 0
Half-page
8 (word addresses)
8 words (16 bytes)
Datasheet
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Register space
6
Register space
6.1
HYPERBUS™ interface
When CA[46] is 1, a read or write transaction accesses the Register space.
Table 6
Register space address map
System
—
—
—
31-27 26-19 18-11 10-3
—
2-0
address
Register
CA bits
47
46
45[38] 44-40 39-32 31-24 23-16 15-8
7-0
00h
01h
00h
00h
01h
01h
Identification Register 0 Read[39]
Identification Register 1 Read[39]
Configuration Register 0 Read
Configuration Register 0 Write
Configuration Register 1 Read
Configuration Register 1 Write
C0h or E0h
C0h or E0h
C0h or E0h
60h
00h
00h
00h
00h
00h
00h
00h
00h
01h
01h
01h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
C0h or E0h
60h
Die Manufacture Information
Register (0-17) Read
C0h or E0h
00h
02h
00h
00h 00h - 11h
6.2
Device Identification Registers
There are two read only, nonvolatile word registers, that provide information on the device selected when CS# is
LOW.
The device information fields identify:
• Manufacturer
• Type
• Density
- Row address bit count
- Column address bit count
Notes
38. CA45 may be either 0 or 1 for either wrapped or linear read. CA45 must be 1 as only linear single word register
writes are supported.
39. The burst type (wrapped/linear) definition is not supported in register reads. Hence C0h/E0h have the same
effect.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Register space
Table 7
Identification Register 0 (ID0) bit assignments
Bits
Functions
MCP die address
Reserved
Settings (Binary)
[15:4]
[13]
00 - Default
0 - Default
00000 - One row address bit
...
[12:8]
Row address bit count
11111 - Thirty-two row address bits
...
01100 - 64 Mb - Thirteen row address bits (default)
0000 - One column address bits
...
[7:4]
[3:0]
Column address bit count 1000 - Nine column address bits (default)
...
1111 - Sixteen column address bits
0001 - Infineon
Manufacturer
0000, 0010 to 1111 - Reserved
Table 8
Identification Register 1 (ID1) bit assignments
Bits Functions
Reserved
Device type
Settings (Binary)
0000_0000_0000 (default)
[15:4]
[3:0]
0001 - HYPERRAM™ 2.0
0000, 0010 to 1111 - Reserved
6.2.1
Density and row boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used
for the row and column addresses as indicated by the row address bit count and column address bit count fields
in the ID0 register. For example: a 64 Mb HYPERRAM™ device has 9 column address bits and 13 row address bits
for a total of 22 word address bits = 222 = 4 Mwords = 8 MB. The 9 column address bits indicate that each row holds
29 = 512 words = 1 KB. The row address bit count indicates there are 8196 rows to be refreshed within each array
refresh interval. The row count is used in calculating the refresh interval.
ID0 value for the 64 Mb HYPERRAM™ is 0x0C81.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
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Register space
6.3
Register space access
Register default values are loaded upon power-up or hardware reset. The registers can be altered at any time
while the device is in the standby state.
Loading a register is accomplished with write transaction without initial latency using a single 16-bit word write
transaction.
Each register is written with a separate single word write transaction. Register write transactions have zero
latency, the single word of data immediately follows the CA. RWDS is not driven by the host during the write
because RWDS is always driven by the memory during the CA cycles to indicate whether a memory array refresh
is in progress. Because a register space write goes directly to a register, rather than the memory array, there is no
initial write latency, related to an array refresh that may be in progress. In a register write, RWDS is also not used
as a data mask because both bytes of a register are always written and never masked.
Reserved register fields must be written with their default value. Writing reserved fields with other than default
values may produce undefined results.
Notes
• The host must not drive RWDS during a write to register space.
• The RWDS signal is driven by the memory during the CA period based on whether the memory array is being
refreshed. This refresh indication does not affect the writing of register data.
• The RWDS signal returns to high impedance after the CA period. Register data is never masked. Both data bytes
of the register data are loaded into the selected register.
Reading of a register is accomplished with read transaction with single or double initial latency using a single
16 bit read transaction. If more than one word is read, the output becomes indeterminate. The contents of the
register is returned in the same manner as reading the memory array, as shown in Figure 9, with one or two
latency counts, based on the state of RWDS during the CA period. The latency count is defined in the Configu-
ration Register 0 Read Latency field (CR0[7:4]).
6.3.1
Configuration Register 0
Configuration Register 0 (CR0) is used to define the power state and access protocol operating conditions for the
HYPERRAM™ device. Configurable characteristics include:
• Wrapped burst length (16-, 32-, 64-, or 128-byte aligned and length data group)
• Wrapped burst type
- Legacy wrap (Sequential access with wrap around within a selected length and aligned group)
- Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
• Initial latency
• Variable latency
- Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected, the
memory will always indicate a refresh latency and delay the read data transfer accordingly. If variable latency
is selected, latency for a refresh is only added when a refresh is required at the same time a new transaction
is starting.
• Output drive strength
• Deep power-down (DPD) mode
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Register space
Table 9
CR0 bit
Configuration Register 0 (CR0) bit assignments
Function
Settings (Binary)
1 - Normal operation (default). HYPERRAM™ will automatically set this value to
‘1’ after DPD exit
0 - Writing 0 causes the device to enter Deep power-down
Deep power-down
enable
[15]
000 - 34 (default)
001 - 115
010 - 67
011 - 46
[14:12]
[11:8]
Drive strength
Reserved
100 - 34
101 - 27
110 - 22
111 - 19
1 - Reserved (default)
Reserved for future use. When writing this register, these bits should be set to
1 for future compatibility.
0000 - 5 Clock latency @ 133 MHz Max frequency
0001 - 6 Clock latency @ 166 MHz Max frequency
0010 - 7 Clock latency @ 200 MHz/166 MHz Max frequency (default)
0011 - Reserved
[7:4]
Initial latency
0100 - Reserved
...
1101 - Reserved
1110 - 3 Clock latency @ 85 MHz Max frequency
1111 - 4 Clock latency @ 104 MHz Max frequency
0 - Variable Latency - 1 or 2 times Initial Latency depending on RWDS during CA
Fixed latency
enable
[3]
[2]
cycles.
1 - Fixed 2 times Initial Latency (default)
0: Wrapped burst sequence to follow hybrid burst sequencing
1: Wrapped burst sequence in legacy wrapped burst manner (default)
Hybrid burst enable
Burst length
This bit setting is effective only when the “Burst type” bit in the
Command/Address register is set to ‘0’, i.e. CA[45] = 0; otherwise, it is ignored.
00 - 128 bytes
01 - 64 bytes
[1:0]
10 - 16 bytes
11 - 32 bytes (default)
Datasheet
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Register space
6.3.2
Wrapped burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching
the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes
alignment and length. During wrapped transactions, access starts at the CA selected location within the group,
continues to the end of the configured word group aligned boundary, then wraps around to the beginning
location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical
word first instruction or data cache line fill read accesses.
6.3.2.1
Hybrid burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing
to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the
transfer is ended by returning CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the
beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access.
The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in
to the cache while the first line is being processed.
Table 10
Bit
CR0[2] control of wrapped burst sequence
Default value
Name
Hybrid burst enable
CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing
CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner
2
1
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
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Register space
Table 11
Example wrapped burst sequences (HYPERBUS™ addressing)
Wrap
boundary
(bytes)
Burst
type
Start address
(hex)
Sequence of word addresses (hex) of data words
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16,
17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A,
2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E,
3F, 00, 01, 02
128 wrap
once then
linear
Hybrid
128
XXXXXX03
(Wrap complete, now linear beyond the end of the initial 128 byte
wrap group)
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02
64 wrap
Hybrid 64 once then
linear
XXXXXX03
XXXXXX2E
(Wrap complete, now linear beyond the end of the initial 64 byte
wrap group)
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, ...
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D
64 wrap
Hybrid 64 once then
linear
(Wrap complete, now linear beyond the end of the initial 64 byte
wrap group)
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
02, 03, 04, 05, 06, 07, 00, 01
16 wrap
Hybrid 16 once then
linear
(Wrap complete, now linear beyond the end of the initial 16 byte
wrap group)
XXXXXX02
XXXXXX0C
XXXXXX0A
08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, ...
0C, 0D, 0E, 0F, 08, 09, 0A, 0B
16 wrap
Hybrid 16 once then
linear
(Wrap complete, now linear beyond the end of the initial 16 byte
wrap group)
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ...
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09
(Wrap complete, now linear beyond the end of the initial 32 byte
wrap group)
32 wrap
Hybrid 32 once then
linear
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ...
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ...
Wrap 64
Wrap 64
64
64
XXXXXX03
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, ...
Wrap 16
Wrap 16
Wrap 32
16
16
32
XXXXXX02
XXXXXX0C
XXXXXX0A
02, 03, 04, 05, 06, 07, 00, 01, ...
0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ...
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, ...
Linear Linear burst
XXXXXX03
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
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Register space
6.3.2.2
Initial latency
Memory space read and write transactions or register space read transactions require some initial latency to
open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC
depends on the HYPERBUS™ frequency can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of
clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of 200
MHz prior to the host system setting a lower initial latency value that may be more optimal for the system.
In the event a distributed refresh is required at the time a memory space read or write transaction or register
space read transaction begins, the RWDS signal goes HIGH during the CA to indicate that an additional initial
latency is being inserted to allow a refresh operation to complete before opening the selected row.
Register space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA
period. The level of RWDS during the CA period does not affect the placement of register data immediately after
the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed
in the memory array in parallel with the capture of register data.
6.3.2.3
Fixed latency
A Configuration Register option bit CR0[3] is provided to make all Memory Space read and write transactions or
Register Space read transactions require the same initial latency by always driving RWDS HIGH during the CA to
indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a
distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. The
fixed latency option may simplify the design of some HYPERBUS™ memory controllers or ensure deterministic
transaction performance. Fixed latency is the default POR or reset configuration. The system may clear this
configuration bit to disable fixed latency and allow variable initial latency with RWDS driven HIGH only when
additional latency for a refresh is required.
6.3.2.4
Drive strength
DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration
Register bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize
the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as
overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid point
of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process condi-
tions, nominal operating voltage (1.8 V or 3.0 V) and 50°C. The impedance values may vary from the typical values
depending on the Process, Voltage, and Temperature (PVT) conditions. Impedance will increase with slower
process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher voltage, or
lower temperature.
Each system design should evaluate the data signal integrity across the operating voltage and temperature
ranges to select the best drive strength settings for the operating conditions.
6.3.2.5
Deep power-down
When the HYPERRAM™ device is not needed for system operation, it may be placed in a very low power consuming
state called deep power-down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the
DPD state within tDPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without
refresh) during DPD state. Exiting DPD requires driving CS# LOW then HIGH, POR, or a reset. Only CS# and RESET#
signals are monitored during DPD mode. For additional details, see “Deep power-down” on page 31.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Register space
6.3.3
Configuration Register 1
Configuration Register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the
HYPERRAM™ device. Configurable characteristics include:
• Partial array refresh
• Hybrid sleep state
• Refresh rate
Table 12
CR1 bit
Configuration Register 1 (CR1) bit assignments
Function
Reserved
Setting (Binary)
FFh - Reserved (default)
[15:8]
[7]
These bits should always be set to FFh
Reserved
1 - Reserved (default)
1 - Single-ended - CK (default)
0 - Differential - CK#, CK
[6]
Master clock type
1 - Causes the device to enter Hybrid sleep state
0 - Normal operation (default)
[5]
Hybrid sleep
000 - Full array (default)
001 - Bottom 1/2 array
010 - Bottom 1/4 array
011 - Bottom 1/8 array
100 - None
Partial array
refresh
[4:2]
101 - Top 1/2 array
110 - Top 1/4 array
111 - Top 1/8 array
10 - 1 μs tCSM (Industrial plus temperature range devices)
Distributed refresh 11 - Reserved
interval (read Only) 00 - Reserved
[1:0]
01 - 4 μs tCSM (Industrial temperature range devices)
6.3.3.1
Master clock type
Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
• In the single ended clock mode (by default), CK# input is not enabled; hence it may be left either floating or
biased to HIGH or LOW.
• In the differential clock mode (when enabled), the CK# input can't be left floating. It must be either driven by
the host, or biased to HIGH or LOW.
6.3.3.2
Partial array refresh
The partial array refresh configuration restricts the refresh operation in HYPERRAM™ to a portion of the memory
array specified by CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole
array.
6.3.3.3
Hybrid sleep (HS)
When the HYPERRAM™ is not needed for system operation but data in the device needs to be retained, it may be
placed in hybrid sleep state to save more power. Enter Hybrid sleep state by writing 1 to CR1[5]. Bringing CS# LOW
will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to
exit hybrid sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can
potentially get lost.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Register space
6.3.3.4
Distributed refresh interval
The DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading
or writing a location in each row within a specified time limit. The read or write access copies a row of bits to an
internal buffer. At the end of the access the bits in the buffer are written back to the row in memory, thereby
recharging (refreshing) the bits in the row of DRAM memory cells.
HYPERRAM™ devices include self-refresh logic that will refresh rows automatically. The automatic refresh of a
row can only be done when the memory is not being actively read or written by the host system. The refresh logic
waits for the end of any active read or write before doing a refresh, if a refresh is needed at that time. If a new read
or write begins before the refresh is completed, the memory will drive RWDS HIGH during the CA period to
indicate that an additional initial latency time is required at the start of the new access in order to allow the
refresh operation to complete before starting the new access.
The required refresh interval for the entire memory array varies with temperature as shown in Table 13. This is
the time within which all rows must be refreshed. Refresh of all rows could be done as a single batch of accesses
at the beginning of each interval, in groups (burst refresh) of several rows at a time, spread throughout each
interval, or as single row refreshes evenly distributed throughout the interval. The self-refresh logic distributes
single row refresh operations throughout the interval so that the memory is not busy doing a burst of refresh
operations for a long period, such that the burst refresh would delay host access for a long period.
Table 13
Array refresh interval per temperature
Device temperature (°C) Array refresh interval (ms)
Array rows
Recommended tCSM (µs)
85
105
64
16
8192
8192
4
1
The distributed refresh method requires that the host does not do burst transactions that are so long as to
prevent the memory from doing the distributed refreshes when they are needed. This sets an upper limit on the
length of read and write transactions so that the refresh logic can insert a refresh between transactions. This limit
is called the CS# LOW maximum time (tCSM). The tCSM value is determined by the array refresh interval divided by
the number of rows in the array, then reducing this calculation by half to ensure that a distributed refresh interval
cannot be entirely missed by a maximum length host access starting immediately before a distributed refresh is
needed. Because tCSM is set to half the required distributed refresh interval, any series of maximum length host
accesses that delay refresh operations will catch up on refresh operations at twice the rate required by the refresh
interval divided by the number of rows.
The host system is required to respect the tCSM value by ending each transaction before violating tCSM. This can
be done by host memory controller logic splitting long transactions when reaching the tCSM limit, or by host
system hardware or software not performing a single read or write transaction that would be longer than tCSM
.
As noted in Table 13, the array refresh interval is longer at lower temperatures such that tCSM could be increased
to allow longer transactions. The host system can either use the tCSM value from the table for the maximum
operating temperature or, may determine it dynamically by reading the read only CR1[1:0] bits in order to set the
distributed refresh interval prior to every access.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Interface states
7
Interface states
Table 14 describes the required value of each signal for each interface state.
Table 14 Interface states
Interface state
V
/ VCCQ
CS# CK, CK#
DQ7-DQ0
RWDS
RESET#
CC
Power-off
< V
X
X
X
X
HIGH-Z
HIGH-Z
X
LKO
Power-on (Cold) reset
V / V Q min
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
Y
X
L
CC
CC
Hardware (Warm) reset
Interface standby
CA
V / V Q min
X
H
L
L
L
L
L
L
X
X
T
T
T
T
T
T
CC
CC
V / V Q min
HIGH-Z
H
H
H
H
H
H
H
CC
CC
V / V Q min
Master output valid
HIGH-Z
CC
CC
Read initial access latency
V / V Q min
L
CC
CC
(Data bus turn around period)
Write initial access latency
(RWDS turn around period)
V / V Q min
HIGH-Z
HIGH-Z
CC
CC
Slave output valid
Z or T
Read data transfer
V / V Q min
Slave output valid
Master output valid
Master output valid
CC
CC
Write data transfer with initial
latency
Master output
valid X or T
V / V Q min
CC
CC
Write data transfer without
Slave output
L or HIGH-Z
V / V Q min
[40]
CC
CC
initial latency
Master or slave
output valid or
HIGH-Z
[41]
Active clock stop
V / V Q min
L
Idle
Y
H
CC
CC
[41]
Deep power-down
V / V Q min
H
H
X or T
X or T
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
H
H
CC
CC
[41]
Hybrid sleep
V / V Q min
CC CC
Legend
L = V H = V
IL ,
IH
X = Either V or V
IL
IH
Y= Either V or V or V or V
IL
IH
OL
OH
Z = Either V or V
OL
OH
L/H = Rising edge
H/L = Falling edge
T = Toggling during information transfer
Idle = CK is LOW and CK# is HIGH level
Valid = All bus signals have stable L or H
Notes
40. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The
HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is
required. Since master write data immediately follows the CA period the HYPERRAM™ device may continue
to drive RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during Writes with zero
latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written
(full word writes).
41. Active clock stop is described in “Active clock stop” on page 30, DPD is described in “Deep power-down”
on page 31, and Hybrid sleep is described in “Hybrid sleep” on page 30.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Power conservation modes
8
Power conservation modes
8.1
Interface standby
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CS# = HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.
8.2
Active clock stop
The Active clock stop state reduces device interface energy consumption to the ICC6 level during the data transfer
portion of a read or write operation. The device automatically enables this state when clock remains stable for
tACC + 30 ns. While in Active clock stop state, read data is latched and always driven onto the data bus. ICC6 shown
in “DC characteristics” on page 34.
Active clock stop state helps reduce current consumption when the host system clock has stopped to pause the
data transfer. Even though CS# may be LOW throughout these extended data transfer cycles, the memory device
host interface will go into the Active clock stop current level at tACC + 30 ns. This allows the device to transition
into a lower current state if the data transfer is stalled. Active read or write current will resume once the data
transfer is restarted with a toggling clock. The Active clock stop state must not be used in violation of the tCSM
limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the active transaction
as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access.
CS#
Clock stopped
CK#, CK
Latency count (1X)
High: 2X Latency count
Low: 1X Latency count
RWDS
RWDS & data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
DoutA+1
[7:0]
DoutB+1
[7:0]
DQ[7:0]
Output driven
Read data
Command - address
(Host drives DQ[7:0] and Memory drives RWDS)
Figure 14
Active clock stop during read transaction (DDR)[42]
8.3
Hybrid sleep
In the Hybrid sleep (HS) state, the current consumption is reduced (iHS). HS state is entered by writing a 1 to
CR1[5]. The device reduces power within tHSIN time. The data in Memory space and register space is retained
during HS state. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 0. Also, POR or a
hardware reset will cause the device to exit Hybrid sleep state. Note that a POR or a hardware reset disables
refresh where the memory core data can potentially get lost. Returning to Standby state requires tEXITHS time.
Following the exit from HS due to any of these events, the device is in the same state as entering Hybrid sleep.
CS#
Clock stopped
CK#, CK
Latency count (1X)
High: 2X Latency count
Low: 1X Latency count
RWDS
RWDS & data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
ADR
ADR
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
DoutA+1
[7:0]
DoutB+1
[7:0]
DQ[7:0]
Output driven
Read data
[31:24]
[23:16]
[15:8]
Command - address
(Host drives DQ[7:0] and Memory drives RWDS)
Figure 15
Enter HS transaction
Note
42. RWDS is low during the CA cycles. In this Read transaction, there is a single initial latency count for read data
access because, this read transaction does not begin at a time when additional latency is required by the
slave.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Power conservation modes
CS#
tCSHS
tEXTHS
Figure 16
Table 15
Exit HS transaction
Hybrid sleep timing parameters
Parameter
tHSIN
Description
Min
–
Max
3
Unit
µs
Hybrid sleep CR1[5] = 1 register write to HS power level
CS# pulse width to Exit HS
tCSHS
60
–
3000
100
ns
tEXTHS
CS# exit hybrid sleep to standby wakeup time
µs
8.4
Deep power-down
In the deep power-down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state
is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop.
The data in Memory space is lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH
will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state.
Returning to Standby state requires tEXTDPD time. Returning to standby state following a POR requires tVCS time,
as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as
following POR.
CS#
CK#, CK
High: 2X Latency count
Low: 1X Latency count
RWDS
tDPDIN
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Write data
CR0 value
Enter deep power-down
tDPDIN
Command - address
(Host drives DQ[7:0], Memory drives RWDS)
DPD
Figure 17
Enter DPD transaction
CS#
tCSDPD
tEXTDPD
Figure 18
Table 16
Exit DPD transaction
Deep power-down timing parameters
Description
Parameter
tDPDIN
Min
–
Max
3
Unit
µs
Deep power-down CR0[15] = 0 register write to DPD power level
CS# pulse width to exit DPD
tCSDPD
200
–
3000
150
ns
tEXTDPD
CS# exit deep power-down to standby wakeup time
µs
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9
Electrical specifications
[45]
9.1
Absolute maximum ratings
Storage temperature plastic packages
-65°C to +150°C
-65°C to +115°C
Ambient temperature with power applied
Voltage with respect to ground
-0.5V to + (VCC + 0.5 V)
All signals[43]
Output short circuit current[44]
100 mA
VCC, VCC
Q
-0.5 V to +4.0 V
Electrostatic discharge voltage:
2000 V
500 V
Human body model (JEDEC Std JESD22-A114-B)
Charged device model (JEDEC Std JESD22-C101-A)
9.2
Input signal overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage
transitions, inputs or I/Os may negative overshoot VSS to -1.0 V or positive overshoot to VCC +1.0 V, for periods up
to 20 ns.
VSSQ to VCC
Q
- 1.0V
20 ns
≤
Figure 19
Maximum negative overshoot waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCC
Q
Figure 20
Notes
Maximum positive overshoot waveform
43. Minimum DC voltage on input or I/O signal is -1.0 V. During voltage transitions, input or I/O signals may
undershoot VSS to -1.0 V for periods of up to 20 ns. See Figure 19. Maximum DC voltage on input or I/O signals
is VCC +1.0 V. During voltage transitions, input or I/O signals may overshoot to VCC +1.0 V for periods up to 20
ns. See Figure 20.
44. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
45. Stresses above those listed under “Absolute maximum ratings[45]” on page 32 may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.3
Table 17
Latch-up characteristics
Latch-up specification[46]
Description
Min
-1.0
-1.0
-100
Max
VCCQ + 1.0
VCCQ + 1.0
+100
Unit
V
Input voltage with respect to VSSQ on all input only connections
Input voltage with respect to VSSQ on all I/O connections
VCCQ current
mA
9.4
Operating ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
9.4.1
Temperature ranges
Spec
Parameter
Symbol
Device
Unit
Min
Max
85
Industrial (I)
Industrial Plus (V)
105
85
Ambient temperature
TA
-40
°C
Automotive, AEC-Q100 grade 3 (A)
Automotive, AEC-Q100 grade 2 (B)
105
9.4.2
Power supply voltages
Description
Min
Max
Unit
1.8 V VCC power supply
1.7
2.0
V
3.0 V VCC power supply
2.7
3.60
Note
46. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested, connections
not being tested are at VSS
.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.5
DC characteristics
Table 18
DC characteristics (CMOS compatible)
64 Mb
Parameter
Description
Test conditions
Unit
[47]
Min
Typ
Max
Input leakage current
3.0 V device reset signal high
Only
V
V
= V to V ,
IN
CC
SS
CC
I
2
LI1
= V max
CC
Input leakage current
1.8 V device reset signal high
only
V
V
= V to V ,
SS CC
IN
CC
I
2
LI2
= V max
CC
µA
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
I
3.0 V device reset signal low
15
15
LI3
= V max
[48]
CC
only
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
I
1.8 V device reset signal low
LI4
= V max
[48]
CC
only
CS# = V , @200 MHz,
CC
SS
= 2.0V
15
15
15
15
15
15
80
25
28
V
CS# = V , @166 MHz,
SS
= 3.6V
I
V
V
active read current
active write current
CC1
CC
CC
V
CC
CS# = VSS, @200 MHz,
= 3.6V
30
V
CC
mA
CS# = V , @200 MHz,
SS
= 2.0V
25
V
CC
CS# = V , @166 MHz,
SS
= 3.6V
I
28
CC2
V
CC
CS# = V , @200 MHz,
SS
= 3.6V
30
V
CC
CS# = V , V = 2.0 V;
CC CC
220
200
180
170
200
180
170
250
230
200
Full array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/4 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/8 array
CS# = V , V = 2.0 V;
CC CC
Top 1/2 array
V
standby current
CC
I
µA
CC4I
(-40°C to +85°C)
CS# = V , V = 2.0 V;
CC CC
Top 1/4 array
CS# = V , V = 2.0 V;
CC CC
Top 1/8 array
CS# = V , V = 3.6 V;
CC CC
90
Full array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/2 array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/4 array
Notes
47. Not 100% tested.
48. RESET# LOW initiates exits from DPD and HS states and initiates the draw of I reset current, making I during RESET#
CC5
LI
LOW insignificant.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
Table 18
DC characteristics (CMOS compatible) (Continued)
64 Mb
Parameter
Description
Test conditions
Unit
[47]
Min
Typ
Max
CS# = V , V = 3.6 V;
CC CC
190
Bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
230
200
190
V
standby current
Top 1/2 array
CC
I
(-40°C to +85°C)
CC4I
CS# = V , V = 3.6 V;
CC CC
Top 1/4 array
CS# = V , V = 3.6 V;
CC CC
Top 1/8 array
CS# = V , V = 2.0 V;
80
330
CC CC
Full array
CS# = V , V = 2.0 V;
CC CC
90
5
300
270
250
300
270
250
360
330
290
270
330
290
270
1
Bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/4 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/8 array
CS# = V , V = 2.0 V;
CC CC
Top 1/2 array
µA
CS# = V , V = 2.0 V;
CC CC
Top 1/4 array
CS# = V , V = 2.0 V;
CC CC
Top 1/8 array
V
standby current
CC
I
(-40°C to +105°C)
CC4P
CS# = V , V = 3.6 V;
CC CC
Full array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/2 array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/4 array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
Top 1/2 array
CS# = V , V = 3.6 V;
CC CC
Top 1/4 array
CS# = V , V = 3.6 V;
CC CC
Top 1/8 array
CS# = V , RESET# = V ,
CC
SS
I
Reset current
CC5
V
= V max
CC
CC
Active clock stop current
(-40 °C to +85 °C)
CS# = V , RESET# = V ,
SS CC
I
8
CC6I
V
= V max
CC
CC
mA
Active clock stop current
(-40°C to +105 °C)
CS# = V , RESET# = V ,
SS CC
I
8
12
CC6IP
V
= V max
CC
CC
V
current during
CS# = V
V
= V max,
CC
CC, CC CC
I
35
[47]
CC7
power up
V
= V Q = 2.0 V or 3.6 V
CC CC
Notes
47. Not 100% tested.
48. RESET# LOW initiates exits from DPD and HS states and initiates the draw of I reset current, making I during RESET#
CC5
LI
LOW insignificant.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
Table 18
DC characteristics (CMOS compatible) (Continued)
64 Mb
Parameter
Description
Test conditions
CS# = V , V = 3.6 V
Unit
[47]
Min
Typ
Max
Deep power-down current
3.0 V (-40°C to +85°C)
12
CC CC
Deep power-down current
1.8 V (-40°C to +85°C)
CS# = V , V = 2.0 V
10
CC CC
[48]
IDPD
Deep power-down current
3.0 V (-40°C to +105°C)
CS# = V , V = 3.6 V
15
CC CC
Deep power-down current
1.8 V (-40°C to +105°C)
CS# = V , V = 2.0 V
12
CC CC
CS# = V , V = 2.0 V;
CC CC
25
200
170
150
140
170
150
140
230
200
170
150
200
170
150
300
270
240
Full array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/4 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/8 array
Hybrid sleep current 1.8 V
(-40 °C to +85 °C)
CS# = V , V = 2.0 V;
CC CC
Top 1/2 array
CS# = V , V = 2.0 V;
CC CC
Top 1/4 array
CS# = V , V = 2.0 V;
CC CC
Top 1/8 array
CS# = V , V = 3.6 V;
CC CC
35
Full array
CS# = V , V = 3.6 V;
CC CC
µA
Bottom 1/2 array
[48]
I
HS
CS# = V , V = 3.6 V;
CC CC
Bottom 1/4 array
Hybrid sleep current 3.0 V
(-40 °C to +85 °C)
CS# = V , V = 3.6 V;
CC CC
Bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
Top 1/2 array
CS# = V , V = 3.6 V;
CC CC
Top 1/4 array
CS# = V , V = 3.6 V;
CC CC
Top 1/8 array
CS# = V , V = 2.0 V;
CC CC
25
Full array
Hybrid sleep current 1.8 V CS# = V , V = 2.0 V;
CC CC
(-40 °C to +105 °C)
Bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
Bottom 1/4 array
Notes
47. Not 100% tested.
48. RESET# LOW initiates exits from DPD and HS states and initiates the draw of I reset current, making I during RESET#
CC5
LI
LOW insignificant.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
Table 18
DC characteristics (CMOS compatible) (Continued)
64 Mb
Parameter
Description
Test conditions
Unit
[47]
Min
Typ
Max
CS# = V , V = 2.0 V;
CC CC
210
Bottom 1/8 array
CS# = V , V = 2.0 V;
CC CC
270
240
210
330
300
260
250
300
260
Top 1/2 array
Hybrid sleep current 1.8 V
(-40 °C to +105 °C)
CS# = V , V = 2.0 V;
CC CC
Top 1/4 array
CS# = V , V = 2.0 V;
CC CC
Top 1/8 array
CS# = V , V = 3.6 V;
CC CC
35
Full array
CS# = V , V = 3.6 V;
[48]
CC CC
I
µA
HS
Bottom 1/2 array
CS# = V , V = 3.6 V;
CC CC
Bottom 1/4 array
Hybrid sleep current 3.0 V CS# = V , V = 3.6 V;
CC CC
(-40 °C to +105 °C)
Bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
Top 1/2 array
CS# = V , V = 3.6 V;
CC CC
Top 1/4 array
CS# = V , V = 3.6 V;
CC CC
250
Top 1/8 array
V
Input low voltage
Input high voltage
Output low voltage
Output high voltage
-0.15 V
0.70 V
Q
0.30 V
CCQ
IL
CC
V
Q
1.15 V
CCQ
IH
CC
V
V
I
I
= 100 µA for DQ[7:0]
= 100 µA for DQ[7:0]
0.20
OL
OL
OH
V
V
Q-0.20
CC
OH
Notes
47. Not 100% tested.
48. RESET# LOW initiates exits from DPD and HS states and initiates the draw of I reset current, making I during RESET#
CC5
LI
LOW insignificant.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.5.1
Table 19
Capacitance characteristics
1.8 V capacitive characteristics[49-51]
64 Mb
Max
3.0
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
I/O capacitance (DQx)
CI
CID
CO
0.25
3.0
pF
CIO
CIOD
3.0
I/O capacitance delta (DQx)
0.25
Table 20
3.0 V capacitive characteristics[49-51]
64 Mb
Max
3.0
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
CI
CID
CO
0.25
3.0
pF
CIO
CIOD
3.0
IO capacitance delta (DQx)
0.25
Table 21
Thermal resistance
Description
24-ball FBGA
Parameter[52]
Test conditions
Unit
package
Thermal resistance
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
JA
JC
66.7
(Junction to ambient)
°C/W
Thermal resistance
(Junction to case)
37
Notes
49. These values are guaranteed by design and are tested on a sample basis only.
50. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector
network analyzer. VCC,VCCQ are applied and all other signals (except the signal under test) floating. DQ’s
should be in the high impedance state.
51. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance
values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as
critical because there are no critical timings between CS# going active (low) and data being presented on
the DQs bus.
52. This parameter is guaranteed by characterization; not tested in production.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.6
Power-up initialization
HYPERRAM™ products include an on-chip voltage sensor used to launch the power-up initialization process. VCC
and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC(min),
the device will require tVCS time to complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min)
is reached during power-up, and then CS# must remain HIGH for a further delay of tVCS. A simple pull-up resistor
from VCCQ to Chip Select (CS#) can be used to insure safe and proper power-up.
If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period
is used primarily to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 21
Power-up with RESET# HIGH
Vcc_VccQ
CS#
VCC Minimum
Device
Access Allowed
tVCS
RESET#
Figure 22
Table 22
Power-up with RESET# LOW
Power-up and reset parameters[53-55]
Parameter
Description
1.8 V VCC power supply
3.0 V VCC power supply
Min
1.7
2.7
Max
2.0
Unit
VCC
VCC
V
3.6
VCC and VCCQminimum and RESET# HIGH to
first access
tVCS
–
150
µs
Notes
53. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS).
54. VCCQ must be the same voltage as VCC
.
55. VCC ramp rate may be non-linear.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.7
Power-down
HYPERRAM™ devices are considered to be powered-off when the array power supply (VCC) drops below the VCC
Lock-out voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or
equal to VCC. At the VLKO level, the HYPERRAM™ device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC VCCQ).
During power-down or voltage drops below VLKO, the array power supply voltages must also drop below VCC
Reset (VRST) for a power-down period (tPD) for the part to initialize correctly when the power supply again rises
to VCC minimum. See Figure 23.
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is
again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no
assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the
HYPERBUS™ device is properly initialized.
V
(Max)
(Min)
CC
V
CC
No Device Access Allowed
V
CC
Device Access
Allowed
t
VCS
V
LKO
V
RST
t
PD
Time
Figure 23
Power-down or voltage drop
The following section describes the HYPERRAM™ device-dependent aspects of power-down specifications.
Table 23
Symbol
1.8 V power-down voltage and timing[56]
Parameter
VCC power supply
Min
1.7
1.5
0.7
50
Max
2.0
–
Unit
V
VCC
VLKO
VRST
tPD
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC VRST
–
–
µs
Table 24
3.0 V power-down voltage and timing[56]
Symbol
VCC
Parameter
VCC power supply
Min
2.7
2.4
0.7
50
Max
3.6
–
Unit
V
VLKO
VRST
tPD
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC VRST
–
–
µs
Note
56. VCC ramp rate can be non-linear.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Electrical specifications
9.8
Hardware reset
The RESET# input provides a hardware method of returning the device to the Standby state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws
CMOS standby current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not
allowed.
A hardware reset will do the following:
• Cause the configuration registers to return to their default values
• Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
• Force the device to exit the hybrid sleep state
• Force the device to exit the deep power-down state
After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped
during RESET# LOW, and the self-refresh row counter is reset to its default value, some rows may not be refreshed
within the required array refresh interval per Table 13. This may result in the loss of DRAM array data during or
immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware
reset and reload any required data.
tRP
RESET#
tRH
tRPH
CS#
Figure 24
Table 25
Hardware reset timing diagram
Power-up and reset parameters
Parameter
Description
RESET# pulse width
Min
200
200
400
Max
Unit
tRP
–
–
–
tRH
tRPH
Time between RESET# (HIGH) and CS# (low)
RESET# LOW to CS# LOW
ns
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
10
Timing specifications
The following section describes HYPERRAM™ device dependent aspects of timing specifications.
10.1
Key to switching waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
10.2
AC test conditions
Device
Under
Test
CL
Figure 25
Table 26
Test setup
Test specification[58]
Parameter
All speeds
15
Unit
Output load capacitance, CL
pF
Minimum input rise and fall slew rates (1.8 V) [57]
Minimum input rise and fall slew rates (3.0 V) [57]
Input pulse levels
1.13
V/ns
2.06
0.0-VCC
Q
Input timing measurement reference levels
Output timing measurement reference levels
VCCQ/2
VCCQ/2
V
VccQ
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Vss
Figure 26
Input waveform and measurement levels[59]
Notes
57. All AC timings assume this input slew rate.
58. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#.
59. Input timings for the differential CK/CK# pair are measured from clock crossings.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
10.3
Timing reference levels
tCK
VCCQ
CK, CK#
VT
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VT
RWDS
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VT
DQ[7:0]
VSSQ
Figure 27
DDR input timing reference level
tSCK
VCCQ
RWDS
VT
VSSQ
VCCQ
tDSS
tDSH
VOH(min)
VOL(max)
VT
DQ[7:0]
VSSQ
Figure 28
DDR output timing reference level
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
10.4
CLK characteristics
tCK
tCKHP
tCKHP
CK#
VIX (Max)
VCCQ / 2
VIX (Min)
CK
Figure 29
Table 27
Clock characteristics
Clock timings[60-62]
200 MHz
166 MHz
Parameter
CK period
Symbol
Unit
Min
Max
–
Min
6
Max
–
tCK
5
ns
CK half period - duty cycle
tCKHP
0.45
0.55
0.45
0.55
tCK
CK half period at frequency
Min = 0.45 tCK Min
Max = 0.55 tCK Min
tCKHP
2.25
2.75
2.7
3.3
ns
VID (AC) (min)
VID (DC) (min)
0
half cycle
-VID (DC) (min)
-VID (AC) (min)
time
Figure 30
Notes
Differential clock (CK/CK#) input swing
60. Clock jitter of ±5% is permitted.
61. Minimum frequency (Maximum tCK) is dependent upon maximum CS# LOW time (tCSM), initial latency and
burst length.
62. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
Table 28
Clock AC/DC electrical characteristics[63, 64]
Parameter Symbol
Min
Max
Unit
DC input voltage
VIN
VID(DC)
VID(AC)
VIX
-0.3
VCCQ + 0.3
VCCQ + 0.6
VCCQ + 0.6
VCCQ 0.6
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
VCCQ 0.4
VCCQ 0.6
VCCQ 0.4
V
Notes
63. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
64. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC
level of VCCQ.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
10.5
AC characteristics
10.5.1
Read transactions
Table 29
HYPERRAM™ specific read timing parameters
200 MHz
Min Max Min Max
166 MHz
Parameter
Symbol
Unit
Chip select HIGH between transactions - 1.8 V
Chip select HIGH between transactions - 3.0 V
HYPERRAM™ read-write recovery time - 1.8 V
HYPERRAM™ read-write recovery time - 3.0 V
Chip select setup to next CK rising edge
Data strobe valid - 1.8 V
6
6
–
–
6
6
–
–
tCSHI
35
35
4.0
–
–
36
36
3
–
tRWR
tCSS
tDSV
–
–
–
–
5.0
6.5
–
–
12
12
–
Data strobe valid - 3.0 V
–
–
Input setup - 1.8 V
0.5
0.5
0.5
0.5
35
35
0
0.6
0.6
0.6
0.6
36
36
0
tIS
Input setup - 3.0 V
–
–
Input hold - 1.8 V
–
–
tIH
Input hold - 3.0 V
–
–
HYPERRAM™ read initial access time - 1.8 V
HYPERRAM™ read initial access time- 3.0 V
Clock to DQs low Z
–
–
tACC
tDQLZ
tCKD
–
–
–
–
CK transition to DQ valid - 1.8 V
CK transition to DQ valid - 3.0 V
CK transition to DQ invalid - 1.8 V
CK transition to DQ invalid - 3.0 V
1
5.0
6.5
4.2
5.7
1
5.5
7
ns
1
1
0
0
4.6
5.6
tCKDI
0.5
0.5
Data valid (tDV min = The lesser of: tCKHP min - tCKD max +
tCKDI max) or tCKHP min - tCKD min + tCKDI min) - 1.8 V
1.45
1.45
–
–
1.8
1.3
–
–
[65, 66]
tDV
Data valid (tDV min = The lesser of: tCKHP min - tCKD max +
tCKDI max) or tCKHP min - tCKD min + tCKDI min) - 3.0 V
CK transition to RWDS valid - 1.8 V
CK transition to RWDS valid - 3.0 V
RWDS transition to DQ valid - 1.8 V
RWDS transition to DQ valid - 3.0 V
RWDS transition to DQ invalid - 1.8 V
RWDS transition to DQ invalid - 3.0 V
Chip select hold after CK falling edge
Chip select inactive to RWDS HIGH-Z - 1.8 V
Chip select inactive to RWDS HIGH-Z - 3.0 V
–
–
5.0
6.5
1
1
5.5
7
tCKDS
tDSS
tDSH
tCSH
-0.4
-0.4
-0.4
-0.4
0
+0.4
+0.4
+0.4
+0.4
–
-0.45 +0.45
-0.45 +0.45
-0.45 +0.45
-0.45 +0.45
0
–
–
–
6
7
–
–
5.0
6.5
t
DSZ
Notes
65. Refer to Figure 33 for data valid timing.
66. The tDV timing calculation is provided for reference only, not to determine the spec limit. The spec limit is
guaranteed by testing.
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
Table 29
HYPERRAM™ specific read timing parameters (Continued)
200 MHz
Min Max Min Max
166 MHz
Parameter
Symbol
tOZ
Unit
Chip select inactive to DQ HIGH-Z - 1.8 V
Chip select inactive to DQ HIGH-Z - 3.0 V
Refresh time - 1.8 V
–
–
5
6.5
–
–
–
6
7
35
35
1
36
36
1
–
tRFH
ns
Refresh time - 3.0 V
–
–
CK transition to RWDS low @CA phase @read - 1.8 V
CK transition to RWDS low @CA phase @read - 3.0 V
5.5
7
5.5
7
tCKDSR
1
1
tCSHI
tCSM
CS#
tCSS
tRWR =Read Write Recovery
CK, CK#
tCSH
tCSS
tACC = Access
4 cycle latency
tDSV
tCKDS
tDSZ
High = 2x Latency Count
RWDS
Low = 1x Latency Count
tDSS
tOZ
tIS
tIH
tDQLZ
tCKD
tDSH
Dn
A
Dn
B
Dn+1 Dn+1
DQ[7:0]
47:40 39:32 31:24 23:16 15:8 7:0
A
B
RWDS and Data
are edge aligned
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 31
Read timing diagram — No additional latency required
CS#
tRWR =Read Write Recovery
Additional Latency
tACC = Access
CK, CK#
4 cycle latency 1
tCKDS
4 cycle latency 2
tDSV
High = 2x Latency Count
RWDS
Low = 1x Latency Count
Dn
A
Dn Dn+1 Dn+1
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
B
A
B
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 32
Read timing diagram — With additional latency required
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Timing specifications
CS#
tCKHP
tCSHS tCSS
CK
CK#
tDSZ
tOZ
tCKDS
RWDS
tDSS
tCKD
tCKDI
tDV
tDQLZ
tCKD
tDSH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
Figure 33
Data valid timing[67-69]
10.5.2
Write transactions
Table 30
Write timing parameters
200 MHz
166 MHz
Parameter
Symbol
Unit
Min
35
35
35
–
Max
Min
36
36
36
–
Max
Read-write recovery time
Access time
tRWR
tACC
tRFH
tCSM
tCSM
tDMV
–
–
–
4
1
–
–
–
–
4
1
–
ns
Refresh time
Chip select maximum low time (85 °C)
Chip select maximum low time (105 °C)
RWDS data mask valid
–
–
µs
0
0
tCSHI
tCSM
CS#
tCSS
tCSH
tCSS
tRWR =Read Write Recovery
tACC = Access
CK,CK#
tDSV
4 cycle latency
tDSZ
tIS
tDMV
tIH
High = 2x Latency Count
Low = 1x Latency Count
RWDS
tIS
tIS
tIH
tIH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
39:32 31:24 23:16 15:8
7:0
DQ[7:0]
47:40
Command-Address
CK and Data
are center aligned
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 34
Notes
Write timing diagram — No additional latency
67. tCKD and tCKDI parameters define the beginning and end position of data valid period.
68. tDSS and tDSH define how early or late DQ may transition relative to RWDS. This is a potential skew between
the CK to DQ delay tCKD and CK to RWDS delay tCKDS
.
69. Since DQ and RWDS are the same output types, the tCKD, and tCKDS values track together (vary by the same
ratio).
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Physical interface
11
Physical interface
11.1
FBGA 24-ball 5 x 5 array footprint
HYPERRAM™ devices are provided in Fortified ball grid-array (FBGA), 1 mm pitch, 24-ball, 5 5 ball array footprint,
with 6mm 8mm body.
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
CK
CS#
RFU
RFU
RFU
DQ4
VssQ
CK#
Vss
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Figure 35
24-ball FBGA, 6 8 mm, 5 5 ball footprint, top view
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Package diagram
12
Package diagram
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
DIMENSIONS
SYMBOL
MIN.
-
NOM.
MAX.
1.00
-
A
-
-
2. ALL DIMENSIONS ARE IN MILLIMETERS.
A1
D
0.20
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D1
E1
MD
ME
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
5
24
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
b
0.35
0.45
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
002-15550 *A
JEDEC SPECIFICATION NO. REF: N/A
10.
Figure 36
Fortified ball grid-array 24-ball 6 8 1.0 mm (VAA024)
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
13
DDR center-aligned read strobe (DCARS) functionality
The HYPERRAM™ device offers an optional feature that enables independent skewing (phase shifting) of the
RWDS signal with respect to the read data outputs. This feature is provided in certain devices, based on the
ordering part number (OPN).
When the DCARS feature is provided, a second differential Phase Shifted Clock input PSC/PSC# is used as the
reference for RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase shifted
90 degrees to place the RWDS edges centered within the DQ signals valid data window. However, other degrees
of phase shift between CK/CK# and PSC/PSC# may be used to optimize the position of RWDS edges within the DQ
signals valid data window so that RWDS provides the desired amount of data setup and hold time in relation to
RWDS edges.
PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven LOW and HIGH respectively or,
both may be driven LOW during write transactions.
The PSC/PSC# is used in HYPERBUS™ devices. If single-ended mode is selected, then PSC# must be driven LOW
but must not be left floating (leakage concerns).
13.1
HYPERRAM™ products with DCARS signal descriptions
RESET#
VCC
VCCQ
CS#
CK
DQ[7:0]
RWDS
CK#
PSC
PSC#
VSS
VSSQ
Figure 37
HYPERBUS™ product with DCARS signal diagram
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
Table 31
Symbol
Signal descriptions
Type
Description
Chip Select. HYPERBUS™ transactions are initiated with a HIGH to LOW transition.
HYPERBUS™ transactions are terminated with a LOW to HIGH transition.
CS#
Differential Clock. Command, address, and data information is output with
respect to the crossing of the CK and CK# signals. Use of differential clock is
optional.
Single Ended Clock. CK# is not used, only a single ended CK is used. The clock is
not required to be free-running.
CK, CK#
Input
Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS signal
with respect to the CK/CK# inputs. If the CK/CK# (differential mode) is configured,
then PSC/PSC# are used. Otherwise, only PSC is used (single ended).
PSC (and PSC#) may be driven HIGH and LOW respectively or both may be driven
LOW during write transactions.
PSC, PSC#
Read-Write Data Strobe. Data bytes output during read transactions are aligned
with RWDS based on the phase shift from CK, CK# to PSC, PSC#. PSC, PSC# cause
the transitions of RWDS, thus the phase shift from CK, CK# to PSC, PSC# is used to
place RWDS edges within the data valid window. RWDS is an input during write
transactions to function as a data mask. At the beginning of all bus transactions
RWDS is an output and indicates whether additional initial latency count is
required (1 = Additional latency count, 0 = No additional latency count).
RWDS
Output
Data Input/Output. CA/Data information is transferred on these DQs during Read
DQ[7:0]
Input/Output
Input
and write transactions.
Hardware Reset. When LOW, the device will self initialize and return to the idle
state. RWDS and DQ[7:0] are placed into the HIGH-Z state when RESET# is LOW.
RESET# includes a weak pull-up, if RESET# is left unconnected it will be pulled up
to the HIGH state.
RESET#
VCC
Array Power.
VCC
Q
Input/Output Power.
Array Ground.
Power supply
VSS
VSS
Q
Input/Output Ground.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
13.2
HYPERRAM™ products with DCARS — FBGA 24-ball, 5 5 array footprint
1
2
3
4
5
A
B
C
D
E
RFU
CK
CS#
Vss
RESET# RFU
CK#
VssQ
VccQ
DQ7
Vcc
DQ2
DQ3
PSC
PSC#
DQ4
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
VccQ VssQ
Figure 38
24-ball FBGA, 6 8 mm, 5 5 ball footprint, top view
13.3
HYPERRAM™ memory with DCARS timing
The illustrations and parameters shown here are only those needed to define the DCARS feature and show the
relationship between the Phase shifted clock, RWDS, and data.
tCSHI
CS#
tCSH
tCSS
tCSS
tACC = Access time
4 cycle latency
CK, CK#
PSC, PSC#
RWDS
tDSV
tPSCRWDS
tDSZ
High = 2x Latency Count
Low = 1x Latency Count
tIS
tIH
tDQLZ
tCKD
tOZ
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
RWDS aligned
by PSC
Command-Address
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 39
Notes
HYPERRAM™ memory DCARS timing diagram[70-72]
70.Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new
transaction is initiated.
71. The memory drives RWDS during read transactions.
72. This example demonstrates a latency code setting of four clocks and no additional initial latency required.
73. This figure shows a closer view of the data transfer portion of Figure 37 in order to more clearly show the
Data valid period as affected by clock jitter and clock to output delay uncertainty.
74. The delay (phase shift) from CK to PSC is controlled by the HYPERBUS master interface (Host) and is gen-
erally between 40 and 140 degrees in order to place the RWDS edge within the data valid window with suffi-
cient set-up and hold time of data to RWDS. The requirements for data set-up and hold time to RWDS are
determined by the HYPERBUS™ master interface design and are not addressed by the HYPERBUS™ slave
timing parameters.
75. The HYPERBUS™ timing parameters of tCKD, and tCKDI define the beginning and end position of the data valid
period. The tCKD and tCKDI values track together (vary by the same ratio) because RWDS and Data are outputs
from the same device under the same voltage and temperature conditions.
Datasheet
53 of 59
002-24692 Rev. *I
2022-04-29
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
CS#
tCKHP
tCSH
tCSS
CK,CK#
PSC,PSC#
tPSCRWDS
tDSZ
tIS
tIH
RWDS
tCKDI
tCKD
tDQLZ
tDV
tOZ
tCKD
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
RWDS and Data are driven by the memory
Figure 40
Table 32
DCARS data valid timing[73-75]
DCARS read timing
Parameter
200 MHZ
166 MHZ
Symbol
Unit
Min
Max
Min
Max
Input setup - CK/CK# setup w.r.t PSC/PSC#
(Edge to edge)
tIS
tIH
0.5
0.5
–
–
0.6
–
CK half period - duty cycle
(Edge to edge)
–
5
0.6
–
–
ns
HYPERRAM™ PSC transition to RWDS
transition
tPSCRWDS
tPSCRWDS - tCKD
6.5
+0.5
Time delta between CK to DQ valid and PSC to
RWDS[76]
-1.0
+0.5
-1.0
Note
76. Sampled, not 100% tested.
Datasheet
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Ordering information
14
Ordering information
14.1
Ordering part number
The ordering part number is formed by a valid combination of the following:
S27KS
064
2
DP
B
H
I
02
0
Packing type
0 = Tray
3 = 13” Tape and reel
Model number (Additional ordering options)
02 = Standard 6 8 1.0 mm package (VAA024)
03 = DDR center-aligned read strobe (DCARS)
6 8 1.0 mm package (VAA024)
Temperature range / grade
I = Industrial (-40°C to + 85°C)
V = Industrial Plus (-40°C to + 105°C)
A = Automotive, (-40°C to + 85°C)
B = Automotive, AEC-Q100 grade 2 (-40°C to + 105°C)
Package materials
H = Low-halogen, Pb-free
Package type
B = 24-ball FBGA, 1.00 mm pitch (5 5 ball footprint)
Speed
GA = 200 MHz
DP = 166 MHz
Device technology
2 = 38-nm DRAM process technology - HYPERBUS™
3 = 38-nm DRAM Process technology - Octal
Density
064 = 64 Mb
Device family
S27KS 1.8 V-only, HYPERRAM™ self-refresh DRAM
S27KL 3.0 V-only, HYPERRAM™ self-refresh DRAM
Datasheet
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002-24692 Rev. *I
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64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Ordering information
14.2
Valid combinations
The Recommended combinations table lists configurations planned to be available in volume. Table 33 and
Table 34 will be updated as new combinations are released. Contact your local sales representative to confirm
availability of specific combinations and to check on newly released combinations.
Table 33
Valid combinations — Standard
Package,
Device
family
material,
and
Model Packing
Ordering part
number
Density Technology Speed
Package marking
number
type
temperature
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
064
064
064
064
064
064
064
064
2
2
2
2
2
2
2
2
DP
DP
GA
GA
DP
DP
GA
GA
BHI
BHI
BHI
BHI
BHV
BHV
BHV
BHV
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KL0642DPBHI020 7KL0642DPHI02
S27KL0642DPBHI023 7KL0642DPHI02
S27KL0642GABHI020 7KL0642GAHI02
S27KL0642GABHI023 7KL0642GAHI02
S27KL0642DPBHV020 7KL0642DPHV02
S27KL0642DPBHV023 7KL0642DPHV02
S27KL0642GABHV020 7KL0642GAHV02
S27KL0642GABHV023 7KL0642GAHV02
S27KS
S27KS
S27KS
S27KS
064
064
064
064
2
2
2
2
GA
GA
GA
GA
BHI
BHI
02
02
02
02
0
3
0
3
S27KS0642GABHI020 7KS0642GAHI02
S27KS0642GABHI023 7KS0642GAHI02
S27KS0642GABHV020 7KS0642GAHV02
S27KS0642GABHV023 7KS0642GAHV02
BHV
BHV
Table 34
Valid combinations — DCARS
Package,
Device
family
Model Packing
Ordering part
Package marking
number
Density Technology Speed material, and
temperature
number
type
S27KL
S27KL
S27KL
S27KL
064
064
064
064
2
2
2
2
DP
DP
GA
GA
BHI
BHI
BHI
BHI
03
03
03
03
0
3
0
3
S27KL0642DPBHI030 7KL0642DPHI03
S27KL0642DPBHI033 7KL0642DPHI03
S27KL0642GABHI030 7KL0642GAHI03
S27KL0642GABHI033 7KL0642GAHI03
S27KS
S27KS
064
064
2
2
GA
GA
BHI
BHI
03
03
0
3
S27KS0642GABHI030 7KS0642GAHI03
S27KS0642GABHI033 7KS0642GAHI03
Datasheet
56 of 59
002-24692 Rev. *I
2022-04-29
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Ordering information
14.3
Valid combinations — Automotive grade / AEC-Q100
Table 35 list configurations that are Automotive grade / AEC-Q100 qualified and are planned to be available in
volume. The table will be updated as new combinations are released. Contact your local sales representative to
confirm availability of specific combinations and to check on newly released combinations.
Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade
products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full
compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require
ISO/TS-16949 compliance.
Table 35
Valid combinations — Automotive grade / AEC-Q100
Package,
Device
family
Model Packing
Ordering part
number
Density Technology Speed material,and
number type
Package marking
temperature
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
S27KL
064
064
064
064
064
064
064
064
2
2
2
2
2
2
2
2
DP
DP
GA
GA
DP
DP
GA
GA
BHA
BHA
BHA
BHA
BHB
BHB
BHB
BHB
02
02
02
02
02
02
02
02
0
3
0
3
0
3
0
3
S27KL0642DPBHA020
S27KL0642DPBHA023
S27KL0642GABHA020
S27KL0642GABHA023
S27KL0642DPBHB020
S27KL0642DPBHB023
S27KL0642GABHB020
S27KL0642GABHB023
7KL0642DPHA02
7KL0642DPHA02
7KL0642GAHA02
7KL0642GAHA02
7KL0642DPHB02
7KL0642DPHB02
7KL0642GAHB02
7KL0642GAHB02
S27KS
S27KS
S27KS
S27KS
064
064
064
064
2
2
2
2
GA
GA
GA
GA
BHA
BHA
BHB
BHB
02
02
02
02
0
3
0
3
S27KS0642GABHA020
S27KS0642GABHA023
S27KS0642GABHB020
S27KS0642GABHB023
7KS0642GAHA02
7KS0642GAHA02
7KS0642GAHB02
7KS0642GAHB02
Datasheet
57 of 59
002-24692 Rev. *I
2022-04-29
64Mb HYPERRAM™ self-refresh DRAM (PSRAM)
HYPERBUS™ interface, 1.8 V/3.0 V
Revision history
Revision history
Document
Date of release
version
Description of changes
Changed document status to Final.
*F
2019-11-25
Added note in Figure 13.
Updated tCKDS and tCKD in Figure 32.
Updated Hybrid Burst Enable binary in Table 9.
Added Hybrid 128 burst in Table 11.
Fixed typos in Table 12 and Table 27.
Updated parameters in Table 17.
Added Thermal values in Table 20.
*G
2020-05-05
Added Figure 27 and Figure 28 in “Timing reference levels” on page 43.
Added ESD information in “Electrical specifications” on page 32.
Added Figure 30 Differential Clock (CK/CK#) Input Swing.
Removed Valid Combinations — DCARS MPNs in “Valid combinations” on
page 56.
Removed Valid Combinations — DCARS Automotive Grade / AEC-Q100 MPNs
in “Valid combinations — Automotive grade / AEC-Q100” on page 57.
Updated Table 15 with HS setting.
Updated leakage current specifications in Table 18.
Updated “Master clock type” on page 27.
Updated Figure 27 and Figure 28 for input and output measurement
reference level.
*H
*I
2022-01-18
2022-04-29
Updated tDSS and tDSH for 166MHz, added note 71 on tDV in Table 29.
Added Figure 33 on “Data valid timing”.
Updated ordering part numbers in Table 33 and Table 35.
Migrated to IFX template.
Updated template.
Updated Figure 35.
Added Table 34.
Datasheet
58 of 59
002-24692 Rev. *I
2022-04-29
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-04-29
Published by
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
Do you have a question about this
document?
Go to www.infineon.com/support
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
Document reference
002-24692 Rev. *I
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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