S29AL016J70BFA013_技术文档

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S29AL016J

16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V,

Boot Sector Flash

Distinctive Characteristics

Architectural Advantages

Performance Characteristics

 Single Power Supply Operation

 High Performance

❐ Full voltage range: 2.7 to 3.6 volt read and write operations

❐ Access times as fast as 55 ns

for battery-powered applications

❐ Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)

❐ Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)

❐ Industrial temperature range (–40°C to +85°C)

❐ Extended temperature range (–40°C to +125°C)

 Ultra Low Power Consumption (typical values at 5 MHz)

 Manufactured on 110 nm Process Technology

❐ Fully compatible with 200 nm S29AL016D

 Secured Silicon Sector region

❐ 128-word/256-byte sector for permanent, secure identifica-

tion through an 8-word/16-byte random Electronic Serial

Number accessible through a command sequence

❐ May be programmed and locked at the factory or by the cus-

tomer

❐ 0.2 µA Automatic Sleep mode current

❐ 0.2 µA standby mode current

❐ 7 mA read current

❐ 20 mA program/erase current

 Cycling Endurance: 1,000,000 cycles per sector typical

 Flexible Sector Architecture

❐ One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64

Kbyte sectors (byte mode)

 Data Retention: 20 years typical

❐ One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32

Package Options

 48-ball Fine-pitch BGA

 64-ball Fortified BGA

 48-pin TSOP

Kword sectors (word mode)

 Sector Group Protection Features

❐ Ahardware method of locking a sector to prevent any program

or erase operations within that sector

❐ Sectors can be locked in-system or via programming equip-

ment

❐ Temporary Sector Unprotect feature allows code changes in

previously locked sectors

Software Features

 CFI (Common Flash Interface) Compliant

 Unlock Bypass Program Command

❐ Provides device-specific information to the system, allowing

host software to easily reconfigure for different Flash devices

❐ Reduces overall programming time when issuing multiple

program command sequences

 Erase Suspend/Erase Resume

 Top or Bottom Boot Block Configurations Available

❐ Suspends an erase operation to read data from, or program

data to, a sector that is not being erased, then resumes the

erase operation

 Compatibility with JEDEC standards

❐ Pinout and software compatible with single-power supply

Flash

❐ Superior inadvertent write protection

 Data# Polling and Toggle Bits

❐ Provides a software method of detecting program or erase

operation completion

Hardware Features

 Ready/Busy# Pin (RY/BY#)

❐ Provides a hardware method of detecting program or erase

cycle completion

 Hardware Reset Pin (RESET#)

❐ Hardware method to reset the device to reading array data

 WP# input pin

❐ For boot sector devices: at V_IL, protects first or last 16 Kbyte

sector depending on boot configuration (top boot or bottom

boot)

Cypress Semiconductor Corporation

Document Number: 002-00777 Rev. *Q

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 21, 2018

S29AL016J

General Description

The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in

48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48-pin TSOP packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with

the standard system 3.0 volt V_CCsupply. A 12.0 V V_PPor 5.0 V_CCare not required for write or erase operations. The device can also

be programmed in standard EPROM programmers.

The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus

contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

The S29AL016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine

that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an

internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal

algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During

erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7

(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array

data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automatically inhibits write operations during power

transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The

RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system

microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters

the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in

both these modes.

Cypress combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost

effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Document Number: 002-00777 Rev. *Q

Page 2 of 57

S29AL016J

Contents

1.

2.

3.

Product Selector Guide............................................... 4

10.10Command Definitions Table ......................................... 30

Block Diagram.............................................................. 4

11. Write Operation Status............................................... 32

11.1 DQ7: Data# Polling....................................................... 32

11.2 RY/BY#: Ready/Busy#.................................................. 33

11.3 DQ6: Toggle Bit I .......................................................... 33

11.4 DQ2: Toggle Bit II ......................................................... 33

11.5 Reading Toggle Bits DQ6/DQ2..................................... 34

11.6 DQ5: Exceeded Timing Limits ...................................... 35

11.7 DQ3: Sector Erase Timer.............................................. 35

Connection Diagrams.................................................. 5

3.1 Special Handling Instructions......................................... 7

4.

5.

6.

Pin Configuration......................................................... 8

Logic Symbol ............................................................... 8

Ordering Information................................................... 9

6.1 S29AL016J Standard Products...................................... 9

6.2 Recommended Combinations...................................... 10

12. Absolute Maximum Ratings....................................... 36

13. Operating Ranges....................................................... 37

7.

Device Bus Operations.............................................. 11

14. DC Characteristics...................................................... 38

14.1 CMOS Compatible........................................................ 38

7.1 Word/Byte Configuration.............................................. 12

7.2 Requirements for Reading Array Data......................... 12

7.3 Writing Commands/Command Sequences.................. 12

7.4 Program and Erase Operation Status.......................... 12

7.5 Standby Mode.............................................................. 13

7.6 Automatic Sleep Mode................................................. 13

7.7 RESET#: Hardware Reset Pin..................................... 13

7.8 Output Disable Mode ................................................... 13

7.9 Autoselect Mode .......................................................... 16

7.10 Sector Group Protection/Unprotection......................... 17

7.11 Temporary Sector Group Unprotect............................. 18

15. Test Conditions........................................................... 39

16. Key to Switching Waveforms..................................... 40

17. AC Characteristics...................................................... 41

17.1 Read Operations........................................................... 41

17.2 Hardware Reset (RESET#)........................................... 42

17.3 Word/Byte Configuration (BYTE#)................................ 43

17.4 Erase/Program Operations........................................... 44

17.5 Temporary Sector Group Unprotect.............................. 47

17.6 Alternate CE# Controlled Erase/Program Operations .. 49

8.

Secured Silicon Sector Flash Memory Region ....... 20

8.1 Factory Locked: Secured Silicon Sector Programmed

and Protected at the Factory........................................ 20

8.2 Customer Lockable: Secured Silicon Sector NOT

Programmed or Protected at the Factory..................... 21

18. Erase and Programming Performance ..................... 50

19. TSOP and BGA Pin Capacitance............................... 50

20. Physical Dimensions.................................................. 51

20.1 TS 048—48-Pin Standard TSOP.................................. 51

20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA)

8.15 mm x 6.15 mm...................................................... 52

20.3 LAE064—64-Ball Fortified Ball Grid Array (BGA)

9 mm x 9 mm................................................................ 53

9.

Common Flash Memory Interface (CFI)................... 22

9.1 Hardware Data Protection............................................ 24

10. Command Definitions................................................ 25

10.1 Reading Array Data ..................................................... 25

10.2 Reset Command.......................................................... 25

10.3 Autoselect Command Sequence ................................. 25

10.4 Enter/Exit Secured Silicon Sector Command

Sequence..................................................................... 26

10.5 Word/Byte Program Command Sequence................... 26

10.6 Unlock Bypass Command Sequence .......................... 26

10.7 Chip Erase Command Sequence ................................ 27

10.8 Sector Erase Command Sequence ............................. 28

10.9 Erase Suspend/Erase Resume Commands ................ 28

21. Document History....................................................... 54

Document History Page ..................................................... 54

Sales, Solutions, and Legal Information .......................... 57

Worldwide Sales and Design Support ......................... 57

Products ....................................................................... 57

PSoC® Solutions ......................................................... 57

Cypress Developer Community ................................... 57

Technical Support ........................................................ 57

Document Number: 002-00777 Rev. *Q

Page 3 of 57

S29AL016J

1. Product Selector Guide

Family Part Number

S29AL016J

Speed Option

Voltage Range: V = 2.7 V–3.6 V

–

70

–

CC

V

= 3.0 V–3.6 V

55

30

CC

Max access time, ns (t

)

70

30

ACC

Max CE# access time, ns (t

)

CE

)

OE

Note

1. See Section 17. AC Characteristics on page 41 for full specifications.

2. Block Diagram

RY/BY#

DQ0–DQ15 (A-1)

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

WE#

BYTE#

WP#

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

V

Detector

CC

Timer

Cell Matrix

A0–A19

Document Number: 002-00777 Rev. *Q

Page 4 of 57

S29AL016J

3. Connection Diagrams

Figure 1. 48-pin Standard TSOP (TS048)

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

A19

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

WP#

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

Document Number: 002-00777 Rev. *Q

Page 5 of 57

S29AL016J

Figure 2. 48-ball Fine-pitch BGA (VBK048)

(Top View, Balls Facing Down)

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

A19

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

WP#

A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

Figure 3. 64-ball Fortified BGA

(Top View, Balls Facing Down)

A8

B8

C8

D8

E8

F8

G8

NC

H8

NC

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

V_CC

WE#

RESET#

NC

A19

DQ5

DQ12

DQ4

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY#

WP#

A18

NC

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

B1

C1

D1

E1

F1

G1

NC

H1

NC

Document Number: 002-00777 Rev. *Q

Page 6 of 57

S29AL016J

3.1 Special Handling Instructions

Special handling is required for Flash Memory products in BGA packages.

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data

integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.

Document Number: 002-00777 Rev. *Q

Page 7 of 57

S29AL016J

4. Pin Configuration

A0–A19

DQ0–DQ14

DQ15/A-1

BYTE#

CE#

20 addresses

15 data inputs/outputs

DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)

Selects 8-bit or 16-bit mode

Chip enable

OE#

Output enable

WE#

Write enable

WP#

Write protect: The WP# contains an internal pull-up; when unconnected, WP is at V .

IH

RESET#

RY/BY#

Hardware reset

Ready/Busy output

V

3.0 volt-only single power supply (see Section 1. Product Selector Guide on page 4 for speed options and voltage supply tolerances)

CC

V

Device ground

SS

NC

Pin not connected internally

5. Logic Symbol

20

A0–A19

16 or 8

DQ0–DQ15

(A-1)

CE#

OE#

WE#

RESET#

BYTE#

WP#

RY/BY#

Document Number: 002-00777 Rev. *Q

Page 8 of 57

S29AL016J

6. Ordering Information

6.1 S29AL016J Standard Products

Cypress standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

S29AL016J

70

T

F

I/A

01

0

Packing Type

0 = Tray

2 = 7” Tape and Reel

3 = 13” Tape and Reel

Model Number

01 = V = 2.7 - 3.6V, top boot sector device (CFI Support)

CC

02 = V = 2.7 - 3.6V, bottom boot sector device (CFI Support)

CC

03 = V = 2.7 - 3.6V, top boot sector device (No CFI Support)

CC

04 = V = 2.7 - 3.6V, bottom boot sector device (No CFI Support)

CC

R1 = V = 3.0 - 3.6V, top boot sector device (CFI Support)

CC

R2 = V = 3.0 - 3.6V, bottom boot sector device (CFI Support)

CC

Temperature Range

I = Industrial (-40°C to +85°C)

N = Extended (-40°C to +125°C)

A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)

M = Automotive, AEC-Q100 Grade 1 (-40 °C to +125 °C)

Package Material Set

F = Pb-Free

H = Low-Halogen, Pb-Free

Package Type

T = Thin Small Outline Package (TSOP) Standard Pinout

B = Fine-pitch Ball-Grid Array Package

F = Fortified Ball-Grid Array Package

Speed Option

55 = 55 ns Access Speed

70 = 70 ns Acess Speed

Device Number/Description

S29AL016J

16 Megabit Flash Memory manufactured using 110 nm process technology

3.0 Volt-only Read, Program, and Erase

Notes

2. BGA package marking omits leading “S29” and packing type designator from ordering part number.

3. TSOP package markings omit packing type designator from ordering part number.

Document Number: 002-00777 Rev. *Q

Page 9 of 57

S29AL016J

6.2 Recommended Combinations

Valid Combinations — S29AL016J

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm

availability of specific valid combinations and to check on newly released combinations.

S29AL016J Valid Combination

Package Type, Material,

Device Number

Speed Option

and Temperature Range

Model Number

Packing Type

Package Description

TFI, TFN

0, 3 ^[4]

TS048 ^[6]

TSOP

55

BFI, BFN, BHI, BHN

FFI, FFN

R1, R2

VBK048 ^[7]

LAE064 ^[7]

TS048 ^[6]

Fine-Pitch BGA

Fortified BGA

TSOP

0, 2, 3 ^[4]

0, 3 ^[4]

TFI, TFN

S29AL016J

BFI, BFN, BHI, BHN

FFI, FFN

01, 02

03, 04

VBK048 ^[7]

LAE064 ^[7]

TS048 ^[6]

Fine-Pitch BGA

Fortified BGA

TSOP

0, 2, 3 ^[4]

70

TFI

0, 3 ^[4]

BFN, BHN

0, 2, 3 ^[4]

VBK048 ^[7]

Fine-Pitch BGA

Notes

4. Type 0 is standard. Specify other options as required.

5. Type 1 is standard. Specify other options as required.

6. TSOP package markings omit packing type designator from ordering part number.

7. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations — Automotive Grade / AEC-Q100

The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The

table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific

combinations and to check on newly released combinations.

Automotive Grade / AEC-Q100 Valid Combinations

Speed

Option

Package Type, Material, and

Temperature Range

Model

Number

Package

Description

Device Number

Packing Type

TFA

BFA, BHA

FFA

0, 3

TS048 ^[9]

VBK048 ^[10]

LAE064 ^[10]

TS048 ^[9]

TSOP

55

R1, R2

Fine-Pitch BGA

Fortified BGA

TSOP

0, 2, 3

0, 3

S29AL016J

TFA

BFA, BHA

FFA

01, 02

02

VBK048 ^[10]

LAE064 ^[10]

TS048 ^[10]

Fine-Pitch BGA

Fortified BGA

TSOP

70

0, 2, 3

3

TFM

Notes

8. Type 0 is standard. Specify other options as required.

9. TSOP package markings omit packing type designator from ordering part number.

10. BGA package marking omits leading S29 and packing type designator from ordering part number.

Document Number: 002-00777 Rev. *Q

Page 10 of 57

S29AL016J

7. Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command

register. The command register itself does not occupy any addressable memory location. The register is composed of latches that

store the commands, along with the address and data information needed to execute the command. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device

bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these

operations in further detail.

Table 1. S29AL016J Device Bus Operations

DQ8–DQ15

BYTE# = V BYTE# = V

IH

Operation

Read

CE#

OE#

L

WE#

H

RESET#

WP#

X

Addresses ^[11]

DQ0– DQ7

IL

L

H

A

D

OUT

IN

OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

L

H

L

[13]

X

[14]

Standby

Output Disable

Reset

V

 0.3 V

X

V

 0.3 V

X

High-Z

CC

L

H

L

X

Sector Group

Protect ^{[12, 13]}

Sector Address, A6 = L,

L

H

L

V

H

[14]

X

ID

A3 = A2 = L, A1 = H, A0 = L

Sector Group

Sector Address, A6 = H,

A3 = A2 = L, A1 = H, A0 = L

Unprotect ^{[12, 13]}

Temporary

Sector Group

Unprotect

X

V

H

A

[14]

High-Z

ID

IN

Legend

L = Logic Low = V H = Logic High = V

IL;

V

= 8.5 V to 12.5 V; X = Don’t Care; A = Address In; D

= Data Out

IH; ID

IN

OUT

Notes

11. Address In = Amax:A0 in WORD mode (BYTE#=V ), Address In = Amax:A-1 in BYTE mode (BYTE#=V ). Sector addresses are Amax to A12 in both WORD mode

IH

IL

and BYTE mode.

12. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Section 7.10 Sector Group Protection/Unprotection on

page 17.

13. If WP# = V , the outermost sector remains protected (determined by device configuration). If WP# = V , the outermost sector protection depends on whether the

IL

IH

sector was last protected or unprotected using the method described in Section 7.10 Sector Group Protection/Unprotection on page 17. The WP# contains an internal

pull-up; when unconnected, WP is at V

.

IH

14. D or D

as required by command sequence, data polling, or sector group protection algorithm.

IN

OUT

Document Number: 002-00777 Rev. *Q

Page 11 of 57

S29AL016J

7.1 Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is

set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by

CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

7.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V_IL. CE# is the power control and selects the

device. OE# is the output control and gates array data to the output pins. WE# should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no

spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read access until the command register contents are altered.

See Section 10.1 Reading Array Data on page 25 for more information. Refer to the AC Section 17.1 Read Operations on page 41

for timing specifications and to Figure 15 on page 41 for the timing diagram. I_CC1in Section 14. DC Characteristics on page 38

represents the active current specification for reading array data.

7.3 Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive WE# and CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Section 7.1

Word/Byte Configuration on page 12 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,

only two write cycles are required to program a word or byte, instead of four. Section 10.5 Word/Byte Program Command

Sequence on page 26 has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 14 and Table 4 on page 15 indicate

the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector.

The Section 10. Command Definitions on page 25 has details on erasing a sector or the entire chip, or suspending/resuming the

erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to Section 7.9 Autoselect Mode on page 16 and Section 10.3 Autoselect Command Sequence on page 25

for more information.

I_CC2in Section 14. DC Characteristics on page 38 represents the active current specification for the write mode. Section 17. AC

Characteristics on page 41 contains timing specification tables and timing diagrams for write operations.

7.4 Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0.

Standard read cycle timings and I_CCread specifications apply. Refer to Section 11. Write Operation Status on page 32 for more

information, and to Section 17. AC Characteristics on page 41 for timing diagrams.

Document Number: 002-00777 Rev. *Q

Page 12 of 57

S29AL016J

7.5 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V_CC 0.3 V. (Note that this is a more

restricted voltage range than V_IH.) If CE# and RESET# are held at V_IH, but not within V_CC 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The device requires standard access time (t_CE) for read access when the device is in

either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

I_CC3and I_CC4represents the standby current specification shown in the table in Section 14. DC Characteristics on page 38.

7.6 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when

addresses remain stable for t_ACC+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.

Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and

always available to the system. I_CC4in the Section 14. DC Characteristics on page 38 represents the automatic sleep mode current

specification.

7.7 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET#

pin to V_ILfor at least a period of t_RP, the device immediately terminates any operation in progress, tristates all data output pins, and

ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading

array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence,

to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V_SS±0.3V, the device draws CMOS standby

current (I_CC4). If RESET# is held at V_ILbut not within V_SS±0.3/0.1V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the

system to read the boot-up firmware from the Flash memory. Note that the CE# pin should only go to V_ILafter RESET# has gone to

V_IH. Keeping CE# at V_ILfrom power up through the first read could cause the first read to retrieve erroneous data.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is

complete, which requires a time of t_READY(during Embedded Algorithms). The system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is

1), the reset operation is completed within a time of t_READY(not during Embedded Algorithms). The system can read data t_RHafter

the RESET# pin returns to V_IH.

Refer to the tables in Section 17. AC Characteristics on page 41 for RESET# parameters and to Figure 16 on page 42 for the timing

diagram.

7.8 Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins are placed in the high impedance state.

Document Number: 002-00777 Rev. *Q

Page 13 of 57

S29AL016J

Table 2. Sector Address Tables (Top Boot Device)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector

SA0

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A14

X

0

A13

X

0

A12

X

0

Kwords)

Byte Mode (x8)

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

Word Mode (x16)

00000–07FFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FBFFF

FC000–FCFFF

FD000–FDFFF

FE000–FFFFF

64/32

32/16

8/4

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8/4

1

X

16/8

Note

15. Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Section 7.1 Word/Byte Configuration on page 12.

Table 3. Secured Silicon Sector Addresses (Top Boot)

Sector Size (bytes/words)

x8 Address Range

x16 Address Range

FFF80h–FFFFFh

256/128

1FFF00h–1FFFFFh

Document Number: 002-00777 Rev. *Q

Page 14 of 57

S29AL016J

Table 4. Sector Address Tables (Bottom Boot Device)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector

SA0

A19

0

1

A18

0

1

0

1

A17

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A14

0

A13

0

A12

X

0

Kwords)

Byte Mode (x8)

000000–003FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

Word Mode (x16)

00000–01FFF

02000–02FFF

03000–03FFF

04000–07FFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FFFFF

16/8

8/4

SA1

0

1

SA2

0

1

8/4

SA3

1

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Note

16. Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the Section 7.1 Word/Byte Configuration on page 12.

Table 5. Secured Silicon Sector Addresses (Bottom Boot)

Sector Size (bytes/words)

x8 Address Range

x16 Address Range

00000h–0007Fh

256/128

000000h–0000FFh

Document Number: 002-00777 Rev. *Q

Page 15 of 57

S29AL016J

7.9 Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier

codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be

programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect mode requires V_ID(8.5 V to 12.5 V) on address pin A9. Address pins A6 and

A3–A0 must be as shown in Table 6. In addition, when verifying sector group protection, the sector address must appear on the

appropriate highest order address bits (see Table 2 on page 14 and Table 4 on page 15). Table 6 shows the remaining address bits

that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the

corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown

in Table 13 on page 30. This method does not require V_ID. See Section 10. Command Definitions on page 25 for details on using the

autoselect mode.

Table 6. S29AL016J Autoselect Codes (High Voltage Method)

Description

Mode CE# OE# WE# A19 to A10 A9

A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 DQ8 to DQ15

DQ7 to DQ0

Manufacturer ID: Cypress

L

H

X

V

X

L

X

L

X

22h

X

01h

C4h

49h

ID

Word

Device ID: S29AL016J

(Top Boot Block)

X

V

X

L

X

L

H

ID

Byte

Word

Byte

22h

X

Device ID: S29AL016J

(Bottom Boot Block)

X

SA

X

V

X

L

X

L

H

L

ID

X

01h (protected)

Sector Group Protection

Verification

L

H

X

00h (unprotected)

Secured Silicon Sector

Indicator Bit (DQ7) Top Boot

Block

8Eh (factory locked)

0Eh (not factory

locked)

H

X

Secured Silicon Sector

Indicator Bit (DQ7) Bottom Boot

Block

96h (factory

locked)16h (not

factory locked)

X

ID

Legend

L = Logic Low = V H = Logic High = V SA = Sector Address; X = Don’t care

IL;

IH;

Note

17. The autoselect codes may also be accessed in-system via command sequences. See Table 13 on page 30.

Document Number: 002-00777 Rev. *Q

Page 16 of 57

S29AL016J

7.10 Sector Group Protection/Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector group (see Table 2

on page 14 to Table 4 on page 15). The hardware sector group unprotection feature re-enables both program and erase operations

in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods.

Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming

equipment. Figure 5 on page 19 shows the algorithms and Figure 26 on page 48 shows the timing diagram. This method uses

standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to

the first sector group unprotect write cycle.

The device is shipped with all sector groups unprotected. Cypress offers the option of programming and protecting sector groups at

its factory prior to shipping the device through Cypress Programming Service. Contact a Cypress representative for details.

It is possible to determine whether a sector group is protected or unprotected. See Section 7.9 Autoselect Mode on page 16 for

details.

Table 7. S29AL016J Top Boot Device Sector/Sector Group Protection

Sector / Sector Block

SA0-SA3

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA29

SA30

A19

0

A18

0

A17

0

A16

X

0

A15

X

0

A14

X

0

A13

X

0

A12

X

Sector / Sector Block Size

256 (4x64) Kbytes

128 (2x64) Kbytes

64 Kbytes

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

X

SA31

1

X

32 Kbytes

SA32

1

0

8 Kbytes

SA33

1

0

1

8 Kbytes

SA34

1

X

16 Kbytes

Table 8. S29AL016J Bottom Boot Device Sector/Sector Group Protection

Sector / Sector Block

SA0

A19

0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

Sector / Sector Block Size

16 Kbytes

X

0

SA1

0

1

8 Kbytes

SA2

0

1

8 Kbytes

SA3

0

1

X

32 Kbytes

SA4

0

1

X

64 (1x64) Kbytes

128 (2x64) Kbytes

256 (4x64) Kbytes

SA5-SA6

SA7-SA10

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

Document Number: 002-00777 Rev. *Q

Page 17 of 57

S29AL016J

7.11 Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group

Unprotect mode is activated by setting the RESET# pin to V_ID. During this mode, formerly protected sector groups can be

programmed or erased by selecting the sector group addresses. Once V_IDis removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 4 shows the algorithm, and Figure 25 on page 47 shows the timing diagrams,

for this feature.

Figure 4. Temporary Sector Group Unprotect Operation

START

[18]

ID

RESET# = V

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector Group

Unprotect Completed ^[19]

Notes

18. All protected sector unprotected. (If WP# = V , the highest or lowest address sector remains protected for uniform sector devices; the top or bottom two address sectors

IL

remains protected for boot sector devices).

19. All previously protected sector groups are protected once again.

Document Number: 002-00777 Rev. *Q

Page 18 of 57

S29AL016J

Figure 5. In-System Sector Group Protect/Unprotect Algorithms

START

Protect all sectors:

PLSCNT = 1

START

The indicated portion

of the sector group protect

algorithm must be

RESET# = V_ID

PLSCNT = 1

RESET# = V_ID

performed for all

unprotected sector groups

prior to issuing the

Wait 1 µs

first sector group

unprotect address

Wait 1 µs

No

First Write

Temporary Sector

Group Unprotect Mode

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Group Unprotect Mode

Yes

No

All sectors

protected?

Yes

Set up sector

group address

Yes

Set up first sector

group address

Sector Group Protect:

Write 60h to sector group

address with

A6 = 0,

A3 = A2 = 0,

A1 = 1, A0 = 0

Sector Group Unprotect:

Write 60h to sector

address with

A6 = 1,

A3 = A2 = 0,

A1 = 1, A0 = 0

Wait 150 µs

Verify Sector Group

Protect: Write 40h

Wait 1.5 ms

to sector group address

with A6 = 0,

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A3 = A2 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

Reset

PLSCNT = 1

A6 = 1,

A3 = A2 = 0,

A1 = 1, A0 = 0

Read from

sector group address

with A6 = 0,

Increment

PLSCNT

A3 = A2 = 0,

A1 = 1, A0 = 0

Read from

No

sector group address

with A6 = 1,

No

A3 = A2 = 0,

PLSCNT

= 25?

Data = 01h?

A1 = 1, A0 = 0

No

Set up

next sector group

address

Yes

No

Yes

PLSCNT

= 1000?

Data = 00h?

Yes

Protect another

sector group?

Device failed

Yes

No

Last sector

No

Device failed

group verified?

Remove V_ID

from RESET#

Yes

Write reset

command

Remove V_ID

from RESET#

Sector Group

Unprotect Algorithm

Sector Group

Protect Algorithm

Sector Group

Protect complete

Write reset

command

Sector Group

Unprotect complete

Document Number: 002-00777 Rev. *Q

Page 19 of 57

S29AL016J

8. Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an

Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether

or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be

changed, which prevents cloning of a factory-locked part. This ensures the security of the ESN once the product is shipped to the

field.

Cypress offers the device with the Secured Silicon Sector either factory-locked or customer-lockable. The factory-locked version is

always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The

customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector in

any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus,

the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory

locked.

The system accesses the Secured Silicon Sector through a command sequence (see Section 10.4 Enter/Exit Secured Silicon Sector

Command Sequence on page 26). After the system writes the Enter Secured Silicon Sector command sequence, it may read the

Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the

system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or

following a hardware reset, the device reverts to sending commands to the boot sectors.

8.1 Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory

In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon

Sector cannot be modified in any way. The device is available pre-programmed with one of the following:

 A random, secure ESN only.

 Customer code through the ExpressFlash service.

 Both a random, secure ESN and customer code through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h–0000Fh in byte

mode (or 00000h–00007h in word mode). In the Top Boot device, the ESN is in sector 34 at addresses 1FFFF0h–1FFFFFh in byte

mode (or FFFF8h–FFFFFh in word mode).

Customers may opt to have their code programmed by Cypress through the Cypress ExpressFlash service. Cypress programs the

customer’s code, with or without the random ESN. The devices are then shipped from the Cypress factory with the Secured Silicon

Sector permanently locked. Contact a Cypress representative for details on using the Cypress ExpressFlash service.

Document Number: 002-00777 Rev. *Q

Page 20 of 57

S29AL016J

8.2 Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory

The customer lockable version allows the Secured Silicon Sector to be programmed once, and then permanently locked after it

ships from Cypress. Note that the unlock bypass functions is not available when programming the Secured Silicon Sector.

The Secured Silicon Sector area can be protected using the following procedures:

 Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector group protect

algorithm as shown in Figure 5 on page 19, substituting the sector group address with the Secured Silicon Sector group address

(A0=0, A1=1, A2=0, A3=1, A4=1, A5=0, A6=0, A7=0). Note that this method is only applicable to the Secured Silicon Sector.

 To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 6 on page 21.

Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command

sequence to return to reading and writing the remainder of the array.

The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for

unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified in

any way.

Figure 6. Secured Silicon Sector Protect Verify

START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# = V_ID

Wait 1 ms

Write 60h to

any address

Remove V_ID

from RESET#

Write 40h to SecSi

Sector address

with A0=0, A1=1,

A2=0, A3=1, A4=1,

A5=0, A6=0, A7=0

Write reset

command

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A0=0, A1=1,

A2=0, A3=1, A4=1,

A5=0, A6=0, A7=0

Document Number: 002-00777 Rev. *Q

Page 21 of 57

S29AL016J

9. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows

specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-

independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors

can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or

address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses

given in Table 9 to Table 12 on page 23. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading

CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query

mode, and the system can read CFI data at the addresses given in Table 9 to Table 12 on page 23. The system must write the reset

command to return the device to the autoselect mode.

Table 9. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

32h

34h

0000h

Address for Alternate OEM Extended Table (00h = none exists)

Table 10. System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

V

Min. (write/erase)

CC

1Bh

1Ch

36h

38h

0027h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0003h

0000h

0009h

0000h

0005h

0000h

0004h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

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S29AL016J

Table 11. Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N(00h = not supported)

Number of Erase Block Regions within device

2Ch

58h

0004h

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0080h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

001Eh

0000h

0001h

Table 12. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

Process Technology (Bits 5-2)

0011b = 0.11 µm Floating Gate NOR

45h

8Ah

000Ch

Erase Suspend

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Group Protect

0 = Not Supported, X= Number of sectors in smallest sector group

Sector Group Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Group Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

49h

92h

0004h

Simultaneous Operation

4Ah

4Bh

4Ch

4Dh

4Eh

94h

96h

98h

9Ah

9Ch

0000h

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00 = Not Supported, D7-D4: Volt, D3-D0: 100mV

ACC (Acceleration) Supply Maximum

00 = Not Supported, D7-D4: Volt, D3-D0: 100mV

WP# Protection

00 = Uniform Device without WP Protect

01 = Boot Device with TOP and Bottom WP Protect

02 = Bottom Boot Device with WP Protect

03 = Top Boot Device with WP Protect

04 = Uniform Device with Bottom WP Protect

05 = Uniform Device with Top WP Protect

06 = Uniform Device with All Sectors WP Protect

4Fh

50h

9Eh

A0h

00XXh

Program Suspend

00 = Not Supported, 01 = Supported

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9.1 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent

writes (refer to Table 13 on page 30 for command definitions). In addition, the following hardware data protection measures prevent

accidental erasure or programming, which might otherwise be caused by spurious system level signals during V_CCpower-up and

power-down transitions, or from system noise.

9.1.1 Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This protects data during V_CCpower-up and power-down.

The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored

until V_CCis greater than V_LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when

V_CCis greater than V_LKO

.

9.1.2 Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

9.1.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle, CE# and WE# must be

a logical zero while OE# is a logical one.

9.1.4 Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically reset to reading array data on power-up.

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10. Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. Table 13

on page 30 defines the valid register command sequences. Writing incorrect address and data values or writing them in the

improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#

or CE#, whichever happens first. Refer to the appropriate timing diagrams in Section 17. AC Characteristics on page 41.

10.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device

is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data

using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.

After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See Section 10.9 Erase Suspend/Erase Resume Commands on page 28 for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect

mode. See Section 10.2 Reset Command on page 25.

See also Section 7.2 Requirements for Reading Array Data on page 12 for more information. The Section 17.1 Read Operations on

page 41 provides the read parameters, and Figure 15 on page 41 shows the timing diagram.

10.2 Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This

resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is

complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins.

This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect

mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also

applies during Erase Suspend).

10.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether

or not a sector is protected. Table 13 on page 30 shows the address and data requirements. This method is an alternative to that

shown in Table 6 on page 16, which is intended for PROM programmers and requires V_IDon address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then

enters the autoselect mode, and the system may read at any address any number of times, without initiating another command

sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read

cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to Table 2 on page 14 and Table 4 on page 15 for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

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10.4 Enter/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN).

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command

sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured

Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation.

Table 13 on page 30 shows the addresses and data requirements for both command sequences. Note that the unlock bypass mode

is not available when the device enters the Secured Silicon Sector. See also “Secured Silicon Sector Flash Memory Region” on

page 20 for further information.

10.5 Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle

operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up

command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is

not required to provide further controls or timings. The device automatically generates the program pulses and verifies the

programmed cell margin. Table 13 on page 30 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer

latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Section 11. Write

Operation Status on page 32 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately

terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to

reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.

Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.

10.6 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program

command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third

write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock

bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the

unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,

resulting in faster total programming time. Table 13 on page 30 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock

bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.

Figure 7 on page 27 illustrates the algorithm for the program operation. See Section 17.4 Erase/Program Operations on page 44 for

parameters, and to Figure 19 on page 44 for timing diagrams.

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Figure 7. Program Operation

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note

20. See Table 13 on page 30 for program command sequence.

10.7 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a

set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these operations. Table 13 on page 30 shows the address and data requirements

for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip

erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device

has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Section 11. Write Operation

Status on page 32 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to

reading array data and addresses are no longer latched.

Figure 8 on page 29 illustrates the algorithm for the erase operation. See Section 17.4 Erase/Program Operations on page 44 for

parameters, and Figure 20 on page 45 for timing diagrams.

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10.8 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by

a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector

erase command. Table 13 on page 30 shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically

programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any

controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector

addresses and sector erase commands may be written. However, these additional erase commands are only one bus cycle long

and should be identical to the sixth cycle of the standard erase command explained above. Loading the sector erase buffer may be

done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles

must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is

recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be

re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed

to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional

sector addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out. (See Section 11.7 DQ3: Sector Erase Timer on

page 35.) The time-out begins from the rising edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that

a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence

should be reinitiated once the device has returned to reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Section 11. Write

Operation Status on page 32 for information on these status bits.)

Figure 8 on page 29 illustrates the algorithm for the erase operation. Refer to Section 17.4 Erase/Program Operations on page 44

for parameters, and to Figure 20 on page 45 for timing diagrams.

10.9 Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,

any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out

period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase

operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately

terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend

command.

When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 35 µs to suspend

the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for

erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions

apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Section 11. Write Operation

Status on page 32 for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data within non-suspended

sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard

program operation. See Section 11. Write Operation Status on page 32 for more information.

The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows

reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See

Section 10.3 Autoselect Command Sequence on page 25 for more information.

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The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the

sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after

the device has resumed erasing.

Figure 8. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes

21. See Table 13 on page 30 for erase command sequence.

22. See Section 11.7 DQ3: Sector Erase Timer on page 35 for more information.

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10.10Command Definitions Table

Table 13. S29AL016J Command Definitions

Bus Cycles^[24-27]

Third Fourth

Addr

First

Addr

Second

Fifth

Addr

Sixth

Command Sequence 1

Data

RD

Addr

Data

Addr

Data

Addr

Data

Read ^[28]

Reset ^[29]

1

RA

XXX

555

AAA

555

AAA

555

AAA

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

X01

X02

X01

X02

22C4

C4

Device ID,

Top Boot Block

AAA

555

2249

49

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Group Protect

Verify ^[31]

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

55

2AA

555

2AA

555

AAA

555

Enter Secured Silicon Sector

Exit Secured Silicon Sector

CFI Query ^[32]

3

4

1

4

3

AA

98

55

88

90

XXX

PA

00

AAA

AA

555

AAA

555

AAA

XXX

555

AAA

555

AAA

XXX

2AA

555

2AA

555

PA

555

AAA

555

Program

AA

55

A0

20

PD

Unlock Bypass

AAA

Unlock Bypass Program ^[33]

Unlock Bypass Reset ^[34]

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

Byte

Word

Byte

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

AAA

Sector Erase ^[37]

SA

AAA

Erase Suspend ^[35]

Erase Resume ^[36]

1

B0

30

Legend

X = Don’t care

RA = Address of the memory location to be read

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.

Notes

23. See Table 1 on page 11 for description of bus operations.

24. All values are in hexadecimal.

25. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

26. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

27. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.

28. No unlock or command cycles required when reading array data.

29. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).

30. The fourth cycle of the autoselect command sequence is a read cycle.

31. The data is 00h for an unprotected sector and 01h for a protected sector. See “Section 10.3 Autoselect Command Sequence on page 25” for more information.

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32. Command is valid when device is ready to read array data or when device is in autoselect mode.

33. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

34. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable.

35. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

36. The Erase Resume command is valid only during the Erase Suspend mode.

37. Additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical to the sixth cycle of the sector erase command

sequence (SA / 30).

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11. Write Operation Status

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 14

on page 35 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for

determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

11.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether

the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7

status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs

the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program

address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if

the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum

output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the

device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read

valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for

approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following

read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low.

Figure 22 on page 46, illustrates this.

Table 14 on page 35 shows the outputs for Data# Polling on DQ7. Figure 10 on page 34 shows the Data# Polling algorithm.

Figure 9. Data# Polling Algorithm

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

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Notes

38. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

39. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

11.2 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The

RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel with a pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)

If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby

mode.

Table 14 on page 35 shows the outputs for RY/BY#. Figures Figure 15 on page 41, Figure 16 on page 42, Figure 19 on page 44

and Figure 20 on page 45 shows RY/BY# for read, reset, program, and erase operations, respectively.

11.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device

has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#

pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The

system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,

then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the

device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see Section 11.1 DQ7: Data# Polling on page 32).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is

written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Table 14 on page 35 shows the outputs for Toggle Bit I on DQ6. Figure 10 on page 34 shows the toggle bit algorithm in flowchart

form, and Section 11.5 Reading Toggle Bits DQ6/DQ2 on page 34 explains the algorithm. Figure 23 on page 46 shows the toggle bit

timing diagrams. Figure 24 on page 47 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on

Section 11.4 DQ2: Toggle Bit II on page 33.

11.4 DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded

Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#

pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use

either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-

suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14

on page 35 to compare outputs for DQ2 and DQ6.

Figure 10 on page 34 shows the toggle bit algorithm in flowchart form, and the section Section 11.5 Reading Toggle Bits DQ6/

DQ2 on page 34 explains the algorithm. See also the Section 11.3 DQ6: Toggle Bit I on page 33 subsection. Figure 23 on page 46

shows the toggle bit timing diagram. Figure 24 on page 47 shows the differences between DQ2 and DQ6 in graphical form.

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11.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 10 on page 34 for the following discussion. Whenever the system initially begins reading toggle bit status, it must

read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the

value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note

whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has

successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully,

and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system

may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous

paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation (top of Figure 10 on page 34).

Figure 10. Toggle Bit Algorithm

START

[40]

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

[40, 41]

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes

40. Read toggle bit twice to determine whether or not it is toggling. See text.

41. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

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11.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5

produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.

The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an

erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a 1.

Under both these conditions, the system must issue the reset command to return the device to reading array data.

11.7 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has

begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire

time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The

system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less

than 50 s. See also Section 10.8 Sector Erase Command Sequence on page 28.

After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit

I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle

has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the

device will accept additional sector erase commands. To ensure the command has been accepted, the system software should

check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check,

the last command might not have been accepted. Table 14 shows the outputs for DQ3.

Table 14. Write Operation Status

Operation

DQ7^[43]

DQ6

Toggle

DQ5 ^[42]

DQ3

N/A

1

DQ2 ^[43]

No toggle

Toggle

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Reading within Erase Suspended Sector

DQ7#

0

1

Standard

Mode

0

1

Toggle

No toggle

N/A

Toggle

Erase

Suspend

Mode

Reading within Non-Erase Suspended

Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes

42. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See Section 11.6 DQ5: Exceeded Timing

Limits on page 35 for more information.

43. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

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12. Absolute Maximum Ratings

Parameter

Storage Temperature Plastic Packages

Rating

–65°C to +150°C

–65°C to +125°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground

[44]

V

–0.5 V to +4.0 V

–0.5 V to +12.5 V

CC

A9, OE#, and RESET# ^[45]

All other pins^[44]

–0.5 V to V +0.5 V

CC

Output Short Circuit Current ^[46]

200 mA

Notes

44. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 11

SS

on page 37. Maximum DC voltage on input or I/O pins is V +0.5 V. During voltage transitions, input or I/O pins may overshoot to V +2.0 V for periods up to 20 ns.

CC

See Figure 12 on page 37.

45. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot V to –2.0 V for periods of up

SS

to 20 ns. See Figure 11 on page 37. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

46. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

47. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum

rating conditions for extended periods may affect device reliability.

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13. Operating Ranges

Parameter

Range

Industrial (I) Devices

Automotive (A) Devices

Extended (N) Devices

Automotive (M) Devices

Full

–40°C to +85°C

Ambient Temperature

–40°C to +125°C

2.7 V to 3.6 V

V

Supply Voltages

CC

Regulated

3.0 V to 3.6 V

Note

48. Operating ranges define those limits between which the functionality of the device is guaranteed.

Figure 11. Maximum Negative Overshoot Waveform

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 12. Maximum Positive Overshoot Waveform

20 ns

V_CC

2.0 V

20 ns

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14. DC Characteristics

14.1 CMOS Compatible

Parameter

Description

Input Load Current

Test Conditions

= V to V , V = V

Min

Typ

–

Max

1.0

25

Unit

V

–

IN

SS

CC

CC max

I

LI

WP# Input Load Current

A9 Input Load Current

Output Leakage Current

= V

, WP# = V to V

SS

–

CC

CC max

CC

µA

I

= V

; A9 = 12.5 V

–

7

2

7

2

35

1.0

12

4

LIT

CC

I

= V to V , V = V

SS CC CC CC max

LO

OUT

5 MHz

1 MHz

5 MHz

1 MHz

CE# = V OE#

V ,

IH

IL,

=

V

= V

, Byte Mode

CC

CC max

I

V

Active Read Current ^[49]

mA

CC1

CC

12

4

CE# = V OE#

V

,

IH,

IL,

=

V

= V

, Word Mode

CC

CC max

CE# = V OE# = V

CC

,

IH

Active Erase/Program Current ^{[50, 51, 52]}

Standby Current ^[52]

20

30

5

mA

µA

IL,

I

V

–

CC2

CC

V

= V

CC max

OE# = V

,

IH

CE#, RESET# = V + 0.3 V/-0.1V,

0.2

CC3

CC

[53]

WP# = V or open, V = V

CC max

CC

V

= V

;

SS

CC

CC max

I

V

Standby Current During Reset ^[52]

RESET# = V + 0.3 V/-0.1V

0.2

5

µA

–

CC4

CC5

CC

WP# = V or open, ^[53]

CC

V

= V

, V = V + 0.3 V,

CC

IL

CC max IH CC

I

Automatic Sleep Mode ^{[51], [52]}

= V + 0.3 V/-0.1 V,

5

SS

WP# = V or open, ^[53]

CC

V

Input Low Voltage

Input High Voltage

-0.1

0.8

IL

–

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and Temporary Sector

Unprotect

V

= 2.7–3.6 V

8.5

–

12.5

ID

CC

–

V

Output Low Voltage

I

= 4.0 mA, V = V

0.45

–

OL

OH

CC

CC min

V

= -2.0 mA, V = V

0.85 x V

CC

OH1

OH2

LKO

CC

CC min

Output High Voltage

= -100 µA, V = V

V –0.4

CC

–

CC

CC min

–

Low V Lock-Out Voltage

2.1

2.5

CC

Notes

49. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.

CC

IH

CC

50. I active while Embedded Erase or Embedded Program is in progress.

CC

51. Automatic sleep mode enables the low power mode when addresses remain stable for t

+ 30 ns.

ACC

52. Not 100% tested.

53. When the device is operated in Extended Temperature range, the currents are as follows:

I

= 0.2 µA (typ), 10 µA (max)

CC3

CC4

CC5

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15. Test Conditions

Figure 13. Test Setup

3.3 V

2.7 k

Device

Under

Test

^CL

6.2 k

Note

54. Diodes are IN3064 or equivalent.

Table 15. Test Specifications

Test Condition

70

55

1 TTL gate

Unit

Output Load

Output Load Capacitance, C (including jig capacitance)

L

30

5

pF

ns

Input Rise and Fall Times

Input Pulse Levels

0.0 or V

CC

Input timing measurement reference levels

Output timing measurement reference levels

0.5 V

V

CC

0.5 V

CC

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16. Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Figure 14. Input Waveforms and Measurement Levels

V_CC

0.5 V_CC

Input

Measurement Level

Output

0.0 V

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17. AC Characteristics

17.1 Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Test Setup

70

55

Unit

t

Read Cycle Time ^[55]

Min

70

55

AVAV

RC

CE# = V

IL

t

Address to Output Delay

Max

70

55

AVQV

ACC

OE# = V

t

Chip Enable to Output Delay

OE# = V

Max

Min

70

30

55

30

ELQV

GLQV

EHQZ

CE

IL

t

Output Enable to Output Delay

–

OE

t

Chip Enable to Output High Z ^[55]

Output Enable to Output High Z ^[55]

Latency Between Read and Write Operations

16

20

0

DF

ns

t

GHQZ

–

t

SR/W

Read

–

t

Output Enable Hold Time ^[55]

OEH

Toggle and Data# Polling

10

Output Hold Time From Addresses, CE# or OE#, Whichever

Occurs First ^[55]

t

–

Min

0

AXQX

OH

Notes

55. Not 100% tested.

56. See Figure 13 on page 39 and Table 15 on page 39 for test specifications.

Figure 15. Read Operations Timings

t

RC

Addresses Stable

Addresses

CE#

t

ACC

t

DF

t

OE

OE#

t

SR/W

t

OEH

WE#

t

CE

t

OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

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17.2 Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

All Speed Options

Unit

t

RESET# Pin Low (During Embedded Algorithms) to Read or Write ^[57]

Max

35

µs

READY

RESET# Pin Low (NOT During Embedded Algorithms) to Read or

Write ^[57]

Max

Min

500

READY

ns

t

RESET# Pulse Width

500

50

35

0

RP

RESET# High Time Before Read ^[57]

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

µs

ns

RPD

t

RB

Note

57. Not 100% tested.

Figure 16. RESET# Timings

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms ^[(⁵N^8]ote 1)

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Note

58. CE# should only go low after RESET# has gone high. Keeping CE# low from power up through the first read could cause the first read to retrieve erroneous data.

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17.3 Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

CE# to BYTE# Switching Low or High

70

55

Unit

t

Max

Min

5

ELFL/ ELFH

t

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

16

ns

FLQZ

t

70

55

FHQV

Figure 17. BYTE# Timings for Read Operations

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

DQ15/A-1

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte to

word mode

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

Address

Input

DQ15

Output

t

FHQV

Figure 18. BYTE# Timings for Write Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note

59. Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

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17.4 Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

70

55

Unit

ns

t

Write Cycle Time 60

Address Setup Time

Address Hold Time

Data Setup Time

Min

Typ

Min

Max

70

55

AVAV

WC

t

0

AVWL

WLAX

AS

AH

DS

DH

t

45

t

35

DVWH

WHDX

t

Data Hold Time

0

t

Output Enable Setup Time

OES

t

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time

GHWL

t

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

35

t

Write Pulse Width High

25

20

6

WPH

t

Latency Between Read and Write Operations

SR/W

Byte

Word

t

Programming Operation ^[61]

µs

WHWH1

6

Sector Erase Operation ^[61]

0.5

50

0

sec

µs

WHWH2

t

V

Setup Time ^[60]

CC

VCS

t

Recovery Time from RY/BY#

RB

ns

t

Program/Erase Valid to RY/BY# Delay

90

BUSY

Notes

60. Not 100% tested.

61. See Section 18. Erase and Programming Performance on page 50 for more information.

Figure 19. Program Operation Timings

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes

62. PA = program address, PD = program data, D

63. Illustration shows device in word mode.

is the true data at the program address.

OUT

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Figure 20. Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

VA

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes

64. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Section 11. Write Operation Status on page 32).

65. Illustration shows device in word mode.

Figure 21. Back to Back Read/Write Cycle Timing

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

t_AH

Valid RA

Valid PA

Addresses

t_CPH

t_ACC

t_CE

CE#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

Data

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

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Figure 22. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

t_OH

WE#

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Notes

66. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

t_OH

WE#

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note

67. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

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Figure 24. DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note

68. The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

17.5 Temporary Sector Group Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

ns

t

V

Rise and Fall Time ^[69]

ID

Min

500

4

VIDR

t

RESET# Setup Time for Temporary Sector Unprotect

µs

RSP

RESET# Hold Time from RY/BY# High for Temporary Sector

Unprotect

t

Min

4

µs

RRB

Note

69. Not 100% tested.

Figure 25. Temporary Sector Group Unprotect/Timing Diagram

12V

RESET#

0 or 3V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

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Figure 26. Sector Group Protect/Unprotect Timing Diagram

V_ID

V_IH

RESET#

SA, A6, A3, A2

A1, A0

Valid*

Sector Group Protect/Unprotect

Verify

40h

Data

60h

Status

Sector Group Protect: 150 µs

Sector Group Unprotect: 1.5 ms

1 µs

CE#

WE#

OE#

Note

70. For sector group protect, A6 = 0, A3 = A2 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A3 = A2 = 0, A1 = 1, A0 = 0.

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17.6 Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

70

55

Unit

ns

t

Write Cycle Time ^[71]

Address Setup Time

Address Hold Time

Data Setup Time

Min

Typ

70

55

AVAV

WC

t

0

AVEL

ELAX

AS

AH

DS

DH

t

45

t

35

DVEH

EHDX

t

Data Hold Time

0

t

Output Enable Setup Time

OES

t

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

GHEL

t

WLEL

WS

t

WE# Hold Time

EHWH

WH

t

CE# Pulse Width

35

ELEH

EHEL

CP

t

CE# Pulse Width High

25

20

6

CPH

t

Latency Between Read and Write Operations

SR/W

Byte

t

Programming Operation ^[72]

Word

µs

WHWH1

WHWH2

WHWH1

6

Sector Erase Operation ^[72]

0.5

sec

WHWH2

Notes

71. Not 100% tested.

72. See Section 18. Erase and Programming Performance on page 50 for more information.

Figure 27. Alternate CE# Controlled Write Operation Timings

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes

73. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

74. Figure indicates the last two bus cycles of the command sequence.

75. Word mode address used as an example.

= data written to the device.

OUT

Document Number: 002-00777 Rev. *Q

Page 49 of 57

S29AL016J

18. Erase and Programming Performance

Parameter

Typ ^[76]

0.5

16

Max ^[77]

Unit

s

Comments

Sector Erase Time

Chip Erase Time

10

Excludes 00h programming prior to erasure

[79]

s

Byte Programming Time

Word Programming Time

6

150

160

120

µs

s

6

Excludes system level overhead ^[80]

Byte Mode

Word Mode

21.6

6.3

Chip Programming Time ^[78]

s

Notes

76. Typical program and erase times assume the following conditions: 25C, V = 3.0 V, 100,000 cycles, checkerboard data pattern.

CC

77. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.

CC

78. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program

times listed.

79. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

80. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 on page 30 for further information

on command definitions.

81. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

19. TSOP and BGA Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

= 0

Package

TSOP

BGA

Typ

4

Max

6

Unit

C

Input Capacitance

V

IN

4

6

TSOP

BGA

4.5

5

5.5

6.5

10

C

Output Capacitance

Control Pin Capacitance

WP# Pin Capacitance

V

= 0

OUT

pF

TSOP

BGA

C

V

= 0

IN2

IN3

IN

5

TSOP

BGA

8.5

C

V

= 0

IN

Notes

82. Sampled, not 100% tested.

83. Test conditions T = 25°C, f = 1.0 MHz.

A

Document Number: 002-00777 Rev. *Q

Page 50 of 57

S29AL016J

20. Physical Dimensions

20.1 TS 048—48-Pin Standard TSOP

STANDARD PIN OUT (TOP VIEW)

2X (N/2 TIPS)

0.10 C

8

0.10

2X

A2

2

0.10

2X

1

N

SEE DETAIL B

R

A

B

(c)

E

5

GAUGE PLANE

0.25 BASIC

e

9

A1

N/2 +1

N/2

0°

5

C

D1

D

4

PARALLEL TO

SEATING PLANE

L

C

0.20

2X (N/2 TIPS)

SEATING PLANE

DETAIL A

B

A

B

SEE DETAIL A

0.08MM M C A-B

b

6

7

WITH PLATING

e/2

REVERSE PIN OUT (TOP VIEW)

3

1

N

c

7

c1

X

X = A OR B

b1

BASE METAL

DETAIL B

N/2

N/2 +1

SECTION B-B

NOTES:

DIMENSIONS

SYMBOL

1. DIMENSIONS ARE IN MILLIMETERS (mm).

MIN. NOM. MAX.

A

A1

A2

b1

b

1.20

2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

0.15

0.05

3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.

0.95

0.17

1.00

0.20

1.05

0.23

0.27

4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE

LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

0.22

5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.

c1

c

0.10

0.16

0.21

6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.

MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR

THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD

TO BE 0.07mm .

D

20.00 BASIC

18.40 BASIC

12.00 BASIC

0.50 BASIC

D1

E

e

L

0

0.50

0.60 0.70

7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10mm AND 0.25mm FROM THE LEAD TIP.

0°

8

0.20

R

N

0.08

8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE

SEATING PLANE.

48

9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.

51-85183 Rev *F

CYPRESS

Company Confidential

Note

For reference only. BSC is an ANSI standard for Basic Space Centering.

Document Number: 002-00777 Rev. *Q

Page 51 of 57

S29AL016J

20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA) 8.15 mm x 6.15 mm

002-19063 Rev **

Document Number: 002-00777 Rev. *Q

Page 52 of 57

S29AL016J

20.3 LAE064—64-Ball Fortified Ball Grid Array (BGA) 9 mm x 9 mm

NOTES:

DIMENSIONS

1.

2.

3.

DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 .

ALL DIMENSIONS ARE IN MILLIMETERS .

SYMBOL

MIN.

NOM.

MAX.

A

-

1.40

BALL POSITION DESIGNATION PER JEP95 SECTION 3, SPP-020 (RECTANGULAR) OR SPP-010 (SQUARE).

REPRESENTS THE SOLDER BALL GRID PITCH .

A1

A2

D

0.40

0.60

-

4.

5.

e

9.00 BSC.

SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

9.00 BSC.

E

D1

E1

7.00 BSC.

8

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL

TO DATUM C .

MD

ME

8

64

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE

POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

N

Øb

0.50

0.60

0.70

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.

eD

1.00 BSC.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.

eE

1.00 BSC.

0.50 BSC.

SD/SE

8.

9

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED

MARK INDENTATION OR OTHER MEANS.

10.

JEDEC SPECIFICATION NO. REF : N/A

002-15537 Rev *A

CYPRESS

Document Number: 002-00777 Rev. *Q

Page 53 of 57

S29AL016J

21. Document History

Document History Page

Document Title: S29AL016J, 16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V, Boot Sector Flash

Document Number: 002-00777

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

–

RYSU

04/10/2007 Spansion Publication Number: S29AL016J_00

Initial release

*A

–

RYSU

05/17/2007 Global Deleted references to ACC input.

General Description Corrected ball count for Fortified BGA package.

Product Selector Guide Changed maximum tOE for 45 ns option.

Autoselect Codes (High Voltage Method) table

Changed address bits A19–A10 for Sector Protection Verification to SA.

Secured Silicon Sector Flash MemoryRegion

Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory:

Changed top

boot sector number and addresses for ESN. Deleted reference to uniform sector device.

Common Flash Memory Interface (CFI) Primary Vendor-Specific Extended Query

table: Added entries for addresses 4Dh–50h (x8 mode).

DC Characteristics CMOS Compatible table: Modified test conditions for ICC3, ICC4,

ICC5

AC Characteristics table Read Operations table: Changed tOE specification for 45 and

55 ns options.

*B

–

RYSU

10/29/2007 Global Removed 44-pin SOP package

Ordering Information Removed all leaded package offerings

S29AL016J Device Bus Operations Table Under Note 3: Removed the line “If WP# =

VHH, all sectors will be unprotected.”

CFI Query Identification String Table Updated the data for CFI addresses 2C hex

S29AL016J Command Definitions Table The 2nd cycle data for the “Unlock Bypass

Reset” command was updated from 'F0' to '00'.

Absolute Maximum Ratings Updated VCC Absolute Maximum Rating

CMOS Compatible Table

Updated ICC3 Standby current test condition

Updated maximum value of VOL

Updated minimum value of VLKO

Figure Back to Back Read/Write Cycle Timing Corrected the tSR/W duration

*C

–

RYSU

03/25/2008 Reset #: Hardware Reset Pin Updated current consumption during RESET# pulse

CMOS Compatible Table

Updated maximum value of ILI

Updated test condition, typical and maximum value of ICC3

Updated test condition, typical and maximum value of ICC4

Updated test condition, typical and maximum value of ICC5

Updated minimum value of VIL

Added Note 5

Ordering Information

Updated valid combination

Removed 45 ns, added 70 ns

*D

–

RYSU

05/23/2008 Ordering Information

Corrected model number 02 and 04 to bottom boot

Added the Regulated Voltage option

Added the Extended Temperature Range

Updated the Valid Combination table

Pin Configuration Updated Pin Configuration table

Device Bus Operation Updated the S29AL016J Device Bus Operation table and

modified Note 3

Operating Ranges

Added Extended Temperature Range information

Added Regulated Voltage

Document Number: 002-00777 Rev. *Q

Page 54 of 57

S29AL016J

Document History Page (Continued)

Document Title: S29AL016J, 16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V, Boot Sector Flash

Document Number: 002-00777

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*E

–

RYSU

08/12/2008 Sector Protection/Unprotection

Title changed to Sector Group Protection and Unprotection

Section amended and restated to Sector Group Protection and Unprotection

Temporary Sector Unprotect

Title changed to Temporary Sector Group Unprotect

Figure 7.2; Title changed to Temporary Sector Group Unprotect Operation

Figure 7.3; Title changed to In-System Sector Protect/Unprotect Algorithms

Temporary Sector Unprotect

Title changed to Temporary Sector Group Unprotect

Figure 17.11; Title changed to Temporary Sector Group Unprotect/Timing Diagram

Figure 17.12; Sector Group Protect/Unprotect Timing Diagram

Reading Toggle Bits DQ6/DQ2 Updated Figure 11.2

Ordering Information

Added SSOP56 package option

Updated the Valid Combination table

Connection Diagrams Added 56-pin Shrink Small Outline Package (SSOP56)

Physical Dimensions Added 56-pin Shrink Small Outline Package (SSOP56)

Alternate CE# Controlled Erase/Program

Operations TDS value changed from 45 ns to 35 ns

Erase/Program Operation Added figure Toggle Bit Timing (During Embedded

Algorithm)

Product Selector Guide Updated Table

*F

–

RYSU

10/27/2008 Customer Lockable: Secured Silicon Sector Programmed and Protected at the

Factory

Modified first bullet

Updated figure Secured Silicon Sector Protect Verify

TSOP and Pin Capacitance Updated Table

*G

*H

–

RYSU

02/03/2009 Ordering Information Updated the Valid Combination table

Erase/Program Operation

Updated Table

Removed Figure Toggle Bit Timing (During Embedded Algorithm)

07/09/2009 Physical Dimensions Updated TS048

Customer Lockable: Secured Silicon Sector NOT Programmed and Protected at

the Factory

Modified first bullet

Erase and Programming Performance Updated Table

*I

–

RYSU

02/18/2010 Sector Erase Command Sequence Added clarification regarding additional sector

erase commands during time-out period.

Command Definitions Table Added Note 15 to clarify additional sector erase

commands during time-out period.

*J

–

RYSU

12/09/2011 Ordering Information Added Low-Halogen 48-ball BGA ordering option

RESET#: Hardware Reset Pin Added sentence regarding use of CE# with RESET#

RESET# Timings Figure Added note

*K

04/12/2012 Global

Removed SSOP-56

*L

*M

*N

5041810

5741492

5791962

RYSU

NIBK

PRIT

12/08/2015 Updated to Cypress Template.

05/20/2017 Updated Cypress Logo and Copyright.

06/30/2017 Updated Distinctive Characteristics:

Updated Performance Characteristics:

Added Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C).

Updated Ordering Information:

Updated S29AL016J Standard Products:

Added Automotive Temperature Range related information.

Added Notes at the end.

Added Recommended Combinations.

Updated Physical Dimensions:

Updated TS 048—48-Pin Standard TSOP:

Updated diagram.

Updated VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA) 8.15 mm x 6.15 mm:

Updated diagram.

Updated LAE064—64-Ball Fortified Ball Grid Array (BGA) 9 mm x 9 mm:

Updated diagram.

*O

6134342

PRIT

04/12/2018 Updated to new template.

Completing Sunset Review.

Document Number: 002-00777 Rev. *Q

Page 55 of 57

S29AL016J

Document History Page (Continued)

Document Title: S29AL016J, 16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V, Boot Sector Flash

Document Number: 002-00777

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*P

6195892

PRIT

06/19/2018 Updated Ordering Information - Temperature Range.

Added a part number - S29AL016J70TFM to Valid Combinations — Automotive Grade

/ AEC-Q100.

*Q

6211763

PRIT

06/21/2018 Updated Performance Characteristics.

Added “Automotive (M) Devices” in Operating Ranges section.

Document Number: 002-00777 Rev. *Q

Page 56 of 57

S29AL016J

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

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cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

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cypress.com/support

cypress.com/memory

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Microcontrollers

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cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

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cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-00777 Rev. *Q

Revised June 21, 2018

Page 57 of 57


型号：	S29AL016J70BFA013
厂家：	Infineon
描述：	Standard Interface
文件：	总58页 (文件大小：1298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S29AL016J70BFA013 [INFINEON]

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