S6E1A11B0AGN2000G [INFINEON]
FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontroller (MCU) Family;
| 型号： | S6E1A11B0AGN2000G |
| 厂家： | 
Infineon |
| 描述： | FM0+ S6E1A-Series Arm® Cortex®-M0+ Microcontroller (MCU) Family 微控制器 |
| 文件： | 总97页 (文件大小：2886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6E1A Series
32-bit Arm® Cortex®-M0+
FM0+ Microcontroller
The S6E1A Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power
consumption and low cost.
This series has the Arm Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as
various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL
MANUAL".
Features
CSIO
Full duplex double buffer
32-bit Arm Cortex-M0+ Core
Built-in dedicated baud rate generator
Overrun error detection function
Serial chip select function (ch.1 and ch.3 only)
Data length: 5 to 16 bits
Processor version: r0p1
Maximum operating frequency: 40 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI
(non-maskable interrupt) and 32 peripheral interrupt with 4
selectable interrupt priority levels
LIN
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
24-bit System timer (Sys Tick): System timer for OS task
management
LIN break field generation function (The length is variable
between 13 bits and 16 bits.)
Bit Band operation
Compatible with Cortex-M3 bit band operation
LIN break delimiter generation function (The length is
variable between 1 bit and 4 bits.)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
On-Chip Memories
Flash memory
Up to 88 Kbyte
I2C
Standard-mode (Max: 100 kbps) supported / Fast-mode
(Max 400kbps) supported.
Read cycle:0 wait-cycle
Security function for code protection
SRAM
The on-chip SRAM of this series has one independent SRAM.
SRAM: 6 Kbyte
Multi-function Serial Interface (Max 3channels)
128 bytes with FIFO in all channels (The number of FIFO
steps varies depending on the settings of the communication
mode or bit length.)
The operation mode of each channel can be selected from
one of the following.
UART
CSIO
LIN
I2C
UART
Full duplex double buffer
Parity can be enabled or disabled.
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions (parity errors, framing errors,
and overrun errors)
Cypress Semiconductor Corporation
Document Number: 002-05091 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 24, 2019
S6E1A Series
A/D Converter (Max: 8 channels)
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. In addition, it
can be used as an up/down counter.
12-bit A/D Converter
Successive approximation type
Conversion time: 0.8 μs @ 5 V (S6E1A1xC0A) / 2.0 μs
(S6E1A1xB0A)
The detection edge for the three external event input pins
AIN, BIN and ZIN is configurable.
Priority conversion available (2 levels of priority)
Scan conversion mode
Built-in FIFO for conversion data storage (for scan
conversion: 16 steps, for priority conversion: 4 steps)
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Base Timer (Max: 4 channels)
The operation mode of each channel can be selected from one
of the following.
Multi-function Timer
16-bit PWM timer
16-bit PPG timer
The Multi-function Timer consists of the following blocks.
16-bit free-run timer × 3 channels
Input capture × 4 channels
16/32-bit reload timer
16/32-bit PWC timer
Output compare × 6 channels
ADC start compare × 6 channel
Waveform generator × 3 channels
16-bit PPG timer × 3 channels
General-purpose I/O Port
This series can use its pin as a general-purpose I/O port when
it is not used for an external bus or a peripheral function. All
ports can be set to fast general-purpose I/O ports or slow
general-purpose I/O ports. In addition, this series has a port
relocate function that can set to which I/O port a peripheral
function can be allocated.
IGBT mode is contained.
The following function can be used to achieve the motor
control.
PWM signal output function
DC chopper waveform output function
Dead time function
All ports are Fast GPIO which can be accessed by 1cycle
Capable of controlling the pull-up of each pin
Capable of reading pin level directly
Input capture function
Port relocate function
ADC start function
Up to 37 fast general-purpose I/O ports @48pin package
Certain ports are 5 V tolerant.
DTIF (motor emergency stop) interrupt function
See "3. Pin Assignment" and "5. I/O Circuit Type" for details
of such pins.
Real-time Clock (RTC)
The Real-time Clock counts
year/month/day/hour/minute/second/day of the week from year
00 to year 99.
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down
counters. The operation mode of each timer channel can be
selected from one of the following.
The RTC can generate an interrupt at a specific time
(year/month/day/hour/minute) and can also generate an
interrupt in a specific year, in a specific month, on a specific
day, at a specific hour or at a specific minute.
Free-running mode
Periodic mode (= Reload mode)
One-shot mode
It has a timer interrupt function generating an interrupt upon
a specific time or at specific intervals.
It can keep counting while rewriting the time.
It can count leap years automatically.
Document Number: 002-05091 Rev. *D
Page 2 of 97
S6E1A Series
Watch Counter
Low-voltage Detector (LVD)
The Watch Counter wakes up the microcontroller from the low
power consumption mode. The clock source can be selected
from the main clock, the sub clock, the built-in high-speed CR
clock or the built-in low-speed CR clock.
This series monitors the voltage on the VCC pin with a 2-stage
mechanism. When the voltage falls below a designated voltage,
the Low-voltage Detector generates an interrupt or a reset.
Interval timer: up to 64 s (sub clock: 32.768 kHz)
LVD1: error reporting via an interrupt
LVD2: auto-reset operation
External Interrupt Controller Unit
Up to 8 external interrupt input pins
Non-maskable interrupt (NMI) input pin: 1
Low Power Consumption Mode
This series has four low power consumption modes.
SLEEP
TIMER
RTC
Watchdog Timer (2 channels)
The watchdog timer generates an interrupt or a reset when the
counter reaches a time-out value.
This series consists of two different watchdogs, "hardware"
watchdog and "software" watchdog.
STOP
Peripheral Clock Gating
The "hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "hardware" watchdog
is active in any low-power consumption modes except RTC
mode and STOP mode.
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
Clock and Reset
Debug
Clocks
Serial Wire Debug Port (SW-DP)
Micro Trace Buffer (MTB)
A clock can be selected from five clock sources (two external
oscillators, two built-in CR oscillator, and main PLL).
Main clock
Sub clock
Built-in high-speed CR clock
Built-in low-speed CR clock
Main PLL clock
: 4 MHz to 40MHz
: 32.768 kHz
: 4 MHz
Unique ID
A 41-bit unique value of the device has been set.
: 100 kHz
Power Supply
Wide voltage range: VCC = 2.7 V to 5.5 V
Resets
Reset request from the INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detection reset
Clock supervisor reset
Clock Supervisor (CSV)
The Clock Supervisor monitors the failure of external clocks
with a clock generated by a built-in CR oscillator.
If an external clock failure (clock stop) is detected, a reset is
asserted.
If an external frequency anomaly is detected, an interrupt or
a reset is asserted.
Document Number: 002-05091 Rev. *D
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S6E1A Series
Contents
1. Product Lineup.................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment................................................................................................................................................................. 8
4. Pin Descriptions.............................................................................................................................................................. 13
5. I/O Circuit Type ............................................................................................................................................................... 24
6. Handling Precautions ..................................................................................................................................................... 30
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 30
Precautions for Package Mounting.............................................................................................................................. 31
Precautions for Use Environment................................................................................................................................ 33
7. Handling Devices ............................................................................................................................................................ 34
8. Block Diagram................................................................................................................................................................. 37
9. Memory Size.................................................................................................................................................................... 38
10. Memory Map.................................................................................................................................................................... 38
11. Pin Status in Each CPU State ........................................................................................................................................ 41
12. Electrical Characteristics ............................................................................................................................................... 45
12.1 Absolute Maximum Ratings......................................................................................................................................... 45
12.2 Recommended Operating Conditions ......................................................................................................................... 46
12.3 DC Characteristics ...................................................................................................................................................... 47
12.3.1 Current Rating.............................................................................................................................................................. 47
12.3.2 Pin Characteristics ....................................................................................................................................................... 50
12.4 AC Characteristics....................................................................................................................................................... 51
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 51
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 52
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 53
12.4.4 Operating Conditions of Main PLL (In the case of using the main clock as the input clock of the PLL) ....................... 54
12.4.5 Operating Conditions of Main PLL
(In the case of using the built-in high-speed CR clock as the input clock of the main PLL).......................................... 54
12.4.6 Reset Input Characteristics.......................................................................................................................................... 55
12.4.7 Power-on Reset Timing................................................................................................................................................ 55
12.4.8 Base Timer Input Timing.............................................................................................................................................. 56
12.4.9 CSIO/UART Timing...................................................................................................................................................... 57
12.4.10 External Input Timing................................................................................................................................................ 73
12.4.11 QPRC Timing ........................................................................................................................................................... 74
12.4.12 I2C Timing................................................................................................................................................................. 76
12.4.13 SW-DP Timing.......................................................................................................................................................... 77
12.5 12-bit A/D Converter.................................................................................................................................................... 78
12.6 Low-voltage Detection Characteristics ........................................................................................................................ 81
12.6.1 Low-voltage Detection Reset ....................................................................................................................................... 81
12.6.2 Low-voltage Detection Interrupt ................................................................................................................................... 82
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 83
12.8 Return Time from Low-Power Consumption Mode...................................................................................................... 84
12.8.1 Return Factor: Interrupt................................................................................................................................................ 84
12.8.2 Return Factor: Reset.................................................................................................................................................... 86
13. Ordering Information ...................................................................................................................................................... 88
14. Package Dimensions ...................................................................................................................................................... 89
15. Major Changes ................................................................................................................................................................ 94
Document Number: 002-05091 Rev. *D
Page 4 of 97
S6E1A Series
Document History................................................................................................................................................................. 96
Sales, Solutions, and Legal Information............................................................................................................................. 97
Document Number: 002-05091 Rev. *D
Page 5 of 97
S6E1A Series
1. Product Lineup
Memory Size
Product name
S6E1A11B0A
S6E1A11C0A
S6E1A12B0A
S6E1A12C0A
88 Kbyte
On-chip Flash memory
On-chip SRAM
56 Kbyte
6 Kbyte
6 Kbyte
Function
S6E1A11B0A
S6E1A11C0A
S6E1A12C0A
Product name
Pin count
S6E1A12B0A
32
48/52
Cortex-M0+
40 MHz
CPU
Frequency
Power supply voltage range
2.7 V to 5.5 V
Multi-function Serial Interface
(UART/CSIO/I2C)
3 ch. (Max)
ch.0/ch.1/ch.3: FIFO
Base Timer
(PWC/Reload timer/PWM/PPG)
4 ch. (Max)
1 unit
A/D start compare 6 ch.
Input capture
Free-run timer
Output compare
Waveform
4 ch.
3 ch.
6 ch.
Multi-function
Timer
3 ch.
3 ch.
generator
PPG
QPRC
1 ch.
Dual Timer
1 unit
Real-time Clock
Watch Counter
Watchdog timer
External Interrupt
I/O port
1 unit
1 unit
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) + NMI × 1
23 pins (Max)
5 ch. (1 unit)
37 pins (Max)
8 ch. (1 unit)
12-bit A/D converter
CSV (Clock Supervisor)
LVD (Low-voltage Detection)
Yes
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
SW-DP
Yes
Built-in CR
Debug Function
Unique ID
Note:
• All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See "14. ELECTRICAL CHARACTERISTICS 14.4 AC Characteristics 14.4.3 Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
Document Number: 002-05091 Rev. *D
Page 6 of 97
S6E1A Series
2. Packages
Product name
S6E1A11B0A
S6E1A12B0A
S6E1A11C0A
S6E1A12C0A
Package
LQFP: LQB032 (0.80 mm pitch)
QFN: WNU032 (0.50 mm pitch)
LQFP: LQA048 (0.50 mm pitch)
QFN: WNY048 (0.50 mm pitch)
LQFP: LQC052 (0.65 mm pitch)
: Supported
-
-
-
-
-
Note:
• See "14. Package Dimensions" for detailed information on each package.
Document Number: 002-05091 Rev. *D
Page 7 of 97
S6E1A Series
3. Pin Assignment
LQB032
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2
VSS
1
2
3
4
5
6
7
8
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
22 AVSS
21 AVCC
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
19 P12/AN02/SOT1_1/IC00_2/INT01_1
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
17 VSS
LQFP - 32
C
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 8 of 97
S6E1A Series
WNU032
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2
1
2
3
4
5
6
7
8
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
22 AVSS
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2
VSS
21 AVCC
QFN - 32
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
19 P12/AN02/SOT1_1/IC00_2/INT01_1
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
17 VSS
C
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 9 of 97
S6E1A Series
LQA048
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/IC01_0
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/ADTG_2
1
2
3
4
5
6
7
8
9
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
33 AVSS
32 AVRH
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2
31 AVCC
LQFP - 48
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
27 P12/AN02/SOT1_1/IC00_2/INT01_1
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
25 P10/AN00
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
VSS 12
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 10 of 97
S6E1A Series
WNY048
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/IC01_0
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
P39/DTTI0X_0/ADTG_2
1
2
3
4
5
6
7
8
9
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
33 AVSS
32 AVRH
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2
31 AVCC
QFN- 48
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
27 P12/AN02/SOT1_1/IC00_2/INT01_1
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
25 P10/AN00
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
VSS 12
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 11 of 97
S6E1A Series
LQC052
(TOP VIEW)
VCC
P50/INT00_0/AIN0_2/SIN3_1/IC01_0
P51/INT01_0/BIN0_2/SOT3_1
P52/INT02_0/ZIN0_2/SCK3_1
NC
1
2
3
4
5
6
7
8
9
39 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
38 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
37 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
36 NC
35 AVSS
P39/DTTI0X_0/ADTG_2
34 AVRH
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2
33 AVCC
LQFP - 52
32 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
31 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
30 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
29 P12/AN02/SOT1_1/IC00_2/INT01_1
28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
27 P10/AN00
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 10
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 11
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 12
VSS 13
Note:
• The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-05091 Rev. *D
Page 12 of 97
S6E1A Series
4. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin no.
Pin name
I/O circuit type
Pin state type
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
1
2
1
2
-
-
VCC
-
P50
INT00_0
AIN0_2
SIN3_1
IC01_0
P51
I*
J
J
INT01_0
BIN0_2
SOT3_1
P52
3
3
-
I*
INT02_0
ZIN0_2
SCK3_1
P39
4
6
4
5
-
-
I*
E
J
I
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA0_1
AIN0_3
7
6
1
F
J
SUBOUT_2
RTCCO_2
INT03_0
SCK0_2
P3B
RTO01_0
TIOA1_1
BIN0_3
8
7
2
F
J
SOT0_2
INT04_0
SCS31_2
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Page 13 of 97
S6E1A Series
Pin no.
Pin name
I/O circuit type
Pin state type
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
P3C
RTO02_0
TIOA2_1
ZIN0_3
SIN0_2
INT05_0
SCS30_2
P3D
9
8
3
F
J
RTO03_0
TIOA3_1
INT06_0
AIN0_0
SCK3_2
P3E
10
9
4
F
J
RTO04_0
TIOA0_0
BIN0_0
SOT3_2
INT15_0
P3F
11
12
10
11
5
6
F
F
J
RTO05_0
TIOA1_0
ZIN0_0
SIN3_2
VSS
I
13
14
15
12
13
14
7
8
9
-
-
-
C
VCC
P46
16
15
10
D
E
X0A
P47
17
18
19
16
17
18
11
12
-
D
B
E
F
C
I
X1A
INITX
P49
TIOB0_0
P4A
20
19
-
E
I
TIOB1_0
Document Number: 002-05091 Rev. *D
Page 14 of 97
S6E1A Series
Pin no.
Pin name
I/O circuit type
Pin state type
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
PE0
ADTG_1
22
20
13
C
J
DTTI0X_1
INT02_2
MD0
23
24
21
22
14
15
J
D
A
PE2
A
X0
PE3
25
26
27
23
24
25
16
17
-
A
-
B
K
X1
VSS
P10
G
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
IC02_0
P12
28
29
26
27
18
19
H*
H*
L
L
AN02
SOT1_1
IC00_2
INT01_1
P13
AN03
SCK1_1
SUBOUT_1
IC01_2
RTCCO_1
INT00_1
P14
30
28
20
H*
L
AN04
SIN0_1
SCS10_1
INT03_1
IC02_2
31
29
-
H*
L
Document Number: 002-05091 Rev. *D
Page 15 of 97
S6E1A Series
Pin no.
Pin name
I/O circuit type
Pin state type
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
P15
AN05
SOT0_1
32
30
-
H*
L
SCS11_1
IC03_2
INT15_2
AVCC
33
34
35
31
32
33
21
-
-
-
-
AVRH
22
AVSS
P23
AN06
SCK0_0
TIOA2_0
IC02_1
AIN0_1
INT04_1
P22
37
38
39
34
35
36
23
24
25
G
G
E
L
L
J
AN07
SOT0_0
TIOB2_0
IC03_1
ZIN0_1
INT05_1
P21
SIN0_0
INT06_1
TIOB1_1
IC01_1
BIN0_1
FRCK0_0
P00
41
42
43
44
37
38
39
40
-
E
E
E
E
I
P01
26
-
H
I
SWCLK
P02
P03
27
H
SWDIO
Document Number: 002-05091 Rev. *D
Page 16 of 97
S6E1A Series
Pin no.
Pin name
I/O circuit type
Pin state type
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
P04
SCK3_0
INT03_2
45
46
47
41
42
43
28
29
I*
E
I*
J
G
I
TIOB0_1
IGTRG0_1
P0F
NMIX
SUBOUT_0
CROUT_1
RTCCO_0
P61
SOT3_0
TIOB2_2
DTTI0X_2
SCS11_2
P60
30
-
SIN3_0
TIOA2_2
INT15_1
IC00_0
IGTRG0_0
SCS10_2
P80
31
48
44
45
I*
K
J
-
-
49
50
SCK1_2
FRCK0_1
P81
I
46
47
-
-
K
K
I
I
SOT1_2
P82
51
52
SIN1_2
VSS
48
-
32
-
-
-
5,21,36,40
NC
*:5V tolerant I/O
Document Number: 002-05091 Rev. *D
Page 17 of 97
S6E1A Series
List of pin functions
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel
on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select
the pin to be used.
Pin no.
Pin
function
Pin name
ADTG_1
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
22
20
13
A/D converter external trigger
input pin
ADTG_2
AN00
6
5
-
27
28
29
30
31
32
37
38
11
7
25
26
27
28
29
30
34
35
10
6
-
AN01
18
19
20
-
AN02
ADC
AN03
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN04
AN05
-
AN06
23
24
5
AN07
TIOA0_0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_0
TIOA1_1
TIOB1_0
TIOB1_1
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_2
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
1
Base Timer
0
19
45
12
8
18
41
11
7
-
28
6
2
Base Timer
1
20
39
37
9
19
36
34
8
-
25
23
3
Base timer ch.2 TIOA pin
Base Timer
2
48
38
47
44
35
43
31
24
30
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base Timer
3
TIOA3_1
SWCLK
SWDIO
10
9
4
Serial wire debug interface clock input pin 42
38
40
26
27
Debugger
Serial wire debug interface data
input / output pin
44
Document Number: 002-05091 Rev. *D
Page 18 of 97
S6E1A Series
Pin no.
Pin
Pin name
INT00_0
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
function
LQFP-52
2
2
-
External interrupt request 00 input pin
External interrupt request 01 input pin
INT00_1
INT01_0
INT01_1
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT05_0
INT05_1
INT06_0
INT06_1
INT15_0
INT15_1
INT15_2
NMIX
30
3
28
3
20
-
29
4
27
4
19
-
External interrupt request 02 input pin
External interrupt request 03 input pin
28
22
7
26
20
6
18
13
1
31
45
8
29
41
7
-
28
2
External
Interrupt
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
37
9
34
8
23
3
38
10
39
11
48
32
46
35
9
24
4
36
10
44
30
42
25
5
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
31
-
29
Document Number: 002-05091 Rev. *D
Page 19 of 97
S6E1A Series
Pin no.
Pin
function
Pin name
P00
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
41
37
-
P01
P02
P03
P04
P0F
P10
P11
P12
P13
P14
P15
P21
P22
P23
P39
P3A
P3B
P3C
P3D
P3E
P3F
P46
P47
P49
P4A
P50
P51
P52
P60
P61
P80
P81
P82
PE0*
PE2
PE3
42
43
44
45
46
27
28
29
30
31
32
39
38
37
6
38
39
40
41
42
25
26
27
28
29
30
36
35
34
5
26
-
General-purpose I/O port 0
27
28
29
-
18
19
20
-
General-purpose I/O port 1
General-purpose I/O port 2
GPIO
-
25
24
23
-
7
6
1
8
7
2
General-purpose I/O port 3
9
8
3
10
11
12
16
17
19
20
2
9
4
10
11
15
16
18
19
2
5
6
10
11
-
General-purpose I/O port 4
-
-
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
3
3
-
4
4
-
GPIO
48
47
49
50
51
22
24
25
44
43
45
46
47
20
22
23
31
30
-
-
-
13
15
16
General-purpose I/O port E
Document Number: 002-05091 Rev. *D
Page 20 of 97
S6E1A Series
Pin no.
Pin
function
Pin name
SIN0_0
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
39
36
25
Multi-function serial interface ch.0 input
pin
SIN0_1
SIN0_2
31
9
29
8
-
3
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SOT0_2
(SDA0_2)
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA0 when used as an I2C
pin (operation mode 4).
38
32
8
35
30
7
24
-
Multi-functio
n Serial 0
2
Multi-function serial interface ch.0 clock
I/O pin.
This pin operates as SCK0 when used as
a CSIO pin (operation mode 2) and as
SCL0 when used as an I2C pin (operation
mode 4).
SCK0_0
(SCL0_0)
37
7
34
6
23
1
SCK0_2
(SCL0_2)
SIN1_1
SIN1_2
28
51
26
47
18
-
Multi-function serial interface ch.1 input
pin
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA1 when used as an I2C
pin (operation mode 4).
Multi-function serial interface ch.1 clock
I/O pin.
This pin operates as SCK1 when used as
a CSIO pin (operation mode 2) and as
SCL1 when used as an I2C pin (operation
mode 4).
29
50
30
49
27
46
28
45
19
SOT1_2
(SDA1_2)
-
SCK1_1
(SCL1_1)
Multi-functio
n Serial 1
20
-
SCK1_2
(SCL1_2)
SCS10_1
SCS10_2
SCS11_1
SCS11_2
SIN3_0
31
48
32
47
48
2
29
44
30
43
44
2
-
Multi-function serial interface ch.1 serial
chip select 0 output/input pin.
-
-
Multi-function serial interface ch.1 serial
chip select 1 output pin.
-
31
-
Multi-function serial interface ch.3 input
pin
SIN3_1
SIN3_2
12
11
6
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA3 when used as an I2C
pin (operation mode 4).
Multi-function serial interface ch.3 clock
I/O pin.
This pin operates as SCK3 when used as
a CSIO (operation mode 2) and as SCL3
when used as an I2C pin (operation mode
4).
47
3
43
3
30
-
Multi-
function
Serial
3
11
45
4
10
41
4
5
28
-
10
9
9
4
Multi-function serial interface ch.3 serial
chip select 0 input/output pin.
Multi-function serial interface ch.3 serial
chip select 1 output pin.
SCS30_2
SCS31_2
8
3
8
7
2
Document Number: 002-05091 Rev. *D
Page 21 of 97
S6E1A Series
Pin no.
Pin
function
Pin name
DTTI0X_0
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
6
5
-
Input signal of waveform generator
controlling RTO00 to RTO05 outputs of
Multi-function Timer 0.
DTTI0X_1
DTTI0X_2
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
22
47
39
49
28
48
29
2
20
43
36
45
26
44
27
2
13
30
25
-
16-bit free-run timer ch.0 external clock
input pin.
18
31
19
-
IC00_2
IC01_0
IC01_1
39
30
28
37
31
38
32
36
28
26
34
29
35
30
25
20
18
23
-
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
IC01_2
IC02_0
IC02_1
IC02_2
IC03_1
24
-
IC03_2
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
Multi-functio
n Timer 0
RTO00_0
(PPG00_0)
7
6
1
2
3
4
5
6
RTO01_0
(PPG00_0)
8
7
RTO02_0
(PPG02_0)
9
8
RTO03_0
(PPG02_0)
10
11
12
9
RTO04_0
(PPG04_0)
10
11
RTO05_0
(PPG04_0)
This pin operates as PPG04 when it is
used in PPG0 output mode.
IGTRG0_0
IGTRG0_1
48
45
44
41
31
28
PPG IGBT mode external trigger input pin
Document Number: 002-05091 Rev. *D
Page 22 of 97
S6E1A Series
Pin no.
Pin
function
Pin name
AIN0_0
Function description
LQFP-48
QFN-48
LQFP-32
QFN-32
LQFP-52
10
9
4
AIN0_1
37
2
34
2
23
-
QPRC ch.0 AIN input pin
AIN0_2
AIN0_3
7
6
1
BIN0_0
11
39
3
10
36
3
5
Quadrature
Position/
Revolution
Counter
BIN0_1
25
-
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
BIN0_2
BIN0_3
8
7
2
ZIN0_0
12
38
4
11
35
4
6
ZIN0_1
24
-
ZIN0_2
ZIN0_3
9
8
3
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
46
30
7
42
28
6
29
20
1
0.5-seconds pulse output pin of Real-time
clock
Real-time
clock
46
30
7
42
28
6
29
20
1
Sub clock output pin
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, input MD0="L".
During serial programming to Flash
memory, input MD0="H".
RESET
Mode
INITX
18
17
12
MD0
23
21
14
VCC
VCC
VSS
VSS
VSS
X0
Power supply pin
1
1
-
POWER
GND
Power supply pin
15
13
26
52
24
16
25
17
14
12
24
48
22
15
23
16
9
GND pin
7
GND pin
17
32
15
10
16
11
GND pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
X0A
X1
CLOCK
X1A
Built-in high-speed CR oscillation clock
output port
CROUT_1
AVCC
46
33
34
42
31
32
29
21
-
A/D converter analog power supply pin
Analog
POWER
A/D converter analog reference voltage
input pin
AVRH
Analog
GND
A/D converter analog reference voltage
input pin
Power supply stabilization capacitance
pin
AVSS
C
35
14
33
13
22
8
C pin
*: PE0 is an open drain pin, cannot output high.
Document Number: 002-05091 Rev. *D
Page 23 of 97
S6E1A Series
5. I/O Circuit Type
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
Digital output
X1
N-ch
R
It is possible to select the main
oscillation / GPIO function
Pull-up resistor control
Digital input
When the main oscillation is
selected.
• Oscillation feedback resistor
: Approximately 1MΩ
• With standby mode control
Standby mode control
Clock input
Feedback
resistor
A
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
Standby mode control
Digital input
• Pull-up resistor
: Approximately 50kΩ
Standby mode control
• IOH= -4mA, IOL= 4mA
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
Document Number: 002-05091 Rev. *D
Page 24 of 97
S6E1A Series
Type
Circuit
Remarks
Pull-up resistor
• CMOS level hysteresis input
B
• Pull-up resistor
: Approximately 50kΩ
Digital input
Digital input
• Open drain output
• CMOS level hysteresis input
C
Digital output
N-ch
Document Number: 002-05091 Rev. *D
Page 25 of 97
S6E1A Series
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
Digital output
X1A
N-ch
R
It is possible to select the sub
oscillation / GPIO function
Pull-up resistor control
Digital input
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5MΩ
• With standby mode control
Standby mode control
Clock input
Feedback
resistor
D
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
Standby mode control
Digital input
• IOH= -4mA, IOL= 4mA
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05091 Rev. *D
Page 26 of 97
S6E1A Series
Type
Circuit
Remarks
P-ch
P-ch
Digital output
Digital output
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
E
N-ch
R
• IOH= -4mA, IOL= 4mA
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
• CMOS level output
P-ch
P-ch
Digital output
Digital output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
F
N-ch
• IOH= -12mA, IOL= 12mA
• When this pin is used as an I2C
pin, the digital output
R
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05091 Rev. *D
Page 27 of 97
S6E1A Series
Type
Circuit
Remarks
Digital output
Digital output
P-ch
P-ch
• CMOS level output
• CMOS level hysteresis input
• With input control
N-ch
• Analog input
• With pull-up resistor control
• With standby mode control
G
• Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
• When this pin is used as an I2C
pin, the digital output
Pull-up resistor control
Digital input
R
P-ch transistor is always off
Standby mode control
Analog input
Input control
Digital output
Digital output
P-ch
P-ch
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• 5V tolerant
N-ch
• With pull-up resistor control
• With standby mode control
H
• Pull-up resistor
: Approximately 50kΩ
Pull-up resistor control
Digital input
• IOH= -4mA, IOL= 4mA
• Available to control of PZR
registers.
R
• When this pin is used as an I2C
pin, the digital output
Standby mode control
P-ch transistor is always off
Analog input
Input control
Document Number: 002-05091 Rev. *D
Page 28 of 97
S6E1A Series
Type
Circuit
Remarks
• CMOS level output
P-ch
P-ch
Digital output
Digital output
• CMOS level hysteresis input
• 5V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
I
N-ch
• IOH= -4mA, IOL= 4mA
R
• Available to control PZR registers
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Mode input
J
CMOS level hysteresis input
Digital output
Digital output
P-ch
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH= -4mA, IOL= 4mA
• When this pin is used as an I2C
pin, the digital output
K
N-ch
R
P-ch transistor is always off
Digital input
Standby mode control
Document Number: 002-05091 Rev. *D
Page 29 of 97
S6E1A Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Code: DS00-00004-2Ea
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Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
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Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
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6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
Lead type
Load capacitance: Approximately 6 pF to 7 pF
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Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as External clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
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Notes on Power-on
Turn power on/off in the following order or at the same time.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Handling when using debug pins
When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input.
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8. Block Diagram
S6E1A11/S6E1A12
To PIN-Function-Ctrl
SWCLK,
SWDIO
SW-DP
Fast
GPIO
Cortex-M0+ Core
@40MHz(Max)
On-Chip SRAM
MTB
6 Kbyte
Bit Band
Wrapper
NVIC
Flash I/F
Security
On-Chip Flash
56 Kbyte/
88 Kbyte
System ROM
table
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
CSV
CLK
Main
X0
X1
Source Clock
PLL
Osc
Sub
Osc
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
AVCC,
AVSS
AVRH
(only S6E1A1xC0A)
12-bit A/D Converter
Unit 0
Power-On
Reset
ANxx
LVD
LVD Ctrl
ADTG
C
Regulator
IRQ-Monitor
Base Timer
16-bit 4ch./
32-bit 2ch.
TIOAx
TIOBx
Watch Counter
Real-Time Clock
AINx
BINx
ZINx
RTCCO,
SUBOUT
QPRC
1ch.
External Interrupt
Controller
INTx
NMIX
8pin + NMI
A/D Activation
Compare 6ch.
MD0
MODE-Ctrl
16-bit Input Capture
4ch.
IC0x
Low-speed CR
Prescaler
16-bit Free-run Timer
3ch.
FRCKx
To Fast GPIO
Peripheral Clock Gating
16-bit Output
Compare 6ch.
P0x,
P1x,
.
.
.
GPIO
PIN-Function-Ctrl
DTTI0X
RTO0x
Waveform Generator
3ch.
Pxx
SCKx
SINx
16-bit PPG
3ch.
Multi-function Serial I/F
3ch.
IGTRGx
SOTx
SCSx
(with FIFO)
Multi-function Timer
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9. Memory Size
See Memory size in 1. Product Lineup to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripheral area
0x41FF_FFFF
0xFFFF_FFFF
Reserved
0xF802_0000
Fast GPIO
(Single-cycle I/O port)
0xF800_0000
Reserved
Reserved
0xF000_3000
ROM table
0xF000_2000
MTB_DWT
0xF000_1000
MTB registers(SFR)
0xF000_0000
0x4003_C800
Cortex-M0+ Private
Peripherals
Peripheral Clock Gating
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
Low Speed CR Prescaler
RTC
0xE000_0000
Watch Counter
Reserved
MFS
Reserved
Reserved
0x4003_5100
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
LVD
Reserved
GPIO
Reserved
INT-Req READ
EXTI
0x4400_0000
32 Mbytes Bit Band alias
0x4200_0000
Reserved
CR Trim
Peripherals
0x4000_0000
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
A/DC
QPRC
0x2400_0000
32 Mbytes Bit Band alias
0x2200_0000
Base Timer
PPG
Reserved
0x2008_0000
SRAM
0x2000_0000
Reserved
0x4002_1000
0x4002_0000
MFT unit 0
Reserved
Reserved
0x4001_6000
0x4001_5000
Dual Timer
Reserved
See “Memory map (2)” for
the memory size details.
0x0010_0008
0x0010_0004
0x0010_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
CR Trim
Security
SW WDT
HW WDT
Clock/Reset
Flash
Reserved
Flash I/F
0x0000_0000
0x4000_1000
0x4000_0000
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S6E1A Series
Memory Map (2)
S6E1A12B0A
S6E1A12C0A
S6E1A11B0A
S6E1A11C0A
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_1800
0x2000_0000
0x2000_1800
0x2000_0000
SRAM
6K bytes
SRAM
6K bytes
Reserved
Reserved
CR trimming
Security
CR trimming
Security
0x0010_0004
0x0010_0000
0x0010_0004
0x0010_0000
Reserved
Reserved
0x0001_6000
0x0000_E000
0x0000_0000
Flash 88K bytes*
Flash 56Kbytes*
0x0000_0000
*: See "S6E1A1 Series Flash Programming Manual" to check details of the flash memory.
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S6E1A Series
Peripheral Address Map
Start address
End address
Bus
Peripheral
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4004_0000
0x4000_0FFF
0x4000_FFFF
Flash memory I/F register
AHB
Reserved
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_FFFF
0x41FF_FFFF
Clock/Reset Control
Hardware Watchdog Timer
Software Watchdog Timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function Timer unit0
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
APB1
GPIO
Reserved
Low-Voltage Detection
Reserved
Multi-function Serial Interface
Reserved
Watch Counter
Real-time clock
Low-speed CR Prescaler
Peripheral Clock Gating
Reserved
AHB
Reserved
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11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
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List of Pin Status
Function group
State upon
power-on
reset or
State at
INITX
State upon
device
State in Run
mode or
State in TIMER mode,
RTC mode, or
low-voltage
detection
input
internal reset
SLEEP mode
STOP mode
Power
Power supply
stable
supply
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0
INITX = 1
-
INITX = 1
-
-
SPL = 0
SPL = 1
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
GPIO selected
Main crystal
previous state
Input enabled
A
oscillator input
pin/
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
External main
clock input
selected
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
GPIO selected
External main
clock input
selected
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
B
Hi-Z /
Internal input Hi-Z /
fixed at "0"/
Input
enabled
Main crystal
oscillator output
pin
Hi-Z / Internal
Internal input input fixed at
fixed at "0"
"0"
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up / Input Pull-up / Input
Pull-up / Input Pull-up / Input
C INITX input pin
D Mode input pin
enabled
enabled
enabled
enabled
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
GPIO selected
Sub crystal
E
oscillator input pin
/
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
Input enabled
External sub
clock input
selected
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S6E1A Series
State upon
power-on
reset or
low-voltage
detection
State at
INITX
input
State upon
device
internal reset
State in Run
mode or
SLEEP mode
State in TIMER mode,
RTC mode, or
STOP mode
Function group
Power
Power supply
stable
supply
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0
INITX = 1
-
INITX = 1
-
-
SPL = 0
SPL = 1
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
Setting
Maintain
previous state
Maintain
previous state
GPIO selected
disabled
disabled
External sub
clock input
selected
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous
Maintain
previous
F
Hi-Z /
Internal input Hi-Z /
fixed at "0"/
Input
enabled
state/When
oscillation
stops*2,
Hi-Z / Internal
input fixed at
"0"
state/When
oscillation
stops*2,
Hi-Z / Internal
input fixed at
"0"
Sub crystal
oscillator output
pin
Hi-Z / Internal
Internal input input fixed at
Maintain
previous state
fixed at "0"
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
NMIX selected
Resource other
than the above
selected
Maintain
previous state
Maintain
previous state
G
Hi-Z /
Input
enabled
Hi-Z / Internal
input fixed at
"0"
Hi-Z /
Input enabled
Hi-Z
Hi-Z
GPIO selected
Pull-up /
Input
enabled
Serial wire debug
selected
Pull-up / Input
enabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
H
I
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
GPIO selected
Resource
selected
Hi-Z /
Input
enabled
Hi-Z / Internal
input fixed at
"0"
Hi-Z /
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z
GPIO selected
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Resource other
than the above
selected
Maintain
previous state
Maintain
previous state
J
Hi-Z /
Input
enabled
Hi-Z / Internal
input fixed at
"0"
Hi-Z /
Input enabled
Hi-Z
Hi-Z
GPIO selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input Internal input
fixed at "0" / fixed at "0" /
Analog input Analog input
Internal input
fixed at "0" /
Analog input
enabled
Internal input
fixed at "0" /
Analog input
enabled
Internal input
fixed at "0" /
Analog input
enabled
Analog input
selected
enabled
enabled
K
Resource other
than the above
selected
Hi-Z / Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
GPIO selected
Document Number: 002-05091 Rev. *D
Page 43 of 97
S6E1A Series
State upon
power-on
reset or
low-voltage
detection
State at
INITX
input
State upon
device
internal reset
State in Run
mode or
SLEEP mode
State in TIMER mode,
RTC mode, or
STOP mode
Function group
Power
Power supply
stable
supply
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0
INITX = 1
-
INITX = 1
-
-
SPL = 0
SPL = 1
Hi-Z /
Internal input Internal input
fixed at "0" / fixed at "0" /
Analog input Analog input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Internal input
fixed at "0" /
Analog input
enabled
Internal input
fixed at "0" /
Analog input
enabled
Analog input
selected
Hi-Z
enabled
enabled
External interrupt
enabled selected
Maintain
previous state
L
Resource other
than the above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
GPIO selected
*1:Oscillation stops in Sub timer mode, Low-speed CR timer mode, STOP mode, RTC mode.
*2:Oscillation stops in STOP mode.
Document Number: 002-05091 Rev. *D
Page 44 of 97
S6E1A Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
VCC
Unit
Remarks
Min
VSS - 0.5
VSS - 0.5
Max
VSS + 6.5
VSS + 6.5
Power supply voltage*1, *2
Analog power supply voltage*1, *3
V
V
AVCC
Only
S6E1A1xC0A
Analog reference voltage*1, *3
AVRH
VSS - 0.5
VSS + 6.5
V
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
10
mA
4 mA type
"L" level maximum output current*4
"L" level average output current*5
IOL
-
20
4
12
100
50
- 10
mA
mA
mA
mA
mA
mA
12 mA type
4 mA type
12 mA type
IOLAV
-
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
-
4 mA type
"H" level maximum output current*4
"H" level average output current*5
IOH
-
- 20
- 4
- 12
- 100
- 50
200
mA
mA
mA
mA
mA
mW
°C
12 mA type
4 mA type
12 mA type
IOHAV
-
"H" level total maximum output current
"H" level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
+ 150
*1:These parameters are based on the condition that VSS = AVss = 0 V.
*2:Vcc must not drop below VSS - 0.5 V.
*3:Ensure that the voltage does not to exceed VCC + 0.5 V at power-on.
*4:The maximum output current is the peak value for a single pin.
*5:The average output is the average current for a single pin over a period of 100 ms.
*6:The total average output current is the average current for all pins over a period of 100 ms.
Warning
• Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings
Document Number: 002-05091 Rev. *D
Page 45 of 97
S6E1A Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.7*2
2.7
Max
5.5
5.5
Power supply voltage
Analog power supply voltage
VCC
AVCC
-
-
V
V
AVCC = VCC
Only
S6E1A1xC0A
For regulator*1
Analog reference voltage
AVRH
-
2.7
AVCC
V
Smoothing capacitor
Operating temperature
CS
Ta
-
-
1
- 40
10
+ 105
μF
°C
“1: See "C Pin" in "6. Handling Precautions" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
Warning
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
4. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-05091 Rev. *D
Page 46 of 97
S6E1A Series
12.3 DC Characteristics
12.3.1 Current Rating
Symbol
HCLK
Value
Typ*1 Max*2
0.7 1.5
(Pin
Conditions
Frequency
Unit Remarks
4
name)
*
4MHz external clock input, PLL
ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
4MHz
8MHz
20MHz
1.3
2.8
2.3
4.0
mA
*3
40MHz
5.7
7.3
4MHz external clock input, PLL
4MHz
8MHz
20MHz
0.6
1.2
2.6
1.4
2.1
3.7
Run mode,
code executed
from Flash
ON*8
Benchmark code executed
Built-in high speed CR stopped
PCLK1 stopped
mA
mA
*3
*3
40MHz
4.8
6.3
4MHz crystal oscillation, PLL ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
4MHz
8MHz
20MHz
1.0
1.7
3.4
2.9
3.6
5.6
40MHz
5.7
8.2
4MHz external clock input, PLL
4MHz
8MHz
20MHz
0.5
0.9
2.0
1.2
1.8
2.9
ON*8
Run mode,
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
code executed
from RAM
mA
mA
*3
Icc
(VCC)
40MHz
3.7
4.8
4MHz external clock input, PLL
ON
NOP code executed
Built-in high speed CR stopped
PCLK1 stopped
Run mode,
code executed
from Flash
40MHz
2.8
3.7
*3,*6,*7
Built-in high speed CR*5
NOP code executed
All peripheral clock stopped by
CKENx
32kHz crystal oscillation
NOP code executed
All peripheral clock stopped by
CKENx
Built-in low speed CR
NOP code executed
All peripheral clock stopped by
CKENx
4MHz
0.8
65
73
1.5
mA
μA
*3
*3
*3
*3
Run mode,
code executed
from Flash
32kHz
100kHz
900
920
μA
4MHz
8MHz
20MHz
40MHz
0.4
0.7
1.5
2.7
1.2
1.6
2.4
3.7
4MHz external clock input, PLL
ON*8
mA
All peripheral clock stopped by
CKENx
Built-in high speed CR*5
All peripheral clock stopped by
CKENx
32kHz crystal oscillation
All peripheral clock stopped by
CKENx
Built-in low speed CR
All peripheral clock stopped by
CKENx
4MHz
0.5
63
66
1.2
mA
μA
μA
*3
*3
*3
Iccs
(VCC)
SLEEP operation
32kHz
100kHz
880
890
Document Number: 002-05091 Rev. *D
Page 47 of 97
S6E1A Series
*1 : Ta=+25℃,VCC=3.0V
*2 : Ta=+105℃,VCC=5.5V
*3 : All ports are fixed
*4 : PCLK0=HCLK/8
*5 : The frequency is set to 4MHz by trimming
*6 : Flash sync down is set to FRWTR.RWT = 11 and FSYNDN.SD = 1111
*7 : VCC=2.7V
*8 : When HCLK=4MHz, PLL OFF
Symbol
Value
Uni
(Pin
Conditions
Ta=25℃
Vcc=3.0V
LVD off
Ta=25℃
Vcc=5.0V
LVD off
Ta=105℃
Remarks
t
Typ
5.6
Max
name)
28
μA
μA
μA
*1
*1
*1
ICCH
(VCC)
STOP mode
6.7
-
30
540
Vcc=5.5V
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
12
13
-
42
μA
μA
μA
μA
μA
μA
*1
*1
*1
*1
*1
*1
ICCT
(VCC)
Sub timer mode
44
730
36
9
ICCR
(VCC)
RTC mode
10
-
38
570
32kHz crystal oscillation
LVD off
*1:All ports are fixed.
Document Number: 002-05091 Rev. *D
Page 48 of 97
S6E1A Series
LVD current
Parameter
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
Symbol
Conditions
Unit
μA
μA
Remarks
name
Typ
0.13
Max
Low-Voltage
0.3
For occurrence of reset
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
For occurrence of
interrupt
0.13
0.3
Flash memory current
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
ICCFLASH
Conditions
Unit
mA
Remarks
name
Typ
9.5
Max
Flash memory
write/erase
current
VCC
At Write/Erase
11.2
A/D convertor current (S6E1A1xC0A)
Pin
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
0.7
Max
0.9
At operation
At stop
mA
Power supply
current
ICCAD
AVCC
0.13
13
μA
Reference
power supply
current
At operation
1.1
1.97
mA
AVRH=5.5V
ICCAVRH
AVRH
At stop
0.1
1.7
μA
(AVRH)
A/D convertor current (S6E1A1xB0A)
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Typ
1.8
Pin
name
Parameter
Symbol
ICCAD
Conditions
Unit
Remarks
Max
2.87
14.7
At operation
At stop
mA
μA
Power supply
current
AVCC
0.23
Peripheral current dissipation
Frequency (MHz)
Clock
Peripheral
system
Conditions
Unit
Remarks
4
0.11
0.03
8
20
0.55
0.15
0.68
40
HCLK
GPIO
Base timer
Multi-functional timer/PPG
At all ports operation
At 4ch operation
At 1unit/4ch operation 0.14
0.22
0.05
0.28
1.10
0.30
1.38
mA
Quadrature
position/Revolution counter
PCLK1
At 1unit operation
0.02
0.04
0.11
0.22
mA
ADC
At 1unit operation
At 1ch operation
0.07
0.15
0.14
0.31
0.37
0.77
0.73
1.54
Multi-function serial
Document Number: 002-05091 Rev. *D
Page 49 of 97
S6E1A Series
12.3.2 Pin Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
hysteresis
input pin,
MD0, PE0
5V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, PE0
5V tolerant
input pin
"H" level input
voltage
(hysteresis
input)
-
-
-
-
VCC × 0.8
-
VCC + 0.3
V
VIHS
VCC × 0.8
VSS - 0.3
VSS - 0.3
-
-
-
VSS + 5.5
VCC × 0.2
VCC × 0.2
V
V
V
"L" level input
voltage
(hysteresis
input)
VILS
VCC ≥ 4.5 V,
IOH = - 4 mA
4 mA type
12 mA type
4 mA type
12 mA type
VCC - 0.5
VCC - 0.5
VSS
-
-
-
VCC
VCC
0.4
V
V
V
V
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
"H" level
output voltage
VOH
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
"L" level
output voltage
VOL
VSS
- 5
-
-
0.4
+ 5
Input leak
current
IIL
-
-
μA
kΩ
Pull-up
resistance
value
VCC ≥ 4.5 V
33
-
50
-
90
RPU
Pull-up pin
VCC < 4.5 V
180
Other than
VCC, VSS,
AVCC,
Input
capacitance
CIN
-
-
5
15
pF
AVSS, AVRH
Document Number: 002-05091 Rev. *D
Page 50 of 97
S6E1A Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
40
20
VCC ≥ 4.5V
VCC < 4.5V
4
4
When the crystal
oscillator is connected
MHz
MHz
ns
Input frequency
Input clock cycle
FCH
When the external
clock is used
-
-
4
40
X0,
X1
When the external
clock is used
tCYLH
-
25
250
Input clock pulse
width
Input clock rising
time and falling time
PWH/tCYLH,
PWL/tCYLH
When the external
clock is used
When the external
clock is used
45
-
55
5
%
tCF,
tCR
-
ns
FCM
FCC
-
-
-
-
-
-
-
-
-
-
-
-
41.2
41.2
41.2
41.2
MHz
MHz
MHz
MHz
Master clock
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
Internal operating
clock*1 frequency
FCP0
FCP1
-
-
-
-
-
-
24.27
24.27
24.27
-
-
-
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCC
tCYCP0
tCYCP1
Internal operating
clock*1 cycle time
*1: For details of each internal operating clock, refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
*2: For details of the APB bus to which a peripheral is connected, see "8. Block Diagram".
X0
Document Number: 002-05091 Rev. *D
Page 51 of 97
S6E1A Series
12.4.2 Sub Clock Input Characteristics
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
When the crystal
oscillator is
-
-
32.768
-
kHz
connected
When the external
clock is used
When the external
clock is used
When the external
clock is used
Input frequency
Input clock cycle
1/tCYLL
-
-
32
10
45
-
-
-
100
31.25
55
kHz
μs
X0A,
X1A
tCYLL
-
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
%
*: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used.
X0A
Document Number: 002-05091 Rev. *D
Page 52 of 97
S6E1A Series
12.4.3 Built-in CR Oscillation Characteristics
Built-in high-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Ta = + 25°C,
Unit
Remarks
Min
3.92
Typ
Max
4.08
4
3.6V < VCC ≤ 5.5V
Ta =0°C to + 85°C,
3.6V < VCC ≤ 5.5V
Ta = - 40°C to + 105°C,
3.6V < VCC ≤ 5.5V
Ta = + 25°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 85°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 40°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
3.9
4
4
4
4
4
4
4
-
4.1
3.88
3.94
3.92
3.9
4.12
4.06
4.08
4.1
During trimming*1
Clock frequency
FCRH
MHz
3.88
2.8
4.12
5.2
Ta = - 40°C to + 105°C
-
Not during trimming
*2
Frequency
stabilization time
tCRWT
-
30
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency
trimming/temperature trimming.
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source
clock.
Built-in low-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Typ
Max
150
Clock frequency
FCRL
-
100
kHz
Document Number: 002-05091 Rev. *D
Page 53 of 97
S6E1A Series
12.4.4 Operating Conditions of Main PLL
(In the case of using the main clock as the input clock of the PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLI
-
FPLLO
FCLKPLL
4
5
75
-
-
-
-
-
16
37
150
40
MHz
multiple
MHz
MHz
*1: The wait time is the time it takes for PLL oscillation to stabilize.
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
12.4.5 Operating Conditions of Main PLL
(In the case of using the built-in high-speed CR clock as the input clock of the main PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
100
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLI
-
FPLLO
FCLKPLL
3.88
19
72
-
4
-
-
4.12
35
150
41.2
MHz
multiple
MHz
MHz
-
*1: The wait time is the time it takes for PLL oscillation to stabilize.
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
Note:
For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency has been trimmed.
Document Number: 002-05091 Rev. *D
Page 54 of 97
S6E1A Series
12.4.6 Reset Input Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
tINITX
Conditions
Unit
ns
Remarks
name
Min
Max
Reset input time
INITX
-
500
-
12.4.7 Power-on Reset Timing
(VSS = 0 V, Ta = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remark
*1
name
Min
1
Typ
Max
-
Power supply shout down time
Power ramp rate
tOFF
dV/dt
tPRT
-
-
-
ms
VCC
VCC: 0.2V to 2.70V
1.0
0.43
1000
3.4
mV/µs *2
ms
Time until releasing Power-on reset
*1: VCC must be held below 0.2V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See "12.6. Low-Voltage Detection Characteristics".
Document Number: 002-05091 Rev. *D
Page 55 of 97
S6E1A Series
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
Input pulse width
tTIWH, tTIWL
-
2 tCYCP
-
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
Input pulse width
tTRGH, tTRGL
-
2 tCYCP
-
tTRGH
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note:
• tCYCP indicates the APB bus clock cycle time.
For the number of the APB bus to which the Base Timer has been connected, see "8. Block Diagram".
Document Number: 002-05091 Rev. *D
Page 56 of 97
S6E1A Series
12.4.9 CSIO/UART Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4 tCYCP
4 tCYCP
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK ↓ → SOT delay time
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
-
-
-
-
2 tCYCP
10
-
2 tCYCP
10
tCYCP
10
-
SCKx
SCKx
-
-
+
tCYCP + 10
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
Document Number: 002-05091 Rev. *D
Page 57 of 97
S6E1A Series
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Synchronous serial (SPI = 0, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
VCC < 4.5V
Min Max
VCC ≥ 4.5V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4 tCYCP
4 tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SCKx,
SINx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
50
0
-
-
30
0
-
-
ns
ns
2 tCYCP
10
tCYCP + 10
-
2 tCYCP
10
tCYCP + 10
-
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
tSLSH
tSHSL
tSHOVE
SCKx
-
-
ns
ns
ns
SCKx
SCKx,
SOTx
-
-
-
50
-
30
External shift
SCKx, clock
SIN → SCK ↓ setup time
tIVSLE
tSLIXE
10
20
-
-
10
20
-
-
ns
ns
SINx
operation
SCKx,
SINx
SCK ↓ → SIN hold time
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 58 of 97
S6E1A Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
tR
VIL
tF
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 59 of 97
S6E1A Series
Synchronous serial (SPI = 1, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4 tCYCP
4 tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
2 tCYCP
30
2 tCYCP
10
-
-
2 tCYCP
30
2 tCYCP
10
-
-
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↑ → SOT delay time
tSLSH
tSHSL
tSHOVE
SCKx
-
-
ns
ns
ns
SCKx
SCKx,
SOTx
tCYCP + 10
-
tCYCP + 10
-
-
50
-
30
External shift
SCKx, clock
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tIVSLE
tSLIXE
10
20
-
-
10
20
-
-
ns
ns
SINx
operation
SCKx,
SINx
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 60 of 97
S6E1A Series
tSCYC
VOH
VOL
VOL
SCK
SOT
SIN
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
VIL
VIH
VIL
SCK
SOT
tSHOVE
tR
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
SIN
MS bit = 1
*: This changes as data is written to the TDR register.
Document Number: 002-05091 Rev. *D
Page 61 of 97
S6E1A Series
Synchronous serial (SPI = 1, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud rate
Serial clock cycle time
-
-
-
-
8
-
-
8
-
Mbps
ns
tSCYC
SCKx
4 tCYCP
4 tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
2 tCYCP
30
2 tCYCP
10
-
-
2 tCYCP
30
2 tCYCP
10
-
-
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK ↓ → SOT delay time
tSLSH
tSHSL
tSLOVE
SCKx
-
-
ns
ns
ns
SCKx
SCKx,
SOTx
tCYCP + 10
-
tCYCP + 10
-
-
50
-
30
External shift
SCKx, clock
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHE
tSHIXE
10
20
-
-
10
20
-
-
ns
ns
SINx
operation
SCKx,
SINx
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 62 of 97
S6E1A Series
tSCYC
VOL
VOH
VOH
SCK
SOT
SIN
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
VIH
tSLOVE
VIH
VIH
SCK
VIL
VIL
VIL
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 63 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
(*1)+0
(*2)+50
Min
Max
(*1)+0
(*2)+50
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
tCSDI
(*1)-50
(*2)+0
(*1)-50
(*2)+0
ns
ns
Internal shift
clock
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
ns
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SUT delay time
SCS↑→SUT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 64 of 97
S6E1A Series
SCS output
SCK output
tCSDI
tCSHI
tCSSI
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
SCK input
tCSDE
tCSHE
tCSSE
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 65 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 1, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
(*1)+0
(*2)+50
Min
Max
(*1)+0
(*2)+50
SCS↓→SCK↑ setup time
SCK↓→SCS↑ hold time
tCSSI
tCSHI
tCSDI
(*1)-50
(*2)+0
(*1)-50
(*2)+0
ns
ns
Internal shift
clock
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
ns
SCS↓→SCK↑ setup time
SCK↓→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 66 of 97
S6E1A Series
SCS output
SCK output
tCSDI
tCSHI
tCSSI
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 67 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
(*1)+0
(*2)+50
Min
Max
(*1)+0
(*2)+50
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
tCSDI
(*1)-50
(*2)+0
(*1)-50
(*2)+0
ns
ns
Internal shift
clock
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
ns
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 68 of 97
S6E1A Series
tCSDI
SCS output
SCK output
tCSHI
tCSSI
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 69 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 1, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Parameter
Symbol
Conditions
Unit
Min
Max
(*1)+0
(*2)+50
Min
Max
(*1)+0
(*2)+50
SCS↑→SCK↑ setup time
SCK↓→SCS↓ hold time
tCSSI
tCSHI
tCSDI
(*1)-50
(*2)+0
(*1)-50
(*2)+0
ns
ns
Internal shift
clock
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
ns
SCS↑→SCK↑ setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
3tCYCP+30
-
ns
ns
ns
ns
ns
0
-
0
-
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 70 of 97
S6E1A Series
tCSDI
SCS output
SCK output
tCSHI
tCSSI
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 71 of 97
S6E1A Series
External clock (EXT = 1): asynchronous only
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
SCK rising time
tR
tR
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
VIL
Document Number: 002-05091 Rev. *D
Page 72 of 97
S6E1A Series
12.4.10 External Input Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Min
Parameter
Symbol
Pin name
ADTGx
Conditions
Unit
Remarks
Max
A/D converter
trigger input
1
Free-run timer
input clock
-
2 tCYCP
*
-
-
ns
FRCKx
Input pulse width
tINH, tINL
ICxx
Input capture
Wave form
generator
External
interrupt, NMI
1
DTTIxX
-
-
2 tCYCP
*
ns
2 tCYCP + 100*1
500*2
-
-
ns
ns
INTxx, NMIX
*1: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the
number of the APB bus to which the Multi-function Timer is connected and that of the APB bus to which the External Interrupt
Controller is connected, see "8. Block Diagram".
*2: In STOP mode and TIMER mode
Document Number: 002-05091 Rev. *D
Page 73 of 97
S6E1A Series
12.4.11 QPRC Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
tAHL
tALL
tBHL
tBLL
Conditions
Unit
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
-
-
-
-
Time from AIN pin "H" level to BIN
rise
Time from BIN pin "H" level to AIN
fall
Time from AIN pin "L" level to BIN
fall
Time from BIN pin "L" level to AIN
rise
Time from BIN pin "H" level to AIN
rise
Time from AIN pin "H" level to BIN
fall
Time from BIN pin "L" level to AIN
fall
Time from AIN pin "L" level to BIN
rise
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2 tCYCP
*
-
ns
ZIN pin "H" width
ZIN pin "L" width
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
Time from determined ZIN level to
AIN/BIN rise and fall
Time from AIN/BIN rise and fall time
to determined ZIN level
tZABE
tABEZ
QCR:CGSC="1"
QCR:CGSC="1"
*: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the
number of the APB bus to which the QPRC is connected, see "8. Block Diagram".
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-05091 Rev. *D
Page 74 of 97
S6E1A Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05091 Rev. *D
Page 75 of 97
S6E1A Series
12.4.12 I2C Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Standard-mode
Min Max
100
Fast-mode
Min Max
Parameter
Symbol
Conditions
Unit
Remarks
SCL clock frequency
(Repeated) START condition
hold time
FSCL
0
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
(Repeated) START setup
time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
CL = 30 pF,
R = (Vp/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. Vp
represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current.
*2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at "L"
(tLOW) does not extend.
*3: A Fast-mode I2C bus device can be used in a Standard-mode I2C bus system, provided that the condition of "tSUDAT ≥ 250 ns" is
fulfilled.
*4: tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which the I2C is connected, see "8. Block Diagram".
To use Standard-mode, set the APB bus clock at 2MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05091 Rev. *D
Page 76 of 97
S6E1A Series
12.4.13 SW-DP Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
15
Max
SWCLK,
SWDIO
SWDIO setup time
tSWS
-
-
-
-
-
ns
SWCLK,
SWDIO
SWDIO hold time
SWDIO delay time
tSWH
tSWD
15
-
ns
ns
SWCLK,
SWDIO
45
Note:
• External load capacitance CL = 30 pF
SWCLK
SWDIO
(When input)
SWD
SWDIO
(When output)
Document Number: 002-05091 Rev. *D
Page 77 of 97
S6E1A Series
12.5 12-bit A/D Converter
Electrical characteristics of A/D Converter
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Symbol
Pin name
Unit
Remarks
Min
Typ
Max
-
-
-
-
-
-
-
-
12
4.5
bit
- 4.5
- 2.5
- 20
AVRH - 20
AVCC-20
-
-
-
-
-
LSB
LSB
mV
mV
+ 2.5
+ 20
AVRH+ 20
AVCC+20
VZT
ANxx
S6E1A1xC0A
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xC0A
AVCC < 4.5V
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xC0A
AVCC < 4.5V
S6E1A1xB0A
Full-scale transition voltage
VFST
ANxx
0.8*1
2.0*1
0.24
-
-
-
-
Conversion time
-
-
-
μs
μs
-
-
Sampling time*2
Ts
10
0.3
0.6
40
Compare clock cycle*3
Tcck
-
1000
1.0
ns
50
100
State transition time to
operation permission
Analog input capacity
Tstt
-
-
-
-
-
-
μs
CAIN
9.7
pF
1.6
2.3
AVCC ≥ 4.5V
AVCC < 4.5V
Analog input resistance
RAIN
-
-
-
kΩ
Interchannel disparity
Analog port input current
-
-
-
-
-
-
-
-
-
-
4
5
LSB
μA
V
ANxx
AVSS
AVSS
2.7
AVRH
AVCC
AVCC
S6E1A1xC0A
S6E1A1xB0A
Only S6E1A1xB0A
Analog input voltage
Reference voltage
-
-
ANxx
AVRH
V
*1: The conversion time is the value of "sampling time (Ts) + compare time (Tc)".
The minimum conversion time is computed according to the following conditions: sampling time = 240 ns, compare time = 560
ns (AVcc ≥ 4.5 V). Must be set 25MHz to the Base clock (HCLK).
Ensure that the conversion time satisfies the specifications of the sampling time (Ts) and compare clock cycle (Tcck).
For details of the settings of the sampling time and compare clock cycle, refer to "CHAPTER: A/D Converter" in "FM0+ Family
PERIPHERAL MANUAL Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (Tc) is the result of (Equation 2).
Document Number: 002-05091 Rev. *D
Page 78 of 97
S6E1A Series
ANxx,
Analog input pins
Comparator
Rext
RAIN
Analog signal
source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistance of A/D Converter = 1.6 kΩ with 4.5 < AVCC < 5.5 ch.1 to ch.5
Input resistance of A/D Converter = 1.4 kΩ with 4.5 < AVCC < 5.5 ch.0, ch.6, ch.7
Input resistance of A/D Converter = 2.3 kΩ with 2.7 < AVCC < 4.5 ch.1 to ch.5
Input resistance of A/D Converter = 2.0 kΩ with 2.7 < AVCC < 4.5 ch.0, ch.6, ch.7
Input capacitance of A/D Converter = 9.7 pF with 2.7 < AVCC < 5.5
Output impedance of external circuit
CAIN:
Rext:
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Compare clock cycle
Tcck:
Document Number: 002-05091 Rev. *D
Page 79 of 97
S6E1A Series
Definitions of 12-bit A/D Converter terms
Resolution
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point (0b000000000000 ←→
Integral Nonlinearity
0b000000000001) and the full-scale transition point (0b111111111110 ←→
0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity
: Deviation from the ideal value of the input voltage that is required to change the output
code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH*1
AVSS
AVRH*1
Analog input
*1: At the 32pin product, it is AVCC
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
Differential Nonlinearity of digital output N =
VFST – VZT
1LSB =
4094
N
: A/D converter digital output value.
VZT
VFST
VNT
: Voltage at which the digital output changes from 0x000 to 0x001.
: Voltage at which the digital output changes from 0xFFE to 0xFFF.
: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05091 Rev. *D
Page 80 of 97
S6E1A Series
12.6 Low-voltage Detection Characteristics
12.6.1 Low-voltage Detection Reset
(Ta = - 40°C to + 105°C)
Value
Typ
2.45
2.50
2.60
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
2.39
Max
2.65
2.70
2.81
SVHR*1
00000
=
=
=
=
=
=
=
=
=
=
=
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SVHR*1
00001
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
3.31 3.60 3.89
Same as SVHR = 00000 value
3.40 3.70 4.00
Same as SVHR = 00000 value
3.68 4.00 4.32
Same as SVHR = 00000 value
3.77 4.10 4.43
Same as SVHR = 00000 value
3.86 4.20 4.54
SVHR*1
00010
SVHR*1
00011
SVHR*1
00100
SVHR*1
00101
SVHR*1
00110
SVHR*1
00111
SVHR*1
01000
SVHR*1
01001
SVHR*1
01010
Same as SVHR = 00000 value
LVD stabilization wait
time
8160×
TLVDW
-
-
-
-
-
-
μs
μs
*2
tCYCP
200
LVD detection delay
time
TLVDDL
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection
reset.
*2: tCYCP indicates the APB1 bus clock cycle time.
Document Number: 002-05091 Rev. *D
Page 81 of 97
S6E1A Series
12.6.2 Low-voltage Detection Interrupt
(Ta = - 40°C to + 105°C)
Value
Typ
Uni
t
Parameter
Symbol
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
Remarks
Min
2.58
Max
3.02
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
8160 ×
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 01010
Released voltage
LVD stabilization wait
time
LVD detection delay
time
TLVDW
TLVDDL
-
-
-
-
-
-
μs
μs
tCYCP
*
200
*:tCYCP represents the APB1 bus clock cycle time.
Document Number: 002-05091 Rev. *D
Page 82 of 97
S6E1A Series
12.7 Flash Memory Write/Erase Characteristics
(VCC = 2.7 V to 5.5 V, Ta = - 40°C to + 105°C)
Value
Parameter
Unit
Remarks
Min
Typ
Max
2.2
Large
sector
Small
sector
-
0.7
The sector erase time includes the time of
writing prior to internal erase.
Sector erase time
s
0.3
30
0.9
528
8
The halfword (16-bit) write time excludes the
system-level overhead.
The chip erase time includes the time of
writing prior to internal erase.
Halfword (16-bit) write time
Chip erase time
-
-
μs
2.6
s
Write/erase cycle and data hold time
Write/erase cycle
Data hold time (year)
Remarks
1,000
20*
10*
10,000
*: This value was converted from the result of a technology reliability assessment. (This value was converted from the result of a
high temperature accelerated test using the Arrhenius equation with the average temperature value being + 85°C).
Document Number: 002-05091 Rev. *D
Page 83 of 97
S6E1A Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value*
Parameter
Symbol
Unit
μs
Remarks
Typ
Max
SLEEP mode
tCYCC
High-speed CR TIMER mode,
Main TIMER mode,
40 + 17×tCYCC
80 + 17×tCYCC
μs
PLL TIMER mode
Ticnt
Low-speed CR TIMER mode
Sub TIMER mode
360
191
720
381
μs
μs
RTC mode,
STOP mode
819
1090
μs
*: The value depends on the accuracy of built-in CR.
The stabilization time of Main clock/Sub clock/Main PLL clock is not included.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05091 Rev. *D
Page 84 of 97
S6E1A Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL".
Document Number: 002-05091 Rev. *D
Page 85 of 97
S6E1A Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max*
SLEEP mode
208
208
378
378
High-speed CR TIMER mode,
Main TIMER mode,
μs
PLL TIMER mode
Trcnt
Low-speed CR TIMER mode
Sub TIMER mode
398
490
288
758
849
538
μs
μs
μs
RTC/STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-05091 Rev. *D
Page 86 of 97
S6E1A Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL".
• The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7 Power-on Reset Timing " for the detail
on the time during the power-on reset/low -voltage detection reset.
• When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
• The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05091 Rev. *D
Page 87 of 97
S6E1A Series
13.Ordering Information
On-chip
On-chip
SRAM
Part number
Flash
Package
Packing
memory
S6E1A11B0AGP20000
S6E1A12B0AGP20000
S6E1A11B0AGN20000
S6E1A12B0AGN20000
S6E1A11B0AGN2B000
S6E1A12B0AGN2B000
S6E1A11C0AGV20000
S6E1A12C0AGV20000
S6E1A11C0AGN20000
S6E1A12C0AGN20000
S6E1A11C0AGN2B000
S6E1A12C0AGN2B000
S6E1A11C0AGF20000
S6E1A12C0AGF20000
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
Plastic LQFP (0.80mm pitch), 32pins
Tray
Tray
(LQB032)
Plastic QFN (0.50mm pitch), 32pins
(WNU032)
Taping
Tray
Plastic LQFP (0.50mm pitch), 48pins
(LQA048)
Tray
Plastic QFN (0.50mm pitch), 48pins
(WNY048)
Taping
Tray
Plastic LQFP (0.65mm pitch), 52pins
(LQC052)
Document Number: 002-05091 Rev. *D
Page 88 of 97
S6E1A Series
14.Package Dimensions
Package Type
Package Code
LQFP 32
LQB032
4
D
5
7
D1
24
17
17
24
25
25
16
16
E1
E
5
4
7
3
6
32
9
9
32
1
8
8
1
2
5
7
e
BOTTOM VIEW
0.10
C
A-B
D
3
0.20
C
A-B D
b
0.20
C
A-B
D
8
TOPVIEW
2
9
θ
c
b
A
SEATING
PLANE
SECTION A-A'
A'
0.25
0.10
C
10
SIDEVIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.60
A
A1
b
0.05
0.32
0.13
0.15
0.35 0.43
0.18
c
D
9.00 BSC
D1
e
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
E
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
002-13879 **
PACKAGE OUTLINE, 32 LEAD LQFP
7.0X7.0X1.6 MM LQB032 REV*.*
Document Number: 002-05091 Rev. *D
Page 89 of 97
S6E1A Series
Package Type
Package Code
QFN 32
WNU032
D
0.10
C A B
D2
A
17
24
0.10
2X
C
0.10
C A B
16
25
(ND-1)× e
E
E2
5
9
32
c
8
1
9
INDEX MARK
8
L
0.10
0.05
C A B
e
b
B
C
0.10
2X
C
4
BOTTOM VIEW
TOP VIEW
0.10
C
A
SEATING PLANE
0.08
9
C
A1
C
SIDE VIEW
NOTE
1. ALL DIMENSIONSARE IN MILLIMETERS.
DIMENSIONS
NOM. MAX.
SYMBOL
A
2. DIMENSIONING AND TOLERANCIN C CONFORMSTO ASME Y14.5-1994.
3. N ISTHE TOTAL NU MBER OF TERMINALS.
MIN.
0.80
0.05
4. DIMENSION "b"APPLIESTO META
LLIZED TERMINAL AND ISMEASURED
A
D
E
0.00
1
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUSON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOTBE MEASURED IN THATRADIUSAREA.
5.00 BSC
5.00 BSC
0.25
5. ND REFERTO THE NUMBER OF
TERMINALSON D OR E SIDE.
0.20
0.30
b
6. MAX. PACKAGE WARPAGE IS0.05mm.
D
3.20 BSC
3.20 BSC
0.50 BSC
0.25 REF
0.40
2
2
7. MAXIMUM ALLOWABL E BURRSIS0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
E
e
c
9. BILATERAL COPLAN ARITY ZONE APPLIESTO THE EXPOSED HEAT
SINK SLUG ASWELL ASTHE TERMINALS.
10. JEDEC SPEC IFICATION NO. REF : N/A
L
0.35
0.45
002-15907 **
PACKAGEOUTLINE, 32 LEAD QFN
5.00X5.00X0.80MM WNU032 3.20X3.20MMEPAD(SAWN)REV**
Document Number: 002-05091 Rev. *D
Page 90 of 97
S6E1A Series
Package Type
Package Code
LQFP 48
LQA048
4
5
D
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
7
e
0.10
C
D
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
θ
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0°
0.75
0.70
L1
θ
0.50
8°
002-13731 **
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
Document Number: 002-05091 Rev. *D
Page 91 of 97
S6E1A Series
Package Type
Package Code
QFN 48
WNY048
0.15
C
A B
D
D2
A
25
36
0.10
2X
C
24
37
0.15
C A B
(ND-1)× e
E2
E
5
13
48
9
c
12
1
INDEX MARK
8
L
b
e
0.10
0.05
C
C
A B
B
0.10
2X
C
TOP VIEW
4
BOTTOM VIEW
A
SEATING PLANE
0.05
C
A1
9
C
SIDE VIEW
NOTE
1. ALLDIMENSIONSAREIN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCING CONFORMSTO ASME Y14.5-1994.
3. N ISTHETOTALNUMBEROFTERMINALS.
MIN. NOM. MAX.
0.80
4. DIMENSION "b"APPLIESTO METALLIZED TERMINALAND ISMEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINALTIP.IFTHETERMINALHAS
THEOPTIONALRADIUSON THEOTHEREND OFTHETERMINAL. THE
DIMENSION "b"SHOULD NOTBEMEASURED IN THATRADIUSAREA.
A
D
E
0.00
0.05
1
7.00 BSC
7.00 BSC
0.25
5. ND REFERTO THENUMBEROFTERMINALSON D ORESIDE.
6. MAX. PACKAGEWARPAGEIS0.05mm.
0.18
0.30
b
D
4.65 BSC
4.65 BSC
0.50 BSC
0.30 REF
0.50
2
2
7. MAXIMUM ALLOWABLEBURRSIS0.076mm IN ALLDIRECTIONS.
8. PIN #1 ID ON TOPW ILLBE LOCATED WITHIN INDICATED ZONE.
E
e
c
9. BILATERALCOPLANARITY ZONEAPPLIESTO THEEXPOSEDHEAT
SINKSLUG ASWELLASTHETERMINALS.
10. JEDECSPECIFICATION NO. REF: N/A
L
0.45
0.55
002-16422 **
PACKAGEOUTLINE, 48 LEAD QFN
7.00X7.00X0.80MM WNY0484.65X4.65MMEPAD(SAWN)REV**
Document Number: 002-05091 Rev. *D
Page 92 of 97
S6E1A Series
Package Type
Package Code
LQFP 52
LQC052
4
D
5
7
D1
39
27
27
39
40
26
26
40
E1
E
4
5
7
3
6
52
14
14
52
1
13
13
1
2
5 7
0.10
C
A-B
D
BOTTOM VIEW
e
3
0.13
C
A-B
D
0.20
C
A-B D
b
8
TOPVIEW
A
2
θ
9 c
A
A1
10
0.25
SEATING
PLANE
L1
b
A'
SECTION A-A'
0.10
C
L
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.265 0.30 0.365
0.09 0.20
0.20
c
D
12.00 BSC
10.00 BSC
0.65 BSC
D1
e
E
12.00 BSC
10.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
002-13880 **
PACKAGE OUTLINE, 52 LEAD LQFP
10.0X10.0X1.7 MM LQC052 REV**
Document Number: 002-05091 Rev. *D
Page 93 of 97
S6E1A Series
15.Major Changes
Spansion Publication Number: S6E1A1_DS710-00001
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revised from "Preliminary" to "Full Production"
Revision 1.0 [July 16,2014]
-
-
3
5
6
9
1. Description
2. Features
2. Features
Revised from "TYPE1" product to "TYPE1-M0+" product
Revised "Processor version"
Revised "Conversion time" of 12-bit A/D converter
Added "Note" for accuracy of built-in CR
3. Product Lineup
21,22,23
,
24,25
6. List of Pin Functions
List of pin functions
Revised Pin number 30 and 31 of LQFP-32 and QFN-32
6. List of Pin Functions
List of pin functions
12. Memory Map
Memory map (1)
12. Memory Map
23
40
41
46
47
Revised Function description of SOT1_x(SDA1_x)
Revised from "MTB resister" to "MTB resister(SFR)"
Revised product name and RAM address
Revised Analog pin input voltage
Memory map (2)
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
14. Electrical Characteristics
14.2 Recommended Operating Conditions
14. Electrical Characteristics
Added note "*2"
• Revised and added "Conditions"
• Revised the value of "TBD"
48,49,50 14.3 DC Characteristics
14.3.1 Current Rating
14. Electrical Characteristics
14.4 AC Characteristics
Revised the value of "Internal operating clock frequency" and
"Internal operating clock cycle time"
52
14.4.1 Main Clock Input Characteristics
14. Electrical Characteristics
14.4 AC Characteristics
14.4.3 Built-in CR Oscillation
Characteristics
54
Revised the value of "TBD"
14. Electrical Characteristics
14.4 AC Characteristics
14.4.5 Operating Conditions of Main
PLL(In the case of using the built-in
high-speed CR clock as the input clock of
the main PLL)
• Revised the value of "TBD"
• Revised the maximum value of "Main PLL clock frequency"
55
14. Electrical Characteristics
14.4 AC Characteristics
14.4.7 Power-on Reset Timing
14. Electrical Characteristics
14.4 AC Characteristics
• Revised the value of "TBD"
• Revised from "LVDL_minimum" to "VDH_minimum"
56
78
• Revised the condition of "Noise filter"
• Revised the note for noise filter
14.4.12 I2C Timing
• Revised the value of "Conversion time", "Sampling time" and
"Compare clock cycle"
• Revised the value of "State transition time to operation
permission"
14. Electrical Characteristics
14.5 12-bit A/D Converter
80
• Revised the note
14. Electrical Characteristics
14.6 Low-voltage Detection
Characteristics
14. Electrical Characteristics
14.7 Flash Memory Write/Erase
Characteristics
83,84
85
Revised the value of SVHR and SVHI
• Revised the value of "TBD"
• Revised the value of typical
Document Number: 002-05091 Rev. *D
Page 94 of 97
S6E1A Series
Page
86,88
90
Section
Change Results
Revised the value of "TBD"
Revised from "LCC-52P-M02" to "FPT-52P-M02"
14. Electrical Characteristics
14.8 Return Time from Low-Power
Consumption Mode
15. Ordering Information
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05091 Rev. *D
Page 95 of 97
S6E1A Series
Document History
Document Title: S6E1A Series, 32-bit Arm® Cortex®-M0+ FM0+ Microcontroller
Document Number: 002-05091
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
-
AKIH
07/16/2014 Migrated to Cypress and assigned document number 002-05091.
No change to document contents or format.
*A
*B
5131394
5626717
AKIH
02/10/2016 Updated to Cypress template.
HTER
04/13/2017 ・Modified RTC description in “Features, Real-Time Clock(RTC)”.
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function (Page 2)
・Updated Package code and dimensions as follows (Page 7-12, 87-92)
- FPT-32P-M30 -> LQB032
- FPT-48P-M49 -> LQA048
- FPT-52P-M02 -> LQC052
- LCC-32P-M73 -> WNU032
- LCC-48P-M74 -> WNY048
・Updated “12.4.7 Power-on Reset Timing”.
Changed parameter from “Power Supply rise time (Tr) [ms]” to “Power
ramp rate (dV/dt) [mV/us]” and add some comments (Page 54)
・Modified the Chapter name “12.4.9 CSIO Timing” to “12.4.9 CSIO/UART
Timing”. (Page 56)
・Added the Baud rate spec in “12.4.9 CSIO Timing”. (Page 56-61)
・Modified “12.4.9 CSIO Timing”. Deleted “SPI=1, MS=0” in the titles and
added MS=0,1 in the schematic (Page 63-70)
・Deleted the DMAC description. (Page 1, 6, 36-39, 48)
Modified according to the Datasheet Errata (002-05092 Rev. **) as below.
・Deleted the Pin name of no available. (Page 8-9, 17, 21)
・Fixed typo from SCLKx_0 to SCKx_0. (Page 56-61)
・Added the note. (Page 63-69)
・Corrected the Ordering Information table. (Page 87)
*C
*D
6062224
6602393
HUAL
XITO
02/07/2018 ・Updated Figure of I/O Circuit type A and type D
・Modified the A/D Converter value in the table 12.5
the changed sampling time is for min value when AVcc < 4.5V for
S6E1AxC0A part and this value is changed from 0.5 to 0.3.
06/24/2019 Updated to new template.
Document Number: 002-05091 Rev. *D
Page 96 of 97
S6E1A Series
Sales, Solutions, and Legal Information
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office closest to you, visit us at Cypress Locations.
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cypress.com/wireless
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
© Cypress Semiconductor Corporation, 2014-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED
USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION
(collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from
any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the
application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for
reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations,
surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly,
the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other
liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates,
distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property
damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk
Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has
given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05091 Rev. *D
June 24, 2019
Page 97 of 97
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