S6E2C38L0AGL2000A [INFINEON]
FM4 S6E2C High Performance Arm® Cortex®-M4 Microcontroller (MCU) Family;
| 型号： | S6E2C38L0AGL2000A |
| 厂家： | 
Infineon |
| 描述： | FM4 S6E2C High Performance Arm® Cortex®-M4 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总201页 (文件大小：5078K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FM4: S6E2C Series Microcontroller Datasheet
200 MHz Arm® Cortex®-M4F
High-Performance MCU
The FM4 S6E2C Series provides a highly integrated single chip solution with 200 MHz of CPU power, up to 2 Mbytes of dual banked
high speed on chip flash memory, up to 256 Kbytes of on chip SRAM, and integrated peripheral features including IEEE 1588
compliant 10/100 base Ethernet, CAN, CAN-FD, USB and inverter control timers.
S6E2C Series Features
Digital Subsystem
High Performance MCU Subsystem
◼3x Multi-Function Timers (MFT)
◼675 CoreMark®, 200 MHz Arm® Cortex®-M4F CPU
◼9x Programmable Pulse Generators (PPG)
◼365 µA/MHz active current with 2.7 V to 5.5 V operating
voltage
◼16x Base Timers, 4x Quadrature
Position/Revolution Counters (QPRC)
◼Ultra-low power 1.0 µA real-time clock (RTC) operating
current
◼1x Dual Timer, 2x CRC, and Watch Counter
◼Up to 2 MB flash and 256 KB SRAM with 16 KB flash
accelerator
◼16 channels of Multi-Function Serial (MFS) interfaces
configurable as SPI, UART, I2C, or LIN
◼Error-Correcting Code (ECC) support, hardware WDT1, low-
voltage detect, and clock supervisor blocks for safety-critical
applications
◼2x USB, 2x CAN, CAN-FD, IEEE 1588 Ethernet, High-
Speed Quad-SPI (HS-QSPI), I2S, and External Bus
Interfaces
Analog Subsystem
◼3x independent 12-bit, 2-Msps ADCs with a 32-channel
multiplexer input
◼2x dedicated 12-bit digital-to-analog converters (DACs)
Cypress Semiconductor Corporation
Document Number: 002-04980 Rev. *E
•
198 Champion Court
S6E2C Series Datasheet
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 10, 2023
S6E2C Series
Ecosystem for Cypress FM4 MCUs
Cypress provides a wealth of data at http://www.cypress.com to help you to select the right MCU for your design, and to help you
to quickly and effectively integrate the device into your design. Following is an abbreviated list for FM4 MCUs:
AN99235 - FM4 S6E2HG Series MCU - 16-Bit PWM Using
◼ Overview: Product Portfolio, Product Roadmap
◼ Product Selectors: FM4 MCUs
a Base Timer: Cypress FM4 Family of 32-bit Arm®
Cortex®-M4 Microcontrollers FM4 S6E2H Series Motor
Control Arm® Cortex®-M4 MCU
AN202487 - Differences Among FM0+, FM3, and FM4 32-
Bit Microcontrollers: Highlights the peripheral differences
in Cypress’s FM family MCUs. It provides dedicated
sections for each peripheral and contains lists, tables, and
descriptions of peripheral feature and register differences.
AN204438 - How to Setup Flash Security for FM0+, FM3
and FM4 Families: This application note describes how to
setup the Flash Security for FM0+, FM3, and FM4 devices
◼ Application notes: Cypress offers a large number of FM4
application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes
for getting started with FM4 family of MCUs are:
AN204468 - FM4 I2S USB MP3 Player Application 32-Bit
Microcontroller FM4 Family: This application note
describes the general structure of the I²S USB MP3Player
software example, its single modules in detail and how it is
used.
◼ Development kits:
AN204471 - FM4 S6E2CC Series External Memory
Programmer: This document describes use of the MCU
Universal Programmer as an off-line programmer for Quad
SPI flash memory programming on the S6E2CC Series
SK.
AN203277 - FM 32-Bit Microcontroller Family Hardware
Design Considerations: This application note reviews
several topics for designing a hardware system around
FM0+, FM3, and FM4 family MCUs. Subjects include
power system, reset, crystal, and other pin connections,
and programming and debugging interfaces.
FM4-U120-9B560 - Arm® Cortex®-M4 MCU Starter Kit
with USB and CMSIS-DAP
FM4-216-ETHERNET Arm® Cortex®-M4 MCU
Development Kit with Ethernet, CAN and USB Host
FM4-176L-S6E2CC-ETH - Arm® Cortex®-M4 MCU
Starter Kit with Ethernet and USB Host
FM4-176L-S6E2GM - Arm® Cortex®-M4 MCU Pioneer Kit
with Ethernet and USB Host
◼ Peripheral Manuals
AN202488 - FM4 MB9BF56x and S6E2HG Series MCU -
Servo Motor Speed Control: This document covers servo
motor speed control solution on FM4 MCU - MB9BF56x
and S6E2HG.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 2 of 200
S6E2C Series
12.4.10 External Bus Timing.....................................107
12.4.11 Base Timer Input Timing ..............................118
12.4.12 CSIO (SPI) Timing .......................................119
12.4.13 External Input Timing ...................................152
12.4.14 Quadrature Position/Revolution Counter Timing
...................................................................153
12.4.15 I2C Timing ....................................................155
12.4.16 SD Card Interface Timing.............................157
12.4.17 ETM/ HTM Timing........................................159
12.4.18 JTAG Timing ................................................160
12.4.19 Ethernet-MAC Timing...................................161
12.4.20 I2S Timing.....................................................166
12.4.21 High-Speed Quad SPI Timing......................171
Table of Contents
S6E2C Series Features................................................... 1
1.
Block Diagram ..................................................... 4
Product Lineup.................................................... 5
Detailed Device Features.................................... 7
Pin Assignments ............................................... 12
Pin Descriptions................................................ 16
I/O Circuit Type.................................................. 53
Handling Precautions........................................ 61
Precautions for Product Design........................ 61
Precautions for Package Mounting................... 62
Precautions for Use Environment..................... 64
Handling Devices............................................... 65
Memory Size ...................................................... 68
Memory Map ...................................................... 68
Pin Status in Each CPU State........................... 74
Electrical Characteristics.................................. 82
Absolute Maximum Ratings.............................. 82
Recommended Operating Conditions............... 84
DC Characteristics............................................ 89
Current Rating ............................................... 89
Pin Characteristics......................................... 99
AC Characteristics.......................................... 101
Main Clock Input Characteristics ................. 101
Sub Clock Input Characteristics................... 102
Built-In CR Oscillation Characteristics ......... 102
Operating Conditions of Main PLL (in the Case of
Using Main Clock for Input Clock of PLL) .... 103
Operating Conditions of USB/Ethernet PLL・I2S
PLL (in the Case of Using Main Clock for Input
Clock of PLL) ............................................... 103
Operating Conditions of Main PLL (in the Case of
Using Built-in High-Speed CR Clock for Input Clock
of Main PLL) ................................................ 104
Reset Input Characteristics.......................... 104
Power-On Reset Timing............................... 105
GPIO Output Characteristics ....................... 106
2.
3.
4.
5.
6.
7.
7.1
7.2
7.3
8.
12.5
12-bit A/D Converter .......................................173
12-bit D/A Converter .......................................176
USB Characteristics........................................177
Low-Voltage Detection Characteristics ...........181
Low-Voltage Detection Reset.......................181
Interrupt of Low-Voltage Detection...............181
MainFlash Memory Write/Erase Characteristics182
9.
12.6
10.
12.7
11.
12.8
12.
12.8.1
12.8.2
12.9
12.1
12.2
12.3
12.3.1
12.3.2
12.4
12.4.1
12.4.2
12.4.3
12.4.4
12.10 Dual Flash Memory Write/Erase Characteristics182
12.11 Standby Recovery Time..................................183
12.11.1 Recovery Cause: Interrupt/WKUP................183
12.11.2 Recovery Cause: Reset ...............................185
13.
14.
15.
16.
Ordering Information.......................................187
Acronyms .........................................................191
Package Dimensions.......................................192
Major Changes.................................................196
Sales, Solutions, and Legal Information...................200
Products ......................................................................200
Cypress Developer Community.................................200
Technical Support.......................................................200
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 3 of 200
S6E2C Series
1. Block Diagram
S6E2C
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
96/144/192 Kbytes
SWJ-DP ETM/HTM*
ROM
TPIU/ETB*
TRACEDx,
TRACECLK
Table
SRAM1
32 Kbytes
I
D
SRAM2
32 Kbytes
FPU MPU NVIC
Sys
MainFlash I/F
MainFlash/DualFlash
2 Mbytes(1M+1M)/
1.5 Mbytes(1M+0.5M)/
1 Mbytes(MainOnly)
Trace Buffer
(16 Kbytes)
Dual-Timer
Security
Watchdog Timer
(Software)
DualFlash I/F
USBVCC0
USB2.0
PHY
UDP0,UDM0
(Host/
Clock Reset
Generator
Device)
UHCONX0
INITX
USBVCC1
USB2.0
PHY
Watchdog Timer
(Hardware)
UDP1,UDM1
(Host/
Device)
UHCONX1
CSV
DMAC
8ch.
CLK
DSTC
CAN ch.0
CAN ch.1
CAN ch.2
TX0,RX0
TX1,RX1
TX2,RX2
PRG-CRC
Accelerator
Source Clock
Main
Osc
I2SMCLK,
I2SWS,
I2SCK
X0
X1
CR
100 kHz
CR
PLL
I2S
1unit
I2SDI
I2SDO
VBAT Domain
4 MHz
P0x,
P1x,
X0A
X1A
Sub
Osc
GPIO
.
.
.
PIN-Function-Ctrl
CROUT
PFx
MD0,
MD1
MODE-Ctrl
AVCC,
AVSS,
AVRH,
AVRL
12-bit A/D Converter
Unit 0
ETHVCC
Ethernet-MAC
ch.0
E_TXx,
E_RXx,
E_MDx
S_CLK,S_CMD
ANxx
Unit 1
Unit 2
ADTGx
S_DATAx
SD-CARD I/F
S_CD,S_WP
Q_SCK, Q_CSx
Q_IOx
TIOAx
TIOBx
Base Timer
16-bit 32ch./
32-bit 16ch.
Hi-Speed Quad SPI
External Bus I/F
MADx
MADATAx
AINx
BINx
ZINx
QPRC
4ch.
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
CAN Prescaler
USB Clock Ctrl
I2S Clock Ctrl
A/D Activation Compare
6ch.
PLL
PLL
16-bit Input Capture
4ch.
IC0x
16-bit Free-run Timer
3ch.
FRCK0
Power-On
Reset
16-bit Output Compare
6ch.
LVD
LVD Ctrl
DTTI0X
RTO0x
Waveform Generator
3ch.
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
16-bit PPG
3ch.
Multi-function Timer × 3
WKUPx
Deep Standby Ctrl
VBAT
VWAKEUP
Peripheral Clock Gating
Low-speed CR Prescaler
VBAT Domain
Real-Time Clock
Port Ctrl.
VREGCTL
RTCCO,
SUBOUT
External Interrupt
Controller
INTx
NMIX
32-pin + NMI
12-bit D/A Converter
2units
SCKx
SINx
Multi-function Serial I/F
16ch.
(with FIFO ch.0 to ch.7)
HW flow control(ch.4,5)
SOTx
CTSx
RTSx
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 4 of 200
S6E2C Series
2. Product Lineup
Here is the information used in the tables below:
S6E2
C
C 9 J0AGV 2000A
Package Identifier
Memory Size
Product Feature Set
C Series
Cypress FM 4 MCU
Memory Size
Memory Size
S6E2Cx8
1024 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
S6E2Cx9
1536 Kbytes
192 Kbytes
128 Kbytes
32 Kbytes
32 Kbytes
S6E2CxA
2048 Kbytes
256 Kbytes
192 Kbytes
32 Kbytes
On-chip flash memory
On-chip
SRAM
SRAM0
SRAM1
SRAM2
32 Kbytes
Package Dependent Features
Feature
H0AGV
144
J0AGV
176
J0AGB
192
L0AGL
216
Pin count and package type
High-speed quad SPI
LQFP: LQS144
(0.5 mm pitch)
N/A
LQFP: LQP176
(0.5 mm pitch)
BGA: LBE192
(0.8 mm pitch)
1 unit
LQFP: LQQ216
(0.4 mm pitch)
Addr: 25-bit
(Max),
Data: 8-/16-bit
CS: 8 (Max),
SRAM,
NOR flash
NAND flash
4-bit ETM/HTM
N/A
Addr: 25-bit (Max),
Addr: 25-bit (Max),
Data: 8-/16-/32-bit
CS: 9 (Max),
Data: 8-/16-bit
CS: 9 (Max),
SRAM,
NOR flash,
NAND flash
SDRAM
SRAM,
NOR flash,
NAND flash,
SDRAM
External bus interface
16-bit ETM/HTM
8-bit ETM/HTM
I2S
1 unit
I/O ports
120 (Max)
24 ch (3 units)
152 (Max)
190 (Max)
12-bit A/D converter
32 ch (3 units)
Note:
−
See 15 Package Dimensions for detailed information on each package.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 5 of 200
S6E2C Series
Product Feature Set
Feature
S6E2CC
S6E2C5
S6E2C4
S6E2C3
S6E2C2
S6E2C1
Cortex-M4F, MPU, NVIC 128 ch
200 MHz
CPU
Freq.
Power supply voltage range
USB2.0 (device/host)
2.7V to 5.5V
2 ch
2 ch
N/A
N/A
2 ch
2 ch
1ch.(Max)
MII: 1 ch
/RMII: 1
ch (Max)
N/A
N/A
N/A
1ch.(Max)
MII: 1 ch
/RMII: 1
ch (Max)
Ethernet-MAC
N/A
N/A
CAN
2 ch (Max) 2 ch (Max) 2 ch (Max)
1 ch 1 ch 1 ch
N/A
N/A
N/A
N/A
CAN-FD (non-ISO CAN FD)
N/A
DMAC
DSTC
8ch
256 ch
Multi-function serial interface
(UART/CSIO/LIN/I2C)
16ch (Max)
ch 0 to ch 7：FIFO, ch 8 to ch 15：No FIFO
Base timer
16 ch (Max)
(PWC/Reload timer/PWM/PPG)
A/D activation
compare
6 ch
Input capture
Free-run timer
Output compare
Waveform generator
PPG
4 ch
3 ch
6 ch
3 ch
3 ch
3 units (Max)
SD card interface
QPRC
1 unit
4 ch (Max)
Dual timer
1 unit
Real-time clock
Watch counter
1 unit
1 unit
CRC accelerator
Watchdog timer
Yes (fixed, programmable)
1 ch (SW) + 1 ch (HW)
External interrupts
12-bit D/A converter
CSV (clock supervisor)
LVD (low-voltage detector)
32 pins (Max)+ NMI × 1
2 units (Max)
Yes
2 ch
High-speed
Low-speed
Debug function
Unique ID
4 MHz
Built-in CR
100 kHz
SWJ-DP/ETM/HTM
Yes
Notes:
−
Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully
work out the pin allocation needed for your design.
You must use the port relocate function of the I/O port according to your function use.
− See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 6 of 200
S6E2C Series
3. Detailed Device Features
Devices in the S6E2C Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the Arm Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor
control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that are
described in this datasheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part (002-04856)."
32-bit Arm Cortex-M4F Core
External Bus Interface
◼Processor version: r0p1
◼Supports SRAM, NOR, NAND flash and SDRAM device
◼Up to 200 MHz frequency operation
◼Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
◼FPU built-in
◼8-/16-/32-bit data width
◼Support DSP instructions
◼Up to 25-bit address bus
◼Memory protection unit (MPU): improves the reliability of an
◼Maximum Access size: 256M byte
embedded system
◼Supports address/data multiplexing
◼Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
◼Supports external RDY function
USB Interface (Max two channels)
The USB interface is composed of a device and a host.
◼24-bit system timer (Sys Tick): system timer for OS task
management
◼USB device
On-chip Memories
USB 2.0 Full-speed supported
Max 6 EndPoint supported
• EndPoint 0 is control transfer
◼Flash memory
This series is based on two independent on-chip flash
• EndPoint 1, 2 can be selected bulk-transfer, interrupt-
transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or interrupt-
transfer
• EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 byte
memories.
Up to 2048 Kbytes
Built-in flash accelerator system with 16 Kbytes trace
buffer memory
Read access to flash memory that can be achieved
without wait-cycle up to an operating frequency of 72 MHz.
Even at the operating frequency more than 72 MHz, an
equivalent single cycle access to flash memory can be
obtained by the flash accelerator system.
• EndPoint 1: 256 byte
Security function for code protection
◼USB host
USB2.0 Full-Speed/Low-Speed supported
◼SRAM
Bulk-transfer, interrupt-transfer, and isochronous-transfer
support
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to system bus of Cortex-M4F core.
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
SRAM0: up to 192 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 7 of 200
S6E2C Series
◼I2C
CAN Interface (Max two channels)
◼Compatible with CAN specification 2.0A/B
◼Maximum transfer rate: 1 Mbps
◼Built-in 32-message buffer
Standard mode (Max 100 kbps)/Fast mode (Max 400
kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch
A and ch 7 = ch B) supported
DMA Controller (Eight Channels)
DMA controller has an independent bus, so the CPU and DMA
CAN-FD Interface (One channel)
◼Compatible with CAN Specification 2.0A/B
◼Maximum transfer rate: 5 Mbps
controller can process simultaneously.
◼Eight independently configured and operated channels
◼Transfer can be started by software or request from the built-
◼Message buffer for receiver: up to 192 messages
◼Message buffer for transmitter: up to 32 messages
◼CAN with flexible data rate (non-ISO CAN FD)
◼Notes:
CAN FD cannot communicate between non-ISO CAN FD
and ISO CAN FD, because non-ISO CAN FD and ISO
CAN FD are different frame format.
in peripherals
◼Transfer address area: 32-bit (4 GB)
◼Transfer mode: Block transfer/Burst transfer/Demand
transfer
◼Transfer data type: bytes/half-word/word
◼Transfer block count: 1 to 16
About the problem of "non-ISO CAN FD", see the White
Paper from CiA(CAN in Automation).
◼Number of transfers: 1 to 65536
http://www.can-
newsletter.org/engineering/standardization/141222_can-
fd-and-crc-issued_white-paper_bosch
DSTC (Descriptor System Data Transfer Controller;
256 channels)
Multi-function Serial Interface (Max 16 Channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can access directly
the memory/peripheral device and perform the data-transfer
operation.
◼Separate 64 byte receive and transmit FIFO buffers for
channels 0 to 7.
◼Operation mode is selectable for each channel from the
following:
UART
CSIO (SPI)
LIN
It supports the software activation, the hardware activation,
and the chain activation functions.
I2C
◼UART
Full-duplex double buffer
A/D Converter (Max 32 Channels)
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
◼12-bit A/D Converter
Successive approximation type
Built-in three units
Various error detect functions available (parity errors,
Conversion time: 0.5 μs at 5 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: 4 steps)
framing errors, and overrun errors)
◼CSIO (SPI)
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch 6 and ch 7 only)
Supports high-speed SPI (ch 4 and ch 6 only)
Data length 5 to 16-bit
D/A Converter (Max two channels)
◼R-2R type
◼12-bit resolution
◼LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/slave mode supported
LIN break field generation (can change to 13- to 16-bit
length)
LIN break delimiter generation (can change to 1- to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 8 of 200
S6E2C Series
Base Timer (Max 16 channels)
Operation mode is selected from the following for each
channel:
Real-Time Clock (RTC)
The real-time clock can count year, month, day, hour, minute,
second, or day of the week from 00 to 99.
◼16-bit PWM timer
◼16-bit PPG timer
◼Interrupt function with specifying date and time
(year/month/day/hour/minute) is available. This function is
also available by specifying only year, month, day, hour, or
minute.
◼16-/32-bit reload timer
◼16-/32-bit PWC timer
◼Timer interrupt function after set time or each set time.
◼Capable of rewriting the time with continuing the time count.
◼Leap year automatic count is available.
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals; moreover,
the port relocate function is built in. It can set the I/O port to
which the peripheral function can be allocated.
Quadrature Position/Revolution Counter (QPRC;
Max four channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. It is also
possible to use up/down counter.
◼Capable of pull-up control per pin
◼Capable of reading pin level directly
◼Built-in port-relocate function
◼The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
◼Up to 120 high-speed general-purpose I/O ports in 144-pin
package
◼16-bit position counter
◼16-bit revolution counter
◼Two 16-bit compare registers
◼Some pins 5 V tolerant I/O.
See "5. Pin Descriptions" and "6. I/O Circuit Type" for the
corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Multi-function Timer (Max three units)
The multi-function timer is composed of the following blocks:
Minimum resolution: 5.00 ns
◼16-bit free-run timer × 3 ch/unit
◼Input capture × 4 ch/unit
Operation mode is selectable from the following for each
channel:
◼Free-running
◼Periodic (= Reload)
◼One shot
◼Output compare × 6 ch/unit
◼A/D activation compare × 6 ch/unit
◼Waveform generator × 3 ch/unit
◼16-bit PPG timer × 3 ch/unit
Watch Counter
The watch counter is used for wake up from low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in High-speed CR clock, or built-in low-speed CR
clock as the clock source.
The following functions can be used to achieve the motor
control:
◼PWM signal output function
◼Interval timer: up to 64 s (max) with a sub clock of
32.768 kHz
◼DC chopper waveform output function
◼Dead time function
External Interrupt Controller Unit
◼External interrupt input pin: Max 32 pins
◼Include one non-maskable interrupt (NMI)
◼Input capture function
◼A/D convertor activate function
◼DTIF (motor emergency stop) interrupt function
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 9 of 200
S6E2C Series
◼Built-in dedicated descriptor-system DMAC
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
◼Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO.
◼Compliant IEEE1588-2008 (PTP)
This series consists of two different watchdogs: a "hardware"
watchdog and a "software" watchdog.
I2S (Inter-IC Sound Bus) Interface (TX x one channel,
RX x one channel)
The hardware watchdog timer is clocked by low-speed internal
CR oscillator. The hardware watchdog is thus active in any
power saving mode except RTC mode and Stop mode.
◼Supports three transfer protocols
I2S17
Left justified
DSP mode
Separate clock generation block for flexible system
integration options
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator helps to verify data transmission or
storage integrity.
◼Master/slave mode selectable
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
◼CCITT CRC16 generator polynomial: 0x1021
◼RX Only, TX Only or TX and RX simultaneous operation
selectable
◼IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
◼Word length is programmable from 7-bits to 32-bits
◼RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66
words x 32-bits)
Programmable Cyclic Redundancy Check
(PRGCRC) Accelerator
◼DMA, interrupts, or polling based data transfer supported
The CRC accelerator helps a verify data transmission or
High-speed Quad SPI
storage integrity.
Up to 66 MHz clock rates for very fast data transfers to and
CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial
are supported.
from SPI compatible devices.
Up to 256 Mbytes of memory mapped address space.
◼CCITT CRC16 generator polynomial: 0x1021
◼IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
◼Generating polynomial
◼Single data rate (SDR)
◼Supports single, dual, and quad data modes
◼Built-in direct mode and command sequencer mode
Direct mode: Access by use of transmission
FIFO/reception FIFO (up to 16 word x 32 bit)
Command sequencer mode: Automatic access assigned
to external device area.
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
◼Part 1 Physical Layer Specification version 3.01
◼Part E1 SDIO Specification version 3.00
Clock and Reset
◼Clocks
◼Part A2 SD Host Controller Standard Specification version
3.00
Five clock sources (two external oscillators, two internal CR
oscillators, and Main PLL) that are dynamically selectable.
◼1-bit or 4-bit data bus
Main clock: 4 MHz to 48 MHz
Sub clock: 30 kHz to 100 kHz
High-speed internal CR clock: 4 MHz
Low-speed internal CR clock: 100 kHz
Main PLL Clock
Ethernet-MAC
◼Compliant with IEEE802.3 specification
◼10 Mbps/100 Mbps data transfer rates supported
◼MII/RMII for external PHY device supported.
◼MII: Max one channel
◼Resets
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detector reset
Clock supervisor reset
◼RMII: Max one channel
◼Full-duplex and half-duplex mode supported.
◼Wake-ON-LAN supported
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 10 of 200
S6E2C Series
Clock Supervisor (CSV)
Clocks generated by internal CR oscillators are used to
VBAT
supervise abnormality of the external clocks.
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
◼External OSC clock failure (clock stop) is detected, reset is
asserted.
◼External OSC frequency anomaly is detected, interrupt or
reset is asserted.
◼RTC
Low-Voltage Detector (LVD)
◼32-kHz oscillation circuit
◼Power-on circuit
◼Back up register: 32 bytes
◼Port circuit
This Series include two-stage monitoring of voltage on the
VCC pins. When the voltage falls below the voltage that has
been set, the low-voltage detector function generates an
interrupt or reset.
◼LVD1: error reporting via interrupt
◼LVD2: auto-reset operation
Debug
◼Serial wire JTAG debug port (SWJ-DP)
Low-power Consumption mode
Six low power consumption modes are supported.
◼Embedded trace macrocells (ETM) provide comprehensive
debug and trace facilities.
◼Sleep
◼Timer
◼RTC
◼Stop
◼AHB trace macrocells (HTM)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
◼Deep standby RTC (selectable from with/without RAM
retention)
◼Five power supplies
Wide range voltage:
◼Deep standby stop (selectable from with/without RAM
retention)
VCC
= 2.7 V to 5.5 V
Power supply for USB ch 0 I/O:
USBVCC0 = 3.0 V to 3.6 V (when USB is used)
Peripheral Clock Gating
= 2.7 V to 5.5 V (when GPIO is used)
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
Power supply for USB ch 1 I/O:
USBVCC1 = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for Ethernet-MAC I/O:
ETHVCC = 3.0 V to 5.5 V (when Ethernet is used.)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for VBAT:
VBAT
= 1.65 V to 5.5 V
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 11 of 200
S6E2C Series
4. Pin Assignments
LQS144
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 12 of 200
S6E2C Series
LQP176
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S6E2C Series Datasheet
Page 13 of 200
S6E2C Series
LQQ216
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 14 of 200
S6E2C Series
LBE192
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 15 of 200
S6E2C Series
5. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
Pin
Alternate Pin Functions
Name
1
2
1
2
1
2
C1
B2
VCC
PA0
-
-
RTO20_0
(PPG20_0)
RTO21_0
(PPG20_0)
RTO22_0
(PPG22_0)
RTO23_0
(PPG22_0)
RTO24_0
(PPG24_0)
TIOA8_0
TIOA9_0
TIOA10_0
TIOA11_0
TIOA12_0
AIN2_0
BIN2_0
INT00_0
MADATA00_0
G
K
3
4
3
4
3
4
5
6
7
8
9
-
C2
C3
D5
D2
D1
D3
D4
E2
E3
E4
PA1
PA2
PA3
PA4
PA5
PA6
PA7
P50
P51
P52
MADATA01_0
MADATA02_0
G
G
G
G
G
E
E
E
E
E
I
I
ZIN2_0
5
5
MADATA03_0
MADATA04_0
TIOA13_0
I
6
6
I
RTO25_0
(PPG24_0)
7
7
SIN1_0
INT01_0
MADATA05_0
K
I
SOT1_0
(SDA1_0))
SCK1_0
8
8
DTTI2X_0
IC20_0
MADATA06_0
MADATA07_0
TIOA8_2
9
9
I
(SCL1_0)
RTO00_1
(PPG00_1)
RTO01_1
10
11
12
10
11
12
SCS72_0
SCS73_0
MADATA16_0
MADATA17_0
I
-
TIOB8_2
I
(PPG00_1)
RTO02_1
(PPG02_1)
RTO03_1
(PPG02_1)
SIN7_0
-
TIOA9_2
MADATA18_0
I
13
14
15
-
-
-
P53
PA8
PA9
TIOB9_2
IC21_0
IC22_0
MADATA19_0
INT02_0
E
I
I
Q
I
13
14
10
11
E5
F1
WKUP1
MADATA08_0
SOT7_0
(SDA7_0)
MADATA09_0
N
SCK7_0
16
15
12
F2
PAA
IC23_0
IC23_0
MADATA10_0
N
I
(SCL7_0)
SCS70_0
SCS71_0
17
18
16
17
13
14
F3
F4
PAB
PAC
RX0_0
TX0_0
FRCK2_0
TIOB8_0
INT03_0
AIN3_0
MADATA11_0
MADATA12_0
E
E
K
I
RTO04_1
(PPG04_1)
RTO05_1
(PPG04_1)
19
20
-
-
-
-
-
-
P54
P55
SIN15_1
TIOA10_2
TIOB10_2
INT00_2
MADATA20_0
E
E
K
I
SOT15_1
(SDA15_1)
SCK15_1
(SCL15_1)
IC00_1
MADATA21_0
MADATA22_0
21
22
23
-
-
-
-
-
-
P56
P57
PAD
DTTI0X_1
TIOB1_1
TIOB9_0
TIOB0_1
MADATA23_0
BIN3_0
E
E
N
I
I
I
SCK3_0
(SCL3_0)
18
15
F5
MADATA13_0
ZIN3_0
SOT3_0
(SDA3_0)
TIOB11_0
IC01_1
24
19
16
F6
PAE
ADTG_0
TIOB10_0
MADATA14_0
N
I
25
26
20
-
17
-
G2
-
PAF
P58
SIN3_0
SIN11_1
INT16_0
TIOB2_1
MADATA15_0
MADATA24_0
-
I
E
K
K
INT02_2
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S6E2C Series Datasheet
Page 16 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
SOT11_1
(SDA11_1)
SCK11_1
(SCL11_1)
FRCK0_1
SIN14_0
27
28
-
-
-
-
-
-
P59
P5A
IC02_1
IC03_1
TIOB3_1
TIOB4_1
MADATA25_0
E
E
I
I
MADATA26_0
29
30
-
21
-
18
-
G3
P5B
P08
TIOB5_1
TIOB12_0
MADATA27_0
INT17_0
E
E
I
K
MDQM0_0
MDQM1_0
SOT14_0
(SDA14_0)
31
32
22
23
19
20
G4
G5
P09
P0A
TIOB13_0
INT18_0
AIN2_1
E
L
K
I
SCK14_0
(SCL14_0)
MADATA28
_0
ADTG_1
MCLKOUT_0
SUBOUT_1
33
34
-
-
-
-
P5C
P30
TIOA11_2
RX0_1
RTCCO_1
INT03_2
E
I
24
G6
TIOA13_2
MDQM2_0
I2SCK0_0
I2SDI0_0
E
K
35
36
37
38
39
40
41
42
43
44
25
26
27
28
29
30
31
32
33
34
-
H4
H2
J1
H3
H1
H5
H6
J5
P31
P32
P33
P34
VCC
VSS
P35
P36
P37
P38
TX0_1
BIN2_1
FRCK0_0
IC03_0
TIOB13_2
INT19_0
ZIN2_1
MDQM3_0
S_DATA1_0
S_DATA0_0
S_CLK_0
E
L
L
L
-
I
K
I
K
-
21
22
23
24
25
26
27
28
29
INT00_1
-
-
IC02_0
IC01_0
IC00_0
ADTG_2
INT01_1
INT02_1
INT03_1
DTTI0X_0
S_CMD_0
S_DATA3_0
S_DATA2_0
S_WP_0
L
L
L
E
K
K
K
I
J4
J3
RTO00_0
(PPG00_0)
45
46
47
35
36
37
30
31
32
J2
K1
K2
P39
P3A
P3B
SIN2_1
TIOA0_1
TIOA1_1
TIOA2_1
AIN3_1
BIN3_1
ZIN3_1
INT19_1
G
G
G
K
K
K
SOT2_1
(SDA2_1)
RTO01_0
(PPG00_0)
SCK2_1
(SCL2_1)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
48
49
38
39
33
34
K3
K4
P3C
P3D
SIN13_0
TIOA3_1
TIOA4_1
G
G
K
I
SOT13_0
(SDA13_0)
SCK13_0
(SCL13_0)
SIN10_1
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
TIOB11_2
MAD20_0
MAD19_0
MNWEX_0
MNREX_0
50
51
52
40
41
42
35
-
L1
L2
L3
P3E
P5D
P5E
TIOA5_1
INT01_2
G
E
E
I
K
I
MADATA29_0 I2SMCLK0_0
I2SDO0_0
SOT10_1
(SDA10_1)
-
TIOA12_2
MADATA30_0
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 17 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
SCK10_1
(SCL10_1)
53
43
-
M2
P5F
TIOB12_2
MADATA31_0
TIOA0_0
I2SWS0_0
E
I
54
55
44
45
36
37
M1
N1
VSS
VCC
-
-
-
-
RTO10_0
(PPG10_0)
56
46
38
N2
P40
SIN3_1
AIN0_0
G
K
SOT3_1
(SDA3_1)
SCK3_1
RTO11_0
(PPG10_0)
RTO12_0
(PPG12_0)
RTO13_0
(PPG12_0)
RTO14_0
(PPG14_0)
RTO15_0
(PPG14_0)
57
58
59
60
61
47
48
49
50
51
39
40
41
42
43
N3
M3
L4
P41
P42
P43
P44
P45
TIOA1_0
TIOA2_0
TIOA3_0
TIOA4_0
TIOA5_0
BIN0_0
ZIN0_0
MCSX6_0
MCSX5_0
MCSX4_0
G
G
G
G
G
I
I
(SCL3_1)
SIN15_0
INT04_0
MCSX3_0
MCSX2_0
K
I
SOT15_0
(SDA15_0)
SCK15_0
(SCL15_0)
M4
N4
I
62
63
64
65
52
53
54
-
44
45
46
-
P2
P3
P4
-
C
-
-
-
-
-
-
VSS
VCC
P4A
SIN12_1
SOT12_1
(SDA12_1)
SCK12_1
(SCL12_1)
SCS72_1
SCS73_1
AIN0_1
BIN0_1
INT04_2
INT05_2
E
K
66
67
-
-
-
-
-
-
P4B
P4C
E
E
I
I
ZIN0_1
68
69
-
-
-
-
-
-
P4D
P4E
RX2_2
TX2_2
E
E
K
I
SCK1_1
(SCL1_1)
70
55
47
L5
P7D
RX2_0
TX2_0
DTTI1X_0
FRCK1_0
INT05_0
L
Q
71
72
73
74
75
76
77
78
79
80
56
57
58
59
60
61
62
63
64
65
48
49
50
51
52
53
54
-
M5
N5
P5
P6
P8
N6
M6
K5
K6
L6
P7E
INITX
P46
P47
VBAT
P48
ADTG_7
MCSX0_0
L
B
P
Q
-
O
O
E
E
I
I
C
S
T
-
U
U
K
K
K
X0A
X1A
VREGCTL
VWAKEUP
SCS63_0
SCS62_0
ADTG_8
SOT1_1
(SDA1_1)
SIN9_0
SOT9_0
(SDA9_0)
P49
PF0
PF1
P70
RX2_1
TX2_1
SIN1_1
FRCK1_1
TIOB15_1
INT06_0
TIOA15_1
INT23_1
MRDY_0
INT22_1
-
55
81
82
83
66
67
68
56
57
58
J6
L8
K8
P71
P72
P73
MAD00_0
TIOB0_0
TIOB1_0
E
E
E
I
K
I
INT07_0
MAD01_0
MAD02_0
SCK9_0
84
85
69
70
59
-
J8
P74
PF2
TIOB2_0
TIOA6_1
MAD03_0
MRASX_0
E
L
I
I
(SCL9_0)
RTO10_1
(PPG10_1)
N8
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 18 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
RTO11_1
(PPG10_1)
RTO12_1
(PPG12_1)
RTO13_1
(PPG12_1)
RTO14_1
(PPG14_1)
RTO15_1
(PPG14_1)
86
87
88
89
71
72
73
74
-
-
-
-
M8
N9
P9
M9
PF3
PF4
PF5
PF6
TIOB6_1
TIOA7_1
TIOB7_1
TIOA14_1
INT05_1
INT06_1
INT07_1
INT20_1
MCASX_0
L
L
L
L
L
K
K
K
K
MSDWEX_0
MCSX8_0
MSDCKE_0
90
91
92
75
76
77
-
L9
K9
PF7
P75
P76
TIOB14_1
TIOB3_0
TIOB4_0
INT21_1
AIN1_0
BIN1_0
MSDCLK_0
INT20_0
K
K
I
60
61
SIN8_0
MAD04_0
E
E
E
SOT8_0
(SDA8_0)
SCK8_0
(SCL8_0)
SCS70_1
SCS71_1
SIN6_0
P10
MAD05_0
93
78
62
N10
P77
TIOB5_0
ZIN1_0
MAD06_0
I
94
95
96
-
-
79
-
-
63
-
-
PF8
PF9
P78
DTTI1X_1
IC10_1
IC10_0
AIN1_1
BIN1_1
INT21_0
E
E
E
I
I
K
L10
MAD07_0
SOT6_0
(SDA6_0)
SCK6_0
(SCL6_0)
DA1
97
98
80
81
64
65
K10
M10
P79
P7A
IC11_0
IC12_0
MAD08_0
MAD09_0
L
L
I
I
99
82
83
66
67
N11
M11
P7B
P7C
SCS60_0
SCS61_0
IC13_0
INT22_0
R
R
J
J
100
DA0
INT04_1
SCK7_1
(SCL7_1)
SOT7_1
(SDA7_1)
SIN7_1
MD1
101
102
-
-
-
-
-
-
PFA
PFB
IC11_1
ZIN1_1
E
E
I
IC12_1
IC13_1
INT07_2
INT06_2
K
103
104
-
84
-
68
-
PFC
PE0
E
C
K
E
N13
105
85
69
N12
MD0
J
D
106
107
86
87
70
71
P12
P13
PE2
PE3
X0
X1
A
A
A
B
108
109
110
111
112
113
88
89
90
91
92
93
72
73
74
75
76
77
N14
M14
M13
M12
L13
L12
VSS
VCC
-
-
-
-
-
-
-
-
-
-
-
-
AVCC
AVSS
AVRL
AVRH
114
115
94
95
78
79
L11
P10
P11
AN00
AN01
SIN10_0
TIOA0_2
TIOB0_2
AIN0_2
BIN0_2
INT08_0
F
F
M
L
SOT10_0
(SDA10_0)
SCK10_0
(SCL10_0)
SIN6_1
SOT6_1
(SDA6_1)
SCS63_1
K13
116
117
118
119
96
97
98
-
80
81
82
-
K12
K14
K11
-
P12
P13
P14
PB8
AN02
AN03
TIOA1_2
RX1_1
ZIN0_2
F
F
F
E
L
M
L
INT25_1
AN04
TX1_1
ADTG_6
INT08_2
TRACED8
O
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 19 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
120
121
-
-
-
-
-
-
PB9
PBA
SIN9_1
SOT9_1
(SDA9_1)
SCK9_1
(SCL9_1)
AIN2_2
BIN2_2
INT09_2
TRACED9
E
E
O
N
TRACED10
122
123
124
125
126
-
-
-
PBB
P15
P16
P17
PB0
ZIN2_2
TRACED11
TIOB1_2
TIOA2_2
TIOB2_2
TIOA9_1
E
N
M
L
99
83
84
85
-
J13
J12
J11
J10
AN05
AN06
AN07
AN16
SIN11_0
AIN1_2
BIN1_2
ZIN1_2
INT09_0
F
F
F
F
SOT11_0
(SDA11_0)
SCK11_0
(SCL11_0)
SCK6_1
(SCL6_1)
SCS60_1
SCS61_1
SCS62_1
SIN2_0
SOT2_0
(SDA2_0)
SCK2_0
(SCL2_0)
SIN12_0
SOT12_0
(SDA12_0)
SCK12_0
(SCL12_0)
100
101
102
L
L
127
128
129
130
103
104
105
106
-
-
-
J9
H10
J14
H9
PB1
PB2
PB3
P18
AN17
AN18
AN19
AN08
TIOB9_1
TIOA10_1
TIOB10_1
TIOA3_2
INT08_1
INT09_1
F
F
F
F
M
M
L
86
INT10_0
INT24_1
M
131
107
87
H12
P19
AN09
TIOB3_2
TRACECLK
TRACED1
F
O
132
133
134
108
109
110
88
89
90
H14
G14
H13
P1A
P1B
P1C
AN10
AN11
AN12
TIOA4_2
TIOB4_2
TIOA5_2
TRACED0
INT11_0
F
F
F
N
O
N
TRACED2
135
136
111
-
91
-
H11
-
P1D
VSS
AN13
TIOB5_2
TRACED3
F
-
N
-
137
138
-
-
-
-
VCC
PB4
-
-
112
G13
AN20
AN21
SIN8_1
SOT8_1
(SDA8_1)
SCK8_1
(SCL8_1)
TIOB12_1
TIOA8_1
RTS5_0
TIOA11_1
TIOB11_1
INT10_1
INT11_1
TRACED4
TRACED5
F
O
139
140
113
114
-
-
F14
G12
PB5
PB6
F
F
O
N
AN22
TIOA12_1
TRACED6
141
142
143
144
115
116
117
118
-
G11
G10
G9
PB7
P1E
P1F
P2A
AN23
AN14
AN15
AN24
TRACED7
INT26_1
TIOB8_1
MAD12_0
F
F
F
F
N
M
M
L
92
93
94
MAD10_0
INT27_1
MAD11_0
F10
CTS5_0
SCK5_0
(SCL5_0)
SOT5_0
(SDA5_0)
SIN5_0
145
146
119
120
95
96
F11
F12
P29
P28
AN25
AN26
MAD13_0
F
F
L
L
MAD14_0
INT24_0
147
148
121
-
97
-
F13
-
P27
PBC
AN27
TX1_2
MAD15_0
INT10_2
F
E
M
N
TRACED12
SCK0_1
(SCL0_1)
SOT0_1
(SDA0_1)
SIN0_1
TX1_0
149
150
-
-
-
-
-
-
PBD
PBE
RX1_2
BIN3_2
AIN3_2
TRACED13
E
E
O
N
TRACED14
INT11_2
151
152
153
154
-
-
-
PBF
P26
P25
P24
ZIN3_2
MAD16_0
RX1_0
TRACED15
MAD17_0
E
E
F
F
O
I
M
L
122
123
124
98
99
100
E10
E11
E12
AN28
AN29
INT25_0
MAD18_0
TIOA13_1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 20 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
SCK0_0
155
156
125
126
101
102
E13
D12
P23
P22
UHCONX1
AN31
AN30
TIOB13_1
F
F
L
(SCL0_0)
INT26_0
INT27_0
SOT0_0
(SDA0_0)
SIN0_0
M
157
158
127
128
103
104
D13
C13
P21
P20
ADTG_4
NMIX
CROUT_0
I
I
K
F
WKUP0
USBV
CC1
P82
159
129
105
E14
-
-
160
161
130
131
106
107
D14
C14
UDM1
UDP1
H
H
R
R
P83
162
132
108
B14
VSS
-
-
163
164
165
166
167
168
169
170
133
134
135
136
137
138
139
140
109
110
111
112
113
114
-
A13
B13
A12
C12
B12
B11
C11
D11
VCC
P00
P01
P02
P03
P04
P90
P91
-
-
TRSTX
TCK
TDI
TMS
TDO
INT12_1
SIN5_1
SOT5_1
(SDA5_1)
SCK5_1
(SCL5_1)
CTS5_1
RTS5_1
RX0_2
E
E
E
E
E
S
S
G
G
G
G
G
K
K
SWCLK
SWDIO
SWO
Q_IO3_0
INT13_1
-
Q_IO2_0
Q_IO1_0
171
172
141
142
-
-
B10
C10
P92
P93
INT14_1
INT15_1
S
S
K
K
Q_IO0_0
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
143
144
-
-
-
-
-
D10
B9
-
P94
P95
P96
P97
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
Q_SCK_0
Q_CS0_0
INT12_2
INT13_2
S
S
S
S
K
K
K
K
K
K
K
E
K
K
K
-
I
I
Q_CS1_0
Q_CS2_0
K
K
V
V
V
V
V
V
V
W
V
V
V
-
-
-
TX0_2
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A9
A8
A7
C7
E_RXER
TIOB6_0
TIOA6_0
TIOB7_0
TIOA7_0
TIOB14_0
TIOA14_0
INT13_0
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
E_MDIO
E_MDC
CROUT_1
E_RXCK_REFCK
TIOB15_0
TIOA15_0
E_COL
E_CRS
ETHVCC
VSS
PCB
PCC
-
L
K
-
W
V
INT28_0
E_TCK
SOT4_1
(SDA4_1)
SIN4_1
RTS4_1
INT30_1
INT31_1
CTS4_1
E_COUT
INT14_0
192
160
130
A6
PCD
E_TXER
L
W
193
194
195
196
197
161
162
163
164
165
131
132
133
134
135
D7
E7
F7
B6
C6
PCE
PCF
PD0
PD1
PD2
INT15_0
INT12_0
E_TX01
E_TX00
FRCK2_1
SCK4_1
(SCL4_1)
E_TX03
E_TX02
L
L
L
L
L
W
W
W
W
V
E_TXEN
IC23_1
198
166
136
D6
P6E
ADTG_5
INT29_0
E_PPS
E
W
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 21 of 200
S6E2C Series
Pin Number
Pin
Name
Alternate Pin Functions
SCK14_1
(SCL14_1)
SOT14_1
(SDA14_1)
SIN14_1
DTTI2X_1
RTO20_1
(PPG20_1)
SCK13_1
(SCL13_0)
SOT13_1
(SDA13_1)
199
200
-
-
-
-
-
-
P6D
P6C
IC22_1
IC21_1
TIOB6_2
TIOA6_2
E
E
I
I
201
202
-
-
-
-
-
-
P6B
P6A
IC20_1
TIOA7_2
TIOB7_2
INT14_2
E
E
K
I
203
204
205
206
207
-
-
-
-
-
-
-
-
P69
P68
P67
P66
P65
TIOB14_2
E
E
E
E
E
I
I
RTO21_1
(PPG20_1)
RTO22_1
(PPG22_1)
RTO23_1
(PPG22_1)
-
TIOA14_2
TIOB15_2
TIOA15_2
-
-
-
I
-
SIN13_1
INT15_2
K
K
RTO24_1
(PPG24_1)
167
E6
INT28_1
RTO25_1
(PPG24_1)
RTS4_0
208
209
210
168
169
170
-
B5
C5
B4
P64
P63
P62
CTS4_0
INT29_1
INT30_0
I
K
K
I
137
138
ADTG_3
SCK4_0
(SCL4_0)
MOEX_0
L
L
MWEX_0
SOT4_0
(SDA4_0)
INT31_0
211
171
139
C4
P61
P60
UHCONX0
SIN4_0
MALE_0
WKUP3
RTCCO_0
SUBOUT_0
L
I
212
213
172
173
140
141
B3
A4
I
Q
-
USBVCC0
-
214
215
174
175
142
143
A3
A2
P80
P81
UDM0
UDP0
H
H
R
R
216
176
144
B1
E1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G1
P7
P11
L14
A11
A5
VSS
-
-
-
-
-
-
-
-
-
N7
M7
L7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K7
J7
-
-
-
-
-
-
-
-
--
-
G7
H7
-
-
-
-
-
-
H8
G8
-
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 22 of 200
S6E2C Series
Signal Descriptions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
F6
G5
J3
C5
D13
D6
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
24
32
44
209
157
198
119
71
19
23
34
169
127
166
-
56
65
94
95
16
20
29
137
103
136
-
A/D converter external trigger input
pin
-
48
55
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
-
M5
L6
80
114
115
116
117
118
123
124
125
130
131
132
133
134
135
142
143
126
127
128
129
138
139
140
141
144
145
146
147
153
154
155
156
L11
K13
K12
K14
K11
J13
J12
J11
H9
H12
H14
G14
H13
H11
G10
G9
96
97
98
99
100
101
106
107
108
109
110
111
116
117
102
103
104
105
112
113
114
115
118
119
120
121
123
124
125
126
A/D
converter
A/D converter analog input pin.
J10
J9
ANxx describes A/D converter ch xx.
-
-
-
-
-
-
-
H10
J14
G13
F14
G12
G11
F10
F11
F12
F13
E11
E12
E13
D12
94
95
96
97
99
100
101
102
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 23 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
N2
J2
L11
L8
-
K13
N3
K1
K12
K8
-
J13
M3
K2
J12
J8
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
56
45
114
82
21
115
57
46
116
83
22
123
58
47
124
84
26
125
59
48
130
91
27
131
46
35
94
67
-
95
47
36
96
68
-
99
48
37
100
69
-
101
49
38
106
76
-
38
30
78
57
-
79
39
31
80
58
-
83
40
32
84
59
-
85
41
33
86
60
-
Base Timer ch 0 TIOA pin
Base Timer ch 0 TIOB pin
Base Timer ch 1 TIOA pin
Base Timer ch 1 TIOB pin
Base Timer ch 2 TIOA pin
Base Timer ch 2 TIOB pin
Base Timer ch 3 TIOA pin
Base Timer ch 3 TIOB pin
Base
Timer
0
Base
Timer
1
Base
Timer
2
-
J11
L4
K3
H9
K9
-
Base
Timer
3
107
87
H12
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
60
49
50
39
108
77
-
42
34
88
61
-
M4
K4
H14
P10
-
Base Timer ch 4 TIOA pin
Base Timer ch 4 TIOB pin
Base Timer ch 5 TIOA pin
Base Timer ch 5 TIOB pin
Base Timer ch 6 TIOA pin
Base Timer ch 6 TIOB pin
Base
Timer
4
132
92
28
133
61
109
51
40
110
78
-
89
43
35
90
62
-
G14
N4
L1
50
Base
Timer
5
134
93
H13
N10
-
29
135
179
85
111
147
70
-
91
117
-
H11
D9
N8
-
Base
Timer
6
200
178
86
-
146
71
-
116
-
B8
M8
-
199
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 24 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TIOA8_0
TIOA8_1
TIOA8_2
TIOB8_0
TIOB8_1
TIOB8_2
TIOA9_0
TIOA9_1
TIOA9_2
TIOB9_0
TIOB9_1
TIOB9_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
181
87
149
72
-
119
F9
Base Timer ch 7 TIOA pin
-
-
N9
-
Base
Timer
7
202
180
88
148
73
-
118
-
E9
P9
-
Base Timer ch 7 TIOB pin
Base Timer ch 8 TIOA pin
Base Timer ch 8 TIOB pin
Base Timer ch 9 TIOA pin
Base Timer ch 9 TIOB pin
Base Timer ch 10 TIOA pin
Base Timer ch 10 TIOB pin
Base Timer ch 11 の TIOA pin
Base Timer ch 11 TIOB pin
Base Timer ch 12 TIOA pin
Base Timer ch 12 TIOB pin
201
2
-
2
2
92
-
B2
G10
E2
F4
G9
E3
C2
J10
E4
F5
J9
142
10
116
10
17
117
11
3
Base
Timer
8
18
14
93
-
143
11
3
3
-
126
12
102
12
18
103
-
Base
Timer
9
-
23
15
-
127
13
-
-
4
4
4
-
C3
H10
-
128
19
104
-
Base
Timer
10
-
24
19
105
-
16
-
F6
J14
-
129
20
-
5
5
5
-
D5
G13
-
138
33
112
-
Base
Timer
11
-
25
20
113
41
6
17
-
G2
F14
L2
D2
G12
L3
G3
G11
M2
139
51
-
6
6
-
140
52
114
42
21
115
43
Base
Timer
12
-
30
18
-
141
53
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 25 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
TX0_0
7
7
124
24
22
125
25
151
74
-
7
D1
Base Timer ch 13 TIOA pin
154
34
100
E12
G6
G4
E13
H4
D8
M9
-
Base
Timer
13
-
31
19
Base Timer ch 13 TIOB pin
Base Timer ch 14 TIOA pin
155
35
101
-
183
89
121
-
Base
Timer
14
204
182
90
-
150
75
-
120
C8
L9
-
Base Timer ch 14 TIOB pin
Base Timer ch 15 TIOA pin
-
-
203
187
78
155
63
-
125
-
B7
K5
-
Base
Timer
15
206
186
79
-
154
64
-
124
-
F8
K6
-
Base timer ch 15 TIOB pin
205
18
-
17
25
-
14
-
F4
H4
-
TX0_1
CAN interface ch 0 TX output pin
CAN interface ch 0 RX output pin
CAN interface ch 1 TX output pin
CAN interface ch 1 RX output pin
35
TX0_2
176
17
-
CAN 0
RX0_0
16
24
-
13
-
F3
G6
-
RX0_1
34
RX0_2
175
152
118
148
153
117
149
71
-
TX1_0
122
98
-
98
82
-
E10
K11
-
TX1_1
TX1_2
CAN 1
RX1_0
123
97
-
99
81
-
E11
K14
-
RX1_1
RX1_2
TX2_0
56
64
-
48
-
M5
K6
-
CAN-FD interface ch 2 TX output
pin
TX2_1
79
TX2_2
69
-
CAN 2
(CAN-FD)
RX2_0
70
55
63
-
47
-
L5
K5
-
CAN-FD interface ch 2 RX input pin
RX2_1
78
RX2_2
68
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 26 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
Serial wire debug interface clock
input pin
Serial wire debug interface data
input/output pin
SWCLK
SWDIO
165
167
135
137
111
113
A12
B12
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
SWO
TCK
TDI
168
165
166
168
138
135
136
138
114
111
112
114
B11
A12
C12
B11
TDO
JTAG test mode state input/output
pin
TMS
167
137
113
B12
Trace CLK output pin of ETM/HTM
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRACED4
TRACED5
TRACED6
TRACED7
TRACED8
TRACED9
TRACED10
TRACED11
TRACED12
TRACED13
TRACED14
TRACED15
TRSTX
131
132
133
134
135
138
139
140
141
119
120
121
122
148
149
150
151
164
107
108
109
110
111
112
113
114
115
-
87
H12
H14
G14
H13
H11
G13
F14
G12
G11
-
88
89
Trace data output pin of ETM/
Trace data output pin of HTM
90
91
Debugger
-
-
-
-
-
-
-
-
Trace data output pin of HTM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTAG test reset Input pin
134
110
B13
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 27 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
J6
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MCSX8_0
81
82
66
67
56
57
58
59
60
61
62
63
64
65
92
93
94
95
96
97
98
99
100
35
34
33
32
31
30
48
47
43
42
41
40
39
38
-
L8
K8
83
68
J8
84
69
K9
91
76
P10
N10
L10
K10
M10
G10
G9
92
77
93
78
96
79
97
80
98
81
142
143
144
145
146
147
152
153
154
50
116
117
118
119
120
121
122
123
124
40
F10
F11
F12
F13
E10
E11
E12
External bus interface address bus
External
bus
L1
K4
K3
K2
K1
J2
49
39
48
38
47
37
46
36
45
35
71
56
M5
L5
70
55
61
51
N4
M4
L4
60
50
External bus interface chip select
output pin
59
49
58
48
M3
N3
N2
P9
57
47
56
46
88
73
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 28 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MADATA16_0
MADATA17_0
MADATA18_0
MADATA19_0
MADATA20_0
MADATA21_0
MADATA22_0
MADATA23_0
MADATA24_0
MADATA25_0
MADATA26_0
MADATA27_0
MADATA28_0
MADATA29_0
MADATA30_0
2
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
-
B2
3
C2
C3
D5
D2
D1
D3
D4
E5
F1
F2
F3
F4
F5
F6
G2
-
4
5
6
7
8
9
14
15
16
17
18
23
24
25
10
11
12
13
19
20
21
22
26
27
28
29
33
51
52
External bus interface data bus
(address/data multiplex bus)
-
-
-
-
-
-
External
bus
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MADATA31_0
MDQM0_0
MDQM1_0
53
30
31
-
-
-
21
22
18
19
G3
G4
External bus interface byte mask
signal output pin
MDQM2_0
MDQM3_0
34
35
-
-
-
-
-
-
External bus interface address latch
enable output signal for multiplex
External bus interface external RDY
input signal
MALE_0
MRDY_0
211
80
171
65
139
55
C4
L6
External bus interface external
clock output pin
MCLKOUT_0
32
23
20
G5
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 29 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
External bus interface ALE signal to
control NAND flash output pin
External bus interface CLE signal to
control NAND flash output pin
External bus interface read enable
signal to control NAND flash
External bus interface write enable
signal to control NAND flash
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
SDRAM interface
SDRAM clock output pin
SDRAM interface
SDRAM clock enable pin
SDRAM interface
SDRAM column active strobe pin
SDRAM interface
SDRAM row active strobe pin
SDRAM interface
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
47
48
37
38
32
33
35
34
137
138
-
K2
K3
L1
50
40
49
39
K4
C5
B4
L9
209
210
90
169
170
75
External
bus
MWEX_0
MSDCLK_0
MSDCKE_0
MRASX_0
MCASX_0
MSDWEX_0
89
74
-
M9
N8
M8
N9
85
70
-
86
71
-
87
72
-
SDRAM write enable pin
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
2
38
19
7
2
28
-
2
23
-
B2
H3
-
External interrupt request 00 input
pin
7
7
D1
H6
L2
E5
J5
-
External interrupt request 01 input
pin
41
51
14
42
26
17
43
34
59
100
65
70
86
68
31
41
13
32
-
26
-
10
27
-
External interrupt request 02 input
pin
External
interrupt
16
33
24
49
83
-
13
28
-
F3
J4
G6
L4
M11
-
External interrupt request 03 input
pin
41
67
-
External interrupt request 04 input
pin
55
71
-
47
-
L5
M8
-
External interrupt request 05 input
pin
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 30 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
80
87
65
72
-
55
L6
External interrupt request 06 input
pin
-
-
N9
-
103
82
67
73
-
57
-
L8
P9
-
External interrupt request 07 input
pin
88
102
114
127
119
123
128
120
130
138
149
133
139
151
194
169
175
184
170
176
192
171
201
193
172
206
25
-
94
103
-
78
-
L11
J9
-
External interrupt request 08 input
pin
-
99
104
-
83
-
J13
H10
-
External interrupt request 09 input
pin
-
106
112
-
86
-
H9
G13
-
External interrupt request 10 input
pin
-
109
113
-
89
-
G14
F14
-
External interrupt request 11 input
pin
-
162
139
-
132
-
E7
C11
-
External interrupt request 12 input
pin
External
interrupt
-
152
140
-
122
-
E8
D11
-
External interrupt request 13 input
pin
-
160
141
-
130
-
A6
B10
-
External interrupt request 14 input
pin
-
161
142
-
131
-
D7
C10
-
External interrupt request 15 input
pin
-
20
35
21
36
22
37
17
30
18
31
19
32
G2
J2
G3
K1
G4
K2
External interrupt request 16 input
pin
45
30
External interrupt request 17 input
pin
46
31
External interrupt request 18 input
pin
47
INT19_0
INT19_1
INT20_0
36
48
91
26
38
76
21
33
60
H2
K3
K9
External interrupt request 19 input
pin
External interrupt request 20 input
pin
INT20_1
89
74
-
M9
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 31 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
96
79
75
63
-
L10
External interrupt request 21 input
pin
90
L9
N11
K5
99
82
66
-
External interrupt request 22 input
pin
78
63
56
46
38
-
N2
External interrupt request 23 input
pin
79
64
K6
147
131
153
117
156
142
157
143
190
207
198
208
209
195
212
196
158
121
107
123
97
97
87
99
81
102
92
103
93
128
-
F13
H12
E11
K14
D12
G10
D13
G9
External interrupt request 24 input
pin
External interrupt request 25 input
pin
126
116
127
117
158
167
166
168
169
163
172
164
128
External interrupt request 26 input
pin
External
interrupt
External interrupt request 27 input
pin
A7
External interrupt request 28 input
pin
E6
136
-
D6
External interrupt request 29 input
pin
B5
137
133
140
134
104
C5
External interrupt request 30 input
pin
F7
B3
External interrupt request 31 input
pin
B6
Non-maskable interrupt input pin
C13
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 32 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
P00
P01
P02
P03
P04
P08
P09
P0A
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P2A
164
165
166
167
168
30
134
135
136
137
138
21
110
111
112
113
114
18
B13
A12
C12
B12
B11
G3
General-purpose I/O port 0
31
22
19
G4
32
23
20
G5
114
115
116
117
118
123
124
125
130
131
132
133
134
135
142
143
158
157
156
155
154
153
152
147
146
145
144
94
78
L11
K13
K12
K14
K11
J13
J12
J11
H9
95
79
96
80
97
81
98
82
99
83
100
101
106
107
108
109
110
111
116
117
128
127
126
125
124
123
122
121
120
119
118
84
85
General-purpose I/O port 1
86
GPIO
87
H12
H14
G14
H13
H11
G10
G9
88
89
90
91
92
93
104
103
102
101
100
99
C13
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
General-purpose I/O port 2
98
97
96
95
94
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 33 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
56
57
58
59
60
61
73
74
76
77
65
66
67
68
69
24
25
26
27
28
31
32
33
34
35
36
37
38
39
40
46
47
48
49
50
51
58
59
61
62
-
-
G6
-
H4
H2
J1
H3
H6
J5
J4
J3
J2
K1
K2
K3
K4
L1
N2
N3
M3
L4
M4
N4
P5
P6
N6
M6
-
21
22
23
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
50
51
53
54
-
General-purpose I/O port 3
GPIO
General-purpose I/O port 4
-
-
-
-
-
-
-
-
-
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 34 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
P5E
P5F
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P6A
P6B
P6C
P6D
P6E
10
11
10
-
E2
11
-
E3
E4
-
12
12
-
13
-
-
19
-
-
-
20
-
-
-
21
-
-
-
22
-
-
-
General-purpose I/O port 5
26
-
-
-
27
-
-
-
28
-
-
-
-
29
-
-
33
-
-
-
51
41
42
43
172
171
170
169
168
167
-
-
L2
L3
M2
B3
C4
B4
C5
B5
E6
-
52
-
GPIO
53
-
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
140
139
138
137
-
-
-
General-purpose I/O port 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
166
136
D6
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 35 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
P96
P97
80
81
65
66
55
56
57
58
59
60
61
62
63
64
65
66
67
47
48
142
143
106
107
-
L6
J6
L8
82
67
83
68
K8
84
69
J8
91
76
K9
92
77
P10
N10
L10
K10
M10
N11
M11
L5
General-purpose I/O port 7
93
78
96
79
97
80
98
81
99
82
100
70
83
GPIO
55
71
56
M5
A3
214
215
160
161
169
170
171
172
173
174
175
176
174
175
130
131
139
140
141
142
143
144
-
A2
General-purpose I/O port 8
D14
C14
C11
D11
B10
C10
D10
B9
-
-
-
General-purpose I/O port 9
-
-
-
-
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 36 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PAA
PAB
PAC
PAD
PAE
PAF
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PBA
PBB
PBC
PBD
PBE
PBF
2
2
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
-
B2
3
C2
C3
D5
D2
D1
D3
D4
E5
F1
F2
F3
F4
F5
F6
G2
J10
J9
H10
J14
G13
F14
G12
G11
-
4
4
5
5
6
6
7
7
8
8
9
9
General-purpose I/O port A
14
13
14
15
16
17
18
19
20
102
103
104
105
112
113
114
115
-
15
16
17
18
23
24
25
GPIO
126
127
128
129
138
139
140
141
119
120
121
122
148
149
150
151
-
-
-
-
-
-
-
General-purpose I/O port B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 37 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PFA
PFB
PFC
177
178
179
180
181
182
183
184
185
186
187
190
191
192
193
194
195
196
197
104
106
107
78
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
84
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
68
70
71
-
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
N13
P12
P13
K5
K6
N8
M8
N9
P9
M9
L9
-
General-purpose I/O port C
General-purpose I/O port D
General-purpose I/O port E
GPIO
86
87
63
79
64
-
85
70
-
86
71
-
87
72
-
88
73
-
General-purpose I/O port F
89
74
-
90
75
-
94
-
-
95
-
-
-
101
102
103
-
-
-
-
-
-
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 38 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
SIN0_0
SIN0_1
157
151
127
-
103
-
D13
Multi-function serial interface ch 0
input pin
-
Multi-function serial interface ch 0
output pin
SOT0_0
(SDA0_0)
156
126
102
D12
This pin operates as SOT0 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA0 when it is used in an I2C
(operation mode 4).
Multi-
Function
Serial
0
SOT0_1
(SDA0_1)
150
-
-
-
Multi-function serial interface ch 0
clock I/O pin
This pin operates as SCK0 when it
is used in a CSIO (operation mode
2) and as SCL0 when it is used in
an I2C (operation mode 4)
SCK0_0
(SCL0_0)
155
149
125
-
101
-
E13
-
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
7
7
7
D1
L6
Multi-function serial interface ch 1
input pin
80
65
55
Multi-function serial interface ch 1
output pin
SOT1_0
(SDA1_0)
8
8
8
D3
This pin operates as SOT1 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA1 when it is used in an I2C
(operation mode 4).
Multi-
Function
Serial
1
SOT1_1
(SDA1_1)
81
66
56
J6
Multi-function serial interface ch 1
clock I/O pin
This pin operates as SCK1 when it
is used in a CSIO (operation mode
2) and as SCL1 when it is used in
an I2C (operation mode 4).
SCK1_0
(SCL1_0)
9
9
9
D4
L5
SCK1_1
(SCL1_1)
70
55
47
SIN2_0
SIN2_1
130
45
106
35
86
30
H9
J2
Multi-function serial interface ch 2
input pin
Multi-function serial interface ch 2
output pin
SOT2_0
(SDA2_0)
131
107
87
H12
This pin operates as SOT2 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA2 when it is used in an I2C
(operation mode 4).
Multi-
Function
Serial
2
SOT2_1
(SDA2_1)
46
36
31
K1
Multi-function serial interface ch 2
clock I/O pin
This pin operates as SCK2 when it
is used in a CSIO (operation mode
2) and as SCL2 when it is used in
an I2C (operation mode 4).
SCK2_0
(SCL2_0)
132
47
108
37
88
32
H14
K2
SCK2_1
(SCL2_1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 39 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
SIN3_0
SIN3_1
25
56
20
46
17
38
G2
Multi-function serial interface ch 3
input pin
N2
F6
Multi-function serial interface ch 3
output pin
SOT3_0
(SDA3_0)
24
19
16
This pin operates as SOT3 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA3 when it is used in an I2C
(operation mode 4).
Multi-
Function
Serial
3
SOT3_1
(SDA3_1)
57
47
39
N3
Multi-function serial interface ch 3
clock I/O pin
This pin operates as SCK3 when it
is used in a CSIO (operation modes
2) and as SCL3 when it is used in
an I2C (operation mode 4).
SCK3_0
(SCL3_0)
23
58
18
48
15
40
F5
SCK3_1
(SCL3_1)
M3
SIN4_0
SIN4_1
212
193
172
161
140
131
B3
D7
Multi-function serial interface ch 4
input pin
Multi-function serial interface ch 4
output pin
SOT4_0
(SDA4_0)
211
171
139
C4
This pin operates as SOT4 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA4 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 4
clock I/O pin
This pin operates as SCK4 when it
is used in a CSIO (operation mode
2) and as SCL4 when it is used in
an I2C (operation mode 4).
SOT4_1
(SDA4_1)
192
160
130
A6
Multi-
Function
Serial
4
SCK4_0
(SCL4_0)
210
198
170
166
138
136
B4
D6
SCK4_1
(SCL4_1)
CTS4_0
CTS4_1
RTS4_0
RTS4_1
208
197
209
194
168
165
169
162
-
B5
C6
C5
E7
Multi-function serial interface ch 4
CTS input pin
135
137
132
Multi-function serial interface ch 4
RTS output pin
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 40 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
SIN5_0
SIN5_1
147
170
121
140
97
-
F13
Multi-function serial interface ch 5
input pin
D11
F12
Multi-function serial interface ch 5
output pin
SOT5_0
(SDA5_0)
146
120
96
This pin operates as SOT5 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA5 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 5
clock I/O pin
This pin operates as SCK5 when it
is used in a CSIO (operation mode
2) and as SCL5 when it is used in
an I2C (operation mode 4).
SOT5_1
(SDA5_1)
171
141
-
B10
Multi-
Function
Serial
5
SCK5_0
(SCL5_0)
145
172
119
142
95
-
F11
SCK5_1
(SCL5_1)
C10
CTS5_0
CTS5_1
RTS5_0
RTS5_1
SIN6_0
SIN6_1
144
173
143
174
96
118
143
117
144
79
94
-
F10
D10
G9
Multi-function serial interface ch 5
CTS input pin
93
-
Multi-function serial interface ch 5
RTS output pin
B9
63
81
L10
K14
Multi-function serial interface ch 6
input pin
117
97
Multi-function serial interface ch 6
output pin
This pin operates as SOT6 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA6 when it is used in an I2C
(operation mode 4).
SOT6_0
(SDA6_0)
97
80
98
64
K10
SOT6_1
(SDA6_1)
118
82
K11
Multi-function serial interface ch 6
clock I/O pin
This pin operates as SCK6 when it
is used in a CSIO (operation mode
2) and as SCL6 when it is used in
an I2C (operation mode 4).
SCK6_0
(SCL6_0)
98
81
65
-
M10
J10
Multi-
Function
Serial
6
SCK6_1
(SCL6_1)
126
102
SCS60_0
SCS60_1
SCS61_0
SCS61_1
SCS62_0
SCS62_1
SCS63_0
SCS63_1
99
127
100
128
79
82
103
83
66
-
N11
J9
Multi-function serial interface ch 6
chip select 0 input/output pin
67
-
M11
H10
K6
Multi-function serial interface ch 6
chip select1 input/output pin
104
64
-
Multi-function serial interface ch 6
chip select2 input/output pin
129
78
105
63
-
J14
K5
-
Multi-function serial interface ch 6
chip select3 input/output pin
119
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 41 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
SIN7_0
14
13
-
10
-
E5
Multi-function serial interface ch 7
input pin
SIN7_1
SOT7_0
(SDA7_0)
103
-
Multi-function serial interface ch 7
output pin
15
14
11
F1
This pin operates as SOT7 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA7 when it is used in an I2C
(operation mode 4).
SOT7_1
(SDA7_1)
102
-
-
-
Multi-function serial interface ch 7
clock I/O pin
This pin operates as SCK7 when it
is used in a CSIO (operation mode
2) and as SCL7 when it is used in
an I2C (operation mode 4).
SCK7_0
(SCL7_0)
16
15
-
12
-
F2
-
Multi-
Function
Serial
7
SCK7_1
(SCL7_1)
101
SCS70_0
SCS70_1
SCS71_0
SCS71_1
SCS72_0
SCS72_1
SCS73_0
SCS73_1
SIN8_0
17
94
18
95
10
68
11
16
-
13
-
F3
-
Multi-function serial interface ch 7
chip select 0 input/output pin
17
-
14
-
F4
-
Multi-function serial interface ch 7
chip select 1 input/output pin
10
-
-
E2
-
Multi-function serial interface ch 7
chip select 2 input/output pin
-
11
-
-
E3
-
Multi-function serial interface ch 7
chip select 3 input/output pin
69
91
138
-
76
112
60
-
K9
G13
Multi-function serial interface ch 8
input pin
SIN8_1
SOT8_0
(SDA8_0)
Multi-function serial interface ch 8
output pin
92
77
61
P10
This pin operates as SOT8 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA8 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 8
clock I/O pin
This pin operates as SCK8 when it
is used in a CSIO (operation mode
2) and as SCL8 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
8
SOT8_1
(SDA8_1)
139
113
-
F14
SCK8_0
(SCL8_0)
93
78
62
-
N10
G12
SCK8_1
(SCL8_1)
140
114
SIN9_0
82
67
-
57
-
L8
-
Multi-function serial interface ch 9
input pin
SIN9_1
SOT9_0
(SDA9_0)
120
Multi-function serial interface ch 9
output pin
83
68
58
K8
This pin operates as SOT9 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA9 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 9
clock I/O pin
This pin operates as SCK9 when it
is used in a CSIO (operation mode
2) and as SCL9 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
9
SOT9_1
(SDA9_1)
121
-
-
-
SCK9_0
(SCL9_0)
84
69
-
59
-
J8
-
SCK9_1
(SCL9_1)
122
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 42 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
L11
L2
SIN10_0
114
51
94
41
78
-
Multi-function serial interface ch 10
input pin
SIN10_1
SOT10_0
(SDA10_0)
Multi-function serial interface ch 10
output pin
115
95
79
K13
This pin operates as SOT10 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA10 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 10
clock I/O pin
This pin operates as SCK10 when it
is used in a CSIO (operation mode
2) and as SCL10 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
10
SOT10_1
(SDA10_1)
52
42
-
L3
SCK10_0
(SCL10_0)
116
53
96
43
80
-
K12
M2
SCK10_1
(SCL10_1)
SIN11_0
123
26
99
-
83
-
J13
-
Multi-function serial interface ch 11
input pin
SIN11_1
SOT11_0
(SDA11_0)
Multi-function serial interface ch 11
output pin
124
100
84
J12
This pin operates as SOT11 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA11 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 11
clock I/O pin
This pin operates as SCK11 when it
is used in a CSIO (operation mode
2) and as SCL11 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
11
SOT11_1
(SDA11_1)
27
-
-
-
SCK11_0
(SCL11_0)
125
28
101
-
85
-
J11
-
SCK11_1
(SCL11_1)
SIN12_0
133
65
109
-
89
-
G14
-
Multi-function serial interface ch 12
input pin
SIN12_1
SOT12_0
(SDA12_0)
Multi-function serial interface ch 12
output pin
134
110
90
H13
This pin operates as SOT12 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA12 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 12
clock I/O pin
This pin operates as SCK12 when it
is used in a CSIO (operation mode
2) and as SCL12 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
12
SOT12_1
(SDA12_1)
66
-
-
-
SCK12_0
(SCL12_0)
135
67
111
-
91
-
H11
-
SCK12_1
(SCL12_1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 43 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
K3
-
SIN13_0
48
38
-
33
-
Multi-function serial interface ch 13
input pin
SIN13_1
SOT13_0
(SDA13_0)
206
Multi-function serial interface ch 13
output pin
49
39
34
K4
This pin operates as SOT13 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA13 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 13
clock I/O pin
This pin operates as SCK13 when it
is used in a CSIO (operation mode
2) and as SCL13 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
13
SOT13_1
(SDA13_1)
205
-
-
-
SCK13_0
(SCL13_0)
50
40
-
35
-
L1
-
SCK13_1
(SCL13_1)
204
SIN14_0
30
21
-
18
-
G3
-
Multi-function serial interface ch 14
input pin
SIN14_1
SOT14_0
(SDA14_0)
201
Multi-function serial interface ch 14
output pin
31
22
19
G4
This pin operates as SOT14 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA14 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 14
clock I/O pin
This pin operates as SCK14 when it
is used in a CSIO (operation mode
2) and as SCL14 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
14
SOT14_1
(SDA14_1)
200
-
-
-
SCK14_0
(SCL14_0)
32
23
-
20
-
G5
-
SCK14_1
(SCL14_1)
199
SIN15_0
59
19
49
-
41
-
L4
-
Multi-function serial interface ch 15
input pin
SIN15_1
SOT15_0
(SDA15_0)
Multi-function serial interface ch 15
output pin
60
50
42
M4
This pin operates as SOT15 when it
is used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA15 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 15
clock I/O pin
This pin operates as SCK15 when it
is used in a CSIO (operation mode
2) and as SCL15 when it is used in
an I2C (operation mode 4).
Multi-
Function
Serial
15
SOT15_1
(SDA15_1)
20
-
-
-
SCK15_0
(SCL15_0)
61
21
51
-
43
-
N4
-
SCK15_1
(SCL15_1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 44 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
Input signal controlling waveform
generator outputs RTO00 to RTO05
of Multi-Function Timer 0.
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
IC00_0
44
21
37
29
43
22
42
26
41
27
38
28
34
-
29
-
J3
-
J1
-
27
-
22
-
16-bit free-run timer ch 0 external
clock input pin
33
-
28
-
J4
-
IC00_1
IC01_0
32
-
27
-
J5
-
16-bit input capture input pin of
Multi-Function Timer 0.
ICxx describes channel number.
IC01_1
IC02_0
31
-
26
-
H6
-
IC02_1
IC03_0
28
-
23
-
H3
-
IC03_1
RTO00_0
(PPG00_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when
it is used in PPG0 output modes.
45
10
46
11
47
12
48
13
49
19
50
20
35
10
36
11
37
12
38
-
30
-
J2
E2
K1
E3
K2
E4
K3
-
RTO00_1
(PPG00_1)
Multi-
Function
Timer 0
RTO01_0
(PPG00_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when
31
-
RTO01_1
(PPG00_1)
it is used in PPG0 output modes.
RTO02_0
(PPG02_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when
it is used in PPG0 output modes.
32
-
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when
it is used in PPG0 output modes.
33
-
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when
39
-
34
-
K4
-
RTO04_1
(PPG04_1)
it is used in PPG0 output modes.
RTO05_0
(PPG04_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when
it is used in PPG0 output modes.
40
-
35
-
L1
-
RTO05_1
(PPG04_1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 45 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
Input signal controlling waveform
generator outputs RTO10 to RTO15
of Multi-Function Timer 1.
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
70
94
55
-
47
-
L5
-
M5
K5
L10
-
71
56
63
79
-
48
-
16-bit free-run timer ch 1 external
clock input pin
78
96
63
-
IC10_1
95
IC11_0
97
80
-
64
-
K10
-
16-bit input capture input pin of
Multi-Function Timer 1.
ICxx describes channel number.
IC11_1
101
98
IC12_0
81
-
65
-
M10
-
IC12_1
102
99
IC13_0
82
-
66
-
N11
-
IC13_1
103
RTO10_0
(PPG10_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when
it is used in PPG1 output modes.
56
85
57
86
46
70
47
71
38
-
N2
N8
N3
M8
RTO10_1
(PPG10_1)
Multi-
Function
Timer 1
RTO11_0
(PPG10_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when
39
-
RTO11_1
(PPG10_1)
it is used in PPG1 output modes.
RTO12_0
(PPG12_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when
it is used in PPG1 output modes.
58
87
59
88
60
89
61
48
72
49
73
50
74
51
40
-
M3
N9
L4
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when
it is used in PPG1 output modes.
41
-
RTO13_1
(PPG12_1)
P9
M4
M9
N4
RTO14_0
(PPG14_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when
42
-
RTO14_1
(PPG14_1)
it is used in PPG1 output modes.
RTO15_0
(PPG14_0)
43
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when
it is used in PPG1 output modes.
RTO15_1
(PPG14_1)
90
75
-
L9
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 46 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
Input signal controlling waveform
generator outputs RTO20 to RTO25
of Multi-Function Timer 1.
DTTI2X_0
DTTI2X_1
FRCK2_0
FRCK2_1
IC20_0
8
8
-
8
-
D3
202
17
-
16
165
9
13
135
9
F3
C6
D4
-
16-bit free-run timer ch 2 external
clock input pin
197
9
IC20_1
201
14
-
-
IC21_0
13
-
10
-
E5
-
16-bit input capture input pin of
Multi-Function Timer 2.
ICxx describes channel number.
IC21_1
200
15
IC22_0
14
-
11
-
F1
-
IC22_1
199
16
IC23_0
15
166
12
136
F2
D6
IC23_1
198
RTO20_0
(PPG20_0)
Waveform generator output pin of
Multi-Function Timer 2.
This pin operates as PPG20 when
it is used in PPG2 output modes.
2
203
3
2
-
2
-
B2
-
RTO20_1
(PPG20_1)
Multi-
Function
Timer 2
RTO21_0
(PPG20_0)
Waveform generator output pin of
Multi-Function Timer 2.
This pin operates as PPG20 when
3
-
3
-
C2
-
RTO21_1
(PPG20_1)
204
4
it is used in PPG2 output modes.
RTO22_0
(PPG22_0)
Waveform generator output pin of
Multi-Function Timer 2.
This pin operates as PPG22 when
it is used in PPG2 output modes.
4
-
4
-
C3
-
RTO22_1
(PPG22_1)
205
5
RTO23_0
(PPG22_0)
Waveform generator output pin of
Multi-Function Timer 2.
This pin operates as PPG22 when
it is used in PPG2 output modes.
5
-
5
-
D5
-
RTO23_1
(PPG22_1)
206
RTO24_0
(PPG24_0)
Waveform generator output pin of
Multi-Function Timer 2.
This pin operates as PPG24 when
6
207
7
6
167
7
6
-
D2
E6
D1
RTO24_1
(PPG24_1)
it is used in PPG2 output modes.
RTO25_0
(PPG24_0)
Waveform generator output pin of
Multi-Function Timer 2.
7
This pin operates as PPG24 when
it is used in PPG2 output modes.
RTO25_1
(PPG24_1)
208
168
-
B5
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 47 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
AIN2_0
AIN2_1
AIN2_2
BIN2_0
BIN2_1
BIN2_2
ZIN2_0
ZIN2_1
ZIN2_2
AIN3_0
AIN3_1
AIN3_2
BIN3_0
BIN3_1
BIN3_2
ZIN3_0
ZIN3_1
ZIN3_2
56
65
46
-
38
-
N2
QPRC ch 0 AIN input pin
-
L11
N3
-
114
57
94
47
-
78
39
-
Quadrature
Position/
Revolution
Counter
0
QPRC ch 0 BIN input pin
QPRC ch 0 ZIN input pin
QPRC ch 1 AIN input pin
QPRC ch 1 BIN input pin
QPRC ch 1 ZIN input pin
QPRC ch 2 AIN input pin
QPRC ch 2 BIN input pin
QPRC ch 2 ZIN input pin
QPRC ch 3 AIN input pin
QPRC ch 3 BIN input pin
QPRC ch 3 ZIN input pin
66
115
58
95
48
-
79
40
-
K13
M3
-
67
116
91
96
76
-
80
60
-
K12
K9
-
94
123
92
99
77
-
83
61
-
J13
P10
-
Quadrature
Position/
Revolution
Counter
1
45
124
93
100
78
-
84
62
-
J12
N10
-
101
125
2
101
2
85
2
J11
B2
G5
-
32
23
-
20
-
120
3
Quadrature
Position/
Revolution
Counter
2
3
3
C2
H2
-
36
26
-
21
-
121
4
4
4
C3
J1
-
37
27
-
22
-
122
18
17
35
-
14
30
-
F4
J2
-
45
149
23
Quadrature
Position/
Revolution
Counter
3
18
36
-
15
31
-
F5
K1
-
46
150
24
19
37
-
16
32
-
F6
K2
-
47
151
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 48 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
RTCCO_0
RTCCO_1
SUBOUT_0
SUBOUT_1
UDM0
211
33
171
-
139
-
C4
0.5 seconds pulse output pin of
real-time clock
-
Real-time
clock
211
33
171
-
139
-
C4
-
Sub-clock output pin
USB ch 0 device/host D – pin
USB ch 0 device/host D + pin
214
215
174
175
142
143
A3
A2
UDP0
USB0
USB1
USB ch 0 external pull-up control
pin
UHCONX0
211
171
139
C4
USB ch 1 device/host D – pin
USB ch 1 device/host D + pin
UDM1
UDP1
160
161
130
131
106
107
D14
C14
USB ch 1 external pull-up control
pin
Deep Standby mode return signal
input pin 0
Deep Standby mode return signal
input pin 1
Deep Standby mode return signal
input pin 2
Deep Standby mode return signal
input pin 3
D/A converter ch 0 analog output
pin
UHCONX1
WKUP0
WKUP1
WKUP2
WKUP3
DA0
155
158
14
125
128
13
101
104
10
E13
C13
E5
Low power
Consumption
mode
70
55
47
L5
212
100
172
83
140
67
B3
M11
D/A
converter
D/A converter ch 1 analog output
pin
DA1
99
76
77
82
61
62
66
53
54
N11
N6
On-board regulator control pin
VREGCTL
VWAKEUP
VBAT
The return signal input pin from a
hibernation state
M6
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
S_CLK_0
S_CMD_0
38
41
28
31
23
26
H3
H6
S_DATA1_0
S_DATA0_0
S_DATA3_0
S_DATA2_0
36
37
42
43
26
27
32
33
21
22
27
28
H2
J1
J5
J4
SD memory card interface
SD memory card data bus
SD I/F
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
S_CD_0
S_WP_0
45
44
35
34
30
29
J2
J3
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 49 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
Collision detection
LQQ
216
LQP
176
LQS
144
LBE
192
E_COL
E_COUT
E_CRS
E_MDC
E_MDIO
E_PPS
186
190
187
184
183
198
181
180
179
178
154
158
155
152
151
166
149
148
147
146
124
128
125
122
121
136
119
118
117
116
F8
Clock output for Ethernet PHY
Carrier detection
A7
B7
E8
D8
D6
F9
E9
D9
B8
Management clock
Management data I/O
PTP counter monitor
Received data0
E_RX00
E_RX01
E_RX02
E_RX03
Received data1
Received data2
Received data3
Ethernet
E_RXCK_REF Received clock input/
185
153
123
A10
Reference clock
CK
E_RXDV
Received data enable
182
177
191
196
195
194
193
197
192
51
150
145
159
164
163
162
161
165
160
41
120
C8
C9
C7
B6
F7
E_RXER
E_TCK
Received data error detection
Transition clock input
115
129
Transition data0
E_TX00
134
Transition data1
E_TX01
133
Transition data2
E_TX02
132
E7
D7
C6
A6
L2
E_TX03
Transition data3
131
E_TXEN
E_TXER
I2SMCLK0_0
I2SDO0_0
I2SWS0_0
I2SDI0_0
I2SCK0_0
Q_SCK_0
Q_IO0_0
Q_IO1_0
Q_IO2_0
Q_IO3_0
Q_CS0_0
Q_CS1_0
Q_CS2_0
Transition data enable
Transition data error detection
I2S external clock pin
135
130
-
-
-
-
-
-
-
-
-
-
-
-
-
I2S serial transition data output pin
I2S frame synchronization signal pin
I2S serial received data input pin
I2S bit clock pin
52
42
L3
I2S
53
43
M2
G6
H4
D10
C10
B10
D11
C11
B9
-
34
24
35
25
SPI clock output pin
173
172
171
170
169
174
175
176
143
142
141
140
139
144
-
SPI data input/output pin
SPI chip select output pin
High-speed
quad SPI
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 50 of 200
S6E2C Series
Pin Number
Module
Pin Name
INITX
Function
LQQ
216
LQP
176
LQS
144
LBE
192
External reset Input pin
A reset is valid when INITX = L.
Reset
72
57
49
N5
Mode 1 pin
MD1
During serial programming to flash
memory, MD1 = L must be input.
Mode 0 pin
During normal operation, MD0 = L
must be input. During serial
programming to flash memory, MD0
= H must be input.
104
84
68
N13
N12
Mode
MD0
VCC
105
85
69
1
39
55
64
109
137
163
213
159
188
40
54
63
108
136
162
189
216
-
1
1
C1
H1
N1
P4
M14
-
29
24
45
37
Power supply pin
54
46
89
73
Power
-
-
133
109
A13
A4
E14
A9
H5
M1
P3
N14
-
USBVCC0
USBVCC1
ETHVCC
173
141
3.3V power supply port for USB I/O
Power supply pin for Ethernet I/O
129
105
156
126
30
25
44
36
53
45
88
72
-
-
132
108
B14
A8
B1
E1
G1
P7
P11
L14
A11
A5
N7
M7
K7
J7
157
127
176
144
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
VSS
GND pin
-
-
-
-
-
-
-
-
-
G7
H7
H8
G8
-
-
-
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 51 of 200
S6E2C Series
Pin Number
Module
Pin Name
Function
LQQ
216
LQP
176
LQS
144
LBE
192
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
X0
X1
106
107
73
86
87
58
59
70
71
50
51
P12
P13
P5
X0A
X1A
Clock
74
P6
CROUT_0
CROUT_1
157
184
127
152
103
122
D13
E8
Built-in High-speed CR-oscillation
clock output port
A/D converter and D/A converter
analog power-supply pin
A/D converter analog reference
voltage input pin
A/D converter analog reference
voltage input pin
AVCC
AVRL
AVRH
110
112
113
90
92
93
74
76
77
M13
L13
L12
Analog
power
VBAT power supply pin
Backup power supply (battery etc.)
and system power supply
A/D converter and D/A converter
GND pin
VBAT
power
VBAT
75
60
52
P8
Analog
GND
AVSS
C
111
62
91
52
75
44
M12
P2
Power supply stabilization capacity
pin
C pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 52 of 200
S6E2C Series
6. I/O Circuit Type
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
Digital output
X1
N-ch
R
It is possible to select the main
oscillation/GPIO function.
Pull-up resistor control
Digital input
When the main oscillation
is selected:
・ Oscillation feedback resistor:
approximately 1 MΩ
Standby mode control
Clock input
・ Standby mode control
Feedback
resistor
A
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
Standby mode control
Digital input
approximately 50 kΩ
Standby mode control
Pull-up
resistor
・ IOH = -4 mA, IOL= 4 mA
R
P-ch
N-ch
P-ch
Digital output
X0
Digital output
Pull-up resistor control
・ CMOS level hysteresis input
・ Pull-up resistor:
Pull-up resistor
B
approximately 50 kΩ
Digital input
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 53 of 200
S6E2C Series
Type
Circuit
Remarks
Digital input
・ Open drain output
C
N-ch
Digital output
・ CMOS level hysteresis input
・ CMOS level output
P-ch
P-ch
Digital output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
E
approximately 50 kΩ
N-ch
Digital output
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
R
Pull-up resistor control
Digital input
Standby mode control
0
P-ch
P-ch
Digital output
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Input control
・ Analog input
N-ch
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
F
approximately 50 kΩ
Pull-up resistor control
Digital input
R
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Standby mode control
Analog input
Input control
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 54 of 200
S6E2C Series
Type
Circuit
Remarks
・ CMOS level output
P-ch
P-ch
Digital output
Digital output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
G
approximately 50 kΩ
N-ch
・ IOH = -12 mA, IOL = 12 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
R
Pull-up resistor
control
Digital input
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select either USB I/O
or GPIO function.
UDP output
UDP/Pxx
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected:
・ Full-speed, low-speed control
Differential
UDM/Pxx
Differential input
USB/GPIO select
H
When the GPIO is selected:
・ CMOS level output
UDM input
・ CMOS level hysteresis input
・ Standby mode control
UDM output
・ IOH = -20.5 mA, IOL = 18.5 mA
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 55 of 200
S6E2C Series
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ 5 V tolerant
P-ch
P-ch
Digital output
Digital output
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
I
・ IOH = -4 mA, IOL= 4 mA
・ Available to control of PZR
registers (pseudo-open drain
control)
N-ch
R
・ For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04856).
Pull-up resistor
control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
P-ch
P-ch
Digital output
・CMOS level output
・TTL level hysteresis input
・Pull-up resistor control
・Standby mode control
・ Pull-up resistor:
K
N-ch
Digital output
R
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 56 of 200
S6E2C Series
Type
Circuit
Remarks
・ CMOS level output
P-ch
P-ch
Digital output
Digital output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
L
approximately 50 kΩ
N-ch
・ IOH = -8 mA, IOL = 8 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Pull-up resistor
control
R
Digital input
Standby mode
control
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
Pull-up resistor
control
P-ch
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
P-ch
Digital output
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA (GPIO)
・ IOL = 20mA (Fast mode Plus)
・ Available to control of PZR
register (pseudo-open drain
control)
N
N-ch
N-ch
Digital output
・ For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04857).
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Fast mode
control
R
Digital input
Standby mode
control
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 57 of 200
S6E2C Series
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ 5 V tolerant
・ Pull-up resistor control
・ Pull-up resistor:
Pull-up resistor
control
P-ch
approximately 50 kΩ
P-ch
N-ch
Digital output
・ IOH = -4 mA, IOL= 4 mA
・ Available to control of PZR
register (pseudo-open drain
control)
O
・ For PZR registers, refer to GPIO
in the “FM4 Family Peripheral
Manual Main Part (MN709-
00001)”.
Digital output
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
R
Digital input
P-ch
Pull-up resistor
control
P-ch
N-ch
Digital output
X0A
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Pull-up resistor:
approximately 50 kΩ
Digital output
P
・ IOH = -4 mA, IOL= 4 mA
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
R
Digital input
Standby mode
control
OSC
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S6E2C Series Datasheet
Page 58 of 200
S6E2C Series
Type
Circuit
Remarks
It is possible to select the sub
oscillation/GPIO function.
Pull-up resistor
control
Digital output
P-ch
P-ch
X1A
When the sub oscillation
is selected:
・ Oscillation feedback resistor:
approximately 10 MΩ
N-ch
Digital output
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Pull-up resistor:
Q
R
Digital input
approximately 50 kΩ
Standby mode
control
OSC
・ IOH = -4 mA, IOL = 4 mA
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
RX
Standby mode
control
Clock input
Pull-up resistor
control
P-ch
・ CMOS level output
・ CMOS level hysteresis input
・ Analog output
P-ch
N-ch
Digital output
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
Digital output
R
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
(4.5 V to 5.5V)
R
・ IOH = -2 mA, IOL = 2 mA
(2.7 V to 4.5 V)
Digital input
Standby mode
control
Analog output
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S6E2C Series Datasheet
Page 59 of 200
S6E2C Series
Type
Circuit
Remarks
・CMOS level output
・(It is possible to select by port
drive capability. Select register
[PDSR])
P-ch
Pull-up resistor control
・CMOS level hysteresis input
・Pull-up resistor control
・Standby mode control
・ Pull-up resistor:
P-ch
N-ch
Digital output
S
approximately 50 kΩ
・IOH = -10 mA, IOL = 10 mA (PDSR
= 1)
Port Drive Select
・ IOH = -4 mA, IOL = 4 mA (PDSR =
0)
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
R
Digital input
Standby mode Control
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S6E2C Series Datasheet
Page 60 of 200
S6E2C Series
7. Handling Precautions
Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be
observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
7.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current
conditions at the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power-supply pin or ground pin.
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S6E2C Series
Latch-Up
Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection,
and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
7.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason, it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
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Page 62 of 200
S6E2C Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent this, do the following:
1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%.
4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in these aluminum laminate bags for storage.
5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock
loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
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S6E2C Series
7.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of static electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive gases, dust, or oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, including cosmic radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, flame
CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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Page 64 of 200
S6E2C Series
8. Handling Devices
Power-Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines,
however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total output current rating.
Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane, as this is expected to produce stable operation.
Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board.
Sub Crystal Oscillator
The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress
recommends a crystal oscillator that meets the following conditions:
◼ Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: approximately 6 pF to 7 pF
◼ Lead type
Load capacitance: approximately 6 pF to 7 pF
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Page 65 of 200
S6E2C Series
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.
X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set
X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
⚫ Example of Using an External Clock
Device
X0(X0A)
Set as external clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Handling When Using Multi-Function Serial Pin As I2C Pin
If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C
pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU
power off.
C Pin
Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and
the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that
meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A smoothing
capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance is
low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important to
prevent the device from erroneously switching to test mode as a result of noise.
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Page 66 of 200
S6E2C Series
Notes on Power-On
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
VBAT only Power-on is possible when VBAT and VCC turn Power-on and Hibernation control is setting and then VCC turns Power-
off. About Hibernation control, see Chapter 7-2: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part (002-04856).
Turning on: VBAT → VCC → USBVCC0
VBAT → VCC → USBVCC1
VBAT →VCC →ETHVCC
VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
ETHVCC → VCC → VBAT
USBVCC1 → VCC → VBAT
USBVCC0 → VCC → VBAT
Serial Communication
There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take
care to design the printed circuit board to minimize noise.
Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in Characteristics within the Product Line
The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the
product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If
you are switching to a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Pin Doubled as Debug Function
The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input.
Document Number: 002-04980 Rev. *E
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S6E2C Series
9. Memory Size
See Memory size in 2. Product Lineup to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
Reserved
0x41FF_FFFF
0x4008_1000
0x4008_0000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_D000
0x4006_C000
Programmable-CRC
CAN ch.3
GPIO
SD-Card I/F
Reserved
I2S
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
0xD000_0000
Cortex-M4 Private
Peripherals
Reserved
0x4006_7000
0x4006_6000
0x4006_4000
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
0x4003_E000
0x4003_D000
0x4003_C800
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
Reg. Area
Ether-Control-Reg.
Ether-MAC ch.0
CAN ch.1
External Device
Area
CAN ch.0
DSTC
DMAC
USB ch.1
0x6000_0000
USB ch.0
Reserved
EXT-bus I/F
Reserved
0x4400_0000
0x4200_0000
32 Mbytes
Bit band alias
I2S prescaler
Reserved
Peripheral Clock Gating
Low Speed CR Prescaler
Peripherals
Reserved
RTC/Port Ctrl
Watch Counter
CRC
0x4000_0000
MFS
0x2400_0000
0x2200_0000
32 Mbytes
Bit band alias
CAN prescaler
USB Clock ctrl
LVD/DS mode
Reserved
D/AC
DualFlash
Reserved
0x200F_0000
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
0x2004_8000
0x2004_0000
0x2003_8000
0x2000_0000
SRAM2
SRAM1
Reserved
Reserved
SRAM0
Reserved
0x1FFF_0000
0x0050_0000
0x4002_8000
0x4002_7000
A/DC
Security/CR Trim
QPRC
0x0040_0000
0x4002_6000
Base Timer
PPG
0x4002_5000
0x4002_4000
MainFlash
Reserved
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
MFT Unit2
MFT Unit1
MFT Unit0
0x0000_0000
Reserved
Dual Timer
Reserved
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
MainFlash I/F
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S6E2C Series Datasheet
Page 68 of 200
S6E2CxAH/J/L
S6E2Cx9H/J/L
S6E2Cx8H/J/L
0x2020_0000
0x2020_0000
0x2020_0000
E2C Series
Reserved
Reserved
Reserved
0x2004_8000
0x2004_0000
0x2003_8000
0x2004_8000
0x2004_0000
0x2003_8000
0x2004_8000
0x2004_0000
0x2003_8000
SRAM2
SRAM2
SRAM2
32 Kbytes
32 Kbytes
32 Kbytes
SRAM1
SRAM1
SRAM1
32 Kbytes
32 Kbytes
32 Kbytes
Reserved
Reserved
Reserved
0x2000_0000
0x2000_0000
0x1FFE_0000
0x2000_0000
0x1FFF_0000
SRAM0
SRAM0
64 Kbytes
SRAM0
128 Kbytes
192 Kbytes
0x1FFD_0000
0x0041_0000
Reserved
Reserved
Reserved
0041_0000
0041_0000
SA0-3(#1) (8KBx4)
SA0-3(#1) (8KBx4)
SA0-3(#1) (8KBx4)
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
SA3(#0) (8KB)
General purpose
CR trimming
Security
SA3(#0) (8KB)
General purpose
CR trimming
Security
SA3(#0) (8KB)
General purpose
CR trimming
Security
Reserved
Reserved
0x0020_0000
0x0010_0000
0x0000_0000
Reserved
SA9-23(#1) (64KBx15)
0018_0000
0x0010_0000
SA9-15(#1) (64KBx7)
SA8(#1) (32KB)
SA8(#1) (32KB)
SA4-7(#1) (8KBx4)
SA4-7(#1) (8KBx4)
0010_0000
SA9-23(#0) (64KBx15)
SA9-23(#0) (64KBx15)
SA9-23(#0) (64KBx15)
SA8(#0) (32KB)
SA8(#0) (32KB)
SA8(#0) (32KB)
SA4-7(#0) (8KBx4)
SA4-7(#0) (8KBx4)
SA4-7(#0) (8KBx4)
0x0000_0000
0x0000_0000
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S6E2C Series Datasheet
Page 69 of 200
S6E2CxAH/J/L
S6E2Cx9H/J/L
S6E2Cx8H/J/L
0x2020_0000
202000
2018_0000
2020_0
Reserved
SA9-23(#1) (64KBx15)
SA9-15(#1) (64KBx7)
Reserved
6E2C Series
SA8(#1) (32KB)
SA4-7(#1) (8KBx4)
SA0-3(#1) (8KBx4)
SA8(#1) (32KB)
SA4-7(#1) (8KBx4)
SA0-3(#1) (8KBx4)
0x2010_0000
0x200F_8000
0x2010_0000
0x200F_8000
0x2010_0000
0x200F_8000
SA0-3(#1) (8KBx4)
Reserved
Reserved
Reserved
0x2004_8000
0x2004_8000
0x2004_0000
0x2003_8000
0x2004_8000
0x2004_0000
0x2003_8000
SRAM2
32 Kbytes
SRAM1
SRAM2
32 Kbytes
SRAM1
SRAM2
32 Kbytes
SRAM1
0x2004_0000
0x2003_8000
32 Kbytes
32 Kbytes
32 Kbytes
Reserved
Reserved
Reserved
0x2000_0000
0x2000_0000
0x1FFE_0000
0x2000_0000
0x1FFF_0000
SRAM0
64 Kbytes
SRAM0
128 Kbytes
SRAM0
192 Kbytes
0x1FFD_0000
0x0041_0000
Reserved
Reserved
Reserved
Reserved
Reserved
0041_0000
0041_0000
Reserved
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_8000
0x0040_6000
0x0040_4000
0x0040_2000
0x0040_0000
SA3(#0) (8KB)
General purpose
CR trimming / HTM
Security
SA3(#0) (8KB)
General purpose
CR trimming / HTM
Security
SA3(#0) (8KB)
General purpose
CR trimming / HTM
Security
Reserved
Reserved
Reserved
0x0010_0000
0x0000_0000
0010_0000
0x0000_0000
0010_0000
0x0000_0000
SA9-23(#0) (64KBx15)
SA9-23(#0) (64KBx15)
SA9-23(#0) (64KBx15)
SA8(#0) (32KB)
SA8(#0) (32KB)
SA8(#0) (32KB)
SA4-7(#0) (8KBx4)
SA4-7(#0) (8KBx4)
SA4-7(#0) (8KBx4)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 70 of 200
S6E2CxAH
S6E2CxAJ
S6E2CxAL
0xD000_0000
0xC000_0000
0xD000_0000
0xC000_0000
0xD000_0000
0xC000_0000
Hi-Speed Quad SPI
256 Mbytes
Hi-Speed Quad SPI
256 Mbytes
6E2C Series
Reserved
Reserved
Reserved
0x8000_0000
0x8000_0000
0x7000_0000
0x6000_0000
0x8000_0000
0x7000_0000
0x6000_0000
SDRAM
256 Mbytes
SDRAM
256 Mbytes
0x7000_0000
0x6000_0000
SRAM
SRAM
SRAM
/NOR Flash Memory
/NAND Flash Memory
256 Mbytes
/NOR Flash Memory
/NAND Flash Memory
256 Mbytes
/NOR Flash Memory
/NAND Flash Memory
256 Mbytes
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
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S6E2C Series
Peripheral Address Map
Start Address
End Address
Bus
AHB
Peripherals
MainFlash I/F register
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
Reserved
Clock/reset control
Hardware watchdog timer
Software watchdog timer
Reserved
APB0
Dual-timer
Reserved
Multi-Function Timer unit 0
0x4002_1000
0x4002_2000
0x4002_3000
0x4002_1FFF
0x4002_2FFF
0x4002_3FFF
Multi-Function Timer unit 1
Multi-Function Timer unit 1
Reserved
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
PPG
Base timer
APB1
Quadrature position/revolution counter
A/D converter
Reserved
Internal CR trimming
Reserved
External interrupt controller
Interrupt request batch-read function
Reserved
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
D/A converter
Reserved
Low voltage detector
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
Deep standby mode Controller
USB clock generator
CAN prescaler
APB2
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
Multi-function serial interface
CRC
Watch counter
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4003_D000
0x4003_E000
0x4003_F000
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_CFFF
0x4003_DFFF
0x4003_EFFF
0x4003_FFFF
RTC/port control
Low-speed CR prescaler
Peripheral clock gating
Reserved
I2S prescaler
Reserved
External memory interface
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 72 of 200
S6E2C Series
Start Address
End Address
Bus
Peripherals
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4006_6000
0x4006_7000
0x4006_C000
0x4006_D000
0x4006_E000
0x4006_F000
0x4007_0000
0x4008_0000
0x4008_1000
0x200E_0000
0xD000_0000
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x4006_5FFF
0x4006_6FFF
0x4006_BFFF
0x4006_CFFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x4007_FFFF
0x4008_0FFF
0x41FF_FFFF
0x200E_FFFF
0xDFFF_FFFF
USB ch 0
USB ch 1
DMAC register
DSTC register
CAN ch 0
CAN ch 1
Ethernet-MAC ch 0
Ethernet-MAC setting register
Reserved
AHB
I2S
Reserved
SD card I/F
GPIO
CAN-FD (CAN ch 2)
Programmable-CRC
Reserved
Workflash I/F register
High-speed quad SPI control register
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 73 of 200
S6E2C Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings:
◼ INITX = 0
This is the period when the INITX pin is at the L level.
◼ INITX = 1
This is the period when the INITX pin is at the H level.
◼ SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is
set to 0.
◼ SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is
set to 1.
◼ Input enabled
Indicates that the input function can be used.
◼ Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
◼ Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
◼ Setting disabled
Indicates that the setting is disabled.
◼ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
◼ Analog input is enabled
Indicates that the analog input is enabled.
◼ Trace output
Indicates that the trace function can be used.
◼ GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
◼ Setting prohibition
Prohibition of a setting by specification limitation
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 74 of 200
S6E2C Series
List of Pin Behavior by Mode State
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Internal
Reset
State
Deep
Standby
mode State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
GPIO
Hi-
Hi-
Maintain
previous
state
Maintain
previous
state
selected,
internal
input fixed
at 0
GPIO
selected
Setting Setting Setting
disabled disabled disabled
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
GPIO
selected
Main crystal
oscillator
input pin/
external
main clock
input
A
Input
Input
Input
Input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
Enabled
enabled enabled enabled enabled
selected
GPIO
selected,
internal
input fixed
at 0
Hi-
Hi-
Maintain
Setting Setting Setting
previous
Maintain
previous
state
GPIO
selected
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
GPIO
selected
disabled disabled disabled
state
External
main clock
input
Hi-
Hi-
Maintain
Setting Setting Setting
previous
Maintain
previous
state
Maintain
previous
state
Maintain
previous
State
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
disabled disabled disabled
state
B
selected
Hi-Z/
internal
input
fixed
at 0/
or input
enable
Hi-Z/
internal internal
input
fixed
at 0
Hi-Z/
Main crystal
oscillator
output pin
Maintain previous state while oscillator active/
When oscillation stops1, it will be Hi-Z/
Internal input fixed at 0
input
fixed
at 0
Pull-up/ Pull-up/ Pull-up/ Pull-up/
input Input Input Input
enabled enabled enabled enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
INITX
input pin
C
D
Mode
input pin
Input
Input
Input
Input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
enabled enabled enabled enabled
Mode
input pin
Input Input Input Input
enabled enabled enabled enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/
input
enabled
Input
enabled
Input
enabled
Hi-Z/
input
enabled
Input
enabled
E
Maintain
Setting Setting Setting
previous
GPIO
selected
GPIO
selected
GPIO
selected
disabled disabled disabled
state
1
Oscillation is stopped at Sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode,
and Deep Standby Stop mode.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 75 of 200
S6E2C Series
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Internal
Reset
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Deep
Standby
mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Maintain
previous
state
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
Maintain
previous
state
SPL=0
SPL=1
NMIX
selected
Setting Setting Setting
disabled disabled disabled
Hi-Z/
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Resource
other than
above
F
Hi-Z/
internal
input fixed
at 0
Hi-Z/
input
Hi-Z/
input
GPIO
selected
enabled
Hi-Z
Hi-Z
selected
GPIO
selected
enabled enabled
Pull-up/ Pull-up/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
input
input
enabled enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected,
internal
input fixed
at 0
G
Hi-Z/
internal
input fixed
at 0
Hi-Z/
internal
input fixed
at 0
GPIO
selected
Setting Setting Setting
disabled disabled disabled
GPIO
selected
Pull-up/ Pull-up/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
input
input
enabled enabled
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
selected
GPIO
GPIO
selected,
internal
input fixed
at 0
H
Hi-
Hi-
Setting Setting Setting
disabled disabled disabled
Z/Internal
input fixed
at 0
Z/Internal
input fixed
at 0
GPIO
selected
selected
GPIO
selected,
internal
input fixed
at 0
Resource
selected
Hi-
Hi-
Hi-Z/
input
enabled enabled
Hi-Z/
input
Maintain
previous
state
Maintain
previous
state
Z/Internal
input fixed
at 0
Z/internal
input fixed
at 0
GPIO
selected
I
Hi-Z
Hi-Z
GPIO
selected
Analog
output
selected
2
3
GPIO
selected,
internal
input fixed
at 0
External
interrupt
enable
selected
Resource
other than
above
Hi-
Maintain
previous
state
Hi-Z/
input
enabled enabled
Hi-Z/
input
Maintain
previous
state
Z/internal
input fixed
at 0
GPIO
selected
J
Maintain
previous
state
Hi-
Z/internal
input fixed
at 0
selected
2
3
Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode.
Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode..
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 76 of 200
S6E2C Series
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Internal
Reset
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Deep
Standby
mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
GPIO
selected
External
interrupt
enable
selected
Resource
other than
above
Maintain
previous
state
Setting Setting Setting
disabled disabled disabled
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Z/internal
input fixed
at 0
GPIO
selected
K
Hi-
Hi-Z/
input
enabled enabled
Hi-Z/
input
Z/internal
input fixed
at 0
Hi-Z
Hi-Z
selected
GPIO
selected
Hi-Z/ Hi-Z/
internal internal internal
Hi-Z/
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal input
fixed
input
fixed at fixed at
0/ 0/
analog analog
input input
input
input
fixed
at 0/
analog
input
Analog
input
selected
input fixed input fixed input fixed input fixed
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
enabled
enabled
enabled
enabled
enabled
L
enabled enabled enabled
Resource
other than
above
selected
GPIO
GPIO
selected,
internal
input fixed
at 0
Hi-
Hi-
Maintain
previous
state
Maintain
previous
state
Setting Setting Setting
disabled disabled disabled
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
GPIO
selected
selected
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal input
fixed
internal internal internal
input
fixed
at 0/
analog analog
input input
input
fixed
at 0/
input
fixed
at 0/
analog
input
Analog
input
input fixed input fixed input fixed input fixed
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
selected
enabled
enabled
enabled
enabled
enabled
enabled enabled enabled
External
interrupt
enable
selected
Resource
M
Maintain
previous
state
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Setting Setting Setting
Z/internal
input fixed
at 0
GPIO
selected
other than disabled disabled disabled
Hi-
above
selected
GPIO
Z/internal
input fixed
at 0
selected
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 77 of 200
S6E2C Series
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Internal
Reset
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Deep
Standby
mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
Hi-Z/
‐
Hi-Z/
‐
Hi-Z/
SPL=0
SPL=1
SPL=0
SPL=1
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal input
fixed
internal internal internal
internal
internal
internal
internal
input
fixed
at0/
input
fixed
at 0/
input
fixed
at 0/
analog
input
Analog
input
selected
input fixed input fixed input fixed input fixed
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
analog analog
input input
enabled
enabled
enabled
enabled
enabled
enabled enabled enabled
N
Trace
selected
Resource
other than
above
selected
GPIO
Trace
output
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Setting Setting Setting
disabled disabled disabled
Z/internal
input fixed
at 0
GPIO
selected
Hi-
Z/internal
input fixed
at 0
selected
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal
Hi-Z/
internal input
fixed
internal internal internal
input
fixed
at 0/
analog analog
input input
input
fixed
at 0/
input
fixed
at 0/
analog
input
Analog
input
input fixed input fixed input fixed input fixed
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
selected
enabled
enabled
enabled
enabled
enabled
enabled enabled enabled
Trace
Trace
selected
output
O
External
interrupt
enable
Maintain
previous
state
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Setting Setting Setting
disabled disabled disabled
Z/internal
input fixed
at 0
GPIO
selected
selected
Resource
other than
above
selected
GPIO
Hi-
Z/internal
input fixed
at 0
selected
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 78 of 200
S6E2C Series
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Internal
Reset
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Deep
Standby
mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
Hi-Z/
‐
Hi-Z/
‐
Hi-Z/
SPL=0
SPL=1
SPL=0
SPL=1
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal input
fixed
internal internal internal
internal
internal
internal
internal
input
fixed at fixed at
0/ 0/
analog analog
input input
input
input
fixed
at 0/
analog
input
Analog
input
selected
input fixed input fixed input fixed input fixed
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
enabled
enabled
enabled
enabled
enabled
enabled enabled enabled
Hi-Z/
WKUP
input
Maintain
previous
state
WKUP
input
enabled
P
WKUP
enabled
enabled
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
Setting Setting Setting
disabled disabled disabled
GPIO
selected
GPIO
selected,
internal
input fixed
at 0
Hi-
Hi-
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
selected
GPIO
selected
Hi-Z/
WKUP
input
WKUP
input
enabled
WKUP
enabled
WKUP input
enabled
Maintain
previous
state
enabled
Setting Setting Setting
disabled disabled disabled
External
interrupt
enable
Maintain
previous
state
Maintain
previous
state
selected
Q
GPIO
selected,
internal
input fixed
at 0
Hi-
Resource
other than
above
Z/internal
input fixed
at 0
GPIO
selected
Hi-
Hi-Z/
input
enabled enabled
Hi-Z/
input
Z/internal
input fixed
at 0
Hi-Z
Hi-Z
selected
GPIO
selected
GPIO
selected,
internal
input fixed
at 0
Hi-
Hi-
Hi-Z/
input
Hi-Z/
input
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Z/internal
input fixed
at 0
Z/internal
input fixed
at 0
GPIO
selected
enabled enabled
Hi-Z at
trans-
mission/
input
Hi-Z at
trans-
mission/
input
enabled/
internal
input fixed input fixed
Hi-Z at
trans-
mission/
input
enabled/
internal
R
Hi-Z/
input
enabled
Hi-Z/
input
enabled
Setting Setting Setting enabled/
disabled disabled disabled internal
Hi-Z/
input enabled
USB I/O pin
input
fixed
at 0 at
reception
at 0 at
reception
at 0 at
reception
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 79 of 200
S6E2C Series
Power-On
Reset or
Low-
Voltage
Detection
State
Run
mode
or Sleep
mode
State
Device
Internal
Reset
Return from
INITX
Input
State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Deep
Standby
mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
Power
Supply
Stable
INITX=1
-
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
Maintain
previous
state
Ethernet I/O Setting Setting Setting
selected4
disabled disabled disabled
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
Z/internal
input fixed
at "0
GPIO
selected
V
Hi-
Hi-Z/
input
enabled enabled
Hi-Z/
input
Z/internal
input fixed
at 0
selected
Hi-Z
GPIO
selected
Ethernet
input/output
selected4
Maintain
previous
state
Setting Setting Setting
disabled disabled disabled
External
interrupt
enable
selected
Resource
other than
above
GPIO
selected,
internal
input fixed
at 0
Hi-
Maintain
previous
state
Maintain
previous
state
Z/internal
input fixed
at 0
GPIO
selected
W
Hi-
Hi-Z/
input
Hi-Z/
input
Z/internal
input fixed
at 0
Hi-Z
selected
GPIO
enabled enabled
selected
4
It shows the case selected by EPFR14.E_SPLC register
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 80 of 200
S6E2C Series
List of VBAT Domain Pin Status
Run
Device mode
Internal or
Return
from
Return
Deep Standby
RTC mode or
VBAT
RTC
from
VBAT
RTC
Power- INITX
Timer mode,
RTC mode, or
Stop mode State
Deep
on
Input
State
Reset Sleep
Deep Standby Standby mode
Stop mode state mode
State
reset5
State
mode
State
State
mode
State
Function
Group
Power
Power Power Power
Supply Supply Supply
Stable Stable Stable
Power
Supply
Stable
Supply Power Supply
Power Supply
Stable
Power Supply
Stable
Unstabl
Stable
e
‐
‐
INITX=0 INITX=1 INITX=1
INITX=1
INITX=1
INITX=1
-
-
-
-
-
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting
previous previous previous previous previous previous previous previous prohibitio
GPIO
selected disabled
Setting
-
state
state
state
state
state
state
state
state
n
Sub
crystal
S
oscillator
input pin/ Input
Maintain Maintain
previous previous
Input
Input
Input
Input
Input
Input
Input
Input
external enabled enabled enabled enabled enabled enabled enabled enabled enabled
sub clock
input
state
state
selected
Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting
previous previous previous previous previous previous previous previous prohibitio
GPIO
selected disabled
Setting
-
state
state
state
state
state
state
state
state
n
External
Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain
previous previous previous previous previous previous previous previous previous previous
sub clock Setting
input disabled
selected
state
state
state
state
state
state
state
state
state
state
T
Hi-Z/
internal
Maintain Maintain Maintain Maintain
previous previous previous previous
Sub
crystal
input Maintain Maintain Maintain state/
state/
When
state/
When
state/ Maintain Maintain Maintain
When previous previous previous
oscillator fixed at previous previous previous When
output
pin
0/
or input
enable
state
state
state oscillation oscillation oscillation oscillation state
state
state
stops,
stops,
stops,
stops,
Hi-Z6
Hi-Z6
Hi-Z6
Hi-Z6
Resource
selected
Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain
Hi-Z previous previous previous previous previous previous previous previous previous previous
state state state state state state state state state state
U
GPIO
selected
5
6
When VBAT and VCC power on.
When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state. When the SOSCNTL bit in the
WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop mode.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 81 of 200
S6E2C Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
V
Remarks
Min
Max
Power supply voltage7,8
VCC
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
Power supply voltage (for USB)7,9
USBVCC
0
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
,
Power supply voltage (for USB) 7 9
USBVCC
1
V
Power supply voltage (for Ethernet-MAC) 7, 10
ETHVCC
VBAT
V
7 ,11
Power supply voltage (VBAT)
V
Analog power supply voltage 7, 12
AVCC
V
7 ,12
Analog reference voltage
AVRH
V
VCC + 0.5
(≤ 6.5V)
Except for USB and
Ethernet-MAC pin
V
USBVCC0 + 0.5
(≤ 6.5V)
USBVCC1 + 0.5
(≤ 6.5V)
VSS - 0.5
VSS - 0.5
V
V
USB ch 0 pin
USB ch 1 pin
Input voltage 7
VI
ETHVCC + 0.5
(≤ 6.5V)
Ethernet-MAC Pin
5V tolerant
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
VSS + 6.5
AVCC + 0.5
(≤ 6.5V)
Analog pin input voltage 7
Output voltage 7
VIA
VO
VCC + 0.5
(≤ 6.5V)
VSS - 0.5
V
4 mA type
8 mA type
mA 10 mA type
12 mA type
mA I2C Fm+
4 mA type
8 mA type
mA 10 mA type
10
20
20
20
22.4
4
8
mA
mA
L level maximum output current13
IOL
-
mA
mA
mA
L level average output current14
IOLAV
-
10
12 mA type
12
20
mA
mA I2C Fm+
L level total maximum output current
L level total maximum output current
∑IOL
∑IOLAV
-
-
100
50
mA
mA
15
4 mA type
mA 8 mA type
10 mA type
mA 12 mA type
- 10
-20
mA
H level maximum output current 13
IOH
-
- 20
- 20
mA
7
These parameters are based on the condition that VSS = AVSS = 0.0V.
VCC must not drop below VSS - 0.5V.
USBVCC0, USBVCC1 must not drop below VSS - 0.5V.
ETHVCC must not drop below VSS - 0.5V.
VBAT must not drop below VSS - 0.5V.
Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period.
The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms period.
8
9
10
11
12
13
14
15
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 82 of 200
S6E2C Series
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
- 4
mA 4 mA type
8 mA type
10 mA type
mA 12 mA type
-8
mA
mA
H level average output current 14
IOHAV
-
- 10
- 12
- 100
- 50
200
+ 150
H level total maximum output current
H level total average output current 15
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
mA
mA
mW
°C
Storage temperature
TSTG
- 55
WARNING:
− Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage,
current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 83 of 200
S6E2C Series
12.2 Recommended Operating Conditions
Value
Parameter
Power supply voltage
Symbol
Conditions
Unit
Remarks
Min
2.7
Max
16
VCC
-
5.5
V
When P81/UDP0 and
P80/UDM0 pins are
used as USB (UDP0,
UDM0)
When P81/UDP0 and
P80/UDM0 pins are
used as GPIO (P81,
P80)
When P83/UDP1 and
P82/UDM1 pins are
used as USB (UDP1,
UDM1)
When P83/UDP1 and
P82/UDM1 pins are
used as GPIO (P83,
P82)
3.6
(≤VCC
3.0
2.7
3.0
)
)
)
Power supply voltage (for USB ch 0)
USBVCC
0
-
-
V
V
5.5
(≤VCC
3.6
(≤VCC
Power supply voltage (for USB ch 1)
USBVCC1
5.5
(≤VCC
2.7
3.0
4.5
)
)
)
When the pins in
Ethernet-MAC Pins,
except the
P6E/ADTG_5/SCK4_1/I
C23_1/INT29_0/E_PPS
pin, are used
3.6
(≤VCC
5.5
(≤VCC
as Ethernet-MAC pins
When the pins in
Ethernet-MAC Pins,
except the
P6E/ADTG_5/SCK4_1/I
C23_1/INT29_0/E_PPS
pin, are used
Power supply voltage (for Ethernet-
MAC)
ETHVCC
-
V
5.5
(≤VCC
2.7
)
as Ethernet-MAC pins
Power supply voltage (VBAT)
Analog power supply voltage
VBAT
AVCC
AVRH
AVRL
TJ
-
-
-
-
-
-
1.65
2.7
17
5.5
5.5
AVCC
AVSS
V
V
V
V
°C
°C
AVCC = VCC
Analog reference voltage
AVSS
- 40
-40
Junction temperature
Operating
+ 125
18
temperature
Ambient temperature
TA
16
17
For the voltage range between VCC(min) and the low voltage detection reset (VDH), the MCU must be clocked from either the High-speed CR or the low-speed CR.
The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5 12-bit A/D Converter for the details.
18
The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the
junction temperature (TJ).
The calculation formula of the ambient temperature (TA) is:
TA (Max) = TJ(Max) - Pd(Max) × θJA
Pd:
θJA
Power dissipation (W)
:
Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL
IOH
:
:
L level output current
H level output current
VOL
:
L level output voltage
H level output voltage
VOH
:
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 84 of 200
S6E2C Series
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Thermal
Maximum Permissible Power
(mW)
Printed Circuit Resistance
Package
Board
θja
(°C/W)
TA = +85 °C
TA = +105 °C
Single-layered
both sides
4 layers
Single-layered
both sides
4 layers
Single-layered
both sides
4 layers
Single-layered
both sides
4 layers
48
33
45
31
46
32
-
833
1212
889
1290
870
1250
-
417
606
444
645
435
625
-
LQS144
(0.5-mm pitch)
LQP176
(0.5-mm pitch)
LQQ216
(0.4-mm pitch)
LBE192
(0.8-mm pitch)
35
1143
571
WARNING:
− The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device.
All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges
may adversely affect reliability and could result in device failure.
− No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 85 of 200
S6E2C Series
Ethernet-MAC Pins
Pin Name
Except For
Ethernet-MAC
Function
Power
Supply
Type
Ethernet-MAC
Function
19
P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS
PC0/E_RXER
PC1/TIOB6_0/E_RX03
PC2/TIOA6_0/E_RX02
PC3/TIOB7_0/E_RX01
E_PPS
P6E/ADTG_5/SCK4_1/IC23_1/INT29_0
PC0
PC1/TIOB6_0
PC2/TIOA6_0
PC3/TIOB7_0
VCC
E_RXER
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
E_MDIO
E_MDC
E_RXCK_REFCK
E_COL
E_CRS
E_COUT
E_TCK
PC4/TIOA7_0/E_RX00
PC4/TIOA7_0
PC5/TIOB14_0/E_RXDV
PC6/TIOA14_0/E_MDIO
PC7/INT13_0/E_MDC/CROUT_1
PC8/E_RXCK_REFCK
PC5/TIOB14_0
PC6/TIOA14_0
PC7/INT13_0/CROUT_1
PC8
PC9/TIOB15_0
PCA/TIOA15_0
PCB/INT28_0
PC9/TIOB15_0/E_COL
ETHVCC
PCA/TIOA15_0/E_CRS
PCB/INT28_0/E_COUT
PCC/E_TCK
PCC
PCD/SOT4_1/INT14_0/E_TXER
PCE/SIN4_1/INT15_0/E_TX03
PCF/RTS4_1/INT12_0/E_TX02
PD0/INT30_1/E_TX01
PD1/INT31_1/E_TX00
PD2/CTS4_1/FRCK2_1/E_TXEN
E_TXER
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
PCD/SOT4_1/INT14_0
PCE/SIN4_1/INT15_0
PCF/RTS4_1/INT12_0
PD0/INT30_1
PD1/INT31_1
PD2/CTS4_1/FRCK2_1
19
It is used to confirm the PTP counter cycle in Ethernet-MAC by waveforms.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 86 of 200
S6E2C Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL
IOH
VOL
VOH
:
L level output current
H level output current
L level output voltage
H level output voltage
:
:
:
ICC is the current drawn by the device.
It can be analyzed as follows.
ICC = ICC (INT) + ΣICC (IO)
ICC (INT): Current drawn by internal logic and memory, etc. through the regulator
ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "12.3. DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For ICC (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC (IO) =
(CINT + CEXT) × VCC × fSW
CINT
CEXT
fSW
:
Pin internal load capacitance
External load capacitance of output pin
Pin switching frequency
:
:
Parameter
Symbol
Conditions
Capacitance Value
4 mA type
8 mA type
12 mA type
1.93 pF
3.45 pF
3.42 pF
Pin internal load
capacitance
CINT
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself:
Measure current value ICC (Typ) at normal temperature (+25°C).
Add maximum leakage current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC (Typ) + ICC (leak_max)
Parameter
Symbol
Conditions
TJ = +125 °C
TJ = +105 °C
TJ = +85 °C
Current Value
79.2 mA
Maximum leakage
current at operating
ICC (leak_max)
39.4 mA
26.5 mA
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 87 of 200
S6E2C Series
Current Explanation Diagram
Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC=ICC (INT)＋ΣICC (IO)
VCC
A
ICC
Chip
ΣICC (IO)
ICC (INT)
A
IOL
Regulator
VOL
V
Flash
VOH
A
IOH
V
Logic
RAM
CEXT
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 88 of 200
S6E2C Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-1 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory
(Flash Accelerator Mode and Trace Buffer Function Enabled)
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency20
Unit
Remarks
Typ21
Max22
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
117
113
106
95
86
73
61
50
39
27
16
8.7
6.4
71
68
64
58
52
44
38
31
24
17
10
6.3
5.0
224
219
211
197
186
169
155
140
126
112
97
88.9
86.1
168
165
159
151
144
134
126
117
109
100
91
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25
27
25
27
26
When all peripheral
clocks are on
Normal
Power
supply
current
operation23
4 MHz
ICC
VCC
24
,
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
(PLL)
26
mA When all peripheral
clocks are off
mA
mA
mA
mA
mA
mA
86.1
84.5
4 MHz
20
21
22
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
TA = +25 °C, VCC = 3.3V
TJ = +125 °C, VCC = 5.5V
23Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.
24
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1)
When all ports are fixed
25
26
27
When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 89 of 200
S6E2C Series
Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled)
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency28
Unit
Remarks
Typ29
Max30
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
128
123
116
102
93
79
67
54
42
30
17
9.2
6.7
74
71
67
59
53
45
39
32
25
18
11
6.5
5.1
236
230
221
205
193
175
161
145
130
115
99
90.0
86.9
170
167
162
152
145
135
127
118
110
101
92
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
33
35
33
35
34
When all peripheral
clocks are on
Normal
operation31
Power
supply
current
4 MHz
ICC
VCC
32
,
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
(PLL)
34
When all peripheral
clocks are off
86.8
85.0
4 MHz
28
29
30
31
32
33
34
35
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
TA = +25 °C, VCC = 3.3V
TJ = +125 °C, VCC = 5.5V
With data access to a MainFlash memory.
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0)
When all ports are fixed
When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 90 of 200
S6E2C Series
Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency36
Unit
Remarks
Typ37
Max38
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
71
62
51
40
29
17
13
8.4
46
41
34
27
20
12
9.4
6.5
161
150
138
125
112
98
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
42
41
When all peripheral
clocks are on
93
Normal
Power
supply
current
4 MHz
88.5
132
125
118
110
102
93
operation
ICC
VCC
39 40
,
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
(PLL)
42
41
When all peripheral
clocks are off
89.7
86.4
4 MHz
36
37
38
39
40
41
42
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
TA = +25 °C, VCC = 3.3 V
TJ = +125 °C, VCC = 5.5 V
With data access to a MainFlash memory.
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
When all ports are fixed
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 91 of 200
S6E2C Series
Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other than PLL), Code with Data Accessing
Running from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency43
Unit
Remarks
Typ44
Max45
49
mA
4.7
84.9
When all peripheral
clocks are on
Normal
operation
48
46 47
4 MHz
,
(main
49
oscillation)
mA
3.9
3.0
83.8
83.2
When all peripheral
clocks are off
49
Normal
mA When all peripheral
clocks are on
operation
46
48
4 MHz
(built-in
High-speed
CR)
49
When all peripheral
clocks are off
2.1
82.0
mA
Power
supply
current
ICC
VCC
49
Normal
0.78
0.77
0.81
0.78
80.37
80.36
80.39
80.38
mA When all peripheral
clocks are on
operation
46 50
48
,
32 kHz
49
(sub
oscillation)
mA When all peripheral
clocks are off
49
Normal
mA When all peripheral
clocks are on
operation
46
48
100 kHz
49
(built-in
low-speed CR)
mA When all peripheral
clocks are off
43
44
45
46
47
48
49
50
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
TA = +25 °C, VCC = 3.3V
TJ = +125 °C, VCC = 5.5V
With data access to a MainFlash memory.
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
When all ports are fixed
When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 92 of 200
S6E2C Series
Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 =
HCLK/2
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency51
Unit
Remarks
Typ52
Max53
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
88
85
80
72
65
55
47
38
30
21
12
7.4
5.8
44
42
40
36
33
28
24
20
16
12
7.6
5.2
4.4
188
184
178
164
156
144
134
124
114
104
93
87.2
85.2
134
132
129
123
119
113
108
103
98
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
55
When all peripheral
clocks are on
Power
supply
current
Sleep
operation54
(PLL)
4 MHz
ICCS
VCC
200 MHz
192 MHz
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
55
When all peripheral
clocks are off
93
87.6
84.7
83.7
4 MHz
51
52
53
54
55
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
TA = +25°C, VCC = 3.3V
TJ = +125°C, VCC = 5.5V
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When all ports are fixed
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 93 of 200
S6E2C Series
Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency56
Unit
Remarks
Typ57
Max58
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
45
38
31
24
18
11
8.6
6.3
20
18
15
12
9.1
6.5
5.5
4.6
130
122
114
106
99
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
60
When all peripheral
clocks are on
91
88.3
85.7
103
99
96
93
89.3
86.1
84.9
83.8
Power
supply
current
Sleep
operation59
(PLL)
4 MHz
ICCS
VCC
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
60
When all peripheral
clocks are off
4 MHz
56
57
58
59
60
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
TA = +25°C, VCC = 3.3V
TJ = +125°C, VCC = 5.5V
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When all ports are fixed
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 94 of 200
S6E2C Series
Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency61
Unit
Remarks
Typ62
Max63
65
mA
3.4
82.6
When all peripheral
clocks are on
Sleep
operation64
(main
4 MHz
65
oscillation)
mA
mA
2.5
81.7
When all peripheral
clocks are off
65
Sleep
operation
(built-in
When all peripheral
2.5
1.7
81.7
80.9
clocks are on
4 MHz
32 kHz
100 kHz
65
Power
supply
current
mA When all peripheral
High-speed CR)
ICCS
VCC
clocks are off
65
0.75
0.74
0.79
0.76
79.97
79.96
80.01
79.98
mA When all peripheral
Sleep
clocks are on
operation66
65
(sub oscillation)
mA When all peripheral
clocks are off
65
Sleep
operation
(built-in
When all peripheral
mA
mA
clocks are on
65
When all peripheral
clocks are off
low-speed CR)
61
62
63
64
65
66
Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
TA = +25 °C, VCC = 3.3V
TJ = +125 °C, VCC = 5.5V
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When all ports are fixed.
When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 95 of 200
S6E2C Series
Table 12-8 Typical and Maximum Current Consumption in Stop Mode, TIMER Mode and RTC Mode
Value
Pin
Name
Parameter Symbol
Conditions
Frequency
Unit
Remarks
Typ67
Max68
69 70
,
0.56
3.01
mA
TA = +25°C
69 70
,
Stop mode
-
-
-
27.03
39.92
mA
mA
ICCH
TA = +85°C
69 70
,
TA = +105°C
69 70
,
1.40
3.85
27.87
40.76
mA
mA
mA
TA = +25°C
Timer mode71
(main oscillation)
69 70
,
4 MHz
-
-
TA = +85°C
69 70
,
TA = +105°C
69 70
,
0.95
3.40
27.42
40.31
3.02
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
TA = +25°C
Timer mode
(built-in
High-speed CR)
69 70
,
-
4 MHz
32 kHz
100 kHz
32 kHz
TA = +85°C
Power
69 70
,
supply
current
VCC
-
ICCT
TA = +105°C
69 70
,
0.57
TA = +25°C
69 70
Timer mode72
(sub oscillation)
,
-
27.04
39.93
3.03
TA = +85°C
69 70
,
-
TA = +105°C
69 70
,
0.58
TA = +25°C
Timer mode
(built-in
low-speed CR)
69 70
,
-
27.05
39.94
3.02
TA = +85°C
69 70
,
-
TA = +105°C
69 70
,
0.57
TA = +25°C
69 70
RTC mode71
(sub oscillation)
,
-
-
27.04
39.93
ICCR
TA = +85°C
69 70
,
TA = +105°C
67
68
69
70
71
72
VCC = 3.3V
VCC = 5.5V
When all ports are fixed
When LVD is off
When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit)
When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 96 of 200
S6E2C Series
Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency
Unit
Remarks
Typ73
Max74
75 76
,
96
248
μA
TA = +25°C
Deep standby
Stop mode
(When RAM
is off)
75 76
,
-
-
3009
3889
259
μA
μA
μA
μA
μA
TA = +85°C
75 76
,
-
TA = +105°C
ICCHD
75 76
,
106
TA = +25°C
Deep standby
Stop mode
(When RAM
is on)
75 76
,
-
-
-
3020
3900
TA = +85°C
75 76
,
TA = +105°C
VCC
75 76
,
96
-
248
3009
3889
μA
μA
μA
TA = +25°C
Deep standby
RTC mode
(When RAM
is off)
75 76
,
TA = +85°C
75 76
Power
supply
current
,
-
TA = +105°C
32 kHz
ICCRD
75 76
,
106
259
3020
3900
0.1
μA
μA
μA
μA
μA
μA
μA
μA
μA
TA = +25°C
Deep standby
RTC mode
(When RAM
is on)
75 76
,
-
TA = +85°C
75 76
,
-
TA = +105°C
75 76 78
,
,
0.0058
TA = +25°C
75 76 78
,
,
RTC stop77
-
1.4
TA = +85°C
75 76 78
,
,
-
1.0
-
3.3
TA = +105°C
VBAT
-
ICCVBAT
75 76
,
1.8
TA = +25°C
75 76
RTC
,
3.2
operation77
TA = +85°C
75 76
,
-
5.1
TA = +105°C
73
74
75
76
77
78
VCC = 3.3 V
VCC = 5.5 V
When all ports are fixed
When LVD is off
In the case of setting RTC after VCC power on.
When sub oscillation is off
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 97 of 200
S6E2C Series
Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/Erase
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Low-voltage
detection
circuit (LVD)
power supply
current
For occurrence of
interrupt
ICCLVD
At operation
-
4
7
μA
When programming
or erase in flash
memory, Flash
Memory Write/Erase
current (ICCFLASH)
is added to the
VCC
MainFlash
memory
write/erase
At
ICCFLASH
-
13.4
15.9
mA
write/erase
current
Power supply
current (ICC).
Peripheral Current Dissipation
Frequency (MHz)
Clock
Peripheral
System
Unit
Unit
Remarks
50
100
200
GPIO
DMAC
All ports
0.39
0.99
0.73
0.25
0.74
0.06
0.77
0.48
1.85
0.51
0.48
0.05
0.21
0.81
1.56
3.82
2.86
0.97
2.90
0.16
2.95
1.89
7.20
1.99
1.49
0.22
0.83
-
1.97
1.49
0.48
1.47
0.08
1.50
0.95
3.63
1.02
0.97
0.10
0.42
DSTC
-
External bus I/F
SD card I/F
-
-
CAN
1 ch
HCLK
mA
CAN-FD
1 ch
USB
Ethernet-MAC
I2S
1 ch
-
-
High-speed Quad SPI
Programmable CRC
Base timer
-
-
4 ch
Multi-functional
timer/PPG
Quadrature
position/revolution
counter
1 unit/4 ch
1 unit
0.83
0.07
1.65
0.13
3.25
0.27
PCLK1
PCLK2
mA
mA
A/D converter
1 unit
1 ch
0.31
0.41
0.60
0.81
1.17
-
Multi-function serial
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 98 of 200
S6E2C Series
12.3.2 Pin Characteristics
(VCC = USBVCC0 = USBVCC1 = ETHVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
V
Remarks
Min
VCC×0.8
Typ
Max
VCC + 0.3
CMOS hysteresis
input pin, MD0,
MD1
-
-
ETHVCC×0.8
-
ETHVCC + 0.3
V
H level
input
voltage
(hysteresis
input)
V
V
CC >3.0V,
CC ≤ 3.6V,
-
At External
Bus
MADATAxx
2.4
-
VCC + 0.3
V
VIHS
5V tolerant input pin
Input pin doubled as
I2C Fm+
VCC×0.8
VCC×0.7
-
-
VSS + 5.5
VSS + 5.5
V
V
-
-
TTL Schmitt
input pin
2.0
-
-
-
-
-
ETHVCC+0.3
VCC×0.2
V
V
V
V
V
CMOS hysteresis
input pin, MD0,
MD1
5V tolerant input pin
Input pin doubled as
I2C Fm+
VSS - 0.3
VSS - 0.3
VSS - 0.3
VSS
-
ETHVCC×0.2
VCC×0.2
L level
input
voltage
(hysteresis
input)
-
-
VILS
VCC×0.3
TTL Schmitt
input pin
-
VSS - 0.3
-
0.8
V
VCC ≥ 4.5V,
IOH = - 4 mA
VCC < 4.5V,
VCC - 0.5
-
VCC
V
IOH = - 2 mA
ETHVCC ≥ 4.5V,
IOH = - 4 mA
ETHVCC < 4.5V,
IOH = - 2 mA
4 mA type
VCC - 0.5
VCC - 0.5
-
-
-
-
-
ETHVCC
V
V
V
V
V
VCC ≥ 4.5V,
IOH = - 8 mA
VCC < 4.5V,
VCC
IOH = - 4 mA
ETHVCC ≥ 4.5V,
IOH = - 8 mA
ETHVCC < 4.5V,
IOH = - 4 mA
8 mA type
ETHVCC - 0.5
VCC - 0.5
ETHVCC
H level
output
voltage
VCC ≥ 4.5V,
VOH
IOH = - 10 mA
VCC < 4.5V,
IOH = - 8 mA
10 mA type
12 mA type
VCC
VCC ≥ 4.5V,
IOH = - 12 mA
VCC < 4.5V,
IOH = - 8 mA
VCC - 0.5
VCC
USBVCC0
and
USBVCC1
are
described
as
USBVCC ≥ 4.5V,
IOH = - 20.5 mA
The pin
doubled as USB I/O
USBVCC
0.4
-
-
-
USBVCC
V
V
USBVCC < 4.5V,
IOH = - 13.0 mA
USBVCC
.
VCC ≥ 4.5V,
IOH = - 4 mA
VCC < 4.5V,
IOH = - 3 mA
The pin
At GPIO
VCC - 0.5
VCC
doubled as I2C Fm+
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 99 of 200
S6E2C Series
Value
Typ
Parameter
Symbol
Pin Name
Conditions
CC ≥ 4.5V,
Unit
Remarks
Min
Max
V
IOL = 4 mA
VSS
-
0.4
V
VCC < 4.5V,
IOL = 2 mA
4 mA type
ETHVCC ≥ 4.5V,
IOL = 4 mA
RTHVCC < 4.5V,
IOL = 2 mA
VSS
VSS
VSS
VSS
-
-
-
-
0.4
0.4
0.4
0.4
V
V
V
V
VCC ≥ 4.5V,
IOL = 8 mA
VCC < 4.5V,
IOL = 4 mA
ETHVCC ≥ 4.5V,
IOL = 8 mA
8 mA type
RTHVCC < 4.5V,
IOL = 4 mA
VCC ≥ 4.5V,
L level
output
voltage
IOL = 10 mA
VCC < 4.5V,
IOL = 8 mA
VOL
10 mA type
12 mA type
VCC ≥ 4.5V,
IOL = 12 mA
VSS
-
-
0.4
0.4
V
V
VCC < 4.5V,
IOL = 8 mA
USBVCC0
and
USBVCC ≥ 4.5V,
IOL = 18.5 mA
USBVCC1
are
described
The pin doubled as
USB I/O
VSS
USBVCC < 4.5V,
IOL = 10.5 mA
as
USBVCC
.
VCC ≥ 4.5V,
IOL = 4 mA
VCC < 4.5V,
IOL = 3 mA
At GPIO
The pin doubled as
I2C Fm+
VSS
- 5
-
-
0.4
+ 5
V
VCC ≤ 4.5V,
At I2C
Fm+
IOL = 20 mA
Input leak
current
Pull-up
resistor
value
IIL
-
-
μA
kΩ
VCC ≥ 4.5V
25
30
50
80
100
200
RPU
Pull-up pin
VCC < 4.5V
Other than
VCC,
USBVCC0,
USBVCC1,
ETHVCC,
VBAT, VSS,
AVCC, AVSS,
AVRH
Input
capacitance
CIN
-
-
5
15
pF
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 100 of 200
S6E2C Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40C to +105C)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
4
4
4
48
20
48
20
250
VCC ≥4.5V
VCC < 4.5V
VCC ≥4.5V
VCC < 4.5V
VCC ≥4.5V
When crystal oscillator is
connected
MHz
MHz
ns
Input frequency
fCH
When using external clock
When using external clock
When using external clock
4
X0,
X1
20.83
Input clock cycle
tCYLH
-
tCF
50
250
VCC < 4.5V
PWH/tCYLH
,
Input clock pulse width
45
55
%
PWL/tCYLH
Input clock rise time and
fall time
,
-
-
5
ns
When using external clock
Base clock (HCLK/FCLK)
tCR
fCC
-
-
-
-
-
-
200
100
MHz
MHz
80
Internal operating clock
APB0bus clock
fCP0
79
frequency
APB1bus clock80
fCP1
fCP2
-
-
-
-
-
-
-
-
200
100
-
MHz
MHz
ns
APB2bus clock 80
Base clock (HCLK/FCLK)
tCYCC
5
Internal operating clock79
cycle time
APB0bus clock 80
APB1bus clock 80
APB2bus clock80
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
10
5
10
-
-
-
ns
ns
ns
79
For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856).
80 For more about each APB bus to which each peripheral is connected, see 1. Block Diagram in this data sheet.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 101 of 200
S6E2C Series
12.4.2 Sub Clock Input Characteristics
(VBAT = 1.65V to 5.5V, VSS = 0V)
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
oscillator is
-
-
32.768
-
kHz
connected81
When using external
clock
Input frequency
1/tCYLL
-
-
32
10
45
-
-
-
100
31.25
55
kHz
μs
X0A,
X1A
When using external
clock
When using external
clock
Input clock cycle
tCYLL
-
PWH/tCYLL
PWL/tCYLL
,
Input clock pulse width
%
tCYLL
0.8 × VBAT
0.8 × VBAT
0.8 × VBAT
0.2 × VBAT
0.2 × VBAT
X0A
PWH
PWL
12.4.3 Built-In CR Oscillation Characteristics
Built-In High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Conditions
Unit
MHz
μs
Remarks
Min
Max
TJ = - 20°C to + 105°C
TJ = - 40°C to + 125°C
TJ = - 40°C to + 125°C
3.92
4
4
4
4.08
4.12
5
When trimming82
Clock frequency
fCRH
3.88
3
When not
trimming
Frequency
stabilization
time
83
tCRWT
-
-
-
30
Built-In Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Unit Remarks
kHz
Value
Typ
Parameter
Symbol
fCRL
Condition
Min
Max
Clock frequency
-
50
100
150
81
82
83
For more information about crystal oscillator, see Sub crystal oscillator in 8. Handling Devices
In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming
This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is able to use the High-speed CR clock as a
source clock.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 102 of 200
S6E2C Series
12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
PLL oscillation stabilization wait time84
(lock up time)
Symbol
Unit
Remarks
Min
Max
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
13
200
-
-
-
-
-
16
MHz
multiplier
MHz
100
400
200
PLL macro oscillation clock frequency
Main PLL clock frequency85
MHz
12.4.5 Operating Conditions of USB/Ethernet PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
PLL oscillation stabilization wait time86
(lock up time)
Symbol
Unit
Remarks
Min
Typ
Max
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
4
13
-
-
16
MHz
multiplier
MHz
100
400
384
USB/Ethernet
I2S
After the M
frequency division
After the M
PLL macro oscillation clock frequency
USB/Ethernet clock frequency87
fPLLO
200
-
-
-
MHz
fCLKPLL
fCLKPLL
-
-
50
MHz
MHz
88
I2S clock frequency
12.288
frequency division
84
85
Time from when the PLL starts operating until the oscillation stabilizes
For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual
Main Part (002-04856).
86
Time from when the PLL starts operating until the oscillation stabilizes
87
For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family Peripheral Manual Communication Macro Part
(002-04862).
88
For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862).
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 103 of 200
S6E2C Series
12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main
PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
PLL oscillation stabilization wait time89
(lock up time)
Symbol
Unit
Remarks
Min
Max
tLOCK
fPLLI
100
-
-
μs
PLL input clock frequency
3.8
4
4.2
MHz
PLL multiplication rate
PLL macro oscillation clock frequency
-
50
190
-
-
95
400
multiplier
MHz
fPLLO
Main PLL clock frequency 90
fCLKPLL
-
-
200
MHz
Note:
− The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the
Main PLL.
12.4.7 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
89
90
Time from when the PLL starts operating until the oscillation stabilizes
For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral
Manual Main Part (002-04856).
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 104 of 200
S6E2C Series
12.4.8 Power-On Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC must
be
held
below
0.2V for a
minimum
period of
tOFF
Improper
.
Power supply shut down time
tOFF
-
1
-
-
ms
initializatio
n
may
occur
this
if
condition
is not met
VCC
This dV/dt
characteri
stic is
applied at
the power-
on of cold
start
(tOFF>1ms)
.
Power ramp rate
dV/dt
VCC: 0.2V to 2.70V
0.6
-
-
1000 mV/µs
Time until releasing Power-on reset
tPRT
-
0.33
0.60
ms
Note:
− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.7 Reset
Input Characteristics.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.8. Low-Voltage Detection Characteristics”.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 105 of 200
S6E2C Series
12.4.9 GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5V
VCC < 4.5V
-
50
MHz
MHz
Pxx91
Output frequency
tPCYCLE
-
32
Pxx
tPCYCLE
91
GPIO is a target.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 106 of 200
S6E2C Series
12.4.10 External Bus Timing
External Bus Clock Output Characteristics
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
5093
MHz
92
Output frequency
tCYCLE
-
MCLKOUT
0.8 × VC
C
VCC
0.8 ×
MCLK
tCYCLE
External Bus Signal I/O Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
V
V
Signal input characteristics
-
VOH
VOL
0.8 × VCC
0.2 × VCC
V
V
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
92
The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family
Peripheral Manual Main Part (002-04856).
93
The Multi-layer AHB clock divided by the (DCLKR:MDIV) divider register, cannot exceed this specification for MCLKOUT or MSDCLK clock.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 107 of 200
S6E2C Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
MOEX
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MOEX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum pulse width
MCSX↓→Address
output delay time
MCSX[7: 0],
MAD[24: 0]
-9
0
+9
MOEX↑→Address
hold time
MOEX,
MAD[24: 0]
MCLK×m+9
MCLK×m+9
MCLK×m+9
MCLK×m+9
-
MCSX↓→
MOEX↓delay time
MCLK×m-
9
MOEX,
MCSX[7: 0]
MOEX↑→
MCSX↑time
0
MCSX↓→
MDQM↓delay time
MCSX,
MDQM[3: 0]
MCLK×m-
9
Data set up→MOEX↑
time
MOEX,
MADATA[31: 0]
20
MOEX↑→
Data hold time
MOEX,
MADATA[31: 0]
tDH - OE
0
-
MWEX
Minimum pulse width
tWEW
MWEX
MCLK×n-3
-
MWEX↑→Address
output delay time
MWEX,
MAD[24: 0]
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DX
0
MCLK×n-9
0
MCLK×m+9
MCLK×n+9
MCLK×m+9
MCLK×n+9
MCLK+9
MCLK×m+9
MCSX↓→
MWEX↓delay time
MWEX,
MCSX[7: 0]
MWEX↑→
MCSX↑delay time
MCSX↓→
MDQM↓delay time
MCSX,
MDQM[3: 0]
MCLK×n-9
MCLK-9
0
MCSX↓→
Data output time
MCSX,
MADATA[31: 0]
MWEX↑→
Data hold time
MWEX,
MADATA[31: 0]
tWEH - DX
Note:
− When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 108 of 200
S6E2C Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7: 0]
tCSL-AV
tOEH-AX
tCSL-AV
MAD[24: 0]
MOEX
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1: 0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15: 0]
tCSL-DX
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7: 0]
tCSL-AV
tOEH-AX
tCSL-AV
MAD[24: 0]
MOEX
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1: 0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15: 0]
tCSL-DX
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 109 of 200
S6E2C Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Remark
Unit
Parameter
Symbol
Pin Name
Conditions
s
Min
Max
MCLK,
MAD[24: 0]
Address delay time
tAV
-
-
1
9
ns
ns
tCSL
1
9
MCLK,
MCSX[7: 0]
MCSX delay time
MOEX delay time
tCSH
tREL
tREH
-
-
-
1
1
1
9
9
9
ns
ns
ns
MCLK,
MOEX
Data set up
→MCLK↑ time
MCLK↑→
Data hold time
MCLK,
MADATA[31: 0]
MCLK,
tDS
-
-
19
0
-
-
ns
ns
tDH
tWEL
tWEH
tDQML
tDQMH
MADATA[31: 0]
-
-
1
1
9
9
ns
ns
MCLK,
MWEX
MWEX delay time
-
-
1
1
9
9
ns
ns
MDQM[1: 0]
delay time
MCLK,
MDQM[3: 0]
MCLK↑→
Data output time
MCLK↑→
Data hold time
MCLK,
MADATA[31: 0]
MCLK,
tODS
tOD
-
-
MCLK+1
1
MCLK+18
18
ns
ns
MADATA[31: 0]
Note:
− When the external load capacitance CL = 30 pF
tCYCLE
MCLK
tCSL
tCSH
MCSX[7: 0]
tAV
tAV
MAD[24: 0]
Address
Address
tREL
tREH
MOEX
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[3: 0]
tWEL
MWEX
tDS
tDH
RD
Invalid
WD
MADATA[31: 0]
tODS
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 110 of 200
S6E2C Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Multiplexed
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
tALE-CHMADV
tCHMADH
-
-
0
10
ns
ns
address delay time
MALE,
MAD[24: 0]
Multiplexed address
hold time
MCLK×n+0 MCLK×n+10
Note:
− When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 111 of 200
S6E2C Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit Remarks
Min
1
Max
tCHAL
tCHAH
tCHMADV
-
-
9
9
MCLK,
MALE
MALE delay time
1
MCLK↑→Multiplexed
address delay time
-
-
1
1
tOD
tOD
ns
ns
MCLK,
MADATA[31: 0]
MCLK↑→Multiplexed
data output time
tCHMADX
Note:
− When the external load capacitance CL = 30 pF
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 112 of 200
S6E2C Series
NAND Flash Mode
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
MNREX
Min pulse width
tNREW
MNREX
-
-
MCLK×n-3
20
-
-
ns
ns
Data set up
→MNREX↑time
MNREX,
MADATA[31: 0]
tDS – NRE
MNREX↑→
Data hold time
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNREX,
MADATA[31: 0]
MNALE,
tDH – NRE
tALEH - NWEL
tALEL - NWEL
-
-
-
0
-
ns
ns
ns
MCLK×m-9
MCLK×m-9
MCLK×m+9
MCLK×m+9
MNWEX
MNALE,
MNWEX
MNCLE↑→
MNWEX delay time
MNCLE,
MNWEX
tCLEH - NWEL
tNWEH - CLEL
-
-
MCLK×m-9
0
MCLK×m+9
MCLK×m+9
ns
ns
MNWEX↑→
MNCLE delay time
MNCLE,
MNWEX
MNWEX
tNWEW
MNWEX
-
-
-
MCLK×n-3
-
ns
ns
ns
Min pulse width
MNWEX↓→
Data output time
MNWEX↑→
Data hold time
MNWEX,
MADATA[31: 0]
MNWEX,
tNWEL – DV
tNWEH – DX
-9
0
9
MCLK×m+9
MADATA[31: 0]
Note:
− When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[31: 0]
Read
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 113 of 200
S6E2C Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Write
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 114 of 200
S6E2C Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
MCLK↑
MRDY input
setup time
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
MCLK,
MRDY
tRDYI
-
19
-
ns
◼ When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
◼ When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
tRDYI
MWEX
0.5×VCC
MRDY
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 115 of 200
S6E2C Series
SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Unit
Parameter
Symbol
Pin Name
Value
Unit
Remarks
Min
Max
Output frequency
tCYCSD
tAOSD
MSDCLK
-
-
-
50
MHz
ns
MSDCLK,
MAD[15: 0]
Address delay time
2
12
MSDCLK↑→
Data output delay time
MSDCLK↑→
Data output Hi-Z time
MSDCLK,
MADATA[31: 0]
MSDCLK,
MADATA[31: 0]
MSDCLK,
MDQM[1: 0]
tDOSD
tDOZSD
tWROSD
-
-
-
2
2
1
12
19.5
12
ns
ns
ns
MDQM[3: 0] delay time
MSDCLK,
MCSX8
MCSX delay time
tMCSSD
tRASSD
-
-
2
2
12
12
ns
ns
MSDCLK,
MRASX
MRASX delay time
MSDCLK,
MCASX
MSDCLK,
MSDWEX
MSDCLK,
MSDCKE
MSDCLK,
MCASX delay time
MSDWEX delay time
MSDCKE delay time
Data set up time
tCASSD
tMWESD
tCKESD
tDSSD
-
-
-
-
-
2
2
12
12
12
-
ns
ns
ns
ns
ns
2
19
0
MADATA[31: 0]
MSDCLK,
MADATA[31: 0]
Data hold time
tDHSD
-
Note:
− When the external load capacitance CL = 30 pF
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 116 of 200
S6E2C Series
tCYCSD
MSDCLK
MAD[24:0]
MDQM[1:0]
MCSX
tAOSD
Address
tWROSD
tMCSSD
tRASSD
MRASX
tCASSD
tMWESD
tCKESD
MCASX
MSDWEX
MSDCKE
tDSSD
RD
tDHSD
MADATA[15:0]
MADATA[15:0]
tDOSD
tDOZSD
WD
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 117 of 200
S6E2C Series
12.4.11 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
tTIWH, tTIWL
Pin Name
Unit
ns
Remarks
Min
Max
TIOAn/TIOBn
(when using as ECK, TIN)
Input pulse width
2tCYCP
-
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Unit Remarks
ns
Value
Parameter
Symbol
Pin Name
Min
Max
TIOAn/TIOBn
(when using as TGIN)
Input pulse width
tTRGH, tTRGL
2tCYCP
-
tTRGH
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is
connected, see 1. Block Diagram in this datasheet.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 118 of 200
S6E2C Series
12.4.12 CSIO (SPI) Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Pin
Parameter
Baud rate
Symbol
Conditions
Name
Min
Max
Min
-
Max
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↓→SOT delay time
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
SIN→SCK↑
setup time
-
-
-
-
SCK↑→SIN hold time
2tCYCP
10
tCYCP
10
-
2tCYCP
10
tCYCP
10
-
Serial clock L pulse width
Serial clock H pulse width
SCK↓→SOT delay time
SCKx
SCKx
-
-
+
+
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift
clock
operation
SIN→SCK↑
setup time
10
20
10
20
SCK↑→SIN hold time
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 119 of 200
S6E2C Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
tR
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 120 of 200
S6E2C Series
Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Pin
Parameter
Baud rate
Symbol
Conditions
Name
Min
Max
Min
-
Max
-
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SCKx,
SINx
SCKx,
SINx
SIN→SCK↓ setup time
SCK↓→SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tIVSLI
tSLIXI
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
2tCYCP
10
tCYCP
10
-
2tCYCP
10
tCYCP
10
-
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
SCKx
SCKx
-
-
+
+
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and
SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 121 of 200
S6E2C Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tF
tR
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 122 of 200
S6E2C Series
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Pin
Parameter
Baud rate
Symbol
Conditions
Name
Min
Max
Min
-
Max
-
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
Internal shift
clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
tIVSLI
tSLIXI
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SCK↓→SIN hold time
2tCYCP
30
2tCYCP
10
tCYCP
10
-
2tCYCP
30
2tCYCP
10
tCYCP
10
-
SOT→SCK↓ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK↑→SOT delay time
tSOVLI
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
-
-
-
-
SCKx
SCKx
-
-
+
+
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift
clock
operation
SIN→SCK↓
setup time
10
20
10
20
SCK↓→SIN hold time
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 123 of 200
S6E2C Series
tSCYC
VOH
VOL
VOL
SCK
SOT
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 124 of 200
S6E2C Series
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Pin
Parameter
Baud rate
Symbol
Conditions
Name
Min
Max
Min
-
Max
-
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
4tCYCP
4tCYCP
SCK↓→SOT delay time
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
SIN→SCK↑ setup time
SCK↑→SIN hold time
SOT→SCK↑ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
-
-
-
-
2tCYCP
30
-
2tCYCP
30
2tCYCP
10
tCYCP
10
-
-
-
2tCYCP
10
-
-
SCKx
SCKx
-
-
tCYCP
10
+
+
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
50
-
-
30
-
External shift
clock
operation
10
20
10
20
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 125 of 200
S6E2C Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 126 of 200
S6E2C Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Min
94-50
95+0
96-50
+5tCYCP
Max
94+0
95+50
Min
Max
94+0
95+50
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
94-50
95+0
ns
ns
Internal shift
clock
operation
96+50
96-50
+5tCYCP
96+50
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
94
95
96
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 127 of 200
S6E2C Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS input
SCK input
tCSDE
tCSHE
tCSSE
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 128 of 200
S6E2C Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Min
97-50
98+0
Max
97+0
98+50
Min
Max
97+0
98+50
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
97-50
98+0
ns
ns
Internal shift
clock operation
99-50
99+50
99-50
+5tCYCP
99+50
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
97
98
99
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 129 of 200
S6E2C Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 130 of 200
S6E2C Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Min
100-50
101+0
Max
100+0
101+50
Min
Max
100+0
101+50
tCSSI
tCSHI
100-50
101+0
ns
ns
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
Internal shift
clock
operation
102-50
102+50
102-50
+5tCYCP
102+50
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
100
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
101
102
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 131 of 200
S6E2C Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 132 of 200
S6E2C Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Units
Parameter
Symbol
Conditions
Min
103-50
104+0
Max
103+0
104+50
Min
Max
103+0
104+50
tCSSI
tCSHI
103-50
104+0
ns
ns
SCS↑→SCK↑setup time
SCK↓→SCS↓hold time
Internal shift
clock
operation
105-50
105+50
105-50
+5tCYCP
105+50
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↑→SCK↑setup time
SCK↓→SCS↓hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External
shift clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
103
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
104
105
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 133 of 200
S6E2C Series
tCSDI
SCS output
SCK output
tCSHI
tCSSI
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
SCK input
tCSHE
tCSSE
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 134 of 200
S6E2C Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Parameter
Symbol
tSCYC
Conditions
Name
Min
Max
Min
Max
Serial clock cycle time
SCK↓→SOT delay time
SCKx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
ns
tSLOVI
- 10
+ 10
- 10
12.5
5
+ 10
Internal shift
clock
operation
14
SCKx,
SINx
SIN→SCK↑ setup time
tIVSHI
-
-
-
-
ns
ns
12.5*
SCKx,
SINx
SCK↑→SIN hold time
tSHIXI
tSLSH
tSHSL
5
Serial clock L pulse width
Serial clock H pulse width
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 5
tCYCP + 10
-
-
2tCYCP - 5
tCYCP + 10
-
-
ns
ns
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
External shift
clock
operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 135 of 200
S6E2C Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
tR
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 136 of 200
S6E2C Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Name
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 10
+ 10
- 10
+ 10
Internal shift
clock
operation
14
SCKx,
SINx
SIN→SCK↓ setup time
SCK↓→SIN hold time
tIVSLI
-
-
12.5
5
-
-
ns
ns
12.5*
SCKx,
SINx
tSLIXI
tSLSH
tSHSL
5
Serial clock L pulse width
Serial clock H pulse width
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
2tCYCP - 5
tCYCP + 10
-
-
2tCYCP - 5
tCYCP + 10
-
-
ns
ns
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
15
-
-
15
-
ns
ns
ns
External shift
clock
operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 137 of 200
S6E2C Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tF
tR
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 138 of 200
S6E2C Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Name
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 10
+ 10
- 10
+ 10
Internal shift
clock
operation
14
SCKx,
SINx
SIN→SCK↓ setup time
tIVSLI
-
12.5
-
ns
12.5*
SCKx,
SINx
SCK↓→SIN hold time
SOT→SCK↓ delay time
tSLIXI
5
-
-
5
-
-
ns
ns
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
tSOVLI
2tCYCP - 10
2tCYCP - 10
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 5
tCYCP + 10
-
-
2tCYCP - 5
tCYCP + 10
-
-
ns
ns
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
15
-
-
15
-
ns
ns
ns
External shift
clock
operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
− When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 139 of 200
S6E2C Series
tSCYC
VOH
VOL
VOL
SCK
SOT
SIN
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 140 of 200
S6E2C Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
VCC ≥ 4.5V
Unit
Parameter
Symbol
tSCYC
Conditions
Name
SCKx
SCKx,
SOTx
Min
Max
Min
Max
Serial clock cycle time
SCK↓→SOT delay time
4tCYCP
-
4tCYCP
-
ns
ns
tSLOVI
- 10
+ 10
- 10
12.5
5
+ 10
14
SCKx,
SINx
Internal shift
clock
operation
SIN→SCK↑ setup time
tIVSHI
tSHIXI
-
-
-
-
ns
ns
12.5*
SCKx,
SINx
SCKx,
SOTx
SCKx
SCK↑→SIN hold time
SOT→SCK↑ delay time
5
tSOVHI
tSLSH
tSHSL
2tCYCP - 10
2tCYCP - 5
tCYCP + 10
-
-
-
2tCYCP - 10
2tCYCP - 5
tCYCP + 10
-
-
-
ns
ns
ns
Serial clock L pulse width
Serial clock H pulse
width
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
External shift
clock
operation
5
5
5
5
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
− When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
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S6E2C Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
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S6E2C Series Datasheet
Page 142 of 200
S6E2C Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol Conditions
Min
106-20
107+0
Max
106+0
107+20
Min
Max
106+0
107+20
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
106-20
107+0
ns
ns
Internal
shift clock
operation
tCSHI
108-20
108+20
108-20
+5tCYCP
108+20
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External
shift clock
operation
tCSDE
tDSE
tDEE
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
106
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
107
108
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S6E2C Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
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S6E2C Series Datasheet
Page 144 of 200
S6E2C Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Min
109-20
110+0
Min
109+0
110+20
Min
Max
109+0
110+20
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
109-20
110+0
ns
ns
Internal shift
clock
operation
111-20
111+20
111-20
+5tCYCP
111+20
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↓→SCK↑ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
0
0
External
shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
109
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
110
111
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S6E2C Series Datasheet
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S6E2C Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
intpu
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 146 of 200
S6E2C Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol Conditions
Min
112-20
113+0
Max
112+0
113+20
Min
Max
112+0
113+20
tCSSI
112-20
113+0
ns
ns
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
Internal shift
clock
operation
tCSHI
114-20
114+20
114-20
+5tCYCP
114+20
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
+5tCYCP
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External
shift clock
operation
tCSDE
tDSE
tDEE
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
112
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
113
114
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S6E2C Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
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S6E2C Series Datasheet
Page 148 of 200
S6E2C Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
VCC < 4.5V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5V
Unit
Parameter
Symbol
Conditions
Min
115-20
116+0
117-20
+5tCYCP
Max
115+0
116+20
117+20
+5tCYCP
Min
Max
115+0
116+20
tCSSI
tCSHI
115-20
116+0
ns
ns
SCS↓→SCK↓ setup time
SCK↑→SCS↓ hold time
Internal shift
clock
operation
117-20
117+20
+5tCYCP
SCS deselect time
tCSDI
ns
+5tCYCP
SCS↑→SCK↑ setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
0
0
External
shift clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
Notes:
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. Block Diagram in this datasheet.
− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
− When the external load capacitance CL = 30 pF.
115
CSSU bit value×serial chip select timing operating clock cycle [ns]
CSHD bit value×serial chip select timing operating clock cycle [ns]
CSDS bit value×serial chip select timing operating clock cycle [ns]
116
117
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S6E2C Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
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S6E2C Series Datasheet
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S6E2C Series
External Clock (EXT = 1): When in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK fall time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rise time
tR
tR
tF
tSHSL
tSLSH
SCK
VIH
VIH
VIH
VIL
VIL
VIL
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S6E2C Series
12.4.13 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Parameter
Symbol
Pin Name
ADTGx
Conditions
Unit
Remarks
Max
A/D converter trigger
input
118
-
2tCYCP
-
ns
Free-run timer input clock
FRCKx
ICxx
DTTIxX
Input capture
Waveform generator
118
-
-
2tCYCP
-
-
ns
ns
Input pulse
width
tINH, tINL
2tCYCP + 100118
INT00 to INT31,
NMIX
External interrupt,
NMI
500119
-
-
ns
ns
WKUPx
-
500120
Deep standby wake up
118
tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about the APB bus number to which the A/D
converter, multi-function timer, and external interrupt are connected, see 1 Block Diagram in this data sheet.
119
When in Stop mode, in Timer mode
When in Deep Standby RTC mode, in Deep Standby Stop mode
120
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S6E2C Series
12.4.14 Quadrature Position/Revolution Counter Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40°C to +105°C)
Value
Unit
Parameter
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
Symbol
Conditions
Min
Max
tAHL
tALL
tBHL
tBLL
-
-
-
-
BIN rise time from
AIN pin H level
AIN fall time from
BIN pin H level
BIN fall time from
AIN pin L level
AIN rise time from
BIN pin L level
AIN rise time from
BIN pin H level
BIN fall time from
AIN pin H level
AIN fall time from
BIN pin L level
BIN rise time from
AIN pin L level
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR: CGSC = 0
QCR: CGSC = 0
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
121
2tCYCP
-
ns
ZIN pin H width
ZIN pin L width
tZHL
tZLL
AIN/BIN rise and fall time
from determined ZIN level
Determined ZIN level from
AIN/BIN rise and fall time
tZABE
tABEZ
QCR: CGSC = 1
QCR: CGSC = 1
SDA
tSUSTA
tSUDAT
tBUF
tLOW
SCL
tHDSTA
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
121
tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the APB bus number to which the quadrature
position/revolution counter is connected, see 1. Block Diagram in this data sheet.
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S6E2C Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
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S6E2C Series
12.4.15 I2C Timing
Standard-Mode, Fast-Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Standard-Mode
Fast-Mode
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Min
Max
SCL clock frequency
(Repeated) START condition
hold time
fSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
Stop condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
CL = 30 pF,
122
R = (Vp/IOL
)
tHDDAT
tSUDAT
tSUSTO
0
3.45123
0
0.9124
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
"Stop condition" and
"START condition"
tBUF
4.7
2 tCYCP
4 tCYCP
-
-
-
1.3
2
-
-
-
μs
ns
2 MHz ≤
125
125
t
CYCP＜40 MHz
40 MHz ≤
tCYCP ＜60
MHz
60 MHz ≤
tCYCP ＜80
MHz
tCYCP
4
tCYCP
125
ns
125
126
Noise filter
tSP
6
tCYCP
125
6 tCYCP
8 tCYCP
-
-
-
-
ns
ns
125
80 MHz ≤
tCYCP ≤100 MHz
8
tCYCP
125
125
122
R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up
resistance and IOL indicates VOL guaranteed current.
123
The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.
124
Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.
125
tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 1.Block Diagram in this data sheet.
When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.
When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.
126
The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
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S6E2C Series
Fast mode Plus (Fm+)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V)
Fast mode Plus (Fm+)127
Symbol
Conditions
Unit
Remarks
Min
Max
SCL clock frequency
(Repeated) START condition
hold time
fSCL
0
1000
kHz
tHDSTA
0.26
-
μs
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
SCL clock frequency
(Repeated) START condition
hold time
tLOW
tHIGH
tSUSTA
0.5
0.26
0.26
-
-
-
μs
μs
μs
CL = 30 pF,
0.45129, 130
128
tHDDAT
0
μs
R = (Vp/IOL
)
SDA ↓ → SCL ↓
Data setup time
tSUDAT
tSUSTO
tBUF
50
-
-
ns
μs
SDA ↓ ↑ → SCL ↑
Stop condition setup time
SCL ↑ → SDA ↑
Bus free time between
"Stop condition" and
"START condition"
0.26
0.5
-
μs
60 MHz ≤
CYCP＜80 MHz
80 MHz ≤
131
6 tCYCP
-
-
ns
ns
t
132
Noise filter
tSP
131
8 tCYCP
tCYCP ≤100 MHz
127
When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter 12: I/O Port in FM4 Family Peripheral
Manual Main Part (002-04856) for the details.
128
R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up
resistance and IOL indicates VOL guaranteed current.
129
The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.
130
The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.
131
tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 1 Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
132
The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
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S6E2C Series
12.4.16 SD Card Interface Timing
Default-Speed mode
◼ Clock CLK (All values are referenced to VIH and VIL transition points)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Clock frequency Data
Transfer mode
fPP
S_CLK
0133
25
MHz
Clock frequency
Identification mode
fOD
S_CLK
0133/100
400
kHz
CCARD ≤ 10
pF
(1card)
Clock low time
Clock high time
Clock rise time
Clock fall time
tWL
tWH
tTLH
tTHL
S_CLK
S_CLK
S_CLK
S_CLK
10
10
-
-
-
10
10
ns
ns
ns
ns
-
◼ Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Value
Parameter
Input set-up time
Input hold time
Symbol
Pin Name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3: 0
S_CMD,
tISU
5
-
ns
ns
CCARD ≤ 10 pF
(1card)
tIH
5
-
S_DATA3: 0
◼ Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Output Delay time during
Data Transfer mode
Output Delay time during
Identification mode
S_CMD,
S_DATA3: 0
S_CMD,
tODLY
0
14
ns
ns
CCARD ≤ 40 pF
(1card)
tODLY
0
50
S_DATA3: 0
tWH
tWL
VIH
VIH
S_CLK
VIH
VIL
VIL
(SD Clock)
tTLH
tTHL
tIH
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3: 0
(Card Input)
tODLY(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3: 0
(Card Output)
Default-Speed mode
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is
the Host.
133
0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
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S6E2C Series
− For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual
Main Part (002-04856).
High-speed mode
◼ Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Clock frequency Data
Transfer mode
Clock low time
Clock high time
Clock rise time
Clock fall time
fPP
S_CLK
0
50
MHz
CCARD ≤ 10
pF
(1card)
tWL
tWH
tTLH
tTHL
S_CLK
S_CLK
S_CLK
S_CLK
7
7
-
-
-
3
3
ns
ns
ns
ns
-
◼ Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Value
Parameter
Input set-up time
Input hold time
Symbol
Pin Name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3: 0
S_CMD,
tISU
6
-
ns
ns
CCARD ≤ 10
pF
(1card)
tIH
2
-
S_DATA3: 0
◼ Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
tODLY
tOH
Pin Name
Conditions
Remarks
Min
Max
Output delay time during
data transfer mode
S_CMD,
S_DATA3: 0
S_CMD,
CL ≤ 40 pF
(1card)
CL ≥ 15 pF
(1card)
0
14
ns
ns
pF
Output hold time
2.5
-
-
S_DATA3: 0
Total system capacitance
for each line134
CL
-
1card
40
tWH
tWL
VIH
VIH
S_CLK
VIH
50%VCC
50%VCC
tIH
VIL
VIL
(SD Clock)
tTLH
tTHL
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3: 0
(Card Input)
tOH(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3: 0
(Card Output)
High-speed mode
134
In order to satisfy severe timing, host shall drive only one card.
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S6E2C Series Datasheet
Page 158 of 200
S6E2C Series
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this
model is the Host.
− For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral
Manual Main Part (002-04856).
12.4.17 ETM/ HTM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Data hold
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5V
2
9
ns
TRACECLK,
TRACED[15: 0]
tETMH
VCC ＜4.5V
VCC ≥ 4.5V
VCC ＜4.5V
2
15
50
32
MHz
MHz
TRACECLK
frequency
1/tTRACE
tTRACE
TRACECLK
VCC ≥ 4.5V
20
-
-
ns
ns
TRACECLK
clock cycle
VCC ＜4.5V
31.25
Note:
− When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[15: 0]
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S6E2C Series Datasheet
Page 159 of 200
S6E2C Series
12.4.18 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5V
TCK,
TMS, TDI
TMS, TDI setup time
tJTAGS
15
-
ns
VCC ＜4.5V
VCC ≥ 4.5V
VCC ＜4.5V
VCC ≥ 4.5V
VCC ＜4.5V
TCK,
TMS, TDI
TMS, TDI hold time
TDO delay time
Note:
tJTAGH
tJTAGD
15
-
ns
ns
-
-
25
45
TCK,
TDO
− When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
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S6E2C Series Datasheet
Page 160 of 200
S6E2C Series
12.4.19 Ethernet-MAC Timing
RMII Transmission (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V135, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
tREFCYC
Pin Name
Conditions
20 ns (typical)
tREFCYCH/tREFCYC
tREFCYCL/tREFCYC
Unit
ns
Min
Max
Reference clock cycle time136
E_RXCK_REFCK
E_RXCK_REFCK
E_RXCK_REFCK
-
-
Reference clock
High-pulse-width duty cycle
Reference clock
Low-pulse-width duty cycle
tREFCYCH
tREFCYCL
35
35
65
65
%
%
E_TX03, E_TX02,
E_TX01, E_TX00,
E_TXEN
Transmitted data → REFCK ↑
delay time
tRMIITX
-
-
12
ns
tREFCYC
VILS
E_RXCK_REFCK
VIHS
VIHS
tREFCYCH
tREFCYCL
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
VOH
VOL
tRMIITX
135
When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output current.
The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications.
136
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S6E2C Series Datasheet
Page 161 of 200
S6E2C Series
RMII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
20 ns (typical)
tREFCYCH/tREFCYC
tREFCYCL/tREFCYC
Unit
ns
Min
Max
Reference clock
tREFCYC
tREFCYCH
tREFCYCL
E_RXCK_REFCK
E_RXCK_REFCK
E_RXCK_REFCK
-
-
cycle time137
Reference clock
High-pulse-width duty cycle
Reference clock
Low-pulse-width duty cycle
35
35
65
65
%
%
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
Received data → REFCK↑
Setup time
tRMIIRXS
-
-
4
2
-
-
ns
ns
Received data → REFCK ↑
Hold time
tRMIIRXH
tREFCYC
VILS
E_RXCK_REFCK
VIHS
VIHS
tREFCYCH
tREFCYCL
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VILS
VIHS
VILS
tRMIIRXS
tRMIIRXH
137
The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications.
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S6E2C Series Datasheet
Page 162 of 200
S6E2C Series
Management Interface
Parameter
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Symbol
tMDCYC
tMDCYCH
tMDCYCL
tMDO
Pin Name
E_MDC
E_MDC
E_MDC
E_MDIO
E_MDIO
E_MDIO
Conditions
Unit
ns
%
Min
Max
Management clock
cycle time138
-
400
-
Management clock
High pulse width duty cycle
Management clock
Low pulse width duty cycle
MDC ↓ → MDIO
Delay time
MDIO → MDC ↑
Setup time
MDC ↑ → MDIO
Hold time
tMDCYCH/tMDCYC
35
35
-
65
65
60
-
tMDCYCL/tMDCYC
%
-
-
-
ns
ns
ns
tMDIS
20
0
tMDIH
-
tMDCYC
VOL
VOH
VOL
VOH
E_MDC (output)
E_MDIO (input)
tMDCYCH
tMDCYCL
VIHS
VILS
tMDIH
VIHS
VILS
VIHS
VIHS
VILS
VILS
tMDIS
tMDIS
tMDIH
tMDO
tMDO
VOH
VOL
VOH
VOL
E_MDIO (output)
138
The clock time should be set to a value greater than the minimum value by setting the Ethernet-MAC setting register.
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S6E2C Series Datasheet
Page 163 of 200
S6E2C Series
MII Transmission (100 Mbps/10 Mbps)
139,
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V
V
SS
= 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
ns
Min
Max
100 Mbps
40 ns (typical)
100 Mbps
-
-
Transmission clock
tTXCYC
E_TCK
Cycle time140
-
-
ns
400 ns (typical)
Transmission clock
High-pulse-width duty cycle
Transmission clock
Low-pulse-width duty cycle
tTXCYCH
tTXCYCL
E_TCK
E_TCK
tTXCYCH/tTXCYC
tTXCYCL/tTXCYC
35
35
65
65
%
%
E_TX03, E_TX02,
E_TX01, E_TX00,
E_TXEN
TXCK ↑ → Transmitted data
delay time
tMIITX
-
-
24
ns
tTXCYC
VIHS
VIHS
E_TCK
VILS
tTXCYCH
tTXCYCL
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
VOH
VOL
tMIITX
139
140
When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output current.
The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the PHY-device specifications.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 164 of 200
S6E2C Series
MII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
ns
Min
Max
100 Mbps
40 ns (typical)
100 Mbps
-
-
Receiving clock
tRXCYC
E_RXCK_REFCK
cycle time141
-
-
ns
400 ns (typical)
Receiving clock
High pulse width duty cycle
Receiving clock
Low pulse width duty cycle
tRXCYCH
tRXCYCL
tMIIRXS
E_RXCK_REFCK
E_RXCK_REFCK
tRXCYCH/tRXCYC
tRXCYCL/tRXCYC
35
35
65
65
%
%
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
Received data →
REFCK ↑Setup time
-
-
5
2
-
-
ns
ns
REFCK ↑ →
Received data Hold time
tMIIRXH
tRXCYC
E_RXCK_REFCK
VIHS
VIHS
VILS
tRXCYCH
tRXCYCL
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VILS
VIHS
VILS
tMIIRXS
tMIIRXH
141
The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 165 of 200
S6E2C Series
12.4.20 I2S Timing
Master Mode Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
Output frequency
fMCYC
tMHW
tMLW
I2SCK
-
-
12.288
MHz
%
45
45
55
55
Output clock pulse width
I2SCK
-
%
I2SCK→I2SWS
delay time
I2SCK→I2SDO
delay time142
I2SDI→I2SCK
setup time
I2SCK,
I2SWS
I2SCK,
I2SDO
tDFS
tDDO
tHSDI
tHDJ
-
-
-
-
0
0
24.0
ns
ns
ns
ns
24.0
25.0
0
-
-
I2SCK,
I2SDI
I2SDI→I2SCK
hold time
Input signal rise time
Input signal fall time
tFI
tFI
-
-
-
-
5
5
ns
ns
I2SDI
Notes:
− When the external load capacitance CL = 20 pF
− When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz.
See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-
04862) for the details.
142
Except for the first bit of transmission frame
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S6E2C Series Datasheet
Page 166 of 200
S6E2C Series
fMCYC
tMHW
tMLW
I2SCK (CPOL=0)
I2SCK (CPOL=1)
tDFS
tDFS
I2SWS
(FSPH=0, FSLN=0)
tDFS
tDFS
I2SWS
(FSPH=1, FSLN=0)
tDFS
tDFS
I2SWS
(FSPH=0, FSLN=1)
tDFS
tDFS
I2SWS
(FSPH=1, FSLN=1)
tDDO
I2SDO
tSDI
tHDI
tSDI
tHDI
I2SDI
(SMPL=0)
tSDI
tHDI
I2SDI
(SMPL=1)
Note:
− See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-
04862) for the details of CPOL, FSPH, FSLIN, and SMPL.
0.8×VCC
0.8×VCC
0.2×VCC
0.8×VCC
0.2×VCC
I2SDI
tFI
tRI
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 167 of 200
S6E2C Series
Slave Mode Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
Input frequency
fSCYC
tSHW
tSLW
I2SCK
-
-
12.288
MHz
%
45
45
55
55
Input clock pulse width
I2SCK
-
%
I2SWS→I2SCK
Setup time
I2SWS→I2SCK
Hold time
I2SCK↑→I2SDO
Delay time143
I2SCK↑→I2SDO
Delay Time144
I2SDI→I2SCK↓
Setup time
I2SCK,
I2SWS
I2SCK,
I2SWS
tSFI
tHFI
-
-
-
-
-
-
8
0
0
0
8
0
-
-
ns
ns
ns
ns
ns
ns
tDDO
tDFB1
tSDI
32
32
-
I2SCK, I2SDO
I2SCK, I2SDI
I2SDI→I2SCK↓
Hold time
tHDI
-
Input signal rise time
Input signal fall time
tFI
tFI
-
-
-
-
5
5
ns
ns
I2SCK,
I2SWS, I2SDI
Notes:
− When the external load capacitance CL = 20 pF
− When I2SWS = 48 kHz, I2MCLK = 256×I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I2S (Inter-IC Sound bus)
Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details.
143
144
Except for the first bit of transmission frame
When FSPH bit = 1.
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S6E2C Series Datasheet
Page 168 of 200
S6E2C Series
fSCYC
tSHW
tSLW
I2SCK (CPOL=0)
I2SCK (CPOL=1)
tSFI
tHFI
I2SWS
(FSPH=0, FSLN=0)
tSFI
tHFI
I2SWS
(FSPH=1, FSLN=0)
tSFI
I2SWS
(FSPH=0, FSLN=1)
tSFI
I2SWS
(FSPH=1, FSLN=1)
tDDO
tDFB1
1
I2SDO
tSDI
tHDI
tSDI
tHDI
I2SDI
(SMPL=0)
tSDI
tHDI
I2SDI
(SMPL=1)
Notes:
− See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-
04862) for the details of FSPH, FSLN, SMPL
− I2SCK input is selectable polarity by CPOL bit of CNTREG register
I2SCK
I2SWS
I2SDI
0.8×VCC
0.8×VCC
0.2×VCC
0.8×VCC
0.2×VCC
tfi
tri
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S6E2C Series Datasheet
Page 169 of 200
S6E2C Series
I2SMCLK Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
Parameter
Input frequency
Symbol
Conditions
Unit
Remarks
Name
Min
Max
fCHS
I2SMCK
-
-
-
25
MHz
Input clock cycle
tCYLHS
-
tCFS
-
-
40
45
-
ns
%
PWHS/tCYLHS
PWLS/tCYLHS
When using
external clock
When using
external clock
Input clock pulse width
55
Input clock rise time and
fall time
-
-
-
5
ns
tCRS
tCYLHS
0.8×VCC
I2SMCLK
0.8×VCC
0.8×VCC
0.2×VCC
0.2×VCC
PWHS
PWLS
tCRS
tCFS
I2SMCLK Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
Parameter
Symbol
fCHS
Conditions
Unit
Remarks
Name
Min
Max
Output frequency
I2SMCK
-
-
12.288
MHz
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S6E2C Series Datasheet
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S6E2C Series
12.4.21 High-Speed Quad SPI Timing
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
When
RTM = 1 and
mode = 0, 1, 3
When
RTM = 1 and
mode = 2 or
RTM = 0 and
mode = 0, 1, 2, 3
Min
Max
CL = 15 pF,
VCC = 3.0 to 3.6V
-
66
MHz
Serial clock frequency
tSCYCM
Q_SCK_0
CL = 30 pF
-
50
MHz
Enabled CS→
CLK Starting Time
(mode0/mode2)
Enabled CS→
CLK Starting Time
(mode1/mode3)
CLK Last→
Disabled CS Time
(mode0/mode2)
CLK Last→
tOSLSK02
tOSLSK13
tOSKSL02
tOSKSL13
1.5×tSCYCM - 5
-
-
-
-
ns
ns
ns
Q_SCK_0,
Q_CS0_0,
Q_CS1_0,
Q_CS2_0
tSCYCM - 5
CL = 30 pF
tSCYCM
Disabled CS Time
(mode1/mode3)
1.5×tSCYCM
ns
ns
CL = 15 pF,
VCC = 3.0 to 3.6V
0
0
5
5
SIO Data output time
tOSDAT
CL = 30 pF
When
Q_SCK_0,
Q_IO0_0,
Q_IO1_0,
Q_IO2_0,
Q_IO3_0
3
-
ns
ns
RTM = 1 and
mode = 0, 1, 3
When
RTM = 1 and
mode = 2 or
RTM = 0 and
mode = 0, 1, 2, 3
SIO Setup
SIO Hold
tDSSET
CL = 30 pF
CL = 30 pF
10
-
-
tSDHOLD
0.5×tSCYCM
Notes:
− See Chapter 8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication Macro Part (002-
04862) for the detail of RTM mode.
− When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for
VCC = 3V. See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 171 of 200
S6E2C Series
Q_CS0,
Q_CS1,
Q_CS2
tSCYCM
mode0
mode2
tOSLSK02
tOSKSL02
Q_SCK
mode1
mode3
tOSKSL13
tOSLSK13
input
Q_IO0,
Q_IO1,
Q_IO2,
Q_IO3
tDSSET tSDHOLD
output
tOSDAT
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 172 of 200
S6E2C Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Value
Typ
Pin
Parameter
Resolution
Integral nonlinearity
Differential nonlinearity
Zero transition voltage
Symbol
Unit
Remarks
Name
Min
-
- 4.5
- 2.5
- 15
Max
12
+ 4.5
+ 2.5
+ 15
-
-
-
-
-
-
-
-
-
-
-
-
bit
LSB
LSB
mV
mV
mV
AVRH
= 2.7V to 5.5V
ANxx
VZT
AVRH – 15
AVCC - 15
AVRH + 15
AVCC + 15
Full-scale transition
voltage
ANxx
-
VFST
-
0.5145
-
-
μs
Conversion time
Sampling time146
AVCC ≥ 4.5V
0.15
0.3
25
-
-
-
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
tS
-
-
-
10
μs
1000
1000
Compare clock cycle147
tCCK
ns
μs
50
-
-
-
AVCC < 4.5V
State transition time to
operation permission
tSTT
1.0
A/D 1 unit
operation
-
-
0.69
1.3
0.92
22
mA
μA
Power supply current
(analog + digital)
-
AVCC
AVRH
When A/D stop
A/D 1 unit
operation
AVRH = 5.5V
-
1.1
1.97
mA
Reference power
supply current (AVRH)
-
-
-
0.3
-
6.3
μA
pF
When A/D stop
Analog input capacity
Analog input resistance
Interchannel disparity
Analog port input leak
current
-
-
12.05
1.2
1.8
4
CAIN
AVCC ≥ 4.5V
AVCC < 4.5V
-
-
kΩ
RAIN
-
-
-
-
-
-
-
LSB
μA
ANxx
5
-
-
-
-
-
AVRH
AVCC
AVCC
AVCC
AVSS
V
V
AVSS
AVSS
4.5
2.7
AVSS
Analog input voltage
-
ANxx
Tcck ＜50 ns
Tcck ≥ 50 ns
-
-
AVRH
AVRL
V
V
Reference voltage
145
The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (tS) and
compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The register
setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus number to which the A/D converter is connected, see
1 Block Diagram in this data sheet.
The sampling clock and compare clock are set at base clock (HCLK).
146
A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1).
The compare time (tC) is the value of (Equation 2).
147
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S6E2C Series Datasheet
Page 173 of 200
S6E2C Series
ANxx
Comparator
Analog input pin
RAIN
Rext
Analog signal
source
CAIN
(Equation 1) tS ≥ (RAIN + Rext) × CAIN × 9
tS: Sampling time
RAIN: Input resistance of A/D = 1.2 kΩ at 4.5V ≤ AVCC ≤ 5.5V
Input resistance of A/D = 1.8 kΩ at 2.7V ≤ AVCC < 4.5V
CAIN: Input capacity of A/D = 12.05 pF at 2.7V ≤ AVCC ≤ 5.5V
Rext: Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC: Compare time
tCCK: Compare clock cycle
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 174 of 200
S6E2C Series
Definition of 12-bit A/D Converter Terms
◼ Resolution:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
◼ Integral nonlinearity:
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
◼ Differential nonlinearity:
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral nonlinearity
Differential nonlinearity
0xFFF
Actual conversion
characteristics
Actual conversion
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
0x001
lly-measured value)
Analog input
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral nonlinearity of digital output N =
Differential nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
1LSB
- 1 [LSB]
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 175 of 200
S6E2C Series
12.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Typ
-
0.69
3.42
-
Pin
Parameter
Resolution
Symbol
Unit
Remarks
Name
Min
-
0.56
2.79
- 16
Max
12
0.81
4.06
+ 16
-
bit
μs
μs
tC20
tC100
INL
Load 20 pF
Load 100 pF
Conversion time
Integral nonlinearity148
Differential
LSB
DNL
VOFF
RO
DAx
- 0.98
-
+ 1.5
LSB
nonlinearity148
-
-
+ 10
+ 1.4
4.50
-
mV
mV
kΩ
When setting 0x000
When setting 0xFFF
D/A operation
Output voltage offset
- 20.0
3.10
2.0
-
3.80
-
Analog output
impedance
MΩ
When D/A stop
D/A 1ch operation AVCC
3.3V
D/A 1ch operation AVCC
5.0V
=
=
260
330
410
μs
IDDA
IDSA
Power supply current148
AVCC
400
-
510
-
620
14
μs
μs
When D/A stop
148
During no load
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 176 of 200
S6E2C Series
12.7 USB Characteristics
(VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit Reference
Min
2.0
Max
USBVCC
+ 0.3
0.8
Input H level voltage
VIH
VIL
VDI
-
-
-
V
V
V
1
1
2
Input L level voltage
Differential input
sensitivity
VSS - 0.3
0.2
Input
characteristics
-
Different common
mode range
VCM
-
0.8
2.8
2.5
V
V
2
3
External pull-
down
resistance =
15 kΩ
External pull-up
resistance =
1.5 kΩ
Output H level voltage
VOH
3.6
UDP0/
UDM0,
UDP1/
UDM1
Output L level voltage
VOL
0.0
0.3
V
3
Crossover voltage
Rise time
Fall time
Rise/fall time matching
VCRS
tFR
tFF
-
1.3
4
4
2.0
20
20
V
4
5
5
5
Output
characteristics
Full-Speed
Full-Speed
Full-Speed
ns
ns
%
tFRFM
90
111.11
Output impedance
ZDRV
Full-Speed
28
44
Ω
6
Rise time
tLR
Low-Speed
75
300
ns
7
Fall time
Rise/fall time matching
tLF
tLRFM
Low-Speed
Low-Speed
75
80
300
125
ns
%
7
7
References:
1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8V,
VIH (Min) = 2.0V (TTL input standard).
There is some hysteresis applied to lower noise sensitivity.
2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input
sensitivity when the differential data input is within 0.8V to 2.5V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 177 of 200
S6E2C Series
3: The output drive capability of the driver is below 0.3V at low state (VOL) (to 3.6V and 1.5 kΩ load), and 2.8V or
above (to the VSS and 1.5 kΩ load) at high state (VOH).
4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3V to 2.0V.
VCRS specified range
5: They indicate rise time (tRISE) and fall time (tFALL) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, tR/tF ratio is regulated as within ± 10% to minimize RFI emission.
D+
90%
90%
10%
10%
D-
TRISE
Rise time
TFALL
Falling time
Full-speed Buffer
Rs=27
Rs=27
TxD+
CL=50 pF
CL=50 pF
TxD-
3-State Enable
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 178 of 200
S6E2C Series
6: USB Full-speed connection is performed via twisted-pair cable shield with 90Ω ± 15% characteristic impedance
(differential mode).
USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a
discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence.”
7: They indicate rise time (tRISE) and fall time (tFALL) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
D+
90%
90%
10%
10%
D-
TRISE
Rise time
TFALL
Falling time
Note:
− See Low-Speed Load (Compliance Load) for conditions of external load.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 179 of 200
S6E2C Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL=50pF to 150pF
CL=50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL=
200pF to 600pF
CL=
200pF to 600pF
Low-Speed Load (Compliance Load)
CL=200pF to 450pF
CL=200pF to 450pF
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 180 of 200
S6E2C Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
Value
Typ
Parameter
Detected voltage
Released voltage
Symbol
VDL
Conditions
Unit
Remarks
Min
Max
When voltage
drops
When voltage
rises
-
-
2.46
2.55
2.60
2.64
V
V
VDH
2.51
2.69
12.8.2 Interrupt of Low-Voltage Detection
Value
Typ
Parameter
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Symbol
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
Conditions
Unit
V
Remarks
Min
Max
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
When voltage
drops
When voltage
rises
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.80
3.90
3.90
4.00
4.20
4.30
4.30
4.40
4.40
4.50
3.00
SVHI = 00111
2.90
2.99
3.09
3.18
3.28
3.67
3.76
3.76
3.86
4.05
4.15
4.15
4.25
4.25
4.34
3.11
3.21
3.31
3.42
3.52
3.93
4.04
4.04
4.14
4.35
4.45
4.45
4.55
4.55
4.66
V
V
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
V
V
V
V
V
V
V
V
V
V
V
V
SVHI = 11000
-
V
LVD stabilization wait
time
6000×tCYCP
-
-
μs
tLVDW
149
149
tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 181 of 200
S6E2C Series
12.9 MainFlash Memory Write/Erase Characteristics
Value
(VCC = 2.7V to 5.5V)
Parameter
Unit
Remarks
Min
Typ
Max
Large Sector
-
0.7
3.7
s
Sector erase
time
Includes write time prior to internal
erase
Small Sector
-
0.3
1.1
s
Write cycles < 100
times
Write cycles > 100
times
Half word (16-
bit)
write time
100
200
68
Not including system-level overhead
time
-
-
12
μs
s
Includes write time prior to internal
erase
Chip erase time150
13.6
Write Cycles and Data Retention Time
Erase/Write Cycles (Cycle)
Data Retention Time (Year)
1,000
10,000
100,000
20151
10151
5151
12.10 Dual Flash Memory Write/Erase Characteristics
It is the same write/erase characteristics as the MainFlash memory.
See 3.6 Dual flash mode in this product's Flash Programming Manual for the detail of dual flash mode.
150
It indicates the chip erase time of 1 MB MainFlash memory
For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required.
See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for the detail.
151
This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C).
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 182 of 200
S6E2C Series
12.11Standby Recovery Time
12.11.1 Recovery Cause: Interrupt/WKUP
The time from the interrupt occurring to the time of program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max152
Sleep mode
HCLK×1
μs
High-speed CR Timer mode
Main Timer mode
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
450
896
900
μs
μs
1136
RTC mode
Stop mode
tICNT
316
270
581
540
μs
μs
(High-speed CR/Main/PLL Run mode return)
RTC mode
Stop mode
(Low-speed CR/sub Run mode return)
without RAM
retention
with RAM
retention
365
365
667
667
μs
μs
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
Example of Standby Recovery Operation (when in External Interrupt Recovery153
)
Ext.INT
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
152
153
The maximum value depends on the built-in CR accuracy.
External interrupt is set to detecting fall edge.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 183 of 200
S6E2C Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery154
)
Internal
Resource INT
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
Notes:
− The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption mode and
Operations of Standby modes in FM4 Family Peripheral Manual Main Part (002-04856).
− The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
154
Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 184 of 200
S6E2C Series
12.11.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max155
Sleep mode
155
266
μs
High-speed CR Timer mode
Main Timer mode
155
266
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
315
315
315
567
567
567
μs
μs
μs
tRCNT
RTC mode
Stop mode
without RAM
retention
with RAM
retention
336
336
667
667
μs
μs
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Start
155
The maximum value depends on the built-in CR accuracy.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 185 of 200
S6E2C Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery156
)
Internal
Resource RST
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Start
Notes:
− The return factor is different in each low power consumption mode.
See Chapter 6: Low Power Consumption mode and Operations of Standby modes in “FM4 Family Peripheral Manual
Main Part (002-04856).
− The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
− When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On
Reset Timing.
− In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock, they
need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock.
− Internal resource reset indicates Watchdog reset and CSV reset.
156
Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the recovery cause.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 186 of 200
S6E2C Series
13.Ordering Information
S6E2
C
C 9 J0AGV 2000A
Package Identifier
Memory Size
Product Feature Set
C Series
Cypress FM 4 MCU
Flash
(MB)
RAM
(KB)
USB
2.0
CAN/
CAN FD
Ethernet-
MAC
Part Number
Package
1ch (max) MII:
1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
S6E2CC8H0AGV2000A
S6E2CC9H0AGV2000A
S6E2CCAH0AGV2000A
S6E2CC8J0AGV2000A
S6E2CC9J0AGV2000A
S6E2CCAJ0AGV2000A
S6E2CC8J0AGB1000A
S6E2CC9J0AGB1000A
S6E2CCAJ0AGB1000A
S6E2CC8L0AGL2000A
S6E2CC9L0AGL2000A
S6E2CCAL0AGL2000A
1
1.5
2
128
192
256
128
192
256
128
192
256
128
192
256
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
2ch/1ch
Plastic LQFP
(0.5 mm pitch),
144 pin
(LQS144)
1
Plastic LQFP
(0.5 mm pitch),
176 pin
1.5
2
(LQP176)
1
Plastic FBGA
(0.8 mm pitch),
192 pin
1.5
2
(LBE192)
1
Plastic LQFP
(0.4 mm pitch),
216 pin
1.5
2
(LQQ216)
RII: 1ch (max)
S6E2C58H0AGV2000A
S6E2C59H0AGV2000A
1
1.5
128
192
2ch
2ch
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C5AH0AGV2000A
2
256
2ch
2ch/1ch
N/A
(LQS144)
S6E2C58J0AGV2000A
S6E2C59J0AGV2000A
1
1.5
128
192
2ch
2ch
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C5AJ0AGV2000A
2
256
2ch
2ch/1ch
N/A
(LQP176)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 187 of 200
S6E2C Series
Flash
(MB)
RAM
(KB)
USB
2.0
CAN/
CAN FD
Ethernet-
MAC
Part Number
Package
S6E2C58J0AGB1000A
S6E2C59J0AGB1000A
1
1.5
128
192
2ch
2ch
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C5AJ0AGB1000A
2
256
2ch
2ch/1ch
N/A
(LBE192)
S6E2C58L0AGL2000A
S6E2C59L0AGL2000A
1
1.5
128
192
2ch
2ch
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C5AL0AGL2000A
2
256
2ch
2ch/1ch
N/A
(LQQ216)
S6E2C48H0AGV2000A
S6E2C49H0AGV2000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C4AH0AGV2000A
2
256
N/A
2ch/1ch
N/A
(LQS144)
S6E2C48J0AGV2000A
S6E2C49J0AGV2000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C4AJ0AGV2000A
2
256
N/A
2ch/1ch
N/A
(LQP176)
S6E2C48J0AGB1000A
S6E2C49J0AGB1000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C4AJ0AGB1000A
2
256
N/A
2ch/1ch
N/A
(LBE192)
S6E2C48L0AGL2000A
S6E2C49L0AGL2000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C4AL0AGL2000A
2
256
N/A
2ch/1ch
N/A
(LQQ216)
S6E2C38H0AGV2000A
S6E2C39H0AGV2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C3AH0AGV2000A
2
256
2ch
N/A
N/A
(LQS144)
S6E2C38J0AGV2000A
S6E2C39J0AGV2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C3AJ0AGV2000A
2
256
2ch
N/A
N/A
(LQP176)
S6E2C38J0AGB1000A
S6E2C39J0AGB1000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C3AJ0AGB1000A
2
256
2ch
N/A
N/A
(LBE192)
S6E2C38L0AGL2000A
S6E2C39L0AGL2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C3AL0AGL2000A
2
256
2ch
N/A
N/A
(LQQ216)
1ch (max)
MII: 1ch
S6E2C28H0AGV2000A
1
128
2ch
N/A
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C29H0AGV2000A
S6E2C2AH0AGV2000A
S6E2C28J0AGV2000A
S6E2C29J0AGV2000A
S6E2C2AJ0AGV2000A
1.5
2
192
256
128
192
256
2ch
2ch
2ch
2ch
2ch
N/A
N/A
N/A
N/A
N/A
(LQS144)
1
Plastic・LQFP
(0.65-mm pitch),
176 pin
1.5
2
RII: 1ch (max)
1ch (max)
MII: 1ch
(LQP176)
RII: 1ch (max)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 188 of 200
S6E2C Series
Flash
(MB)
RAM
(KB)
USB
2.0
CAN/
CAN FD
Ethernet-
MAC
Part Number
Package
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
S6E2C28J0AGB1000A
1
1.5
2
128
192
256
128
192
256
2ch
2ch
2ch
2ch
2ch
2ch
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C29J0AGB1000A
S6E2C2AJ0AGB1000A
S6E2C28L0AGL2000A
S6E2C29L0AGL2000A
S6E2C2AL0AGL2000A
(LBE192)
1
Plastic・LQFP
(0.4-mm pitch),
216 pin
1.5
2
(LQQ216)
RII: 1ch (max)
S6E2C18H0AGV2000A
S6E2C19H0AGV2000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C1AH0AGV2000A
2
256
N/A
N/A
N/A
(LQS144)
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C18J0AGV2000A
1
128
N/A
N/A
N/A
S6E2C19J0AGV2000A
S6E2C1AJ0AGV2000A
1.5
2
192
256
N/A
N/A
N/A
N/A
N/A
N/A
(LQP176)
S6E2C18J0AGB1000A
S6E2C19J0AGB1000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C1AJ0AGB1000A
2
256
N/A
N/A
N/A
(LBE192)
S6E2C18L0AGL2000A
S6E2C19L0AGL2000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
(LQQ216)
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C1AL0AGL2000A
2
256
N/A
N/A
N/A
S6E2C48J0AGB1000A
S6E2C49J0AGB1000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
S6E2C4AJ0AGB1000A
2
256
N/A
2ch/1ch
N/A
(LBE192)
S6E2C48L0AGL2000A
S6E2C49L0AGL2000A
1
1.5
128
192
N/A
N/A
2ch/1ch
2ch/1ch
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C4AL0AGL2000A
2
256
N/A
2ch/1ch
N/A
(LQQ216)
S6E2C38H0AGV2000A
S6E2C39H0AGV2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C3AH0AGV2000A
2
256
2ch
N/A
N/A
(LQS144)
S6E2C38J0AGV2000A
S6E2C39J0AGV2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C3AJ0AGV2000A
2
256
2ch
N/A
N/A
(LQP176)
S6E2C38J0AGB1000A
S6E2C39J0AGB1000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C3AJ0AGB1000A
2
256
2ch
N/A
N/A
(LBE192)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 189 of 200
S6E2C Series
Flash
(MB)
RAM
(KB)
USB
2.0
CAN/
CAN FD
Ethernet-
MAC
Part Number
Package
S6E2C38L0AGL2000A
S6E2C39L0AGL2000A
1
1.5
128
192
2ch
2ch
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C3AL0AGL2000A
2
256
2ch
N/A
N/A
(LQQ216)
1ch (max)
MII: 1ch
S6E2C28H0AGV2000A
1
128
2ch
N/A
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C29H0AGV2000A
S6E2C2AH0AGV2000A
S6E2C28J0AGV2000A
S6E2C29J0AGV2000A
S6E2C2AJ0AGV2000A
S6E2C28J0AGB1000A
S6E2C29J0AGB1000A
S6E2C2AJ0AGB1000A
S6E2C28L0AGL2000A
S6E2C29L0AGL2000A
S6E2C2AL0AGL2000A
1.5
2
192
256
128
192
256
128
192
256
128
192
256
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
2ch
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(LQS144)
1
Plastic・LQFP
(0.65-mm pitch),
176 pin
1.5
2
(LQP176)
1
Plastic・LQFP
(0.8-mm pitch),
192 pin
1.5
2
(LBE192)
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
RII: 1ch (max)
1ch (max)
MII: 1ch
1
Plastic・LQFP
(0.4-mm pitch),
216 pin
1.5
2
(LQQ216)
RII: 1ch (max)
S6E2C18H0AGV2000A
S6E2C19H0AGV2000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.5-mm pitch),
144 pin
S6E2C1AH0AGV2000A
2
256
N/A
N/A
N/A
(LQS144)
Plastic・LQFP
(0.65-mm pitch),
176 pin
S6E2C18J0AGV2000A
1
128
N/A
N/A
N/A
S6E2C19J0AGV2000A
S6E2C1AJ0AGV2000A
1.5
2
192
256
N/A
N/A
N/A
N/A
N/A
N/A
(LQP176)
S6E2C18J0AGB1000A
S6E2C19J0AGB1000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.8-mm pitch),
192 pin
S6E2C1AJ0AGB1000A
2
256
N/A
N/A
N/A
(LBE192)
S6E2C18L0AGL2000A
S6E2C19L0AGL2000A
1
1.5
128
192
N/A
N/A
N/A
N/A
N/A
N/A
Plastic・LQFP
(0.4-mm pitch),
216 pin
S6E2C1AL0AGL2000A
2
256
N/A
N/A
N/A
(LQQ216)
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 190 of 200
S6E2C Series
14.Acronyms
Acronym
ADC
Description
analog-to-digital converter
acknowledge
ACK
AHB
ARM®
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
Advanced RISC Machine, a CPU architecture
Consumer Electronics Control, a command and control interface over HDMI (High Definition Multimedia
Interface)
CEC
CMOS
CPU
CR
complementary metal oxide semiconductor
central processing unit
clock and reset
CRC
CSIO
CSV
cyclic redundancy check, an error-checking protocol
clock synchronous serial interface
clock supervisor
CTS
clear to send, a flow control signal in some data communication interfaces
descriptor system data transfer controller
end of message
DTSC
EOM
FIFO
GPIO
HDMI
HDMI-CEC
I/F
I2C, or IIC
I2S, or IIS
I/O
first in, first out
general-purpose input/output
High Definition Multimedia Interface
High Definition Multimedia Interface - Consumer Electronics Control, see CEC
interface
Inter-Integrated Circuit, a communications protocol
Inter-IC (integrated circuit) Sound, a communications protocol
input/output, see also GPIO
interrupt request
IRQ
LIN
LVD
Local Interconnect Network, a communications protocol
low-voltage detect
MFS
MSB
MTB
NMI
multi-function serial
most significant byte
micro trace buffer
non-maskable interrupt
NVIC
OS
nested vectored interrupt controller
operating system
OSC
PLL
oscillator
phase-locked loop
PPG
PWC
PWM
RAM
RX
programmable pulse generator
pulse-width counter
pulse-width modulator
random access memory
receive
RTS
SPI
SRAM
SW-DP
TX
request to send, a flow control signal in some data communication interfaces
Serial Peripheral Interface, a communications protocol
static random access memory
serial wire debug port
transmit
UART
USB
universal asynchronous receiver transmitter
Universal Serial Bus
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 191 of 200
S6E2C Series
15.Package Dimensions
Package Type
Package Code
Specification No.
LQFP 144
LQS 144
002-13015 *B
4
4
5
D
D
5
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
144
144
37
37
1
1
36
36
2
A-B
5
D
7
BOTTOM VIEW
e
3
0.10
C
0.20
C
A-B D
b
0.08
C
A-B
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
L
b
L1
10
A'
SECTION A-A'
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
22.00 BSC
20.00 BSC
0.50 BSC
D1
e
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 192 of 200
S6E2C Series
Package Type
Package Code
Specification No.
LQFP 176
LQP 176
002-15150 *A
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
7
4
3
6
176
45
45
176
1
44
44
1
e
2
A-B
5
7
D
3
0.10
A-B
C
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
θ
A
SEA TING
PLANE
A1
0.25
A'
b
SECTION A-A'
L1
10
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17
0.09
0.15
0.27
0.20
0.22
c
D
26.00 BSC
24.00 BSC
0.50 BSC
26.00 BSC
24.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0.75
0.70
L1
θ
0.50
0°
8°
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 193 of 200
S6E2C Series
Package Type
Package Code
Specification No.
LQFP 216
LQQ 216
002-15153 **
4
D
5
7
D1
162
109
109
162
163
108
108
163
E1
E
5
4
7
3
6
216
55
55
216
1
1
54
54
e
2
A-B
5
D
7
8
3
0.10
C
BOTTOM VIEW
0.20
C A-B D
0.07
C
A-B
D
b
TOP VIEW
2
A
c
9
θ
A
SEA TING
PLANE
A'
A1
10
b
0.25
0.08
C
L1
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.13 0.18 0.23
0.09 0.20
0.15
c
D
26.00 BSC.
24.00 BSC.
0.40 BSC
D1
e
E
26.00 BSC.
24.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
PACKAGE OUTLINE, 216 LEAD LQFP
24.0X24.0X1.7 MM LQQ216 REV**
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 194 of 200
S6E2C Series
Package Type
Package Code
Specification No.
PFBGA 192
LBE 192
002-13493 *A
A
0.20
2X
C
14
13
12
11
10
9
7
8
7
6
5
4
3
2
1
P
N
M
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
8
PIN A1
CORNER
B
7
192xφb
0.08
C A B
0.20
2X
C
6
TOPVIEW
BOTTOM VIEW
DETAIL A
C
0.10
C
SIDE VIEW
DETAIL A
NOTES
1. ALL DIMENSIONSARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
1.45
2. DIMENSIONSAND TOLERANCES METHODSPERASMEY14.5-2009.
THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.
4. "e" REPRESENTSTHE SOLDERBALLGRID PITCH.
A
D
E
0.25
0.35
12.00 BSC
12.00 BSC
10.40 BSC
10.40 BSC
14
0.45
1
5. SYMBOL "MD"ISTHE BALLMATRIX SIZE IN THE "D"DIRECTION.
SYMBOL "ME"ISTHE BALL MATRIX SIZE IN THE "E"DIRECTION.
n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX
SIZE MD X ME.
D
E
1
6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
1
MD
ME
n
7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND
DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.
WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"OR"SE"=0.
14
192
WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,
"SD"= eD/2 AND "SE" = eE/2.
Φb
eD
0.35
0.45
0.55
0.80 BSC
0.80 BSC
0.40 BSC
8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.
METALLIZED MARK INDENTATION OROTHERMEANS.
eE
9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.
SD /SE
PACKAGE OUTLINE, 192 BALLFBGA
12.00X12.00X1.45 MM LBE192 REV*A
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 195 of 200
S6E2C Series
16.Major Changes
Spansion Publication Number: DS709-00009
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 0.2
Added the following products.
S6E2CC8HHA/S6E2CC9HHA/S6E2CCAHHA/
S6E2CC8JHA/S6E2CC9JHA/S6E2CCAJHA/
S6E2CC8LHA/S6E2CC9LHA/S6E2CCALHA
1, 3
Title
Added “Crypto Assist Function”
Added “Crypto Assist Function”
14
2.Feature
16, 17
3.Product Lineup
Added the following products.
S6E2CC8HHA/S6E2CC9HHA/S6E2CCAHHA/
S6E2CC8JHA/S6E2CC9JHA/S6E2CCAJHA/
S6E2CC8LHA/S6E2CC9LHA/S6E2CCALHA
Added the following part numbers.
18
4.Packages
S6E2CC8HHAGV20000/S6E2CC9HHAGV20000/S6E2CCAHHAGV2000/
S6E2CC8JHAGV20000/S6E2CC9JHAGV20000/S6E2CCAJHAGV20000/
S6E2CC8JHAGB10000/S6E2CC9JHAGB10000/S6E2CCAJHAGB10000/
S6E2CC8LHAGL20000/S6E2CC9LHAGL20000/S6E2CCALHAGL20000
212
15.ORDERING INFORMATION
Revision 0.3
1, 3
Added the following products.
S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA
Title
14
2.Features
3.Product Lineup
Added Voice Function
Added the following products.
S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA
15, 16
Added the following products.
S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA
Added the following products.
17
4.Packages
S6E2CCAJGAGV20000/ S6E2CC8JGAGB10000/ S6E2CC8JFAGB10000
S6E2CCAJGAGB10000/ S6E2CCAJFAGB10000
211
15.Ordering Information
Revision 1.0
7
2. Features
3. Product Lineup
2. Features
3. Product Lineup
10. Block Diagram
12. Memory Map
Added that CAN-FD Interface supported non-CAN FD.
Deleted HDM-CEC/Remote Control Receiver.
15
12
15
90
91
Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1)
Modified the pin name of I2S. (MI2S*_0→MI2S*0_0)
18-20
5. Pin Assignments
Deleted the pin of IGTRG0_0.
Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1)
Modified the pin name of I2S. (MI2S*_0→MI2S*0_0)
22-24
75-82
6. Pin Descriptions
7. I/O Circuit Type
Modified the pin number of PF7 in LQFP216.(91→90)
Modified the pin number of X1. (73, 58, 50, P5→107, 87, 71, P13)
Modified the pin number of X0A. (107, 87, 71, P13→73, 58, 50, P5)
Modified IOH/IOL of Type S.(IOH=-12mA→-10mA, IOL=12mA→10mA)
Added the case of using I2C in Type E, F, G, L, N, S.
97-105
13. Pin Status In Each CPU State
14.1. Absolute Maximum Ratings
Deleted X and Y in Pin Status Type.
Added 10mA type.
106-107
Added AVRL in Analog reference voltage.
Modified the mistake in Ethernet-MAC Pins.
Modified the leakage current in Maximum leakage current at operating
14.2.
Conditions
Recommended
Operating
108-112
113-122
123-124
14.3.1. Current Rating
Modified the maximum current of each category.
Added the characteristic of external bus in H level input voltage (hysteresis
input).
14.3.2. Pin Characteristics
Added the characteristic of 10mA type.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 196 of 200
S6E2C Series
Page
Section
Change Results
14.4.5. Operating Conditions of
USB/Ethernet PLL・I2S PLL (in the Modified the maximum of I2S PLL macro oscillation clock frequency.
127
(307.2MHz→384MHz)
case of using main clock for input
clock of PLL)
Modified the minimum of Sampling time.
196
204
14.5.12-bit A/D Converter
Modified the characteristic of State transition time to operation permission
Added AVRL in Analog reference voltage.
14.8.2. Interrupt of Low-Voltage
Detection
Modified the SVHI values in Conditions
NOTE: Please see “Document History” for later revised information.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 197 of 200
S6E2C Series
Document History
Document Title: FM4: S6E2C Series Microcontroller Datasheet 200 MHz Arm® Cortex®-M4F High-Performance MCU
Document Number: 002-04980
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
-
AKIH
03/25/2015 New spec.
Company name and layout design change.
02/05/2016 Added the note of TAP pin.
*A
5126421
HITK
Updated Package Code and Dimensions (LQFP-144, LQFP-176, LQFP-216).
Updated “12.4.8 Power-On Reset Timing” to change parameter from “Power Supply
rise time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some
comments.
Modified typos in “12.4.12 CSIO (SPI) Timing”. Deleted “SPI=1, MS=0” in the
titles and added MS=0,1 in the schematic
Modified Real-Time Clock(RTC) in “Features”
Changed starting count value from 01 to 00. Deleted “second, or day of the week”
in the Interrupt function.
Modifications related to the VBAT in the following chapter.
“8 Handling Devices” Notes on Power-on “11. Pin Status in Each CPU State” List
of VBAT Domain Pin Status “12.3.1 Current Rating”
Deleted descriptions about Voice function
Deleted MPNs below from “13. Ordering Information”
S6E2CCAJGAGV20000, S6E2CC8JGAGB10000, S6E2CC8JFAGB10000,
S6E2CCAJGAGB10000, S6E2CCAJFAGB10000
S6E2CC8H0AGV20000, S6E2CC9H0AGV20000, S6E2CCAH0AGV20000,
S6E2CC8HHAGV20000, S6E2CC9HHAGV20000, S6E2CCAHHAGV20000,
S6E2CC8J0AGV20000, S6E2CC9J0AGV20000, S6E2CCAJ0AGV20000,
S6E2CC8JHAGV20000, S6E2CC9JHAGV20000, S6E2CCAJHAGV20000,
S6E2CC8J0AGB10000, S6E2CC9J0AGB10000, S6E2CCAJ0AGB10000,
S6E2CC8JHAGB10000, S6E2CC9JHAGB10000, S6E2CCAJHAGB10000,
S6E2CC8L0AGL20000, S6E2CC9L0AGL20000, S6E2CCAL0AGL20000,
S6E2CC8LHAGL20000, S6E2CC9LHAGL20000, S6E2CCALHAGL20000
Added MPNs below to “13. Ordering Information”
*B
5634625
YSKA
02/20/2017
S6E2CC8H0AGV2000A, S6E2CC9H0AGV2000A, S6E2CCAH0AGV2000A,
S6E2CC8HHAGV2000A, S6E2CC9HHAGV2000A, S6E2CCAHHAGV2000A,
S6E2CC8J0AGV2000A, S6E2CC9J0AGV2000A, S6E2CCAJ0AGV2000A,
S6E2CC8JHAGV2000A, S6E2CC9JHAGV2000A, S6E2CCAJHAGV2000A,
S6E2CC8J0AGB1000A, S6E2CC9J0AGB1000A, S6E2CCAJ0AGB1000A,
S6E2CC8JHAGB1000A, S6E2CC9JHAGB1000A, S6E2CCAJHAGB1000A,
S6E2CC8L0AGL2000A, S6E2CC9L0AGL2000A, S6E2CCAL0AGL2000A,
S6E2CC8LHAGL2000A, S6E2CC9LHAGL2000A, S6E2CCALHAGL2000A
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 198 of 200
S6E2C Series
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12 CSIO (SPI)
Timing”
Modified the expression of the “Built-in CR” and add Note in the “2. Product Lineup”
Modified typo(SCLKx_0 -> SCKx_0)
Change the name from “USB Function” to “USB Device”
Added Maximum Access size in “Features”
Updated IO circuit (type A)
Completing Sunset Review.
Updated Document Title to read as “FM4: S6E2C Series Microcontroller Datasheet
200 MHz ARM Cortex-M4F High-Performance MCU”.
Merged S6E2CC, S6E2C5, S6E2C4, S6E2C3, S6E2C2, and S6E2C1 datasheets.
Recreated Pin Assignments drawings using only the pin names and added a pin
multiplexing table that shows alternative functions. Added navigation aids to tables
with hyperlinks to circuit types and pin behavior. Added part differentiation tables at
the beginning of the document and reorganized the front of the datasheet to match
Cypress specifications. Replaced table footnotes with continuous footnote
numbering (throughout). Added and expanded Ordering Information table. Added
the Acronyms table. Updated Package Outlines in 15 Package Dimensions to
latest. Changed Typ to Max in 12.4.7 Reset Input Characteristics, 12.4.8 Power-On
Reset Timing, and 12.4.9 GPIO Output Characteristics.
*C
6110443
MBGR
03/26/2018
Removed Crypo function and part numbers that supported Crypto.
Completing Sunset Review.
*D
6579097
HUAL
05/22/2019 Updated to new template.
Updated Block diagram.
Updated Pin Description:
Updated pin description of pin 25 and 26 corresponding to LQQ216 package.
Updated Package Dimensions:
05/10/2023 Spec 002-13015 – Changed revision from *A to *B.
Spec 002-15150 – Changed revision from ** to *A.
Updated some format issues across the document.
Updated links across the document.
*E
7901049
BOO
Completing Sunset Review.
Document Number: 002-04980 Rev. *E
S6E2C Series Datasheet
Page 199 of 200
S6E2C Series
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Document Number: 002-04980 Rev. *E
May 10, 2023
Page 200 of 200
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