S6E2GK6J0AGV20000 [INFINEON]
FM4 S6E2G-Series Connectivity Arm® Cortex®-M4 Microcontroller (MCU) Family;
| 型号： | S6E2GK6J0AGV20000 |
| 厂家： | 
Infineon |
| 描述： | FM4 S6E2G-Series Connectivity Arm® Cortex®-M4 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总191页 (文件大小：3571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S6E2G Series
32-bit Arm® Cortex®-M4F
FM4 Microcontroller
S6E2G Series are FM4 devices with up to 180 MHz CPU, 1 MB flash, 192 KB SRAM, 20x communication peripherals, 33x digital
peripherals and 3x analog peripherals. They are designed for industrial automation and metering applications.
Devices in the S6E2G Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is
based on the Arm® Cortex®-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor control
timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that are described in
this data sheet are placed into TYPE5-M4 product categories in the "FM4 Family Peripheral Manual Main Part (002-04856)”.
Features
32-bit Arm Cortex-M4F Core
Watch Counter
Up to 180 MHz frequency operation
External Interrupt Controller Unit
On-chip Memories
Flash memory: Up to 1024 Kbytes
SRAM memory:
• SRAM0: up to 128 Kbytes
• SRAM1: 32 Kbytes
Watchdog Timer (Two channels)
Cyclic Redundancy Check (CRC) Accelerator
SD Card Interface Available on S6E2GM, S6E2GH, and
S6E2GK Devices Only
• SRAM2: 32 Kbytes
Ethernet-MAC Available on S6E2GM, S6E2GK, and
Direct Memory Access (DMA) Controller (Eight Channels)
S6E2G2 Devices only
Descriptor System Data Transfer Controller (DSTC);
Smartcard Interface (Max 2 channels)
Five Clock Sources
256 channels
External Bus Interface
Six Reset Sources
USB Interface (Max two channels): Host and Device
Clock Supervisor (CSV)
Low-Voltage Detector (LVD)
CAN Interface (Max one channel) Available on S6E2GM
and S6E2GH Devices Only
Multi-function Serial Interface (Max 10 Channels)
UART (Universal Asynchronous Receiver/Transmitter)
Clock Synchronous Serial Interface (CSIO (SPI))
Local Interconnect Network (LIN)
Six Low-power Consumption Modes
Sleep
Timer
RTC
Stop
Deep standby RTC
Deep standby stop
Inter-Integrated Circuit (I2C)
Inter-IC Sound (I2S)
Base Timer (Max 16 channels)
General Purpose I/O Port
Up to 121 high-speed general-purpose I/O ports in 144-pin
package
Up to 153 high-speed general-purpose I/O ports in 176-pin
package
Peripheral Clock Gating System
Crypto Assist Function
Debug
Serial wire JTAG debug port (SWJ-DP)
Embedded trace macrocells (ETM) provide comprehensive
Multi-function Timer (Max two units)
Real-Time Clock (RTC)
debug and trace facilities.
AHB trace macrocells (HTM)
41-bit Unique ID
Analog to Digital Converter (ADC) (Max 32 Channels)
Dual Timer (32-/16-bit Down Counter)
Wide range voltage: VCC = 2.7 to 5.5 V
Quadrature Position/Revolution Counter (QPRC; Max two
channels)
Cypress Semiconductor Corporation
Document Number: 001-98708 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 24, 2019
S6E2G Series
Ecosystem for Cypress FM4 MCUs
Cypress provides a wealth of data at www.cypress.com to help you to select the right MCU for your design, and to help you to
quickly and effectively integrate the device into your design. Following is an abbreviated list for FM4 MCUs:
Overview: Product Portfolio, Product Roadmap
a Base Timer: Cypress FM4 Family of 32-bit Arm®
Product Selectors: FM4 MCUs
AN99235 - FM4 S6E2HG Series MCU - 16-Bit PWM Using
Cortex®-M4 Microcontrollers FM4 S6E2H Series Motor
Control Arm® Cortex®-M4 MCU
Application notes: Cypress offers a large number of FM4
application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes
for getting started with FM4 family of MCUs are:
AN204468 - FM4 I2S USB MP3 Player Application 32-Bit
Microcontroller FM4 Family: This application note
describes the general structure of the I²S USB MP3Player
software example, its single modules in detail and how it is
used.
AN204471 - FM4 S6E2CC Series External Memory
Programmer: This document describes use of the MCU
Universal Programmer as an off-line programmer for Quad
SPI flash memory programming on the S6E2CC Series
SK.
AN203277 - FM 32-Bit Microcontroller Family Hardware
Design Considerations: This application note reviews
several topics for designing a hardware system around
FM0+, FM3, and FM4 family MCUs. Subjects include
power system, reset, crystal, and other pin connections,
and programming and debugging interfaces.
AN202487 - Differences Among FM0+, FM3, and FM4
32-Bit Microcontrollers: Highlights the peripheral
differences in Cypress’s FM family MCUs. It provides
dedicated sections for each peripheral and contains lists,
tables, and descriptions of peripheral feature and register
differences.
AN204438 - How to Setup Flash Security for FM0+, FM3
and FM4 Families: This application note describes how to
setup the Flash Security for FM0+, FM3, and FM4 devices
Development kits:
FM4-U120-9B560 - Arm® Cortex®-M4 MCU Starter Kit
with USB and CMSIS-DAP
FM4-216-ETHERNET Arm® Cortex®-M4 MCU
Development Kit with Ethernet, CAN and USB Host
FM4-176L-S6E2CC-ETH - Arm® Cortex®-M4 MCU Starter
Kit with Ethernet and USB Host
FM4-176L-S6E2GM - Arm® Cortex®-M4 MCU Pioneer Kit
with Ethernet and USB Host
AN202488 - FM4 MB9BF56x and S6E2HG Series MCU -
Servo Motor Speed Control: This document covers servo
motor speed control solution on FM4 MCU - MB9BF56x
and S6E2HG.
Peripheral Manuals
Document Number: 001-98708 Rev. *E
Page 2 of 190
S6E2G Series
12.4.7 Reset Input Characteristics............................. 106
12.4.8 Power-On Reset Timing.................................. 107
12.4.9 GPIO Output Characteristics........................... 107
12.4.10 External Bus Timing........................................ 108
12.4.11 Base Timer Input Timing................................. 119
12.4.12 CSIO (SPI) Timing .......................................... 120
12.4.13 External Input Timing...................................... 153
12.4.14 Quadrature Position/Revolution Counter Timing
........................................................................ 154
12.4.15 I2C Timing ....................................................... 157
12.4.16 SD Card Interface Timing................................ 160
12.4.17 ETM/ HTM Timing........................................... 162
12.4.18 JTAG Timing................................................... 164
12.4.19 Ethernet-MAC Timing ..................................... 165
12.4.20 I2S Timing (Multi-function Serial Interface)...... 170
12.5 12-bit A/D Converter.......................................... 171
12.6 USB Characteristics........................................... 175
12.7 Low-Voltage Detection Characteristics.............. 179
12.7.1 Low-Voltage Detection Reset.......................... 179
12.7.2 Interrupt of Low-Voltage Detection.................. 179
12.8 MainFlash Memory Write/Erase Characteristics
........................................................................... 180
Table of Contents
1.
S6E2G Series Block Diagram................................ 4
Product Lineup....................................................... 5
Package-Dependent Features............................... 7
Product Features in Detail..................................... 8
Pin Assignments.................................................. 12
Pin Descriptions................................................... 14
I/O Circuit Type..................................................... 54
Handling Precautions .......................................... 63
Precautions for Product Design........................... 63
Precautions for Package Mounting...................... 64
Precautions for Use Environment........................ 66
Handling Devices ................................................. 67
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
8.3
9.
10. Memory Map ......................................................... 70
11. Pin Status in Each CPU State.............................. 74
12. Electrical Characteristics .................................... 84
12.1 Absolute Maximum Ratings................................. 84
12.2 Recommended Operating Conditions ................. 86
12.3 DC Characteristics .............................................. 91
12.3.1 Current Rating .................................................. 91
12.3.2 Pin Characteristics.......................................... 101
12.4 AC Characteristics............................................. 103
12.4.1 Main Clock Input Characteristics .................... 103
12.4.2 Sub Clock Input Characteristics...................... 104
12.4.3 Built-In CR Oscillation Characteristics ............ 104
12.4.4 Operating Conditions of Main PLL (in the Case of
Using Main Clock for Input Clock of PLL) ....... 105
12.9 Standby Recovery Time .................................... 181
12.9.1 Recovery Cause: Interrupt/WKUP .................. 181
12.9.2 Recovery Cause: Reset .................................. 183
13. Ordering Information.......................................... 185
14. Package Dimensions.......................................... 186
Document History....................................................... 188
Worldwide Sales and Design Support....................... 190
12.4.5 Operating Conditions of USB/Ethernet PLL (in the
Case of Using Main Clock for Input Clock of PLL)
....................................................................... 105
12.4.6 Operating Conditions of Main PLL (in the Case of
Using Built-in High-Speed CR Clock for Input Clock
of Main PLL) ................................................... 106
Document Number: 001-98708 Rev. *E
Page 3 of 190
S6E2G Series
1. S6E2G Series Block Diagram
Document Number: 001-98708 Rev. *E
Page 4 of 190
S6E2G Series
2. Product Lineup
Memory Size
Product Name
S6E2GM6
S6E2GK6
S6E2GH6
S6E2G36
S6E2G26
S6E2GM8
S6E2GK8
S6E2GH8
S6E2G38
S6E2G28
Memory Type
On-chip flash
memory
512 Kbytes
1024 Kbytes
SRAM
128 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
192 Kbytes
128 Kbytes
32 Kbytes
32 Kbytes
SRAM0
On-chip
SRAM1
SRAM2
Function Availability by Part
Description
Product Name
S6E2GM6
S6E2GM8
S6E2GK6
S6E2GK8
S6E2GH6
S6E2GH8
S6E2G36
S6E2G38
S6E2G26
S6E2G28
Cortex-M4F, MPU, NVIC 128 ch
CPU
Freq.
180 MHz
Power supply voltage
range
2.7 V to 5.5 V
2 ch
USB2.0 (Device/Host)
1 ch. (Max)
MII: 1 ch /
1ch. (Max)
MII: 1 ch /
Ethernet-MAC
N/A
RMII: 1 ch (Max)
RMII: 1 ch (Max)
CAN
1 ch (Max)
N/A
1 unit
1 ch (Max)
N/A
N/A
SD card interface
DMAC
8 ch
DSTC
256 ch
Addr: 25-bit (Max),
Data: 8-/16-bit
CS: 9 (Max),
SRAM,
External bus interface
NOR flash
NAND flash
SDRAM
Multi-function serial
interface
10ch (Max)
ch 1, ch 4 to ch 7: FIFO,
(UART/CSIO(SPI)/LIN/I2C
/I2S)
ch 0, ch 2, ch3, ch 8 to ch 15: No FIFO
ch 1: I2S
Document Number: 001-98708 Rev. *E
Page 5 of 190
S6E2G Series
Product Name
Description
S6E2GM6
S6E2GM8
S6E2GK6
S6E2GK8
S6E2GH6
S6E2GH8
S6E2G36
S6E2G38
S6E2G26
S6E2G28
Base timer
(PWC/Reload
16 ch (Max)
timer/PWM/PPG)
A/D
activation
compare
6 ch
Input
capture
4 ch
3 ch
6 ch
Free-run
timer
2 units (Max)
Output
compare
Waveform
generator
3 ch
3 ch
PPG
Smartcard (ISO7816)
QPRC
2 ch (Max)
2 ch (Max)
1 unit
Dual timer
Real-time clock
Watch counter
1 unit
1 unit
CRC accelerator
Yes (fixed)
1 ch (SW) + 1 ch (HW)
32 pins (Max)+ NMI × 1
Yes
Watchdog timer
External interrupts
CSV (clock supervisor)
LVD (low-voltage
detector)
2 ch
High-speed
Built-in CR
4 MHz
100 kHz
Low-speed
Debug function
Unique ID
SWJ-DP/ETM/HTM
Yes
*1: Crypto Assist Function is built in following products.
S6E2GM6HHA, S6E2GM8HHA, S6E2GM6JHA, S6E2GM8JHA
Notes:
−
Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully
work out the pin allocation needed for your design.
You must use the port relocate function of the I/O port according to your function use.
−
See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR.
Document Number: 001-98708 Rev. *E
Page 6 of 190
S6E2G Series
3. Package-Dependent Features
All S6E2G Series of parts are available in both 144-pin LQFP and 176-pin LQFP.
Base Part Number
S6E2G
Description
Package Suffix
H0A
HHA*
J0A
JHA*
LQFP: (0.5 mm pitch)
I/O Ports
144 pins
176 pins
121 pins (Max)
24 (3 units)
153 pins (Max)
32 ch (3 units)
12-bit ADC converter
Crypto Assist Function
—
Yes
—
Yes
*HHA and JHA parts have the Crypto Assist Function built in. HHA and JHA options are not available for the S6E2GH or S6E2G3
parts. The HHA and JHA options are available on the S6E2GM, S6E2GK, and S6E2G2 parts.
Notes:
−
For an explicit list of part numbers and the feature differences among them, see 13. Ordering Information
−
See 14. Package Dimensions for detailed information on each package.
Document Number: 001-98708 Rev. *E
Page 7 of 190
S6E2G Series
• EndPoint 0 is control transfer
4. Product Features in Detail
• EndPoint 1,2 can be selected bulk-transfer, interrupt-
transfer or isochronous-transfer
32-bit Arm Cortex-M4F Core
Up to 180 MHz frequency operation
FPU built-in
• EndPoint 3 to 5 can select bulk-transfer or interrupt-
transfer
EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 byte
• EndPoint 1: 256 byte
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
USB Host
USB2.0 Full-Speed/Low-Speed supported
Bulk-transfer, interrupt-transfer, and isochronous-
transfer support
USB Device connected/dis-connected automatically
detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
embedded system
Integrated nested vectored interrupt controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
On-chip Memories
Flash memory
This series is on-chip flash memories.
CAN Interface (Max one channel) Available on
S6E2GM and S6E2GH Devices Only
Up to 1024 Kbytes
Built-in flash accelerator for zero wait state
Security function for code protection
Compatible with CAN specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32-message buffer
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2
are connected to system bus of Cortex-M4F core.
Multi-function Serial Interface (Max 10 Channels)
Separate 64 byte receive and transmit FIFO buffers for
channels 1 and channels 4 to 7.
SRAM0: up to 128 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
Operation mode is selectable for each channel from the
following:
UART
CSIO (SPI)
LIN
I2C
I2S
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
UART
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
CSIO (SPI)
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch 6 and ch 7 only)
Supports high-speed SPI (ch 4 and ch 6 only)
Data length 5 to 16-bit
USB Interface (Max two channels)
The USB interface is composed of a Device and a Host.
LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/slave mode supported
LIN break field generation (can change to 13- to 16-bit
length)
USB Device
USB 2.0 Full-speed supported
Max 6 EndPoint supported
Document Number: 001-98708 Rev. *E
Page 8 of 190
S6E2G Series
LIN break delimiter generation (can change to 1- to 4-bit
16-bit PPG timer
length)
16-/32-bit reload timer
16-/32-bit PWC timer
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I2C
Event counter mode (External clock mode)
Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps)
supported
General Purpose I/O Port
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals;
moreover, the port relocate function is built in. It can set the
I/O port to which the peripheral function can be allocated.
and ch 7 = ch B) supported
I2S
Using CSIO (SPI) (ch 1 only) and I2S clock generator
Supports two transfer protocol: I2S and MSB-justified
Master mode only
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port-relocate function
DMA Controller (Eight Channels)
DMA controller has an independent bus, so the CPU and
Up to 121 high-speed general-purpose I/O ports in 144-pin
DMA controller can process simultaneously.
package
Eight independently configured and operated channels
Some pins 5 V tolerant I/O.
Transfer can be started by software or request from the
built-in peripherals
See 6. Pin Descriptions and 7. I/O Circuit Type for the
corresponding pins.
Transfer address area: 32-bit (4 GB)
Multi-function Timer (Max two units)
The multi-function timer is composed of the following blocks:
Minimum resolution: 5.56 ns
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Number of transfers: 1 to 65536
Output compare × 6 ch/unit
A/D activation compare × 6 ch/unit
Waveform generator × 3 ch/unit
DSTC (Descriptor System Data Transfer Controller;
256 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can access directly
the memory/peripheral device and perform the data-transfer
operation.
16-bit PPG timer × 3 ch/unit
The following functions can be used to achieve the motor
control:
PWM signal output function
DC chopper waveform output function
Dead time function
It supports the software activation, the hardware activation,
and the chain activation functions.
Input capture function
A/D convertor activate function
DTIF (motor emergency stop) interrupt function
A/D Converter (Max 32 Channels)
12-bit A/D Converter
Successive approximation type
Real-Time Clock (RTC)
Built-in three units
The real-time clock can count year, month, day, hour, minute,
Conversion time: 0.5 μs at 5 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: 4 steps)
second, or day of the week from 00 to 99.
Interrupt function with specifying date and time
(year/month/day/hour/minute) is available. This function is
also available by specifying only year, month, day, hour, or
minute.
Base Timer (Max 16 channels)
Operation mode is selected from the following for each
channel:
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
16-bit PWM timer
Document Number: 001-98708 Rev. *E
Page 9 of 190
S6E2G Series
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 generator polynomial: 0x1021
Quadrature Position/Revolution Counter (QPRC;
Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. It is also
possible to use up/down counter.
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
SD Card Interface Available on S6E2GM, S6E2GH,
and S6E2GK Devices Only
It is possible to use the SD card that conforms to the
The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
following standards.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
3.00
1-bit or 4-bit data bus
Operation mode is selectable from the following for each
channel:
Ethernet-MAC Available on S6E2GM, S6E2GK, and
S6E2G2 Devices only
Free-running
Periodic (= Reload)
One shot
Compliant with IEEE802.3 specification
10 Mbps/100 Mbps data transfer rates supported
MII/RMII for external PHY device supported.
MII: Max one channel
Watch Counter
RMII: Max one channel
The watch counter is used for wake up from low-power
consumption mode. It is possible to select the main clock,
sub clock, built-in High-speed CR clock, or built-in low-speed
CR clock as the clock source.
Full-duplex and half-duplex mode supported.
Wake-ON-LAN supported
Built-in dedicated descriptor-system DMAC
Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO.
Compliant IEEE1558-2008 (PTP)
Interval timer: up to 64 s (max) with a sub clock of 32.768
kHz
External Interrupt Controller Unit
Smartcard Interface (Max 2 channels)
Compliant with ISO7816-3 specification
Card Reader only/B class card only
External interrupt input pin: Max 32 pins
Both edges(Rise edge and Fall edge) detect
Include one non-maskable interrupt (NMI)
Available protocols
Transmitter: 8E2, 8O2, 8N2
Receiver: 8E1, 8O1, 8N2, 8N1, 9N1
Inverse mode
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes)
This series consists of two different watchdogs: a "hardware"
watchdog and a "software" watchdog.
Clock and Reset
Clocks
The hardware watchdog timer is clocked by low-speed
internal CR oscillator. The hardware watchdog is thus active
in any power saving mode except RTC mode and Stop mode.
Five clock sources (two external oscillators, two internal CR
oscillators, and Main PLL) that are dynamically selectable.
Main clock: 4 MHz to 48 MHz
Sub clock: 30 kHz to 100 kHz
High-speed internal CR clock: 4 MHz
Low-speed internal CR clock: 100 kHz
Main PLL Clock
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator helps to verify data transmission or
storage integrity.
Document Number: 001-98708 Rev. *E
Page 10 of 190
S6E2G Series
Resets
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detector reset
Clock supervisor reset
Crypto Assist Function
These features are enabled for the crypto assist function.
The dedicated middleware is necessary for this calculator
operation.
PKA (Public Key Accelerator)
PKA（Public Key Accelerator）is modular exponentiation
calculation accelerator used of RSA Public Key crypto and
so on.
Clock Supervisor (CSV)
Clocks generated by internal CR oscillators are used to
Available bit length: Up to 2048-bit
supervise abnormality of the external clocks.
AES calculator
AES (Advanced Encryption Standard) calculator is a AES
common key crypto accelerator which is compliant with
FIPS (Federal Information Processing Standard
Publication)197.
Available key length: 128/192/256-bit
CBC mode and ECB mode support
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
External Bus Data Scramble
It enables to scramble input/output data of External Bus
This Series include two-stage monitoring of voltage on the
VCC pins. When the voltage falls below the voltage that has
been set, the low-voltage detector function generates an
interrupt or reset.
Interface.
Debug
Serial wire JTAG debug port (SWJ-DP)
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Embedded trace macrocells (ETM) provide comprehensive
debug and trace facilities.
AHB trace macrocells (HTM)
Low-power Consumption Mode
Six low power consumption modes are supported.
Unique ID
Unique value of the device (41-bit) is set.
Sleep
Timer
RTC
Stop
Power Supply
Four power supplies
Wide range voltage:
VCC = 2.7 V to 5.5 V
Deep standby RTC (selectable from with/without RAM
retention)
Power supply for USB ch 0 I/O: USBVCC0
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for USB ch 1 I/O: USBVCC1
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Deep standby stop (selectable from with/without RAM
retention)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral
functions not used.
Power supply for Ethernet-MAC I/O: ETHVCC
= 3.0 V to 5.5 V (when Ethernet is used.)
Document Number: 001-98708 Rev. *E
Page 11 of 190
S6E2G Series
5. Pin Assignments
LQS144
Note:
−
Only the GPIO function is shown on GPIO pins. See the table in Pin Descriptions for the full, multiplexed signal name.
Document Number: 001-98708 Rev. *E
Page 12 of 190
S6E2G Series
LQP176
Note:
−
Only the GPIO function is shown on GPIO pins. See the table in Pin Descriptions for the full, multiplexed signal name.
Document Number: 001-98708 Rev. *E
Page 13 of 190
S6E2G Series
6. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
1
1
VCC
PA0
-
-
RTO00_1
(PPG00_1)
TIOA8_0
INT00_0
2
2
E
K
MADATA00_0
IC0_CIN_0
PA1
RTO01_1
(PPG01_1)
3
4
5
6
3
4
5
6
E
E
E
E
I
I
I
I
TIOA9_0
MADATA01_0
IC0_DATA_0
PA2
RTO02_1
(PPG02_1)
TIOA10_0
MADATA02_0
IC0_RST_0
PA3
RTO03_1
(PPG03_1)
TIOA11_0
MADATA03_0
IC0_VPEN_0
PA4
RTO04_1
(PPG04_1)
TIOA12_0
MADATA04_0
IC0_VCC_0
PA5
RTO05_1
(PPG05_1)
TIOA13_0
INT01_0
7
7
E
K
MADATA05_0
IC0_CLK_0
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Page 14 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PA6
DTTI0X_1
INT00_2
MADATA06_0
PA7
8
8
E
E
E
K
K
I
IC00_1
INT02_2
MADATA07_0
RTCCO_1
SUBOUT_1
P50
9
9
SCS72_0
IC01_1
10
-
TIOA8_2
P51
SCS73_0
IC02_1
11
12
-
-
E
E
I
I
TIOB8_2
P52
IC03_1
TIOA9_2
PA8
SIN7_0
FRCK0_1
13
10
I
Q
INT02_0
WKUP1
MADATA08_0
PA9
SOT7_0
(SDA7_0)
14
15
11
12
N
N
I
I
AIN1_1
MADATA09_0
PAA
SCK7_0
(SCL7_0)
BIN1_1
MADATA10_0
PAB
SCS70_0
ZIN1_1
16
17
13
14
E
E
K
I
INT03_0
MADATA11_0
PAC
SCS71_0
TIOB8_0
MADATA12_0
Document Number: 001-98708 Rev. *E
Page 15 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PAD
SCK3_0
(SCL3_0)
18
19
15
N
N
I
I
TIOB9_0
MADATA13_0
PAE
ADTG_0
SOT3_0
(SDA3_0)
16
TIOB10_0
MADATA14_0
PAF
SIN3_0
20
21
17
18
TIOB11_0
INT16_0
MADATA15_0
P08
I
K
K
TIOB12_0
E
INT17_0
MDQM0_0
P09
TIOB13_0
22
23
19
20
E
L
K
I
INT18_0
MDQM1_0
P0A
ADTG_1
MCLKOUT_0
P30
MI2SWS1_1
24
25
-
-
RX0_1
E
E
K
TIOB11_2
INT01_2
P31
MI2SMCK1_1
TX0_1
I
TIOA12_2
P32
26
27
21
22
INT19_0
S_DATA1_0
P33
L
L
K
I
FRCK0_0
S_DATA0_0
Document Number: 001-98708 Rev. *E
Page 16 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P34
IC03_0
INT00_1
S_CLK_0
VCC
28
23
L
K
29
30
24
25
-
-
-
-
VSS
P35
IC02_0
INT01_1
S_CMD_0
P36
31
32
26
27
L
L
K
K
IC01_0
INT02_1
S_DATA3_0
P37
IC00_0
33
34
28
29
L
K
I
INT03_1
S_DATA2_0
P38
ADTG_2
E
DTTI0X_0
S_WP_0
P39
RTO00_0
(PPG00_0)
TIOA0_1
AIN1_0
INT16_1
S_CD_0
MAD24_0
P3A
35
30
G
K
RTO01_0
(PPG01_0)
TIOA1_1
BIN1_0
INT17_1
MAD23_0
P3B
36
37
31
32
G
G
K
K
RTO02_0
(PPG02_0)
TIOA2_1
ZIN1_0
INT18_1
MAD22_0
Document Number: 001-98708 Rev. *E
Page 17 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P3C
SIN2_1
RTO03_0
(PPG03_0)
38
39
33
G
G
K
TIOA3_1
INT19_1
MAD21_0
P3D
SOT2_1
(SDA2_1)
34
RTO04_0
I
(PPG04_0)
TIOA4_1
MAD20_0
P3E
SCK2_1
(SCL2_1)
40
41
35
RTO05_0
(PPG05_0)
G
E
I
TIOA5_1
MAD19_0
P5D
SIN1_1
-
MI2SDI1_1
TIOB12_2
INT03_2
P5E
K
SOT1_1
(SDA1_1)
42
43
-
-
E
E
I
I
MI2SDO1_1
TIOA13_2
P5F
SCK1_1
(SCL1_1)
MI2SCK1_1
TIOB13_2
VSS
44
45
36
37
-
-
-
-
VCC
P40
SIN7_1
RTO10_0
(PPG10_0)
46
38
G
K
TIOA0_0
AIN0_0
INT23_0
MCSX7_0
Document Number: 001-98708 Rev. *E
Page 18 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P41
SOT7_1
(SDA7_1)
RTO11_0
(PPG11_0)
47
39
G
I
TIOA1_0
BIN0_0
MCSX6_0
P42
SCK7_1
(SCL7_1)
RTO12_0
(PPG12_0)
48
40
G
I
TIOA2_0
ZIN0_0
MCSX5_0
P43
SCS70_1
RTO13_0
(PPG13_0)
49
41
G
K
TIOA3_0
INT04_0
MCSX4_0
P44
SCS71_1
RTO14_0
(PPG14_0)
50
51
42
43
G
G
I
I
TIOA4_0
MCSX3_0
P45
SCS72_1
RTO15_0
(PPG15_0)
TIOA5_0
MCSX2_0
C
52
53
54
44
45
46
-
-
-
-
-
-
VSS
VCC
P46
55
47
D
S
X0A
P47
56
57
48
49
D
B
T
X1A
INITX
C
Document Number: 001-98708 Rev. *E
Page 19 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PF0
SCS73_1
RX0_2
58
59
-
E
E
K
K
TIOA15_1
INT22_1
PF1
TX0_2
-
TIOB15_1
INT23_1
P48
SIN1_0
MI2SDI1_0
DTTI1X_0
INT06_0
MRASX_0
P49
60
61
50
L
L
K
SOT1_0
(SDA1_0)
51
I
MI2SDO1_0
IC10_0
MCASX_0
P4A
SCK1_0
(SCL1_0)
62
63
52
53
L
L
I
MI2SCK1_0
IC11_0
MSDWEX_0
P4B
MI2SWS1_0
IC12_0
K
INT04_2
MCSX8_0
P4C
MI2SMCK1_0
IC13_0
64
65
54
55
L
L
K
K
INT05_2
MSDCKE_0
P4D
FRCK1_0
INT07_0
MSDCLK_0
Document Number: 001-98708 Rev. *E
Page 20 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P4E
SCK9_0
(SCL9_0)
66
67
56
L
L
Q
INT05_0
WKUP2
MCSX1_0
P70
ADTG_7
57
I
SOT9_0
(SDA9_0)
MCSX0_0
P71
ADTG_8
SIN9_0
INT04_1
MRDY_0
P72
68
69
70
58
59
60
I
K
I
TIOB0_0
INT06_2
MAD00_0
P73
E
E
SIN8_0
TIOB1_0
INT20_0
MAD01_0
P74
K
SOT8_0
(SDA8_0)
71
72
61
62
E
E
I
I
TIOB2_0
MAD02_0
P75
SCK8_0
(SCL8_0)
TIOB3_0
MAD03_0
P76
SIN6_0
TIOB4_0
INT21_0
MAD04_0
P77
73
74
63
64
E
L
K
SOT6_0
(SDA6_0)
I
TIOB5_0
MAD05_0
Document Number: 001-98708 Rev. *E
Page 21 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P78
SCK6_0
(SCL6_0)
75
76
65
L
I
AIN0_1
MAD06_0
P79
SCS60_0
BIN0_1
66
67
-
E
K
INT22_0
MAD07_0
P7A
SCS61_0
ZIN0_1
77
78
E
E
K
INT07_2
MAD08_0
PF2
SCS62_0
DTTI1X_1
TIOA6_1
IC1_CLK_1
PF3
I
SCS63_0
FRCK1_1
TIOB6_1
INT05_1
IC1_VCC_1
PF4
79
80
81
-
-
-
E
E
E
K
K
K
IC10_1
TIOA7_1
INT06_1
IC1_VPEN_1
PF5
SIN3_1
IC11_1
TIOB7_1
INT07_1
IC1_RST_1
PF6
SOT3_1
(SDA3_1)
IC12_1
TIOA14_1
INT20_1
82
-
E
K
IC1_DATA_1
Document Number: 001-98708 Rev. *E
Page 22 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PF7
SCK3_1
(SCL3_1)
IC13_1
TIOB14_1
INT21_1
IC1_CIN_1
PE0
83
-
E
K
84
85
86
68
69
70
C
J
E
D
A
MD1
MD0
PE2
A
X0
PE3
87
71
A
B
X1
88
89
90
91
92
93
72
73
74
75
76
77
VSS
-
-
-
-
-
-
-
-
-
-
-
-
VCC
AVCC
AVSS
AVRL
AVRH
P10
AN00
TIOA0_2
INT08_0
MNREX_0
IC1_CLK_0
P11
94
78
F
M
AN01
95
96
79
80
TIOB0_2
MNWEX_0
IC1_VCC_0
P12
F
F
L
L
AN02
TIOA1_2
MNCLE_0
IC1_VPEN_0
P13
AN03
SIN9_1
TIOB1_2
INT25_1
MNALE_0
IC1_RST_0
97
81
F
M
Document Number: 001-98708 Rev. *E
Page 23 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P14
AN04
SOT9_1
(SDA9_1)
98
82
F
N
TIOA2_2
IC1_DATA_0
TRACED0
P15
AN05
SCK9_1
(SCL9_1)
99
83
84
F
F
N
O
TIOB2_2
IC1_CIN_0
TRACED1
P16
AN06
SIN6_1
RX0_0
100
INT09_0
TRACED2
P17
AN07
SOT6_1
(SDA6_1)
101
102
85
F
F
N
N
TX0_0
TRACED3
PB0
AN16
SCK6_1
(SCL6_1)
-
TIOA9_1
TRACED8
PB1
AN17
SCS60_1
TIOB9_1
AIN0_2
103
-
F
O
INT08_1
TRACED9
PB2
AN18
SCS61_1
TIOA10_1
BIN0_2
104
-
F
O
INT09_1
TRACED10
Document Number: 001-98708 Rev. *E
Page 24 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PB3
AN19
SCS62_1
TIOB10_1
ZIN0_2
TRACED11
P18
105
106
-
F
F
N
O
AN08
SIN2_0
TIOA3_2
INT10_0
TRACED4
P19
86
87
AN09
SOT2_0
(SDA2_0)
107
F
O
TIOB3_2
INT24_1
TRACED5
P1A
AN10
SCK2_0
(SCL2_0)
108
109
88
89
F
F
N
O
TIOA4_2
TRACED6
P1B
AN11
TIOB4_2
INT11_0
TRACED7
PB4
AN20
SCS63_1
TIOA11_1
INT10_1
TRACED12
PB5
110
111
-
-
F
F
O
O
AN21
SIN8_1
TIOB11_1
AIN1_2
INT11_1
TRACED13
Document Number: 001-98708 Rev. *E
Page 25 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PB6
AN22
SOT8_1
(SDA8_1)
112
-
F
N
TIOA12_1
BIN1_2
TRACED14
PB7
AN23
SCK8_1
(SCL8_1)
113
-
F
N
TIOB12_1
ZIN1_2
TRACED15
P1C
AN12
SCK0_1
(SCL0_1)
114
90
F
N
TIOA5_2
TRACECLK
P1D
AN13
SOT0_1
(SDA0_1)
115
116
91
92
F
F
L
TIOB5_2
MAD09_0
P1E
AN14
SIN0_1
TIOA8_1
INT26_1
MAD10_0
P1F
M
AN15
RTS5_0
TIOB8_1
INT27_1
MAD11_0
P2A
117
118
93
94
F
F
M
M
AN24
CTS5_0
INT08_2
MAD12_0
Document Number: 001-98708 Rev. *E
Page 26 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P29
AN25
SCK5_0
(SCL5_0)
119
120
95
F
F
M
M
INT09_2
MAD13_0
P28
AN26
SOT5_0
(SDA5_0)
96
INT10_2
MAD14_0
P27
AN27
121
122
97
98
SIN5_0
INT24_0
MAD15_0
P26
F
E
M
M
ADTG_6
TIOA6_2
INT11_2
MAD16_0
P25
AN28
123
124
99
TIOB6_2
INT25_0
MAD17_0
P24
F
F
M
L
AN29
100
TIOA13_1
MAD18_0
P23
UHCONX1
AN30
125
126
101
102
F
E
L
SCK0_0
(SCL0_0)
TIOB13_1
P22
AN31
M
SOT0_0
(SDA0_0)
INT26_0
Document Number: 001-98708 Rev. *E
Page 27 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P21
ADTG_4
SIN0_0
INT27_0
CROUT_0
P20
127
103
I
I
K
F
128
104
NMIX
WKUP0
USBVCC1
P82
129
130
105
106
-
-
H
R
UDM1
P83
131
107
H
R
UDP1
VSS
132
133
108
109
-
-
-
-
VCC
P00
134
135
136
137
110
111
112
113
E
E
E
E
G
G
G
G
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
138
139
114
TDO
E
E
G
K
SWO
P90
RTO10_1
(PPG10_1)
-
TIOB0_1
INT12_1
IC0_CLK_1
P91
SIN5_1
RTO11_1
(PPG11_1)
140
-
E
K
TIOB1_1
INT13_1
IC0_VCC_1
Document Number: 001-98708 Rev. *E
Page 28 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P92
SOT5_1
(SDA5_1)
RTO12_1
(PPG12_1)
141
-
E
K
TIOB2_1
INT14_1
IC0_VPEN_1
P93
SCK5_1
(SCL5_1)
RTO13_1
(PPG13_1)
142
-
E
K
TIOB3_1
INT15_1
IC0_RST_1
P94
CTS5_1
RTO14_1
(PPG14_1)
143
144
-
-
E
E
I
I
TIOB4_1
IC0_DATA_1
P95
RTS5_1
RTO15_1
(PPG15_1)
TIOB5_1
IC0_CIN_1
PC0
145
146
115
116
K
K
V
V
E_RXER
PC1
TIOB6_0
E_RX03
PC2
147
148
149
150
117
118
119
120
TIOA6_0
E_RX02
PC3
K
K
K
K
V
V
V
V
TIOB7_0
E_RX01
PC4
TIOA7_0
E_RX00
PC5
TIOB14_0
E_RXDV
Document Number: 001-98708 Rev. *E
Page 29 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
PC6
TIOA14_0
E_MDIO
PC7
151
152
121
K
E
V
INT13_0
E_MDC
CROUT_1
PC8
122
W
153
154
123
124
K
K
V
V
E_RXCK_REFCK
PC9
TIOB15_0
E_COL
PCA
155
125
TIOA15_0
E_CRS
ETHVCC
VSS
K
V
156
157
126
127
-
-
-
-
PCB
158
159
128
129
INT28_0
E_COUT
PCC
L
W
V
K
E_TCK
PCD
SOT4_1
(SDA4_1)
160
130
L
W
INT14_0
E_TXER
PCE
SIN4_1
INT15_0
E_TX03
PCF
161
162
131
132
L
L
W
W
RTS4_1
INT12_0
E_TX02
PD0
163
164
165
133
134
135
INT30_1
E_TX01
PD1
L
L
L
W
W
V
INT31_1
E_TX00
PD2
CTS4_1
E_TXEN
Document Number: 001-98708 Rev. *E
Page 30 of 190
S6E2G Series
Pin Number
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-176
LQFP-144
P6E
ADTG_5
SCK4_1
(SCL4_1)
166
136
E
W
INT29_0
E_PPS
P65
167
168
-
-
E
I
K
K
INT28_1
P64
CTS4_0
INT29_1
P63
ADTG_3
RTS4_0
INT30_0
MOEX_0
P62
169
170
137
138
L
L
K
SCK4_0
(SCL4_0)
I
TIOB7_2
MWEX_0
P61
UHCONX0
SOT4_0
(SDA4_0)
171
172
139
140
L
I
TIOA7_2
MALE_0
RTCCO_0
SUBOUT_0
P60
SIN4_0
INT31_0
WKUP3
USBVCC0
P80
I
Q
173
174
141
142
-
-
H
R
UDM0
P81
175
176
143
144
H
R
UDP0
VSS
-
-
Document Number: 001-98708 Rev. *E
Page 31 of 190
S6E2G Series
Signal Descriptions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
Module
Pin Name
Function
LQFP 176
19
LQFP 144
16
20
29
137
103
136
98
57
58
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
-
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
23
34
169
127
166
122
67
A/D converter external trigger input pin
68
94
AN01
95
AN02
96
AN03
97
AN04
98
AN05
99
AN06
100
101
106
107
108
109
114
115
116
117
102
103
104
105
110
111
112
113
118
119
120
121
123
124
125
126
AN07
AN08
AN09
AN10
A/D
converter
AN11
AN12
AN13
AN14
AN15
A/D converter analog input pin.
ANxx describes A/D converter ch xx.
AN16
AN17
-
AN18
-
AN19
-
AN20
-
AN21
-
AN22
-
AN23
-
AN24
94
95
96
97
99
100
101
102
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Document Number: 001-98708 Rev. *E
Page 32 of 190
S6E2G Series
Pin Number
LQFP 176
Module
Pin Name
Function
LQFP 144
38
30
78
59
-
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
46
35
Base Timer ch 0 TIOA pin
94
Base Timer
0
69
Base Timer ch 0 TIOB pin
Base Timer ch 1 TIOA pin
Base Timer ch 1 TIOB pin
Base Timer ch 2 TIOA pin
Base Timer ch 2 TIOB pin
Base Timer ch 3 TIOA pin
Base Timer ch 3 TIOB pin
Base Timer ch 4 TIOA pin
Base Timer ch 4 TIOB pin
Base Timer ch 5 TIOA pin
Base Timer ch 5 TIOB pin
Base Timer ch 6 TIOA pin
Base Timer ch 6 TIOB pin
139
95
79
39
31
80
60
-
47
36
96
Base Timer
1
70
140
97
81
40
32
82
61
-
48
37
98
Base Timer
2
71
141
99
83
41
33
86
62
-
49
38
106
72
Base Timer
3
142
107
50
87
42
34
88
63
-
39
108
73
Base Timer
4
143
109
51
89
43
35
90
64
-
40
114
74
Base Timer
5
144
115
147
78
91
117
-
122
146
79
98
116
-
Base Timer
6
123
99
Document Number: 001-98708 Rev. *E
Page 33 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TIOA8_0
TIOA8_1
TIOA8_2
TIOB8_0
TIOB8_1
TIOB8_2
TIOA9_0
TIOA9_1
TIOA9_2
TIOB9_0
TIOB9_1
TIOA10_0
TIOA10_1
TIOB10_0
TIOB10_1
TIOA11_0
TIOA11_1
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
TIOA14_0
TIOA14_1
TIOB14_0
TIOB14_1
149
80
119
Base Timer ch 7 TIOA pin
-
171
148
81
139
Base Timer
7
118
Base Timer ch 7 TIOB pin
Base Timer ch 8 TIOA pin
Base Timer ch 8 TIOB pin
Base Timer ch 9 TIOA pin
-
170
2
138
2
116
10
92
-
Base Timer
8
17
14
117
11
93
-
3
3
102
12
-
Base Timer
9
-
18
15
Base Timer ch 9 TIOB pin
Base Timer ch 10 TIOA pin
Base Timer ch 10 TIOB pin
Base Timer ch 11 TIOA pin
103
4
-
4
104
19
-
Base Timer
10
16
105
5
-
5
110
20
-
Base Timer
11
17
Base Timer ch 11 TIOB pin
Base Timer ch 12 TIOA pin
Base Timer ch 12 TIOB pin
Base Timer ch 13 TIOA pin
Base Timer ch 13 TIOB pin
111
24
-
-
6
6
112
25
-
-
18
-
Base Timer
12
21
113
41
-
7
7
124
42
100
-
Base Timer
13
22
19
101
-
125
43
151
82
121
-
Base Timer ch 14 TIOA pin
Base Timer ch 14 TIOB pin
Base Timer
14
150
83
120
-
Document Number: 001-98708 Rev. *E
Page 34 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
Base Timer ch 15 TIOA pin
Base timer ch 15 TIOB pin
LQFP 176
LQFP 144
TIOA15_0
TIOA15_1
TIOB15_0
TIOB15_1
TX0_0
155
58
125
-
Base Timer
15
154
59
124
-
85
-
101
25
CAN interface ch 0 TX output pin
CAN interface ch 0 RX input pin
TX0_1
TX0_2
59
-
CAN 0
RX0_0
100
24
84
-
RX0_1
RX0_2
58
-
Serial wire debug interface clock input
pin
SWCLK
SWDIO
135
137
111
113
Serial wire debug interface data input/
output pin
Serial wire viewer output pin
JTAG test clock input pin
SWO
138
135
136
138
137
114
98
114
111
112
114
113
90
82
83
84
85
86
87
88
89
-
TCK
JTAG test data input pin
TDI
JTAG debug data output pin
JTAG test mode state input/output pin
Trace CLK output pin of ETM/HTM
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRACED4
TRACED5
TRACED6
TRACED7
TRACED8
TRACED9
TRACED10
TRACED11
TRACED12
TRACED13
TRACED14
TRACED15
TRSTX
99
Trace data output pin of ETM/
Trace data output pin of HTM
100
101
106
107
108
109
102
103
104
105
110
111
112
113
134
Debugger
-
Trace data output pin of HTM
-
-
-
-
-
-
JTAG test reset Input pin
110
Document Number: 001-98708 Rev. *E
Page 35 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
59
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MCSX8_0
69
70
60
71
61
72
62
73
63
74
64
75
65
76
66
77
67
115
116
117
118
119
120
121
122
123
124
40
91
92
93
External bus interface address bus
94
95
96
97
98
External
bus
99
100
35
39
34
38
33
37
32
36
31
35
30
67
57
66
56
51
43
50
42
External bus interface chip select
output pin
49
41
48
40
47
39
46
38
63
53
Document Number: 001-98708 Rev. *E
Page 36 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
2
3
2
3
4
4
5
5
6
6
7
7
8
8
9
9
External bus interface data bus
(address/data multiplex bus)
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
External bus interface byte mask signal
output pin
MDQM1_0
External bus interface address latch
enable output signal for multiplex
MALE_0
MRDY_0
171
68
139
58
External bus interface external RDY
input signal
External
bus
External bus interface external clock
output pin
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
23
20
External bus interface ALE signal to
control NAND flash output pin
97
81
External bus interface CLE signal to
control NAND flash output pin
96
80
External bus interface read enable signal
to control NAND flash
94
78
External bus interface write enable signal
to control NAND flash
95
79
External bus interface read enable
signal for SRAM
169
170
65
137
138
55
External bus interface write enable
signal for SRAM
MWEX_0
SDRAM interface
SDRAM clock output pin
MSDCLK_0
MSDCKE_0
MRASX_0
MCASX_0
MSDWEX_0
SDRAM interface
SDRAM clock enable pin
64
54
SDRAM interface
SDRAM row active strobe pin
60
50
SDRAM interface
SDRAM column active strobe pin
61
51
SDRAM interface
SDRAM write enable pin
62
52
Document Number: 001-98708 Rev. *E
Page 37 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT13_0
INT13_1
2
2
23
8
External interrupt request 00 input pin
28
8
7
7
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
31
26
-
24
13
10
27
9
32
9
16
13
28
-
33
41
49
41
58
53
56
-
68
63
66
79
64
54
50
-
60
80
External
interrupt
69
59
55
-
65
81
77
67
78
-
94
103
118
100
104
119
106
110
120
109
111
122
162
139
152
140
94
84
-
95
86
-
96
89
-
98
132
-
External interrupt request 12 input pin
External interrupt request 13 input pin
122
-
Document Number: 001-98708 Rev. *E
Page 38 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
130
-
INT14_0
INT14_1
INT15_0
INT15_1
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
160
141
161
142
20
External interrupt request 14 input pin
External interrupt request 15 input pin
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
External interrupt request 26 input pin
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
131
-
17
30
18
31
19
32
21
33
60
-
35
21
36
22
37
26
38
70
82
73
63
-
83
76
66
-
58
External
interrupt
46
38
-
59
121
107
123
97
97
87
99
81
102
92
103
93
128
-
126
116
127
117
158
167
166
168
169
163
172
164
128
136
-
137
133
140
134
104
External interrupt request 31 input pin
Non-maskable interrupt input pin
Document Number: 001-98708 Rev. *E
Page 39 of 190
S6E2G Series
Pin Number
LQFP 176
Module
Pin Name
Function
LQFP 144
110
111
112
113
114
18
P00
P01
P02
P03
P04
P08
P09
P0A
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P2A
134
135
136
137
138
21
General-purpose I/O port 0
22
19
23
20
94
78
95
79
96
80
97
81
98
82
99
83
100
101
106
107
108
109
114
115
116
117
128
127
126
125
124
123
122
121
120
119
118
84
85
General-purpose I/O port 1
86
GPIO
87
88
89
90
91
92
93
104
103
102
101
100
99
General-purpose I/O port 2
98
97
96
95
94
Document Number: 001-98708 Rev. *E
Page 40 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
-
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P5D
P5E
P5F
P60
P61
P62
P63
P64
P65
P6E
24
25
26
27
28
31
32
33
34
35
36
37
38
39
40
46
47
48
49
50
51
55
56
60
61
62
63
64
65
66
10
11
-
21
22
23
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
-
General-purpose I/O port 3
GPIO
General-purpose I/O port 4
-
12
41
42
43
172
171
170
169
168
167
166
-
General-purpose I/O port 5
-
-
-
140
139
138
137
-
General-purpose I/O port 6
-
136
Document Number: 001-98708 Rev. *E
Page 41 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PAA
PAB
PAC
PAD
PAE
PAF
67
68
69
70
71
72
73
74
75
76
77
174
175
130
131
139
140
141
142
143
144
2
57
58
59
60
61
62
63
64
65
66
67
142
143
106
107
-
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port 9
-
-
GPIO
-
-
-
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
General-purpose I/O port A
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
Document Number: 001-98708 Rev. *E
Page 42 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
102
103
104
105
110
111
112
113
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
84
-
-
-
-
General-purpose I/O port B
GPIO
-
-
-
-
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
68
70
71
-
General-purpose I/O port C
GPIO
General-purpose I/O port D
General-purpose I/O port E
86
87
58
59
-
78
-
79
-
General-purpose I/O port F
80
-
81
-
82
-
83
-
Document Number: 001-98708 Rev. *E
Page 43 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
103
SIN0_0
SIN0_1
127
116
Multi-function serial interface ch 0 input
pin
92
Multi-function serial interface ch 0 output
pin
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
SOT0_0
(SDA0_0)
126
115
125
114
102
Multi-
Function
Serial
0
SOT0_1
(SDA0_1)
91
Multi-function serial interface ch 0 clock
I/O pin
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2) and
as SCL0 when it is used in an I2C
(operation mode 4)
SCK0_0
(SCL0_0)
101
90
SCK0_1
(SCL0_1)
SIN1_0
(MI2SDI1_0)
Multi-function serial interface ch 1 input
pin.
60
41
50
SIN1 pin operates as MI2SDI1 when used
SIN1_1
(MI2SDI1_1)
as an I2S pin (operation mode 2).
-
Multi-function serial interface ch 1 output
pin
SOT1_0
(SDA1_0)
61
51
(MI2SDO1_0)
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA1 when it is used in an I2C (operation
mode 4).
SOT1_1
(SDA1_1)
42
-
(MI2SDO1_1)
SOT1 pin operates as MI2SDO1 when used as
an I2S pin (operation mode 2).
Multi-
Function
Serial
1
Multi-function serial interface ch 1 clock
I/O pin
SCK1_0
(SCL1_0)
62
43
52
This pin operates as SCK1 when it is
used in a CSIO (operation mode 2) and
as SCL1 when it is used in an I2C
(operation mode 4).
(MI2SCK1_0)
SCK1_1
(SCL1_1)
(MI2SCK1_1)
-
SCK1 pin operates as MI2SCK1 when
used as an I2S pin (operation mode 2).
MI2SWS1_0
MI2SWS1_1
MI2SMCK1_0
MI2SMCK1_1
63
24
64
25
53
-
I2S word select (WS) output pin
I2S master clock I/O pin
54
-
Document Number: 001-98708 Rev. *E
Page 44 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
SIN2_0
SIN2_1
106
38
86
33
Multi-function serial interface ch 2 input
pin
Multi-function serial interface ch 2 output
pin
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
SOT2_0
(SDA2_0)
107
87
34
88
35
Multi-
Function
Serial
2
SOT2_1
(SDA2_1)
39
Multi-function serial interface ch 2 clock
I/O pin
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2) and
as SCL2 when it is used in an I2C
(operation mode 4).
SCK2_0
(SCL2_0)
108
40
SCK2_1
(SCL2_1)
SIN3_0
SIN3_1
20
81
17
Multi-function serial interface ch 3 input
pin
-
Multi-function serial interface ch 3 output
pin
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
SOT3_0
(SDA3_0)
19
82
18
83
16
Multi-
Function
Serial
3
SOT3_1
(SDA3_1)
-
Multi-function serial interface ch 3 clock
I/O pin
This pin operates as SCK3 when it is
used in a CSIO (operation modes 2) and
as SCL3 when it is used in an I2C
(operation mode 4).
SCK3_0
(SCL3_0)
15
-
SCK3_1
(SCL3_1)
SIN4_0
SIN4_1
172
161
140
131
Multi-function serial interface ch 4 input
pin
Multi-function serial interface ch 4 output
pin
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
SOT4_0
(SDA4_0)
171
160
170
166
139
130
138
136
SOT4_1
(SDA4_1)
Multi-
Function
Serial
4
Multi-function serial interface ch 4 clock
I/O pin
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2) and
as SCL4 when it is used in an I2C
(operation mode 4).
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
CTS4_0
CTS4_1
RTS4_0
RTS4_1
168
165
169
162
-
Multi-function serial interface ch 4 CTS
input pin
135
137
132
Multi-function serial interface ch 4 RTS
output pin
Document Number: 001-98708 Rev. *E
Page 45 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
SIN5_0
SIN5_1
121
140
97
Multi-function serial interface ch 5 input
pin
-
Multi-function serial interface ch 5 output
pin
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
SOT5_0
(SDA5_0)
120
141
119
142
96
SOT5_1
(SDA5_1)
-
Multi-
Function
Serial
5
Multi-function serial interface ch 5 clock
I/O pin
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
SCK5_0
(SCL5_0)
95
-
SCK5_1
(SCL5_1)
CTS5_0
CTS5_1
RTS5_0
RTS5_1
SIN6_0
SIN6_1
118
143
117
144
73
94
-
Multi-function serial interface ch 5 CTS
input pin
93
-
Multi-function serial interface ch 5 RTS
output pin
63
84
Multi-function serial interface ch 6 input
pin
100
Multi-function serial interface ch 6 output
pin
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
SOT6_0
(SDA6_0)
74
101
75
64
85
65
-
SOT6_1
(SDA6_1)
Multi-function serial interface ch 6 clock
I/O pin
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2) and
as SCL6 when it is used in an I2C
(operation mode 4).
SCK6_0
(SCL6_0)
Multi-
Function
Serial
6
SCK6_1
(SCL6_1)
102
SCS60_0
SCS60_1
SCS61_0
SCS61_1
SCS62_0
SCS62_1
SCS63_0
SCS63_1
76
103
77
66
-
Multi-function serial interface ch 6 chip
select 0 input/output pin
67
-
Multi-function serial interface ch 6 chip
select1 input/output pin
104
78
-
Multi-function serial interface ch 6 chip
select2 input/output pin
105
79
-
-
Multi-function serial interface ch 6 chip
select3 input/output pin
110
-
Document Number: 001-98708 Rev. *E
Page 46 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
SIN7_0
SIN7_1
13
46
10
38
Multi-function serial interface ch 7 input
pin
Multi-function serial interface ch 7 output
pin
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
SOT7_0
(SDA7_0)
14
47
15
48
11
39
12
40
SOT7_1
(SDA7_1)
Multi-function serial interface ch 7
clock I/O pin
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2) and
as SCL7 when it is used in an I2C
(operation mode 4).
SCK7_0
(SCL7_0)
Multi-
Function
Serial
7
SCK7_1
(SCL7_1)
SCS70_0
SCS70_1
SCS71_0
SCS71_1
SCS72_0
SCS72_1
SCS73_0
SCS73_1
SIN8_0
16
49
17
50
10
51
11
13
41
14
42
-
Multi-function serial interface ch 7 chip
select 0 input/output pin
Multi-function serial interface ch 7 chip
select 1 input/output pin
Multi-function serial interface ch 7 chip
select 2 input/output pin
43
-
Multi-function serial interface ch 7 chip
select 3 input/output pin
58
70
111
-
60
-
Multi-function serial interface ch 8 input
pin
SIN8_1
Multi-function serial interface ch 8 output
pin
This pin operates as SOT8 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA8 when it is
used in an I2C (operation mode 4).
SOT8_0
(SDA8_0)
71
112
72
61
Multi-
Function
Serial
8
SOT8_1
(SDA8_1)
-
Multi-function serial interface ch 8 clock
I/O pin
This pin operates as SCK8 when it is
used in a CSIO (operation mode 2) and
as SCL8 when it is used in an I2C
(operation mode 4).
SCK8_0
(SCL8_0)
62
-
SCK8_1
(SCL8_1)
113
SIN9_0
SIN9_1
68
97
58
81
Multi-function serial interface ch 9 input
pin
Multi-function serial interface ch 9 output
pin
This pin operates as SOT9 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA9 when it is
used in an I2C (operation mode 4).
SOT9_0
(SDA9_0)
67
98
66
99
57
82
56
83
Multi-
Function
Serial
9
SOT9_1
(SDA9_1)
Multi-function serial interface ch 9 clock
I/O pin
This pin operates as SCK9 when it is
used in a CSIO (operation mode 2) and
as SCL9 when it is used in an I2C
(operation mode 4).
SCK9_0
(SCL9_0)
SCK9_1
(SCL9_1)
Document Number: 001-98708 Rev. *E
Page 47 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
Input signal controlling waveform
generator outputs RTO00 to RTO05 of
Multi-Function Timer 0.
DTTI0X_0
DTTI0X_1
34
8
29
8
FRCK0_0
FRCK0_1
IC00_0
IC00_1
IC01_0
IC01_1
IC02_0
IC02_1
IC03_0
IC03_1
27
13
33
9
22
10
28
9
16-bit free-run timer ch 0 external
clock input pin
32
10
31
11
28
12
27
-
16-bit input capture input pin of
Multi-Function Timer 0.
ICxx describes channel number.
26
-
23
-
RTO00_0
(PPG00_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
35
2
30
2
RTO00_1
(PPG00_1)
Multi-
Function
Timer 0
RTO01_0
(PPG00_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when it is
36
3
31
3
RTO01_1
(PPG00_1)
used in PPG0 output modes.
RTO02_0
(PPG02_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
37
4
32
4
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
38
5
33
5
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
39
6
34
6
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when it is
40
7
35
7
RTO05_1
(PPG04_1)
used in PPG0 output modes.
Document Number: 001-98708 Rev. *E
Page 48 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
Input signal controlling waveform
generator outputs RTO10 to RTO15 of
Multi-Function Timer 1.
DTTI1X_0
DTTI1X_1
60
78
50
-
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
65
79
61
80
62
81
63
82
64
83
55
-
16-bit free-run timer ch 1 external
clock input pin
51
-
52
-
16-bit input capture input pin of
Multi-Function Timer 1.
ICxx describes channel number.
53
-
54
-
RTO10_0
(PPG10_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when it is
used in PPG1 output modes.
46
139
47
38
-
RTO10_1
(PPG10_1)
Multi-
Function
Timer 1
RTO11_0
(PPG10_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when it is
39
-
RTO11_1
(PPG10_1)
140
48
used in PPG1 output modes.
RTO12_0
(PPG12_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
40
-
RTO12_1
(PPG12_1)
141
49
RTO13_0
(PPG12_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
41
-
RTO13_1
(PPG12_1)
142
50
RTO14_0
(PPG14_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when it is
used in PPG1 output modes.
42
-
RTO14_1
(PPG14_1)
143
51
RTO15_0
(PPG14_0)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when it is
43
-
RTO15_1
(PPG14_1)
144
used in PPG1 output modes.
Document Number: 001-98708 Rev. *E
Page 49 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
46
75
38
65
-
QPRC ch 0 AIN input pin
103
47
Quadrature
Position/
Revolution
Counter
0
39
66
-
QPRC ch 0 BIN input pin
QPRC ch 0 ZIN input pin
QPRC ch 1 AIN input pin
QPRC ch 1 BIN input pin
QPRC ch 1 ZIN input pin
76
104
48
40
67
-
ZIN0_1
77
ZIN0_2
105
35
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
30
11
-
14
111
36
Quadrature
Position/
Revolution
Counter
1
31
12
-
15
112
37
32
13
-
ZIN1_1
16
ZIN1_2
113
171
9
RTCCO_0
RTCCO_1
SUBOUT_0
SUBOUT_1
UDM0
139
9
0.5 seconds pulse output pin of
real-time clock
Real-time
clock
171
9
139
9
Sub-clock output pin
USB ch 0 device/host D – pin
USB ch 0 device/host D + pin
USB ch 0 external pull-up control pin
USB ch 1 device/host D – pin
USB ch 1 device/host D + pin
USB ch 1 external pull-up control pin
174
175
171
130
131
125
142
143
139
106
107
101
USB0
USB1
UDP0
UHCONX0
UDM1
UDP1
UHCONX1
Deep standby mode return signal input
pin 0
WKUP0
WKUP1
WKUP2
WKUP3
128
13
104
10
Deep standby mode return signal input
pin 1
Low power
consump-
tion
Deep standby mode return signal input
pin 2
66
56
mode
Deep standby mode return signal input
pin 3
172
140
Document Number: 001-98708 Rev. *E
Page 50 of 190
S6E2G Series
Pin Number
Module
Pin Name
S_CLK_0
S_CMD_0
Function
LQFP 176
LQFP 144
SD memory card interface
SD memory card clock output pin
28
31
23
SD memory card interface
SD memory card command output
26
S_DATA1_0
S_DATA0_0
S_DATA3_0
S_DATA2_0
26
27
32
33
21
22
27
28
SD memory card interface
SD memory card data bus
SD I/F
SD memory card interface
SD memory card detection pin
S_CD_0
S_WP_0
35
34
30
29
SD memory card interface
SD memory card write protection
Collision detection
Clock output for Ethernet PHY
Carrier detection
E_COL
E_COUT
E_CRS
E_MDC
E_MDIO
E_PPS
154
158
155
152
151
166
149
148
147
146
124
128
125
122
121
136
119
118
117
116
Management clock
Management data I/O
PTP counter monitor
Received data0
E_RX00
E_RX01
E_RX02
E_RX03
Received data1
Received data2
Received data3
Ethernet
E_RXCK_RE Received clock input/
153
123
Reference clock
FCK
Received data enable
Received data error detection
Transition clock input
Transition data0
E_RXDV
E_RXER
E_TCK
150
145
159
164
163
162
161
165
160
120
115
129
134
133
132
131
135
130
E_TX00
E_TX01
E_TX02
E_TX03
E_TXEN
E_TXER
Transition data1
Transition data2
Transition data3
Transition data enable
Transition data error detection
Document Number: 001-98708 Rev. *E
Page 51 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
IC0_VCC_0
IC0_VCC_1
IC0_VPEN_0
IC0_VPEN_1
IC0_RST_0
IC0_RST_1
IC0_CIN_0
IC0_CIN_1
IC0_CLK_0
IC0_CLK_1
IC0_DATA_0
IC0_DATA_1
IC1_VCC_0
IC1_VCC_1
IC1_VPEN_0
IC1_VPEN_1
IC1_RST_0
IC1_RST_1
IC1_CIN_0
IC1_CIN_1
IC1_CLK_0
IC1_CLK_1
IC1_DATA_0
IC1_DATA_1
6
140
5
6
-
Smartcard ch 0 power enable output pin
Smartcard ch 0 programming output pin
Smartcard ch 0 reset output pin
5
-
141
4
4
-
142
2
Smartcard0
2
-
Smartcard ch 0 insert detection input pin
144
7
7
-
Smartcard ch 0 serial interface clock
output pin
139
3
3
-
Smartcard ch 0 serial interface data I/O
pin
143
95
79
96
80
97
81
99
83
94
78
98
82
79
-
Smartcard ch 1 power enable output pin
Smartcard ch 1 programming output pin
Smartcard ch 1 reset output pin
80
-
81
-
Smartcard1
83
-
Smartcard ch 1 insert detection input pin
78
-
Smartcard ch 1 serial interface clock
output pin
82
-
Smartcard ch 1 serial interface data I/O
pin
Document Number: 001-98708 Rev. *E
Page 52 of 190
S6E2G Series
Pin Number
Module
Pin Name
Function
External reset Input pin
LQFP 176
LQFP 144
Reset
INITX
57
49
A reset is valid when INITX = L.
Mode 1 pin
During serial programming to flash
memory, MD1 = L must be input.
MD1
MD0
84
68
69
Mode
Mode 0 pin
During normal operation, MD0 = L must
be input. During serial programming to
flash memory, MD0 = H must be input.
85
1
1
29
24
45
37
Power supply pin
VCC
54
46
Power
89
73
133
173
129
156
30
109
141
105
126
25
USBVCC0
USBVCC1
ETHVCC
3.3V power supply port for USB I/O
Power supply pin for Ethernet I/O
44
36
53
45
GND pin
GND
VSS
88
72
132
157
176
86
108
127
144
70
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
X0
X1
87
71
X0A
55
47
Clock
X1A
56
48
CROUT_0
CROUT_1
127
152
103
122
Built-in high-speed CR-oscillation clock
output port
A/D converter and D/A converter
analog power-supply pin
AVCC
AVRL
AVRH
90
92
93
74
76
77
Analog
power
A/D converter analog reference voltage
input pin
A/D converter analog reference voltage
input pin
Analog
GND
A/D converter and D/A converter
GND pin
AVSS
C
91
52
75
44
Power supply stabilization capacity pin
C pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 001-98708 Rev. *E
Page 53 of 190
S6E2G Series
7. I/O Circuit Type
Type
Circuit
Remarks
P-ch
P-ch
Digital output
Digital output
X1
N-ch
R
It is possible to select the main
Oscillation/GPIO function.
Pull-up resistor control
When the main oscillation
is selected:
Digital input
・ Oscillation feedback resistor:
approximately 1 MΩ
Standby mode control
Clock input
・ Standby mode control
A
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
Standby mode control
Digital input
approximately 50 kΩ
Standby mode control
・ IOH = -4 mA, IOL= 4 mA
R
P-ch
P-ch
N-ch
Digital output
X0
Digital output
Pull-up resistor control
・ CMOS level hysteresis input
・ Pull-up resistor:
Pull-up resistor
B
approximately 50 kΩ
Digital input
Document Number: 001-98708 Rev. *E
Page 54 of 190
S6E2G Series
Type
Circuit
Remarks
Digital input
・ Open drain output
・ CMOS level hysteresis input
C
N-ch
Digital output
Document Number: 001-98708 Rev. *E
Page 55 of 190
S6E2G Series
Type
Circuit
Remarks
P-ch
P-ch
Digital output
Digital output
X1A
N-ch
R
It is possible to select the sub
oscillation/GPIO function.
Pull-up resistor control
When the main oscillation
is selected:
Digital input
・ Oscillation feedback resistor:
approximately 5 MΩ
Standby mode control
Clock input
・ Standby mode control
D
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
Standby mode control
Digital input
approximately 50 kΩ
Standby mode control
・ IOH = -4 mA, IOL= 4 mA
R
P-ch
P-ch
N-ch
Digital output
X0A
Digital output
Pull-up resistor control
Document Number: 001-98708 Rev. *E
Page 56 of 190
S6E2G Series
Type
Circuit
Remarks
P-ch
P-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
E
N-ch
Digital output
approximately 50 kΩ
R
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
Pull-up resistor control
Digital input
Standby mode control
P-ch
P-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Input control
・ Analog input
N-ch
Digital output
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
F
approximately 50 kΩ
Pull-up resistor control
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
R
Digital input
Standby mode control
Analog input
Input control
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S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
P-ch
P-ch
Digital output
Digital output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
G
approximately 50 kΩ
N-ch
・ IOH = -12 mA, IOL = 12 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
R
Pull-up resistor
control
Digital input
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select either USB I/O
or GPIO function.
UDP output
UDP/Pxx
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected:
・ Full-speed, low-speed control
Differential
UDM/Pxx
Differential input
USB/GPIO select
H
When the GPIO is selected:
・ CMOS level output
UDM input
・ CMOS level hysteresis input
・ Standby mode control
UDM output
・ IOH = -20.5 mA, IOL = 18.5 mA
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
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S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ 5 V tolerant
P-ch
P-ch
Digital output
Digital output
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
I
・ IOH = -4 mA, IOL= 4 mA
N-ch
・ Available to control of PZR registers
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
the FM4 Family Peripheral Manual
Main Part (002-04856).
R
Pull-up resistor
control
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
P-ch
P-ch
Digital output
Digital output
・CMOS level output
・TTL level hysteresis input
・Pull-up resistor control
・Standby mode control
K
N-ch
・ Pull-up resistor:
R
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
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S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
P-ch
P-ch
Digital output
Digital output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
L
approximately 50 kΩ
N-ch
・ IOH = -8 mA, IOL = 8 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Pull-up resistor
control
R
Digital input
Standby mode
control
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
Pull-up resistor
P-ch
control
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
P-ch
Digital output
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA (GPIO)
・ IOL = 20mA (Fast mode Plus)
・ Available to control of PZR register
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
the FM4 Family Peripheral Manual
Main Part (002-04856).
・ When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
N
N-ch
N-ch
Digital output
Fast mode
control
R
Digital input
Standby mode
control
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S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
Pull-up resistor
control
・ CMOS level hysteresis input
・ 5 V tolerant
P-ch
P-ch
Digital output
・ Pull-up resistor control
・ Pull-up resistor:
approximately 50 kΩ
O
・ IOH = -4 mA, IOL= 4 mA
・ Available to control of PZR register
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
the FM4 Family Peripheral Manual
Main Part (002-04856).
N-ch
Digital output
R
Digital input
P-ch
Pull-up resistor
control
Digital output
P-ch
X0A
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Pull-up resistor:
N-ch
Digital output
P
approximately 50 kΩ
・ IOH = -4 mA, IOL= 4 mA
R
Digital input
Standby mode
control
OSC
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S6E2G Series
Type
Circuit
Remarks
Pull-up resistor
control
Digital output
P-ch
P-ch
It is possible to select the sub
oscillation/GPIO function.
X1A
When the sub oscillation
is selected:
N-ch
Digital output
・ Oscillation feedback resistor:
approximately 10 MΩ
Q
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Pull-up resistor:
R
Digital input
Standby mode
control
OSC
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
RX
Standby mode
control
Clock input
Pull-up resistor
P-ch
control
・ CMOS level output
・ CMOS level hysteresis input
・ Analog output
P-ch
N-ch
Digital output
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
Digital output
R
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
(4.5V to 5.5V)
R
・ IOH = -2 mA, IOL = 2 mA
(2.7V to 4.5V)
Digital input
Standby mode
control
Analog output
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8. Handling Precautions
Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must
be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
8.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power-supply pin or ground pin.
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Latch-Up
Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels
in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection,
and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support,
etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages
arising from such use without prior approval.
8.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering,
you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your
sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
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S6E2G Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent this, do the following:
1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%.
4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in these aluminum laminate bags for storage.
5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock
loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
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8.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of static electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive gases, dust, or oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, including cosmic radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, flame
CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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9. Handling Devices
Power-Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines,
however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total output current rating.
Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device
as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane, as this is expected to produce stable operation.
Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board.
Sub Crystal Oscillator
The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress
recommends a crystal oscillator that meets the following conditions:
Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: approximately 6 pF to 7 pF
Lead type
Load capacitance: approximately 6 pF to 7 pF
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Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.
X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set
X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as external clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Handling When Using Multi-Function Serial Pin as I2C Pin
If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C
pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU
power off.
C Pin
Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and
the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that
meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A
smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance
is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important
to prevent the device from erroneously switching to test mode as a result of noise.
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Notes on Power-On
Turn power on/off in the sequence shown below or at the same time. If not using the A/D converter and D/A converter, connect
AVCC = VCC and AVSS = VSS.
Turning on: VCC → USBVCC0
VCC → USBVCC1
VCC →ETHVCC
VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
ETHVCC → VCC
USBVCC1 → VCC
USBVCC0 → VCC
Serial Communication
There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take
care to design the printed circuit board to minimize noise.
Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in Characteristics within the Product Line
The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the
product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If
you are switching to a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Pin Doubled as Debug Function
The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input.
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10.Memory Map
Memory Map (1)
See "Memory Map (2) for
memory size details.
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Memory Map (2)
*: See S6E2GM/GK/GH/G3/G2 Series Flash Programming Manual to confirm the detail of flash Memory.
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S6E2G Series
Peripheral Address Map
Start Address
0x4000_0000
End Address
Bus
Peripherals
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
MainFlash I/F register
AHB
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
Reserved
Clock/reset control
Hardware watchdog timer
Software watchdog timer
Reserved
APB0
Dual-timer
Reserved
Multi-Function Timer unit 0
Multi-Function Timer unit 1
Reserved
PPG
Base timer
APB1
Quadrature position/revolution counter
A/D converter
Reserved
Internal CR trimming
Reserved
External interrupt controller
Interrupt request batch-read function
Reserved
Low voltage detector
Deep standby mode Controller
USB clock generator
CAN prescaler
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
Multi-function serial interface
CRC
APB2
Watch counter
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_C8FF
RTC/port control
Low-speed CR prescaler
Peripheral clock gating
Reserved
0x4003_C900
0x4003_CA00
0x4003_CB00
0x4003_F000
0x4003_C9FF
0x4003_CAFF
0x4003_EFFF
0x4003_FFFF
I2S clock generator
Smartcard Interface
Reserved
External memory interface
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S6E2G Series
Start Address
0x4004_0000
End Address
0x4004_FFFF
Bus
Peripherals
USB ch 0
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4006_6000
0x4006_7000
0x4006_E000
0x4006_F000
0x4007_0000
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x4006_5FFF
0x4006_6FFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
USB ch 1
DMAC register
DSTC register
CAN ch 0
Reserved
AHB
Ethernet-MAC ch 0
Ethernet-MAC setting register
Reserved
SD card I/F
GPIO
Reserved
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11.Pin Status in Each CPU State
The terms used for pin status have the following meanings:
INITX = 0
This is the period when the INITX pin is at the L level.
INITX = 1
This is the period when the INITX pin is at the H level.
SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation
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List of Pin Behavior by Mode State
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Internal
Reset
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
A
Main crystal
oscillator
input pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
external main enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
Enabled
clock input
selected
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
Setting
Setting Setting
disabled disabled disabled
B
Hi-Z/
Hi-Z/
internal internal
input
fixed
at 0
Hi-Z/
internal
input fixed
at 0/
or input
enabled
Main crystal
oscillator
output pin
Maintain previous state while oscillator active/
When oscillation stops*1, it will be Hi-Z/
Internal input fixed at 0
input
fixed
at 0
Pull-up/
input
enabled enabled enabled
Pull-up/ Pull-up/
Input Input
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
INITX
input pin
Pull-up/
Input enabled
Pull-up/
Input enabled
Pull-up/
Input enabled
C
D
Mode
input pin
Input
Input
Input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
enabled enabled enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z/
input
enabled
Hi-Z/
input
enabled
GPIO
selected
Setting
Setting Setting
GPIO
selected
GPIO
selected
disabled disabled disabled
Document Number: 001-98708 Rev. *E
Page 75 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Maintain
previous
state
Maintain
previous
state
NMIX
selected
Setting
Setting Setting
disabled disabled disabled
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z/
WKUP
input enabled
Resource
other than
above
F
Hi-Z/
internal
input fixed
at 0
Hi-Z/
input
enabled enabled
Hi-Z/
input
GPIO
selected
Hi-Z
selected
GPIO
selected
Pull-up/ Pull-up/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
input
input
enabled enabled
Maintain
previous
state
Maintain
previous
state
G
GPIO
selected,
internal input
fixed
Hi-Z/
internal
input fixed
at 0
Hi-Z/
internal input
fixed
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
at 0
Pull-up/ Pull-up/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
input
input
enabled enabled
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
H
GPIO
selected,
Hi-Z/Internal
Hi-Z/Internal
Setting
Setting Setting
GPIO
selected
input fixed internal input input fixed
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
GPIO
selected
GPIO
selected,
Resource
selected
Hi-Z/
input
enabled enabled
Hi-Z/
input
Maintain
previous
state
Maintain
previous
state
Hi-Z/Internal
Hi-Z/internal
GPIO
selected
I
Hi-Z
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 76 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Analog output
selected
*2
*3
External
interrupt
enable
Maintain
previous
state
GPIO
selected,
internal input input fixed
Maintain
previous
state
Hi-Z/internal
Hi-Z/
input
enabled enabled
Hi-Z/
input
GPIO
selected
J
selected
Hi-Z
fixed
at 0
at 0
Maintain
previous
state
Resource
other than
above
Hi-Z/internal
input fixed
at 0
selected
GPIO
selected
External
interrupt
enable
Maintain
previous
state
Setting
Setting Setting
disabled disabled disabled
selected
GPIO
Maintain
previous
state
Maintain
previous
state
selected,
internal input input fixed
Hi-Z/internal
Resource
other than
above
GPIO
selected
K
fixed
at 0
at 0
Hi-Z/
input
enabled enabled
Hi-Z/
input
Hi-Z/internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
Hi-Z/
internal internal
input input
fixed at fixed at
Hi-Z/
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Analog input
selected
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
0/
0/
analog
input
analog
input
enabled
enabled
enabled
enabled enabled
L
Resource
other than
above
GPIO
selected,
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
Hi-Z/internal
Setting
Setting Setting
GPIO
selected
input fixed internal input input fixed
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 77 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Hi-Z/
internal internal
input
fixed
at 0/
analog
input
enabled enabled
Hi-Z/
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
input
fixed
at 0/
analog
input
Analog input
selected
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
enabled
enabled
enabled
External
interrupt
enable
M
Maintain
previous state
selected
GPIO
Maintain
previous
state
Maintain
previous
state
selected,
internal input input fixed
Hi-Z/internal
Resource
other than
above
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
fixed
at 0
at 0
Hi-Z/internal
input fixed
at 0
selected
GPIO
selected
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
input
fixed
at0/
analog
input
input
fixed
at 0/
analog
input
Analog input
selected
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
enabled
enabled
enabled
enabled enabled
N
Trace
Trace
selected
output
GPIO
selected,
internal input input fixed
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
Setting
Setting Setting
GPIO
selected
Hi-Z/internal
input fixed
at 0
disabled disabled disabled
fixed
at 0
at 0
selected
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 78 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Hi-Z/
internal internal
input
fixed
at 0/
analog
input
enabled enabled
Hi-Z/
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
input
fixed
at 0/
analog
input
Analog input
selected
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
enabled
enabled
enabled
Trace
Trace
selected
output
O
External
interrupt
enable
Maintain
previous state
GPIO
selected,
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
internal input input fixed
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
fixed
at 0
at 0
Resource
other than
above
Hi-Z/internal
input fixed
at 0
selected
GPIO
selected
Hi-Z/
internal internal
input input
fixed at fixed at
Hi-Z/
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Hi-Z/
internal input
fixed
at 0/
analog
input enabled
Analog input
selected
Hi-Z
at 0/
analog
input
at 0/
analog
input
at 0/
analog
input
0/
0/
analog
input
analog
input
enabled
enabled
enabled
enabled enabled
WKUP
input
enabled
Hi-Z/
WKUP input
enabled
WKUP
enabled
Maintain
previous state
P
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Setting
Setting Setting
GPIO
selected
GPIO
selected,
disabled disabled disabled
Hi-Z/internal
Hi-Z/internal
selected
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 79 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Hi-Z/
WKUP
input enabled
WKUP
enabled
WKUP input
enabled
WKUP input
enabled
Maintain
previous
state
Setting
Setting Setting
External
interrupt
enable
disabled disabled disabled
Maintain
previous
state
Maintain
previous
state
selected
GPIO
selected,
internal input input fixed
Q
Hi-Z/internal
Resource
other than
above
GPIO
selected
fixed
at 0
at 0
Hi-Z/
input
enabled enabled
Hi-Z/
input
Hi-Z/internal
input fixed
at 0
Hi-Z
Hi-Z
selected
GPIO
selected
GPIO
selected,
Hi-Z/
input
enabled enabled
Hi-Z/
input
Maintain
previous
state
Hi-Z/internal
Hi-Z/internal
GPIO
selected
Maintain
previous state
GPIO
selected
input fixed internal input input fixed
at 0
fixed
at 0
at 0
Hi-Z at
trans-
Hi-Z at
trans-
Hi-Z at
trans-
R
mission/
input
enabled/
mission/
input
enabled/
mission/
input
enabled/
Hi-Z/
input
enabled
Setting
Setting Setting
Hi-Z/
Hi-Z/
USB I/O pin
disabled disabled disabled
input enabled input enabled
internal input internal input internal input
fixed
at 0 at
fixed
at 0 at
fixed
at 0 at
reception
reception
reception
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
S
Sub crystal
oscillator
input pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
external main enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
Enabled
clock input
selected
Document Number: 001-98708 Rev. *E
Page 80 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
Setting
Setting Setting
disabled disabled disabled
T
Hi-Z/
Hi-Z/
internal internal
input
fixed
at 0
Hi-Z/
internal
input fixed
at 0/
or input
enabled
Sub crystal
oscillator
output pin
Maintain previous state while oscillator active/
When oscillation stops*5, it will be Hi-Z/
Internal input fixed at 0
input
fixed
at 0
Ethernet I/O
selected
*4
Maintain
previous
state
Setting
Setting Setting
disabled disabled disabled
GPIO
Maintain
previous
state
Maintain
previous
state
selected,
internal input input fixed
Hi-Z/internal
Resource
other than
above
GPIO
selected
V
fixed
at 0
at "0
Hi-Z/
input
enabled enabled
Hi-Z/
input
Hi-Z/internal
input fixed
at 0
selected
Hi-Z
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 81 of 190
S6E2G Series
Power-On
Reset or
Low-
Voltage
Detection
State
Device
Internal
Reset
Return from
Deep
Standby
INITX
Input
State
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
State
mode State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
‐
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Ethernet
input/output
selected*4
Maintain
previous
state
Setting
Setting Setting
disabled disabled disabled
External
interrupt
enable
GPIO
Maintain
previous
state
Maintain
previous
state
selected,
internal input input fixed
Hi-Z/internal
GPIO
selected
W
selected
fixed
at 0
at 0
Resource
other than
above
Hi-Z/
input
enabled enabled
Hi-Z/
input
Hi-Z/internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
S
Sub crystal
oscillator
input pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
external main enabled enabled enabled
enabled
enabled
enabled
enabled
enabled
Enabled
clock input
selected
GPIO
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed internal input input fixed
selected,
Hi-Z/internal
GPIO
selected
Setting
Setting Setting
GPIO
selected
disabled disabled disabled
at 0
fixed
at 0
at 0
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
Setting
Setting Setting
disabled disabled disabled
T
Hi-Z/
Hi-Z/
internal internal
input
fixed
at 0
Hi-Z/
internal
input fixed
at 0/
or input
enabled
Sub crystal
oscillator
output pin
Maintain previous state while oscillator active/
When oscillation stops*5, it will be Hi-Z/
Internal input fixed at 0
input
fixed
at 0
Document Number: 001-98708 Rev. *E
Page 82 of 190
S6E2G Series
1: Oscillation is stopped at Sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode,
and Deep Standby Stop mode.
2: Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode.
3: Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode.
4: It shows the case selected by EPFR14.E_SPLC register.
Document Number: 001-98708 Rev. *E
Page 83 of 190
S6E2G Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage*1,*2
VCC
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
V
V
V
Power supply voltage (for USB) *1,*3
Power supply voltage (for USB) *1,*3
Power supply voltage (for Ethernet-MAC) *1, *4
USBVCC
0
USBVCC
1
ETHVCC
AVCC
*1 ,*5
Analog power supply voltage
*1 ,*5
Analog reference voltage
AVRH
Except for USB and
Ethernet-MAC pin
VSS - 0.5
VCC + 0.5 (≤ 6.5 V)
V
USB ch 0 pin
USB ch 1 pin
Ethernet-MAC Pin
5 V tolerant
VSS - 0.5 USBVCC0 + 0.5 (≤ 6.5 V)
VSS - 0.5 USBVCC1 + 0.5 (≤ 6.5 V)
V
V
V
V
*1
Input voltage
VI
VSS - 0.5
VSS - 0.5
ETHVCC + 0.5 (≤ 6.5 V)
VSS + 6.5
*1
Analog pin input voltage
VIA
VO
VSS - 0.5
VSS - 0.5
AVCC + 0.5 (≤ 6.5 V)
V
*1
Output voltage
VCC + 0.5 (≤ 6.5 V)
V
4 mA type
8 mA type
12 mA type
I2C Fm+
10
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
L level maximum output current *6
L level average output current *7
IOL
-
-
20
22.4
4
4 mA type
8 mA type
12 mA type
I2C Fm+
8
IOLAV
12
20
L level total maximum output current
L level total average output current*8
∑IOL
-
-
100
50
∑IOLAV
4 mA type
8 mA type
12 mA type
4 mA type
8 mA type
12 mA type
- 10
-20
- 20
- 4
H level maximum output current *6
H level average output current *7
IOH
-
-
IOHAV
-8
- 12
- 100
- 50
+ 150
H level total maximum output current
H level total average output current *8
Storage temperature
∑IOH
∑IOHAV
TSTG
-
-
- 55
1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
Document Number: 001-98708 Rev. *E
Page 84 of 190
S6E2G Series
2: VCC must not drop below VSS - 0.5 V.
3: USBVCC0, USBVCC1 must not drop below VSS - 0.5 V.
4: ETHVCC must not drop below VSS - 0.5 V.
5: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100-ms period.
8: The total average output current is defined as the average current value flowing through all of corresponding pins for a
100-ms period.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 001-98708 Rev. *E
Page 85 of 190
S6E2G Series
12.2 Recommended Operating Conditions
Value
Parameter
Power supply voltage
Symbol
Conditions
Unit
Remarks
Min
Max
VCC
-
2.7*10
5.5
V
*1
*2
*3
*4
3.0
2.7
3.0
2.7
3.6 (≤VCC
5.5 (≤VCC
3.6 (≤VCC
5.5 (≤VCC
)
)
)
)
Power supply voltage (for USB ch 0)
Power supply voltage (for USB ch 1)
USBVCC
0
-
-
V
V
USBVCC
1
*5
*5
3.0
4.5
2.7
3.6 (≤VCC
5.5 (≤VCC
5.5 (≤VCC
)
)
)
Power supply voltage (for
Ethernet-MAC)
ETHVCC
-
V
*6
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
AVCC = VCC
AVCC
AVRH
AVRL
CS
-
-
-
-
-
-
2.7
*9
5.5
AVCC
AVSS
10
V
V
AVSS
1
V
for built-in regulator *7
μF
°C
°C
Junction temperature
Operating
TJ
- 40
-40
+ 125
*8
temperature
Ambient temperature
TA
1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0)
2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80)
3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1)
4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82)
5: When the pins in Ethernet-MAC Timing, except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used as
Ethernet-MAC pin
6: When the pins in Ethernet-MAC Timing, except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used as function
pins
7: See "C pin" in 9 Handling Devices for the connection of the smoothing capacitor.
8: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction
temperature (TJ).
The calculation formula of the ambient temperature (TA) is:
TA (Max) = TJ(Max) - Pd(Max) × θJA
Pd:
θJA:
Power dissipation (W)
Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL
IOH
VOL
VOH
:
:
L level output current
H level output current
L level output voltage
H level output voltage
:
:
9: The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5.
12-bit A/D Converter for the details.
10: For the voltage range between VCC(min) and the low voltage detection reset (VDH), the MCU must be clocked from either
the High-speed CR or the low-speed CR.
Document Number: 001-98708 Rev. *E
Page 86 of 190
S6E2G Series
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Maximum Permissible Power
(mW)
Thermal
Resistance
θja
Printed
Circuit Board
Package
TA = +85 °C
TA = +105 °C
(°C/W)
Single-layered
both sides
48
33
45
31
833
1212
889
417
606
444
645
LQS144
(0.5-mm pitch)
4 layers
Single-layered
both sides
LQP176
(0.5-mm pitch)
4 layers
1290
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
−
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 001-98708 Rev. *E
Page 87 of 190
S6E2G Series
Ethernet-MAC Pins
Except For
Ethernet-MAC
Function
Power
Supply
Type
Ethernet-MAC
Pin Name
Function
P6E/ADTG_5/SCK4_1/INT29_0/E_PPS
PC0/E_RXER
E_PPS *
E_RXER
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
E_MDIO
E_MDC
P6E/ADTG_5/SCK4_1/INT29_0
PC0
VCC
PC1/TIOB6_0/E_RX03
PC2/TIOA6_0/E_RX02
PC3/TIOB7_0/E_RX01
PC4/TIOA7_0/E_RX00
PC5/TIOB14_0/E_RXDV
PC6/TIOA14_0/E_MDIO
PC7/INT13_0/E_MDC/CROUT_1
PC8/E_RXCK_REFCK
PC9/TIOB15_0/E_COL
PCA/TIOA15_0/E_CRS
PCB/INT28_0/E_COUT
PCC/E_TCK
PC1/TIOB6_0
PC2/TIOA6_0
PC3/TIOB7_0
PC4/TIOA7_0
PC5/TIOB14_0
PC6/TIOA14_0
PC7/INT13_0/CROUT_1
E_RXCK_REFCK PC8
E_COL
PC9/TIOB15_0
ETHVCC
E_CRS
E_COUT
E_TCK
PCA/TIOA15_0
PCB/INT28_0
PCC
PCD/SOT4_1/INT14_0/E_TXER
PCE/SIN4_1/INT15_0/E_TX03
PCF/RTS4_1/INT12_0/E_TX02
PD0/INT30_1/E_TX01
E_TXER
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
PCD/SOT4_1/INT14_0
PCE/SIN4_1/INT15_0
PCF/RTS4_1/INT12_0
PD0/INT30_1
PD1/INT31_1/E_TX00
PD1/INT31_1
PD2/CTS4_1/E_TXEN
PD2/CTS4_1
*: It is used to confirm the PTP counter cycle in Ethernet-MAC by waveforms.
Document Number: 001-98708 Rev. *E
Page 88 of 190
S6E2G Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL
IOH
VOL
VOH
:
L level output current
H level output current
L level output voltage
H level output voltage
:
:
:
ICC is the current drawn by the device.
It can be analyzed as follows.
ICC = ICC (INT) + ΣICC (IO)
ICC (INT): Current drawn by internal logic and memory, etc. through the regulator
ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "12.3. DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For ICC (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC (IO) =
(CINT + CEXT) × VCC × fSW
CINT
CEXT
fSW
:
Pin internal load capacitance
External load capacitance of output pin
Pin switching frequency
:
:
Parameter
Symbol
Conditions
4 mA type
8 mA type
12 mA type
Capacitance Value
1.93 pF
Pin internal load
capacitance
CINT
3.45 pF
3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself:
Measure current value ICC (Typ) at normal temperature (+25°C).
Add maximum leakage current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC (Typ) + ICC (leak_max)
Parameter
Symbol
Conditions
TJ = +125 °C
TJ = +105 °C
TJ = +85 °C
Current Value
53.6 mA
Maximum leakage current
at operating
ICC (leak_max)
26.6 mA
17.5 mA
Document Number: 001-98708 Rev. *E
Page 89 of 190
S6E2G Series
Current Explanation Diagram
Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC=ICC (INT)＋ΣICC (IO)
VCC
A
ICC
Chip
ΣICC (IO)
ICC (INT)
A
IOL
Regulator
VOL
V
Flash
VOH
A
IOH
V
Logic
RAM
CEXT
Document Number: 001-98708 Rev. *E
Page 90 of 190
S6E2G Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-1 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory
(Flash Accelerator Mode and Trace Buffer Function Enabled)
Value
Typ*1 Max*2
Pin
Name
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
*5
*6
*5
*6
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
73
65
59
50
43
35
27
19
11
131
123
117
108
101
93
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*3
When all peripheral
clocks are on
85
77
69
6.9
5.3
44
40
36
31
27
22
17
13
7.9
5.2
4.3
64
Normal
operation
*7,*8
4 MHz
63
Power
supply
current
ICC
VCC
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
102
98
(PLL)
94
89
85
*3
When all peripheral
clocks are off
80
75
71
65
63
4 MHz
62
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1)
6: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.”
8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 91 of 190
S6E2G Series
Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled)
Value
Typ*1 Max*2
Pin
Name
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
*5
*6
*5
*6
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
82
74
68
58
49
40
31
22
13
7.5
5.6
48
44
41
35
30
25
20
14
8.7
5.6
4.5
140
132
126
116
107
98
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*3
When all peripheral
clocks are on
89
80
71
65
Normal
operation
*7,*8
4 MHz
63
Power
supply
current
ICC
VCC
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
106
102
99
(PLL)
93
88
*3
83
When all peripheral
clocks are off
78
72
66
63
4 MHz
62
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0)
6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
7: With data access to a MainFlash memory.
8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 92 of 190
S6E2G Series
Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Value
Typ*1 Max*2
Pin
Name
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
54
47
39
31
23
14
11
112
105
97
89
81
72
69
65
95
91
86
81
75
69
66
63
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*3
*5
When all peripheral
clocks are on
Normal
operation
*6,*7
4 MHz
7.2
37
33
28
23
17
11
Power
supply
ICC
VCC
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
current
(PLL)
*3
*5
When all peripheral
clocks are off
8.3
5.9
4 MHz
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
6: With data access to a MainFlash memory.
7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 93 of 190
S6E2G Series
Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other than PLL), Code with Data Accessing
Running from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Value
Pin
Name
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
Typ*1
Max*2
*3
mA
4.3
62
When all peripheral
clocks are on
Normal
operation
*6, *7
*5
4 MHz
(main
oscillation)
*3
mA
3.7
61
When all peripheral
clocks are off
*3
Normal
operation
*6
(built-in
High-speed
CR)
3.5
2.9
61
60
58
58
58
58
mA
mA
mA
mA
mA
mA
When all peripheral
clocks are on
*5
*5
*5
4 MHz
32 kHz
100 kHz
*3
When all peripheral
clocks are off
Power
supply
ICC
VCC
current
*3
0.47
0.46
0.51
0.50
Normal
operation
*6, *8
(sub
oscillation)
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
*3
Normal
operation
*6
(built-in
low-speed
CR)
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
6: With data access to a MainFlash memory.
7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 94 of 190
S6E2G Series
Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Value
Pin
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
Name
Typ*1
58
Max*2
116
110
106
98
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
52
48
40
35
93
*3
86
28
When all peripheral clocks
are on
80
22
74
16
67
9.7
6.2
5.0
30
64
Sleep
operation*5
(PLL)
Power
4 MHz
63
supply
current
ICCS
VCC
180 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
88
27
85
25
83
21
79
18
76
*3
When all peripheral clocks
are off
15
73
12
70
9.3
6.2
4.5
4.0
67
64
62
4 MHz
62
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 95 of 190
S6E2G Series
Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Value
Pin
Parameter Symbol
Conditions
Frequency*4
Unit
Remarks
Name
Typ*1
32
Max*2
90
85
81
76
71
66
64
63
73
71
69
67
65
63
62
62
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
27
23
*3
18
When all peripheral clocks
are on
13
8.5
6.9
5.3
15
Sleep
operation*5
(PLL)
Power
4 MHz
supply
current
ICCS
VCC
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
12 MHz
8 MHz
13
11
*3
9.3
7.3
5.4
4.7
4.1
When all peripheral clocks
are off
4 MHz
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 96 of 190
S6E2G Series
Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Value
Pin
Parameter Symbol
Conditions
Frequency*4
Unit
mA
mA
Remarks
Name
Typ*1
Max*2
*3
2.6
60
When all peripheral clocks
are on
Sleep
operation*5
(main oscillation)
4 MHz
*3
2.0
2.0
60
60
59
58
58
58
58
When all peripheral clocks
are off
*3
When all peripheral clocks
are on
mA
mA
mA
mA
mA
mA
Sleep
operation
(built-in
4 MHz
32 kHz
100 kHz
*3
High-speed CR)
When all peripheral clocks
1.3
Power
are off
supply
current
ICCS
VCC
*3
When all peripheral clocks
are on
0.46
0.45
0.47
0.46
Sleep
operation*6
(sub oscillation)
*3
When all peripheral clocks
are off
*3
When all peripheral clocks
Sleep
operation
(built-in
are on
*3
low-speed CR)
When all peripheral clocks
are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0.
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 97 of 190
S6E2G Series
Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode
Value
Pin
Name
Parameter Symbol
Conditions
Frequency
Unit
Remarks
Typ*1
Max*2
*3, *4
TA = +25°C
0.41
1.9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*3, *4
TA = +85°C
Stop mode
-
-
18
26
2.9
19
27
2.2
19
27
1.9
18
27
1.9
18
27
1.9
18
27
ICCH
*3, *4
TA = +105°C
-
*3, *4
TA = +25°C
1.4
Timer mode*5
(main oscillation)
*3, *4
TA = +85°C
4 MHz
4 MHz
-
*3, *4
TA = +105°C
-
*3, *4
TA = +25°C
0.71
Timer mode
(built-in
*3, *4
TA = +85°C
-
High-speed CR)
*3, *4
TA = +105°C
-
Power
supply
current
VCC
ICCT
*3, *4
TA = +25°C
0.41
Timer mode*6
(sub oscillation)
*3, *4
TA = +85°C
32 kHz
100 kHz
32 kHz
-
*3, *4
TA = +105°C
-
*3, *4
TA = +25°C
0.42
Timer mode
(built-in
low-speed CR)
*3, *4
TA = +85°C
-
*3, *4
TA = +105°C
-
*3, *4
TA = +25°C
0.42
RTC mode*6
(sub oscillation)
*3, *4
TA = +85°C
-
-
ICCR
*3, *4
TA = +105°C
1: VCC = 3.3 V
2: VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: When LVD is off
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 98 of 190
S6E2G Series
Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode
Value
Pin
Parameter Symbol
Conditions
Frequency
Unit
Remarks
*3, *4
Name
Typ*1
Max*2
89
162
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
TA = +25°C
Deep standby
Stop mode
(When RAM
is off)
*3, *4
TA = +85°C
-
-
1689
2189
245
*3, *4
TA = +105°C
-
ICCHD
*3, *4
TA = +25°C
101
Deep standby
Stop mode
(When RAM
is on)
*3, *4
TA = +85°C
-
-
2401
3223
166
*3, *4
TA = +105°C
-
Power
supply
current
VCC
*3, *4
TA = +25°C
93
Deep standby
RTC mode*6
(When RAM
is off)
*3, *4
TA = +85°C
-
1693
2193
249
*3, *4
TA = +105°C
-
32 kHz
ICCRD
*3, *4
TA = +25°C
105
Deep standby
RTC mode*6
(When RAM
is on)
*3, *4
TA = +85°C
-
-
2405
3227
*3, *4
TA = +105°C
1: VCC = 3.3 V
2: VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: When LVD is off
5: When sub oscillation is off
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 99 of 190
S6E2G Series
Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/Erase
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
Low-voltage
detection
circuit (LVD)
power supply
current
For occurrence of
interrupt
ICCLVD
At operation
-
4
7
μA
VCC
MainFlash
memory
write/erase
current
At
*1
ICCFLASH
-
13.4
15.9
mA
write/erase
1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power
supply current (ICC).
Table 12-11 Peripheral Current Dissipation
Frequency (MHz)
Clock
Peripheral
Unit
Unit
Remarks
System
45
90
180
2.76
2.83
2.12
0.87
2.18
0.12
1.64
5.84
1.50
GPIO
DMAC
All ports
0.69
0.74
0.58
0.23
0.56
0.09
0.41
1.52
0.38
1.39
1.46
1.13
0.44
1.10
0.10
0.83
2.97
0.76
-
DSTC
-
-
External bus I/F
SD card I/F
CAN
TA=+25°C,
VCC=3.3 V
HCLK
mA
-
1 ch
1 ch
-
USB
Ethernet-MAC
Base timer
4 ch
Multi-functional
timer/PPG
1 unit/4 ch
1 unit
0.72
0.06
1.43
0.12
2.83
0.22
TA=+25°C,
VCC=3.3 V
PCLK1
PCLK2
mA
mA
Quadrature
position/revolution
counter
A/D converter
Multi-function serial
IC Card Interface
I2S clock generator
1 unit
1 ch
1 ch
1 ch
0.31
0.36
0.27
0.26
0.61
0.72
0.54
0.53
1.22
-
-
-
TA=+25°C,
VCC=3.3 V
Document Number: 001-98708 Rev. *E
Page 100 of 190
S6E2G Series
12.3.2 Pin Characteristics
(VCC = USBVCC0 = USBVCC1 = ETHVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit Remarks
Min
Typ
Max
VCC×0.8
-
-
VCC + 0.3
V
V
CMOS hysteresis input pin,
MD0, MD1
-
ETHVCC×0.8
ETHVCC + 0.3
H level input
voltage
(hysteresis
input)
At External
V
V
CC >3.0 V,
CC ≤ 3.6 V,
MADATAxx
2.4
-
VCC + 0.3
V
Bus
VIHS
5V tolerant input pin
Input pin doubled as I2C Fm+
TTL Schmitt input pin
-
-
-
VCC×0.8
VCC×0.7
2.0
-
-
-
-
-
-
-
-
VSS + 5.5
VSS + 5.5
ETHVCC+0.3
VCC×0.2
V
V
V
V
V
V
V
V
VSS - 0.3
VSS - 0.3
VSS - 0.3
VSS
CMOS hysteresis input pin,
MD0, MD1
-
ETHVCC×0.2
VCC×0.2
L level input
voltage
(hysteresis
input)
5V tolerant input pin
Input pin doubled as I2C Fm+
TTL Schmitt input pin
-
VILS
-
VCC×0.3
-
VSS - 0.3
0.8
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC - 0.5
-
-
-
-
VCC
ETHVCC
VCC
V
V
V
V
VCC < 4.5 V,
IOH = - 2 mA
4 mA type
ETHVCC ≥ 4.5 V,
IOH = - 4 mA
VCC - 0.5
ETHVCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 8 mA
VCC - 0.5
VCC < 4.5 V,
IOH = - 4 mA
8 mA type
ETHVCC ≥ 4.5 V,
IOH = - 8 mA
H level output
voltage
ETHVCC - 0.5
ETHVCC
VOH
ETHVCC < 4.5 V,
IOH = - 4 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
12 mA type
VCC - 0.5
USBVCC - 0.4
VCC - 0.5
-
-
-
VCC
USBVCC
VCC
V
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 20.5 mA
The pin
doubled as USB I/O
V
V
*1
USBVCC < 4.5 V,
IOH = - 13.0 mA
VCC ≥ 4.5 V,
IOH = - 4 mA
The pin doubled as I2C Fm+
At GPIO
VCC < 4.5V,
IOH = - 3 mA
Document Number: 001-98708 Rev. *E
Page 101 of 190
S6E2G Series
Value
Typ
Parameter
Symbol
Pin Name
Conditions
CC ≥ 4.5 V,
Unit Remarks
Min
Max
V
IOL = 4 mA
VSS
-
-
-
-
-
-
0.4
V
VCC < 4.5 V,
IOL = 2 mA
4 mA type
ETHVCC ≥ 4.5 V,
IOL = 4 mA
VSS
VSS
VSS
VSS
VSS
0.4
0.4
0.4
0.4
0.4
V
V
V
V
RTHVCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 8 mA
VCC < 4.5 V,
IOL = 4 mA
8 mA type
ETHVCC ≥ 4.5 V,
IOL = 8 mA
RTHVCC < 4.5 V,
IOL = 4 mA
L level output
voltage
VOL
VCC ≥ 4.5 V,
IOL = 12 mA
12 mA type
VCC < 4.5 V,
IOL = 8 mA
USBVCC ≥ 4.5 V,
IOL = 18.5 mA
The pin doubled
as USB I/O
V
V
*1
USBVCC < 4.5 V,
IOL = 10.5 mA
VCC ≥ 4.5 V,
IOL = 4 mA
At GPIO
VCC < 4.5 V,
IOL = 3 mA
The pin doubled
as I2C Fm+
VSS
-
-
0.4
+ 5
At I2C
Fm+
VCC ≤ 4.5 V,
IOL = 20 mA
Input leak
current
IIL
-
-
- 5
μA
kΩ
VCC ≥ 4.5 V
25
30
50
80
100
200
Pull-up
resistor value
RPU
Pull-up pin
VCC < 4.5 V
Other than
VCC,
USBVCC0,
USBVCC1,
ETHVCC,
VSS,
Input
capacitance
CIN
-
-
5
15
pF
AVCC, AVSS,
AVRH
1: USBVCC0 and USBVCC1 are described as USBVCC
.
Document Number: 001-98708 Rev. *E
Page 102 of 190
S6E2G Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40C to +105C)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
4
4
48
20
V
CC ≥4.5 V
VCC < 4.5 V
CC ≥4.5 V
VCC < 4.5 V
CC ≥4.5 V
VCC < 4.5 V
PWH/tCYLH
When crystal oscillator is
connected
MHz
MHz
ns
Input frequency
fCH
4
48
V
When using external clock
When using external clock
4
20
X0,
X1
V
20.83
50
250
250
Input clock cycle
tCYLH
,
Input clock pulse width
When using external clock
When using external clock
-
45
55
5
%
PWL/tCYLH
Input clock rise time and
fall time
tCF
,
-
-
ns
tCR
Base clock (HCLK/FCLK)
APB0bus clock *2
fCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
180
MHz
MHz
MHz
MHz
ns
fCP0
90
Internal operating clock *1
frequency
APB1bus clock *2
fCP1
-
180
APB2bus clock *2
fCP2
-
90
-
Base clock (HCLK/FCLK)
APB0bus clock *2
tCYCC
tCYCP0
tCYCP1
tCYCP2
5.56
11.1
5.56
11.1
-
ns
Internal operating clock *1
cycle time
APB1bus clock *2
-
ns
APB2bus clock *2
-
ns
1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main
Part (002-04856).
2: For more about each APB bus to which each peripheral is connected, see 1. S6E2G Series Block Diagram in this data
sheet.
X0
Document Number: 001-98708 Rev. *E
Page 103 of 190
S6E2G Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
When crystal
Min
Max
oscillator is connected
-
-
32.768
-
kHz
*
Input frequency
1/tCYLL
When using external
clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
μs
X0A,
X1A
When using external
clock
Input clock cycle
tCYLL
PWH/tCYLL
PWL/tCYLL
,
When using external
clock
Input clock pulse width
-
%
*: For more information about crystal oscillator, see Sub crystal oscillator in 9. Handling Devices.
tCYLL
0.8 × VCC
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
X0A
PWH
PWL
12.4.3 Built-In CR Oscillation Characteristics
Built-In High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
3.92
3.88
2.9
Typ
4
Max
4.08
4.12
5
TJ = - 20°C to + 105°C
TJ = - 40°C to + 125°C
TJ = - 40°C to + 125°C
*1
When trimmed
Clock frequency
fCRH
4
MHz
When not trimmed
*2
4
Frequency
stabilization
time
tCRWT
-
-
-
30
μs
1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming
2: This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is
able to use the High-speed CR clock as a source clock.
Built-In Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
Clock frequency
fCRL
-
50
100
150
kHz
Document Number: 001-98708 Rev. *E
Page 104 of 190
S6E2G Series
12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
13
200
-
-
-
-
-
16
MHz
multiplier
MHz
100
400
180
PLL macro oscillation clock frequency
Main PLL clock frequency*2
MHz
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual
Main Part (002-04856).
12.4.5 Operating Conditions of USB/Ethernet PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
-
4
-
-
-
16
MHz
multiplier
MHz
PLL multiplication rate
13
100
400
PLL macro oscillation clock frequency
USB/Ethernet
fPLLO
200
After the M
frequency division
*2
USB/Ethernet clock frequency
fCLKPLL
-
-
50
MHz
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family
Peripheral Manual Communication Macro Part (002-04862).
Document Number: 001-98708 Rev. *E
Page 105 of 190
S6E2G Series
12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
fPLLI
100
-
-
μs
PLL input clock frequency
3.8
4
4.2
MHz
PLL multiplication rate
-
50
-
-
95
multiplier
MHz
PLL macro oscillation clock frequency
fPLLO
190
400
Main PLL clock frequency *2
fCLKPLL
-
-
180
MHz
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part
(002-04856).
Note:
−
The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main
PLL.
12.4.7 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol Pin Name
tINITX INITX
Conditions
Unit
Remarks
Min
Max
Reset input time
-
500
-
ns
Document Number: 001-98708 Rev. *E
Page 106 of 190
S6E2G Series
12.4.8 Power-On Reset Timing
(VSS = 0V)
Value
Typ
-
Pin
Parameter
Symbol
Conditions
Unit
Remarks
Name
Min
1
Max
Power supply shut down time
Power ramp rate
*1
*2
tOFF
dV/dt
tPRT
-
-
ms
VCC
VCC: 0.2V to 2.70V
0.6
0.33
-
-
1000 mV/µs
0.60 ms
Time until releasing Power-on reset
-
1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”.
12.4.9 GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol Pin Name
Conditions
Unit
Remarks
Min
Max
50
VCC ≥ 4.5V
VCC < 4.5V
-
-
MHz
MHz
Output frequency
tPCYCLE
Pxx*
32
*: GPIO is a target.
Pxx
tPCYCLE
Document Number: 001-98708 Rev. *E
Page 107 of 190
S6E2G Series
12.4.10 External Bus Timing
External Bus Clock Output Characteristics
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
MCLKOUT *1
50 *2
Output frequency
tCYCLE
-
MHz
1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral
Manual Main Part (002-04856).
2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz.
0.8 × VCC
0.8 × VCC
MCLK
tCYCLE
External Bus Signal I/O Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
VIH
Conditions
Value
Unit
V
Remarks
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
Signal input characteristics
VIL
V
-
VOH
V
Signal output characteristics
VOL
V
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Document Number: 001-98708 Rev. *E
Page 108 of 190
S6E2G Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
MOEX
Minimum pulse width
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MOEX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCSX↓→Address
output delay time
MCSX[7: 0],
MAD[24: 0]
-9
+9
MOEX↑→Address
hold time
MOEX,
MAD[24: 0]
0
MCLK×m+9
MCLK×m+9
MCLK×m+9
MCLK×m+9
-
MCSX↓→
MOEX↓delay time
MCLK×m-9
MOEX,
MCSX[7: 0]
MOEX↑→
MCSX↑time
0
MCSX↓→
MDQM↓delay time
MCSX,
MDQM[3: 0]
MCLK×m-9
Data set up→MOEX↑
time
MOEX,
MADATA[31: 0]
20
MOEX↑→
Data hold time
MOEX,
MADATA[31: 0]
tDH - OE
0
-
MWEX
Minimum pulse width
tWEW
MWEX
MCLK×n-3
-
MWEX↑→Address
output delay time
MWEX,
MAD[24: 0]
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DX
0
MCLK×n-9
0
MCLK×m+9
MCLK×n+9
MCLK×m+9
MCLK×n+9
MCLK+9
MCLK×m+9
MCSX↓→
MWEX↓delay time
MWEX,
MCSX[7: 0]
MWEX↑→
MCSX↑delay time
MCSX↓→
MDQM↓delay time
MCSX,
MDQM[3: 0]
MCLK×n-9
MCLK-9
0
MCSX↓→
Data output time
MCSX,
MADATA[31: 0]
MWEX↑→
Data hold time
MWEX,
MADATA[31: 0]
tWEH - DX
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
Document Number: 001-98708 Rev. *E
Page 109 of 190
S6E2G Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7: 0]
tCSL-AV
tOEH-AX
tCSL-AV
MAD[24: 0]
MOEX
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1: 0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15: 0]
tCSL-DX
Document Number: 001-98708 Rev. *E
Page 110 of 190
S6E2G Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Address delay time
MCSX delay time
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
MCLK,
MAD[24: 0]
tAV
-
1
9
ns
tCSL
tCSH
tREL
tREH
-
-
-
-
1
1
1
1
9
9
9
9
ns
ns
ns
ns
MCLK,
MCSX[7: 0]
MCLK,
MOEX
MOEX delay time
Data set up
→MCLK↑ time
MCLK,
MADATA[31: 0]
tDS
tDH
-
-
19
0
-
-
ns
ns
MCLK↑→
Data hold time
MCLK,
MADATA[31: 0]
tWEL
tWEH
tDQML
tDQMH
-
-
-
-
1
1
1
1
9
9
9
9
ns
ns
ns
ns
MCLK,
MWEX
MWEX delay time
MDQM[1: 0]
delay time
MCLK,
MDQM[3: 0]
MCLK↑→
Data output time
MCLK,
MADATA[31: 0]
tODS
tOD
-
-
MCLK+1
1
MCLK+18
18
ns
ns
MCLK↑→
Data hold time
MCLK,
MADATA[31: 0]
Note:
−
When the external load capacitance CL = 30 pF
tCYCLE
MCLK
tCSL
tCSH
MCSX[7: 0]
tAV
tAV
Address
Address
MAD[24: 0]
MOEX
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[3: 0]
MWEX
tWEL
tDS
tDH
RD
Invalid
WD
MADATA[31: 0]
tODS
Document Number: 001-98708 Rev. *E
Page 111 of 190
S6E2G Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Multiplexed
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
tALE-CHMADV
tCHMADH
-
-
0
10
ns
ns
address delay time
MALE,
MAD[24: 0]
Multiplexed address hold
time
MCLK×n+0 MCLK×n+10
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
Document Number: 001-98708 Rev. *E
Page 112 of 190
S6E2G Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
tCHAL
tCHAH
tCHMADV
tCHMADX
-
-
1
9
9
MCLK,
MALE
MALE delay time
1
1
MCLK↑→Multiplexed
address delay time
-
-
tOD
tOD
ns
ns
MCLK,
MADATA[31: 0]
MCLK↑→Multiplexed
data output time
1
Note:
−
When the external load capacitance CL = 30 pF
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
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Page 113 of 190
S6E2G Series
NAND Flash Mode
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
MNREX
Min pulse width
tNREW
MNREX
-
-
-
-
-
-
-
-
-
-
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data set up
→MNREX↑time
MNREX,
MADATA[31: 0]
tDS – NRE
20
-
MNREX↑→
Data hold time
MNREX,
MADATA[31: 0]
tDH – NRE
0
-
MNALE↑→
MNWEX delay time
MNALE,
MNWEX
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
MCLK×m-9
MCLK×m-9
MCLK×m-9
0
MCLK×m+9
MCLK×m+9
MCLK×m+9
MCLK×m+9
-
MNALE↓→
MNWEX delay time
MNALE,
MNWEX
MNCLE↑→
MNWEX delay time
MNCLE,
MNWEX
MNWEX↑→
MNCLE delay time
MNCLE,
MNWEX
MNWEX
Min pulse width
MNWEX
MCLK×n-3
-9
MNWEX↓→
Data output time
MNWEX,
MADATA[31: 0]
tNWEL – DV
tNWEH – DX
9
MNWEX↑→
Data hold time
MNWEX,
MADATA[31: 0]
0
MCLK×m+9
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[31: 0]
Read
Document Number: 001-98708 Rev. *E
Page 114 of 190
S6E2G Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Write
Document Number: 001-98708 Rev. *E
Page 115 of 190
S6E2G Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
MCLK↑
MRDY input
setup time
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
MCLK,
MRDY
tRDYI
-
19
-
ns
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
tRDYI
MWEX
0.5×VCC
MRDY
Document Number: 001-98708 Rev. *E
Page 116 of 190
S6E2G Series
SDRAM Mode
Parameter
(VCC = 2.7V to 3.6V, VSS = 0V)
Unit
Symbol
Pin Name
Value
Unit
Remarks
Min
Max
Output frequency
tCYCSD
tAOSD
MSDCLK
-
-
-
50
MHz
ns
MSDCLK,
MAD[15: 0]
Address delay time
2
2
12
12
19.5
12
12
12
12
12
12
-
MSDCLK↑→
Data output delay time
MSDCLK,
MADATA[31: 0]
tDOSD
tDOZSD
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSDCLK↑→
Data output Hi-Z time
MSDCLK,
MADATA[31: 0]
2
MSDCLK,
MDQM[1: 0]
MDQM[3: 0] delay time
MCSX delay time
1
MSDCLK,
MCSX8
2
MSDCLK,
MRASX
MRASX delay time
MCASX delay time
MSDWEX delay time
MSDCKE delay time
Data set up time
2
MSDCLK,
MCASX
2
MSDCLK,
MSDWEX
2
MSDCLK,
MSDCKE
2
MSDCLK,
MADATA[31: 0]
19
0
MSDCLK,
MADATA[31: 0]
Data hold time
tDHSD
-
Note:
−
When the external load capacitance CL = 30 pF
Document Number: 001-98708 Rev. *E
Page 117 of 190
S6E2G Series
tCYCSD
SDRAM Access
MSDCLK
tAOSD
MAD[24:0]
MDQM[1:0]
MCSX
Address
tWROSD
tMCSSD
tRASSD
MRASX
tCASSD
tMWESD
tCKESD
MCASX
MSDWEX
MSDCKE
tDSSD
RD
tDHSD
MADATA[15:0]
MADATA[15:0]
tDOSD
tDOZSD
WD
Document Number: 001-98708 Rev. *E
Page 118 of 190
S6E2G Series
12.4.11 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Conditi
ons
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as ECK, TIN)
Input pulse width
tTIWH, tTIWL
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Conditi
ons
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as TGIN)
Input pulse width
tTRGH, tTRGL
-
2tCYCP
-
ns
tTRGH
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is
connected, see 1. S6E2G Series Block Diagram in this data sheet.
Document Number: 001-98708 Rev. *E
Page 119 of 190
S6E2G Series
12.4.12 CSIO (SPI) Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
SCK↓→SOT delay time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
tSLOVI
tIVSHI
tSHIXI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Internal shift
clock operation
SIN→SCK↑
setup time
SCKx,
SINx
-
-
-
-
SCKx,
SINx
SCK↑→SIN hold time
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
-
-
2tCYCP - 10
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock
operation
SIN→SCK↑
setup time
SCKx,
SINx
10
20
10
20
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 120 of 190
S6E2G Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
tR
VIH
SCK
VIL
VIL
SLOVE
t
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 121 of 190
S6E2G Series
Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
ns
Internal shift
clock operation
SCKx,
SINx
SIN→SCK↓ setup time
tIVSLI
50
-
30
-
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
tSLSH
tSHSL
0
-
-
-
0
-
-
-
ns
ns
ns
Serial clock L pulse width
Serial clock H pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
2tCYCP - 10
tCYCP + 10
SCKx,
SOTx
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock operation
SCKx,
SINx
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 122 of 190
S6E2G Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
tSHOVE
VIH
SCK
VIL
VIL
VIL
tF
tR
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 123 of 190
S6E2G Series
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↓
setup time
SCKx,
SINx
Internal shift
clock operation
tIVSLI
tSLIXI
tSOVLI
50
0
-
-
-
30
0
-
-
-
ns
ns
ns
SCKx,
SINx
SCK↓→SIN hold time
SOT→SCK↓ delay time
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
-
-
2tCYCP - 10
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
SIN→SCK↓
setup time
SCKx,
SINx
External shift
clock operation
10
20
10
20
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 124 of 190
S6E2G Series
tSCYC
VOH
VOL
VOL
SCK
SOT
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 001-98708 Rev. *E
Page 125 of 190
S6E2G Series
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
SCK↓→SOT delay time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
tSLOVI
tIVSHI
tSHIXI
tSOVHI
- 30
+ 30
- 20
+ 20
ns
ns
ns
ns
SCKx,
SINx
SIN→SCK↑ setup time
SCK↑→SIN hold time
SOT→SCK↑ delay time
Internal shift
clock operation
50
0
-
-
-
30
0
-
-
-
SCKx,
SINx
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
-
-
2tCYCP - 10
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
SCKx,
SINx
External shift
clock operation
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 126 of 190
S6E2G Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
V
IL
VIL
VIL
t
SLOVE
SOT
SIN
VOH
VOL
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 127 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Unit
Parameter
Symbol
Conditions
Min
Max
Min
Max
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
(*1)-50
(*2)+0
(*1)+0
(*2)+50
(*1)-50
(*1)+0
(*2)+50
ns
ns
Internal shift
clock
(*2)+0
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 128 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 129 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Unit
Parameter
Symbol
Conditions
Min
Max
Min
Max
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
(*1)-50
(*2)+0
(*1)+0
(*2)+50
(*1)-50
(*1)+0
(*2)+50
ns
ns
Internal shift
clock
(*2)+0
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+30
-
3tCYCP+30
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 130 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 131 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Unit
Parameter
Symbol Conditions
Min
Max
Min
Max
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
tCSSI
(*1)-50
(*2)+0
(*1)+0
(*2)+50
(*1)-50
(*1)+0
(*2)+50
ns
ns
Internal shift
tCSHI
(*2)+0
clock
operation
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External shift
clock
operation
tCSDE
tDSE
tDEE
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 132 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 133 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Units
Parameter
Symbol Conditions
Min
Max
Min
Max
SCS↑→SCK↑setup time
SCK↓→SCS↓hold time
tCSSI
(*1)-50
(*2)+0
(*1)+0
(*2)+50
(*1)-50
(*1)+0
(*2)+50
ns
ns
Internal shift
tCSHI
(*2)+0
clock
operation
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
SCS deselect time
ns
SCS↑→SCK↑setup time
SCK↓→SCS↓hold time
SCS deselect time
tCSSE
3tCYCP+30
-
-
3tCYCP+30
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External
shift clock
operation
tCSDE
tDSE
tDEE
3tCYCP+30
-
3tCYCP+30
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 134 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 135 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
SCK↓→SOT delay time
- 10
+ 10
- 10
12.5
5
+ 10
Internal shift
clock operation
14
SCKx,
SINx
SIN→SCK↑ setup time
SCK↑→SIN hold time
tIVSHI
-
-
-
-
ns
ns
12.5*
SCKx,
SINx
tSHIXI
5
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 5
-
-
2tCYCP - 5
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
SCKx,
SINx
External shift
clock operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 136 of 190
S6E2G Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
tR
VIH
VIL
VIL
tSLOVE
SOT
SIN
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 137 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Parameter
Serial clock cycle time
SCK↑→SOT delay time
Symbol
tSCYC
Conditions
Name
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
tSHOVI
- 10
+ 10
- 10
+ 10
Internal shift
clock operation
14
SCKx,
SINx
SIN→SCK↓ setup time
SCK↓→SIN hold time
tIVSLI
-
-
12.5
5
-
-
ns
ns
12.5*
SCKx,
SINx
tSLIXI
5
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 5
-
-
2tCYCP - 5
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
15
-
-
15
-
ns
ns
ns
SCKx,
SINx
External shift
clock operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 138 of 190
S6E2G Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
tSHOVE
VIH
SCK
VIL
V
IL
VIL
tF
tR
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
V
V
IH
IH
V
IL
V
IL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 139 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Parameter
Serial clock cycle time
SCK↑→SOT delay time
Symbol
tSCYC
Conditions
Name
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
tSHOVI
- 10
+ 10
- 10
+ 10
14
SCKx,
SINx
Internal shift
clock operation
SIN→SCK↓ setup time
tIVSLI
-
12.5
-
ns
12.5*
SCKx,
SINx
SCK↓→SIN hold time
SOT→SCK↓ delay time
tSLIXI
5
-
-
5
-
-
ns
ns
SCKx,
SOTx
tSOVLI
2tCYCP - 10
2tCYCP - 10
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 5
-
-
2tCYCP - 5
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↑→SOT delay time
SIN→SCK↓ setup time
SCK↓→SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
15
-
-
15
-
ns
ns
ns
SCKx,
SINx
External shift
clock operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 140 of 190
S6E2G Series
tSCYC
VOH
VOL
VOL
SCK
SOT
SIN
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
V
IL
V
IH
IL
IH
V
V
MS bit = 1
*: Changes when writing to TDR register
Document Number: 001-98708 Rev. *E
Page 141 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Pin
Name
Parameter
Symbol
Conditions
Min
Max
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
SCK↓→SOT delay time
- 10
+ 10
- 10
+ 10
14
SCKx,
SINx
SIN→SCK↑ setup time
tIVSHI
Internal shift
clock operation
-
12.5
-
ns
12.5*
SCKx,
SINx
SCK↑→SIN hold time
SOT→SCK↑ delay time
tSHIXI
5
-
-
5
-
-
ns
ns
SCKx,
SOTx
tSOVHI
2tCYCP - 10
2tCYCP - 10
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 5
-
-
2tCYCP - 5
-
-
ns
ns
tCYCP + 10
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
SCKx,
SINx
External shift
clock operation
5
5
5
5
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 142 of 190
S6E2G Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
SCK
VIH
VIH
VIH
V
IL
VIL
V
IL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
V
V
IH
IH
V
IL
V
IL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 143 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Parameter
Symbol Conditions
Min
Max
Min
Max
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
(*1)-20
(*2)+0
(*1)+0
(*2)+20
(*1)-20
(*1)+0
(*2)+20
ns
ns
Internal shift
tCSHI
(*2)+0
clock
operation
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External shift
clock
operation
tCSDE
tDSE
tDEE
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 144 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 145 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC≥ 4.5 V
Unit
Parameter
Symbol
Conditions
Min
Min
Min
Max
SCS↓→SCK↓ setup time
SCK↑→SCS↑ hold time
tCSSI
tCSHI
(*1)-20
(*2)+0
(*1)+0
(*2)+20
(*1)-20
(*1)+0
(*2)+20
ns
ns
Internal shift
clock
(*2)+0
operation
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↓→SCK↑ setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 146 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 147 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Parameter
Symbol Conditions
Min
Max
Min
Max
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
tCSSI
(*1)-20
(*2)+0
(*1)+0
(*2)+20
(*1)-20
(*1)+0
(*2)+20
ns
ns
Internal shift
tCSHI
(*2)+0
clock
operation
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
tCSHE
0
0
External shift
clock
operation
tCSDE
tDSE
tDEE
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 148 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 149 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Parameter
Symbol
Conditions
Min
Max
Min
Max
SCS↓→SCK↓ setup time
SCK↑→SCS↓ hold time
tCSSI
tCSHI
(*1)-20
(*2)+0
(*1)+0
(*2)+20
(*1)-20
(*1)+0
(*2)+20
ns
ns
Internal shift
clock
(*2)+0
operation
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
SCS deselect time
tCSDI
ns
SCS↑→SCK↑ setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSE
tCSHE
tCSDE
tDSE
3tCYCP+15
-
-
3tCYCP+15
-
-
ns
ns
ns
ns
ns
0
0
External shift
clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
40
-
-
40
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 150 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
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S6E2G Series
External Clock (EXT = 1): When in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol Condition
Unit
Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK fall time
tSLSH
tCYCP + 10
-
-
ns
ns
ns
ns
tSHSL
tCYCP + 10
CL = 30 pF
tF
-
-
5
5
SCK rise time
tR
tR
tF
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
V
V
IL
V
IL
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S6E2G Series
12.4.13 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
2tCYCP
2tCYCP
Max
A/D converter trigger input
ADTGx
FRCKx
*1
*1
-
-
ns
Free-run timer input clock
Input capture
Icxx
Waveform generator
DTTIxX
-
-
-
-
ns
ns
Input pulse
width
tINH, tINL
2tCYCP + 100*1
500*2
INT00 to INT31,
NMIX
External interrupt,
NMI
-
-
ns
ns
500*3
Deep standby wake up
WKUPx
-
1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about
the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 1. S6E2G
Series Block Diagram in this data sheet.
2: When in Stop mode, in Timer mode
3: When in Deep Standby RTC mode, in Deep Standby Stop mode
Document Number: 001-98708 Rev. *E
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S6E2G Series
12.4.14 Quadrature Position/Revolution Counter Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Unit
Parameter
AIN pin H width
Symbol
Conditions
Min
Max
tAHL
tALL
tBHL
tBLL
-
-
-
-
AIN pin L width
BIN pin H width
BIN pin L width
BIN rise time from
AIN pin H level
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
AIN fall time from
BIN pin H level
BIN fall time from
AIN pin L level
AIN rise time from
BIN pin L level
AIN rise time from
BIN pin H level
-
ns
2tCYCP
*
BIN fall time from
AIN pin H level
AIN fall time from
BIN pin L level
BIN rise time from
AIN pin L level
ZIN pin H width
ZIN pin L width
tZHL
tZLL
QCR: CGSC = 0
QCR: CGSC = 0
AIN/BIN rise and fall time
from determined ZIN level
tZABE
tABEZ
QCR: CGSC = 1
QCR: CGSC = 1
Determined ZIN level from
AIN/BIN rise and fall time
*: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the
APB bus number to which the quadrature position/revolution counter is connected, see 1. S6E2G Series Block Diagram in
this data sheet.
Document Number: 001-98708 Rev. *E
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S6E2G Series
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
Document Number: 001-98708 Rev. *E
Page 155 of 190
S6E2G Series
ZIN
ZIN
AIN/BIN
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S6E2G Series
12.4.15 I2C Timing
Standard-Mode, Fast-Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Standard-Mode
Fast-Mode
Conditions
Unit Remarks
Parameter
Symbol
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
CL = 30 pF,
*1
R = (Vp/IOL
)
Data hold time
SCL ↓ → SDA ↓ ↑
3.45*2
0.9*3
tHDDAT
tSUDAT
tSUSTO
0
0
μs
ns
μs
Data setup time
SDA ↓ ↑ → SCL ↑
250
4.0
-
-
100
0.6
-
-
Stop condition setup time
SCL ↑ → SDA ↑
Bus free time between
Stop condition and
START condition
tBUF
4.7
-
1.3
-
μs
ns
2 MHz ≤
CYCP＜40 MHz
*4
*4
*4
*4
*4
*4
*4
*4
-
-
-
-
-
-
-
-
2 tCYCP
4 tCYCP
6 tCYCP
8 tCYCP
2 tCYCP
4 tCYCP
6 tCYCP
8 tCYCP
t
40 MHz ≤
tCYCP ＜60 MHz
ns
Noise filter
tSP
*5
60 MHz ≤
tCYCP ＜80 MHz
ns
ns
80 MHz ≤
tCYCP ≤100 MHz
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see
1.S6E2G Series Block Diagram in this data sheet.
When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.
When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
Document Number: 001-98708 Rev. *E
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S6E2G Series
Fast mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Fast mode Plus (Fm+)*6
Parameter
Symbol
fSCL
Conditions
Unit
kHz
μs
Remarks
Min
Max
SCL clock frequency
0
1000
(Repeated) START condition
hold time
tHDSTA
0.26
-
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
tLOW
tHIGH
0.5
-
-
μs
μs
0.26
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
0.26
-
μs
CL = 30 pF,
*1
R = (Vp/IOL
)
Data hold time
SCL ↓ → SDA ↓ ↑
0.45*2, *3
tHDDAT
tSUDAT
tSUSTO
0
μs
ns
μs
Data setup time
SDA ↓ ↑ → SCL ↑
50
-
-
Stop condition setup time
SCL ↑ → SDA ↑
0.26
Bus free time between
Stop condition and
START condition
tBUF
0.5
-
μs
60 MHz ≤
CYCP＜80 MHz
*4
*4
-
-
ns
ns
6 tCYCP
8 tCYCP
t
Noise filter
tSP
*5
80 MHz ≤
tCYCP ≤100 MHz
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.”
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see
1.S6E2G Series Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.
See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.
Document Number: 001-98708 Rev. *E
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S6E2G Series
Document Number: 001-98708 Rev. *E
Page 159 of 190
S6E2G Series
12.4.16 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referenced to VIH and VIL transition points)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Clock frequency Data
Transfer mode
fPP
fOD
S_CLK
S_CLK
0
25
MHz
kHz
Clock frequency
Identification mode
0/100
400
CCARD ≤ 10 pF
(1card)
Clock low time
Clock high time
Clock rise time
Clock fall time
tWL
tWH
tTLH
tTHL
S_CLK
S_CLK
S_CLK
S_CLK
10
10
-
-
ns
ns
ns
ns
-
10
10
-
*: 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3: 0
Input set-up time
tISU
tIH
5
-
ns
ns
CCARD ≤ 10 pF
(1card)
S_CMD,
S_DATA3: 0
Input hold time
5
-
Card Outputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Output Delay time during
Data Transfer mode
S_CMD,
S_DATA3: 0
tODLY
tODLY
0
14
ns
ns
CCARD ≤ 40 pF
(1card)
Output Delay time during
Identification mode
S_CMD,
S_DATA3: 0
0
50
tWH
tWL
VIH
VIH
S_CLK
VIH
VIL
VIL
(SD Clock)
tTLH
tTHL
tIH
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3: 0
(Card Input)
tODLY(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3: 0
(Card Output)
Default-Speed mode
Document Number: 001-98708 Rev. *E
Page 160 of 190
S6E2G Series
Notes:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
−
For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main
Part (002-04856).
High-speed Mode
Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Max
Min
Clock frequency Data Transfer
mode
fPP
S_CLK
0
45
MHz
Clock low time
Clock high time
Clock rise time
Clock fall time
tWL
tWH
tTLH
tTHL
S_CLK
S_CLK
S_CLK
S_CLK
7
7
-
-
-
ns
ns
ns
ns
CCARD ≤ 10 pF
(1 card)
3
3
-
Card Inputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
S_CMD,
S_DATA3: 0
Input set-up time
Input hold time
tISU
tIH
6
-
ns
ns
CCARD ≤ 10 pF
(1 card)
S_CMD,
S_DATA3: 0
2
-
Card Outputs CMD, DAT (referenced to Clock CLK)
Value
Parameter
Symbol
Pin Name
Conditions
Remarks
Min
Max
Output delay time during data
transfer mode
S_CMD,
S_DATA3: 0
CL ≤ 40 pF
(1 card)
tODLY
tOH
0
14
ns
ns
pF
S_CMD,
S_DATA3: 0
CL ≥ 15 pF
(1 card)
Output hold time
2.5
-
Total system capacitance for
each line*
CL
-
1 card
-
40
*: In order to satisfy severe timing, host shall drive only one card.
Document Number: 001-98708 Rev. *E
Page 161 of 190
S6E2G Series
tWH
tWL
VIH
VIH
S_CLK
VIH
50%VCC
50%VCC
tIH
VIL
VIL
(SD Clock)
tTLH
tTHL
tISU
S_CMD,
VIH
VIL
VIH
VIL
S_DATA3: 0
(Card Input)
tOH(Min)
tODLY(Max)
S_CMD,
VOH
VOL
VOH
VOL
S_DATA3: 0
(Card Output)
High-speed mode
Notes:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is
the Host.
−
For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual
Main Part (002-04856).
12.4.17 ETM/ HTM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
2
9
ns
TRACECLK,
Data hold
tETMH
TRACED[15: 0]
VCC ＜4.5 V
VCC ≥ 4.5 V
VCC ＜4.5 V
2
15
50
32
MHz
MHz
TRACECLK
frequency
1/tTRACE
TRACECLK
VCC ≥ 4.5 V
20
-
-
ns
ns
TRACECLK
clock cycle
tTRACE
VCC ＜4.5 V
31.25
Note:
−
When the external load capacitance CL = 30 pF.
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Page 162 of 190
S6E2G Series
HCLK
TRACECLK
TRACED[15: 0]
Document Number: 001-98708 Rev. *E
Page 163 of 190
S6E2G Series
12.4.18 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
TCK,
TMS, TDI setup time
tJTAGS
15
-
ns
TMS, TDI
VCC ＜4.5 V
VCC ≥ 4.5 V
VCC ＜4.5 V
VCC ≥ 4.5 V
VCC ＜4.5 V
TCK,
TMS, TDI
TMS, TDI hold time
tJTAGH
15
-
ns
ns
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 001-98708 Rev. *E
Page 164 of 190
S6E2G Series
12.4.19 Ethernet-MAC Timing
RMII Transmission (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
Reference clock cycle time*2
tREFCYC
tREFCYCH
tREFCYCL
E_RXCK_REFCK
E_RXCK_REFCK
E_RXCK_REFCK
20 ns (typical)
tREFCYCH/tREFCYC
tREFCYCL/tREFCYC
-
-
ns
%
%
Reference clock
High-pulse-width duty cycle
35
35
65
65
Reference clock
Low-pulse-width duty cycle
E_TX03, E_RX02,
E_TX01, E_TX00,
E_TXEN
REFCK ↑ → Transmitted data
delay time
tRMIITX
-
-
12
ns
*1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output
current.
*2: The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device
specifications.
tREFCYC
E_RXCK_REFCK
VIHS
VIHS
VILS
tREFCYCH
tREFCYCL
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
VOH
VOL
tRMIITX
Document Number: 001-98708 Rev. *E
Page 165 of 190
S6E2G Series
RMII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Parameter
Reference clock
Symbol
Pin Name
Conditions
Unit
Min
Max
tREFCYC
tREFCYCH
tREFCYCL
E_RXCK_REFCK
E_RXCK_REFCK
E_RXCK_REFCK
20 ns (typical)
tREFCYCH/tREFCYC
tREFCYCL/tREFCYC
-
-
ns
%
%
cycle time*
Reference clock
High-pulse-width duty cycle
35
35
65
65
Reference clock
Low-pulse-width duty cycle
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
Received data → REFCK↑
Setup time
tRMIIRXS
-
-
4
2
-
-
ns
ns
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
REFCK ↑ → Received data
Hold time
tRMIIRXH
*: The reference clock is fixed to 50 MHz in the RMII specifications.
The clock accuracy should meet the PHY-device specifications.
tREFCYC
VILS
E_RXCK_REFCK
VIHS
VIHS
tREFCYCH
tREFCYCL
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VILS
VIHS
VILS
tRMIIRXH
tRMIIRXS
Document Number: 001-98708 Rev. *E
Page 166 of 190
S6E2G Series
Management Interface
Parameter
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Symbol
Pin Name
Conditions
Unit
Min
Max
Management clock
cycle time*
tMDCYC
tMDCYCH
tMDCYCL
tMDO
E_MDC
E_MDC
E_MDC
E_MDIO
E_MDIO
E_MDIO
-
400
-
ns
%
Management clock
High pulse width duty cycle
tMDCYCH/tMDCYC
35
35
-
65
65
60
-
Management clock
Low pulse width duty cycle
tMDCYCL/tMDCYC
%
MDC ↓ → MDIO
Delay time
-
-
-
ns
ns
ns
MDIO → MDC ↑
Setup time
tMDIS
20
0
MDC ↑ → MDIO
Hold time
tMDIH
-
*: The clock time should be set to a value greater than the minimum value by setting the Ethernet-MAC setting register.
tMDCYC
VOH
VOL
VOH
VOL
E_MDC (output)
E_MDIO (input)
tMDCYCH
tMDCYCL
VIHS
VILS
VIHS
VILS
VIHS
VILS
VIHS
VILS
tMDIS
tMDIH
tMDIS
tMDIH
tMDO
tMDO
VOH
VOL
VOH
VOL
E_MDIO (output)
Document Number: 001-98708 Rev. *E
Page 167 of 190
S6E2G Series
MII Transmission (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
100 Mbps
40 ns (typical)
-
-
ns
ns
%
%
Transmission clock
Cycle time*2
tTXCYC
E_TCK
100 Mbps
400 ns (typical)
-
-
Transmission clock
High-pulse-width duty cycle
tTXCYCH
tTXCYCL
E_TCK
E_TCK
tTXCYCH/tTXCYC
tTXCYCL/tTXCYC
35
35
65
65
Transmission clock
Low-pulse-width duty cycle
E_TX03, E_TX02,
E_TX01, E_TX00,
E_TXEN
TXCK ↑ → Transmitted data delay
time
tMIITX
-
-
24
ns
1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output current.
2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the
PHY-device specifications.
tTXCYC
VIHS
VIHS
E_TCK
VILS
tTXCYCH
tTXCYCL
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
VOH
VOL
tMIITX
Document Number: 001-98708 Rev. *E
Page 168 of 190
S6E2G Series
MII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
100 Mbps
40 ns (typical)
-
-
ns
ns
%
%
Receiving clock
cycle time*
tRXCYC
E_RXCK_REFCK
100 Mbps
400 ns (typical)
-
-
Receiving clock
High pulse width duty cycle
tRXCYCH
tRXCYCL
E_RXCK_REFCK
E_RXCK_REFCK
tRXCYCH/tRXCYC
tRXCYCL/tRXCYC
35
35
65
65
Receiving clock
Low pulse width duty cycle
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
Received data →
REFCK ↑Setup time
tMIIRXS
-
-
5
2
-
-
ns
ns
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
REFCK ↑ →
Received data Hold time
tMIIRXH
*: The receiving clock 100Mbps is fixed to 25MHz or 2.5MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tRXCYC
E_RXCK_REFCK
VIHS
VIHS
VILS
tRXCYCH
tRXCYCL
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VILS
VIHS
VILS
tMIIRXS
tMIIRXH
Document Number: 001-98708 Rev. *E
Page 169 of 190
S6E2G Series
12.4.20 I2S Timing (Multi-function Serial Interface)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit Remarks
Min
-
Max
6.144
-
I2SCK max frequency *1
I2S clock cycle time *1
I2S clock Duty cycle
fI2SCK
tICYC
∆
MI2SCKx
MI2SCKx
MI2SCKx
-
-
MHz
%
4 tCYCP2
45
55
%
MI2SCKx,
MI2SWSx
I2SCK↓ → I2SWS delay time
I2SCK↓ → I2SDO delay time
tSWDT
tSDDT
-
-
-20
-20
+20
+20
ns
ns
MI2SCKx,
MI2SDOx
I2SDI → I2SCK ↑ setup time
I2SCK ↑ → I2SDI hold time
I2SCK falling time
tDSST
tSDHT
tF
-
-
-
-
36
0
-
-
-
ns
ns
ns
ns
MI2SCKx, MI2SDIx
MI2SCKx
5
5
I2SCK rising time
tR
-
*1: I2S clock should meet the multiple of PCLK(tICYC) and the frequency less than fI2SCK meantime.
Note:
−
See Chapter 1-6: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04856)
for the details.
VIH
VIH
MI2SCK
VIL
VIL
tF
tR
tSWDT,
tSDDT
VOH
VOL
MI2SWS
and
MI2SDO
tDSST
tSDHT
VIH
VIH
MI2SDI
VIL
VIL
Document Number: 001-98708 Rev. *E
Page 170 of 190
S6E2G Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Value
Parameter
Resolution
Symbol Pin Name
Unit
Remarks
Min
Typ
Max
12
-
-
-
-
-
-
-
-
-
bit
Integral nonlinearity
Differential nonlinearity
Zero transition voltage
-
-
± 4.5
± 2.5
± 7
LSB
LSB
LSB
-
-
AVRH
= 2.7 V to 5.5 V
Offset calibration
when used
Anxx
± 2
VZT
Full-scale transition voltage
Anxx
-
AVRH ± 2
AVRH ± 7
LSB
VFST
Total error
-
-
-
-
-
± 3
± 8
LSB
μs
0.5 *1
0.15
0.3
Conversion time
AVCC ≥ 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
-
-
-
-
-
-
Sampling time *2
tS
-
10
μs
25
1000
1000
Compare clock cycle*3
tCCK
tSTT
-
-
-
ns
μs
50
State transition time to
operation permission
-
-
1.0
A/D 1 unit operation
When A/D stop
-
-
0.69
1.3
0.92
22
mA
μA
Power supply current (analog +
digital)
AVCC
A/D 1 unit operation
AVRH = 5.5 V
-
1.1
1.97
mA
Reference power supply
current (AVRH)
-
AVRH
When A/D stop
-
-
0.3
6.3
12.05
1.2
μA
pF
Analog input capacity
Analog input resistance
-
-
-
CAIN
RAIN
AVCC ≥ 4.5 V
AVCC < 4.5 V
-
-
kΩ
1.8
Interchannel disparity
-
-
-
-
-
-
-
-
-
-
-
4
LSB
μA
V
Analog port input leak current
Anxx
-
5
AVRH
AVSS
AVSS
4.5
Analog input voltage
Reference voltage
-
Anxx
V
AVCC
AVCC
AVCC
AVSS
Tcck ＜50 ns
-
-
AVRH
AVRL
V
V
Tcck ≥ 50 ns
2.7
AVSS
1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it
satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog
Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information
about the APB bus number to which the A/D converter is connected, see 1. S6E2G Series Block Diagram in this data sheet.
The sampling clock and compare clock are set at base clock (HCLK).
2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1).
3: The compare time (tC) is the value of (Equation 2).
Document Number: 001-98708 Rev. *E
Page 171 of 190
S6E2G Series
ANxx
Comparator
Analog input pin
RAIN
Rext
Analog signal
source
CAIN
(Equation 1) tS ≥ (RAIN + Rext) × CAIN × 9
tS:
Sampling time
RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 1.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN: Input capacity of A/D = 12.05 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext: Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK
:
Compare clock cycle
Document Number: 001-98708 Rev. *E
Page 172 of 190
S6E2G Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential nonlinearity:Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral nonlinearity
Differential nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
Ideal characteristics
value)
VNT
(Asured
value)
0x001
ly-measured value)
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
Analog input
VNT - {1LSB × (N - 1) + VZT}
Integral nonlinearity of digital output N =
Differential nonlinearity of digital output N =
[LSB]
1LSB
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 001-98708 Rev. *E
Page 173 of 190
S6E2G Series
Total error: A difference between actual value and theoretical value.
The overall error includes zero-transition voltage, full-scale transition voltage and linearity error.
Total error
0xFFF
V
FST’=1.5LSB’
0xFFE
0xFFD
Actual conversion
characteristics
{1LSB’ x (N-1) + 0.5 LSB’}
0x004
0x003
0x002
0x001
VNT
(Actually-measured
value)
Actual conversion
characteristics
Ideal characterisics
VZT’=0.5LSB’
AVRL
AVRH
Analog input
V
NT – {1 LSB’ X (N-1) + 0.5 LSB’}
1 LSB’
Total error of digital output N =
[LSB]
AVRH – AVRL
[V]
1 LSB’ (ideal value) =
4096
[V]
[V]
V
V
V
ZT’ (ideal value) =
AVRL + 0.5 LSB’
AVRH - 1.5 LSB’
FST’ (ideal value) =
NT’: A voltage for causing transition of digital output from (N-1) to N
Document Number: 001-98708 Rev. *E
Page 174 of 190
S6E2G Series
12.6 USB Characteristics
(VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V)
Value
Pin
Name
Parameter
Symbol
Conditions
Unit Remarks
Min
2.0
Max
Input H level voltage
VIH
VIL
VDI
-
-
-
USBVCC + 0.3
V
V
V
*1
*1
*2
Input L level voltage
VSS - 0.3
0.2
0.8
Input
characteristics
Differential input sensitivity
-
Different common mode
range
VCM
VOH
VOL
-
0.8
2.8
0.0
2.5
3.6
0.3
V
V
V
*2
*3
*3
External pull-down
resistance = 15 kΩ
Output H level voltage
Output L level voltage
External pull-up
resistance = 1.5 kΩ
UDP0/
UDM0,
UDP1/
UDM1
Crossover voltage
Rise time
VCRS
tFR
-
1.3
4
2.0
20
V
*4
*5
*5
*5
Full-Speed
Full-Speed
Full-Speed
ns
ns
%
Output
characteristics
Fall time
tFF
4
20
Rise/fall time matching
tFRFM
90
111.11
Output impedance
Rise time
ZDRV
tLR
Full-Speed
Low-Speed
28
75
44
Ω
*6
*7
300
ns
Fall time
tLF
Low-Speed
Low-Speed
75
80
300
125
ns
%
*7
*7
Rise/fall time matching
tLRFM
1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There is some hysteresis applied to lower noise sensitivity.
2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input
sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
Document Number: 001-98708 Rev. *E
Page 175 of 190
S6E2G Series
3: The output drive capability of the driver is below 0.3 V at low state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or
above (to the VSS and 1.5 kΩ load) at high state (VOH).
4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
5: They indicate rise time (tRISE) and fall time (tFALL) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, tR/tF ratio is regulated as within ± 10% to minimize RFI emission.
D+
90%
90%
10%
10%
D-
TRISE
TFALL
Falling time
Rise time
Full-speed Buffer
Rs=27
Rs=27
TxD+
CL=50pF
CL=50pF
TxD-
3-State Enable
Document Number: 001-98708 Rev. *E
Page 176 of 190
S6E2G Series
6: USB Full-speed connection is performed via twisted-pair cable shield with 90Ω ± 15% characteristic impedance
(differential mode).
USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence.”
7: They indicate rise time (tRISE) and fall time (tFALL) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
D+
90%
90%
10%
10%
D-
TRISE
TFALL
Rise time
Falling time
Note:
See Low-Speed Load (Compliance Load) for conditions of external load.
−
Document Number: 001-98708 Rev. *E
Page 177 of 190
S6E2G Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL=50pF to 150pF
CL=50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL=
200pF to 600pF
CL=
200pF to 600pF
Low-Speed Load (Compliance Load)
CL=200pF to 450pF
CL=200pF to 450pF
Document Number: 001-98708 Rev. *E
Page 178 of 190
S6E2G Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
2.46
2.51
Max
2.64
2.69
Detected voltage
Released voltage
When voltage drops
When voltage rises
VDL
VDH
-
-
2.55
2.60
V
V
12.7.2 Interrupt of Low-Voltage Detection
Value
Typ
Parameter
Symbol
Conditions
SVHI = 00111
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
Unit
Remarks
Min
2.80
2.90
2.99
3.09
3.18
3.28
3.67
3.76
3.76
3.86
4.05
4.15
4.15
4.25
4.25
4.34
Max
3.00
3.11
3.21
3.31
3.42
3.52
3.93
4.04
4.04
4.14
4.35
4.45
4.45
4.55
4.55
4.66
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.90
3.00
3.10
3.20
3.30
3.40
3.80
3.90
3.90
4.00
4.20
4.30
4.30
4.40
4.40
4.50
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SVHI = 11000
LVD stabilization wait
time
-
-
-
μs
tLVDW
6000×tCYCP*
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 001-98708 Rev. *E
Page 179 of 190
S6E2G Series
12.8 MainFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Parameter
Unit
Remarks
Min
Typ
0.7
0.3
Max
3.7
Large Sector
-
-
s
s
Includes write time prior to internal
erase
Sector erase time
Small Sector
1.1
Write cycles < 100 times
Write cycles > 100 times
100
200
Half word (16-bit)
write time
Not including system-level overhead
time
-
12
μs
s
Includes write time prior to internal
erase
Chip erase time*
-
13.6
68
*: It indicates the chip erase time of 1MB MainFlash memory
For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required.
See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for
the detail.
Write Cycles and Data Retention Time
Erase/Write Cycles (Cycle)
Data Retention Time (Year)
1,000
10,000
100,000
20*
10*
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C).
Document Number: 001-98708 Rev. *E
Page 180 of 190
S6E2G Series
12.9 Standby Recovery Time
12.9.1 Recovery Cause: Interrupt/WKUP
The time from the interrupt occurring to the time of program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
HCLK×1
μs
High-speed CR Timer mode
Main Timer mode
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
450
896
900
μs
μs
Sub Timer mode
1136
RTC mode
Stop mode
tICNT
316
270
581
540
μs
μs
(High-speed CR/Main/PLL Run mode return)
RTC mode
Stop mode
(Low-speed CR/sub Run mode return)
without RAM
retention
365
365
667
667
μs
μs
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
with RAM retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in External Interrupt Recovery*)
Ext.INT
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 001-98708 Rev. *E
Page 181 of 190
S6E2G Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption mode and
Operations of Standby modes in FM4 Family Peripheral Manual Main Part (002-04856).
−
The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
Document Number: 001-98708 Rev. *E
Page 182 of 190
S6E2G Series
12.9.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
155
266
μs
High-speed CR Timer mode
Main Timer mode
155
266
μs
PLL Timer mode
Low-speed CR Timer mode
315
315
567
567
μs
μs
Sub Timer mode
tRCNT
RTC mode
Stop mode
315
567
μs
without RAM
retention
336
336
667
667
μs
μs
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
with RAM retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Start
Document Number: 001-98708 Rev. *E
Page 183 of 190
S6E2G Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Start
*: Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the
recovery cause.
Notes:
−
The return factor is different in each low power consumption mode.
See Chapter 6: Low Power Consumption mode and Operations of Standby modes in “FM4 Family Peripheral Manual
Main Part (002-04856).
−
−
−
−
The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On
Reset Timing.
In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock,
they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock.
Internal resource reset indicates Watchdog reset and CSV reset.
Document Number: 001-98708 Rev. *E
Page 184 of 190
S6E2G Series
13.Ordering Information
Part Number
Flash
RAM
CAN
✓
✓
✓
Ethernet SD Card
Crypto
Package
S6E2GM6H0AGV2000A
S6E2GM8H0AGV2000A
✓
✓
✓
✓
✓
✓
512 KB 128 KB
1 MB
192 KB
Plastic LQFP (0.5 mm pitch),
144 pin
S6E2GM6HHAGV2000A
✓
✓
512 KB 128 KB
(LQS144)
✓
✓
✓
S6E2GM8HHAGV2000A
S6E2GM6J0AGV2000A
S6E2GM8J0AGV2000A
S6E2GM6JHAGV2000A
S6E2GM8JHAGV2000A
S6E2GK6H0AGV2000A
1 MB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
192 KB
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Plastic LQFP (0.5 mm pitch),
176 pin
✓
✓
(LQP176)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Plastic LQFP (0.5 mm pitch),
144 pin
S6E2GK8H0AGV2000A
S6E2GK6HHAGV2000A
S6E2GK8HHAGV2000A
S6E2GK6J0AGV2000A
S6E2GK8J0AGV2000A
S6E2GK6JHAGV2000A
S6E2GK8JHAGV2000A
S6E2GH6H0AGV2000A
S6E2GH8H0AGV2000A
S6E2GH6J0AGV2000A
S6E2GH8J0AGV2000A
S6E2G36H0AGV2000A
S6E2G38H0AGV2000A
S6E2G36J0AGV2000A
S6E2G38J0AGV2000A
1 MB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
192 KB
✓
✓
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
✓
✓
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
✓
✓
✓
✓
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
1 MB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
192 KB
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
S6E2G26H0AGV2000A
S6E2G28H0AGV2000A
S6E2G26HHAGV2000A
✓
✓
✓
Plastic LQFP (0.5 mm pitch),
144 pin
✓
✓
(LQS144)
S6E2G28HHAGV2000A
S6E2G26J0AGV2000A
S6E2G28J0AGV2000A
S6E2G26JHAGV2000A
S6E2G28JHAGV2000A
✓
✓
✓
✓
✓
1 MB
512 KB 128 KB
1 MB 192 KB
512 KB 128 KB
1 MB 192 KB
192 KB
Plastic LQFP (0.5 mm pitch),
176 pin
✓
✓
(LQP176)
Document Number: 001-98708 Rev. *E
Page 185 of 190
S6E2G Series
14.Package Dimensions
Package Type
Package Code
LQFP 144
LQS144
4
4
5
D
D
5
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
144
144
37
37
1
1
36
36
2
A-B
5
D
7
BOTTOM VIEW
e
3
0.10
C
0.20
C
A-B D
b
0.08
C
A-B
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
L
b
L1
10
A'
SECTION A-A'
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
22.00 BSC
20.00 BSC
0.50 BSC
D1
e
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
002-13015 *A
Document Number: 001-98708 Rev. *E
Page 186 of 190
S6E2G Series
Package Type
Package Code
LQFP 176
LQP176
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
7
4
3
6
176
45
45
176
1
44
44
1
e
2
A-B
5
7
D
3
0.10
A-B
C
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
θ
A
SEA TING
PLANE
A1
0.25
A'
b
L1
10
0.08
C
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17
0.09
0.15
0.27
0.20
0.22
c
D
26.00 BSC
24.00 BSC
0.50 BSC
26.00 BSC
24.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0.75
0.70
L1
θ
0.50
0°
8°
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
002-15150 **
Document Number: 001-98708 Rev. *E
Page 187 of 190
S6E2G Series
Document History
Document Title: S6E2G Series 32-bit Arm® Cortex®-M4F, FM4 Microcontroller
Document Number: 001-98708
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
New spec.
**
4861788
4945035
YOHO
HITK
07/27/2015
11/20/2015
Changed status from Preliminary to Final.
Updated 4 Pin Description:
*A
Added “Note” about TAP pins.
Updated 12.2 Recommended Operating Conditions:
Added the "Smoothing capacitor (CS)”.
Added the “Current Value” in “Maximum leak current at operating”.
Updated 12.3.1 Current Rating:
Updated Table 12-1 to Table 12-9:
Added the “MAX” value.
Updated Table 12-11:
Updated 12.5 12-bit A/D Converter:
Updated “Zero transition” and “Full-scale transition” value.
Added “Total error”.
Removed full multiplexed signal names from the Pin Assignments drawing.
Consolidated the G Series of Cypress MCUs into one data sheet.
Added tables to differentiate parts in 2 Product Lineup and 3
Package-Dependent Features.
*B
5122844
BOO
03/29/2016
Added hyperlinks to 6 Pin Descriptions.
Added circuit type D to 7 I/O Circuit Type and pin state types S and T to 11
Pin Status in Each CPU State.
Consolidated 10 Memory Map to two pages.
Expanded 13 Ordering Information.
Modified typo about the number (from 5 to 4) of power supplies. (Page 11)
Updated “12.4.8 Power-On Reset Timing”. Changed parameter from
“Power Supply rise time(tVCCR) [ms]” to “Power ramp rate(dV/dt) [mV/us]”
and add some comments. (Page 107)
*C
5448447
YSKA
04/12/2017
Modified “12.4.12 CSIO(SPI) Timing”. Deleted “SPI=1, MS=0” in the titles
and added MS=0,1 in the schematic (Page 128-135, 144-151)
Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12
CSIO(SPI) Timing”(Page 136-142)
“Modified RTC description in “4. Product Features in Detail, Real-Time
Clock(RTC)”
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function (Page 9)
Updated “14. Package dimensions” (Page 186-187)
Change the name from “USB Function” to “USB Device” (Page 50)
Deleted MPNs below from “13. Ordering Information” (Page 185)
S6E2G26H0AGV20000, S6E2G26HHAGV20000,
S6E2G26J0AGV20000,
S6E2G26JHAGV20000, S6E2G28H0AGV20000,
S6E2G28HHAGV20000,
S6E2G28J0AGV20000, S6E2G28JHAGV20000, S6E2G36H0AGV20000,
S6E2G36J0AGV20000, S6E2G38H0AGV20000, S6E2G38J0AGV20000,
Document Number: 001-98708 Rev. *E
Page 188 of 190
S6E2G Series
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
S6E2GH6H0AGV20000, S6E2GH6J0AGV20000,
S6E2GH8H0AGV20000,
S6E2GH8J0AGV20000, S6E2GK6H0AGV20000,
S6E2GK6HHAGV20000,
S6E2GK6J0AGV20000, S6E2GK6JHAGV20000,
S6E2GK8H0AGV20000,
S6E2GK8HHAGV20000, S6E2GK8J0AGV20000,
S6E2GK8JHAGV20000,
S6E2GM6H0AGV20000, S6E2GM6HHAGV20000,
S6E2GM6J0AGV20000,
S6E2GM6JHAGV20000, S6E2GM8H0AGV20000,
S6E2GM8HHAGV20000,
S6E2GM8J0AGV20000, S6E2GM8JHAGV20000
Added MPNs below to “13. Ordering Information” (Page 185)
S6E2G26H0AGV2000A, S6E2G26HHAGV2000A,
S6E2G26J0AGV2000A,
S6E2G26JHAGV2000A, S6E2G28H0AGV2000A,
S6E2G28HHAGV2000A,
S6E2G28J0AGV2000A, S6E2G28JHAGV2000A,
S6E2G36H0AGV2000A,
S6E2G36J0AGV2000A, S6E2G38H0AGV2000A,
S6E2G38J0AGV2000A,
S6E2GH6H0AGV2000A, S6E2GH6J0AGV2000A,
S6E2GH8H0AGV2000A,
S6E2GH8J0AGV2000A, S6E2GK6H0AGV2000A,
S6E2GK6HHAGV2000A,
S6E2GK6J0AGV2000A, S6E2GK6JHAGV2000A,
S6E2GK8H0AGV2000A,
S6E2GK8HHAGV2000A, S6E2GK8J0AGV2000A,
S6E2GK8JHAGV2000A,
S6E2GM6H0AGV2000A, S6E2GM6HHAGV2000A,
S6E2GM6J0AGV2000A,
S6E2GM6JHAGV2000A, S6E2GM8H0AGV2000A,
S6E2GM8HHAGV2000A,
S6E2GM8J0AGV2000A, S6E2GM8JHAGV2000A
Modified typo about the munber of QPRC channels(from 4ch to 2ch) (Page
1,6,10)
Modified the expression of the “Built-in CR” in “2. Product Lineup” (Page 6).
Updated Cypress Logo and Copyright.
Updated to new template.
Completing Sunset Review.
*D
*E
6298066
6602132
XITO
XITO
09/03/2018
06/24/2019
Updated to new template.
Completing Sunset Review.
Document Number: 001-98708 Rev. *E
Page 189 of 190
S6E2G Series
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© Cypress Semiconductor Corporation, 2015-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
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reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED
USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION
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the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other
liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates,
distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property
damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-98708 Rev. *E
June 24, 2019
Page 190 of 190
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