S70FS01GSAGBHM210_技术文档

S70FS01GS

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Features

• SPI with multi-I/O

- SPI clock polarity and phase modes 0 and 3

- DDR

- Extended addressing: 24- or 32-bit address options

- Serial command subset and footprint compatible with S25FL1-K, S25FL-P, and S25FL-S SPI families

- Multi I/O command subset and footprint compatible with S25FL-P, S25FL1-K, and S25FL-S SPI families

• Read

- Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O

- Modes: Burst wrap, Quad peripheral interface (QPI)

- Serial flash discoverable parameters (SFDP) and common flash interface (CFI), for configuration information.

• Program

- 256 or 512 bytes page programming buffer

- Program suspend and resume

- Automatic error correcting code (ECC) – Internal hardware ECC with single bit error correction

• Erase

- Hybrid sector option

• Physical set of eight 4 KB sectors and one 224 KB sector at the top or bottom of address space with all

remaining sectors of 256 KB

- Uniform sector option

• Physical uniform 256 KB blocks

- Erase suspend and resume

- Erase status evaluation

- 100,000 Program-erase cycles on any sector, minimum

- 20 year data retention, minimum

• Security features

- OTP array of 1024 bytes

- Block protection:

• Status Register bits to control protection against program or erase of a contiguous range of sectors.

• Hardware and software control options

- Advanced sector protection (ASP)

• Individual sector protection controlled by boot code or password

• Option for password control of read access

• Technology

- 65-nm MIRRORBIT™ Technology with Eclipse architecture

• Single supply voltage with CMOS I/O

- 1.7 V to 2.0 V

• Temperature range

- Industrial (–40 °C to +85 °C)

- Industrial Plus (–40 °C to +105 °C)

- Automotive, AEC-Q100 grade 3 (–40 °C to +85 °C)

- Automotive, AEC-Q100 grade 2 (–40 °C to +105 °C)

- Automotive, AEC-Q100 grade 1 (–40 °C to +125 °C)

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Logic block diagram

• Packages (all Pb-free)

- 16-lead SOIC 300 mil

- BGA-24 6  8 mm

• 5  5 ball footprint

Logic block diagram

S70FS01GS Device

S25FS512S Die 1

SRAM

CS#

SCK

MirrorBit Array

SI/IO0

Y Decoders

Data Latch

I/O

SO/IO1

WP#/IO2

Control

Logic

RESET#/IO3

Data Path

S25FS512S Die 2

SRAM

MirrorBit Array

Y Decoders

Data Latch

I/O

Control

Logic

Data Path

Datasheet

2 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Performance summary

Maximum Read rates

Command

Read

Fast Read

Dual Read

Clock rate (MHz)

MBps

6.25

16.5

33

66

80

50

133

80

Quad Read

DDR Quad I/O Read

Typical Program and Erase rates

Operation

Page Programming (256-bytes page buffer)

Page Programming (512-bytes page buffer)

4-KB Physical Sector Erase (Hybrid Sector Option)

256-KB Sector Erase (Uniform Logical Sector Option)

KBps

711

1078

17

275

Typical current consumption, –40 °C to +85 °C

Operation

Current (mA)

Serial Read 50 MHz

Serial Read 133 MHz

Quad Read 133 MHz

Quad DDR Read 80 MHz

Program

10

20

60

70

60

Erase

60

Standby

Deep Power Down (DPD)

0.07

0.006

Datasheet

3 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Table of contents

Features ...........................................................................................................................................1

Logic block diagram ..........................................................................................................................2

Performance summary ......................................................................................................................3

Table of contents...............................................................................................................................4

1 Overview .......................................................................................................................................6

1.1 General description ................................................................................................................................................6

1.2 Migration notes .......................................................................................................................................................6

1.3 Glossary ...................................................................................................................................................................9

2 SPI with multiple input / output (SPI-MIO) ......................................................................................11

3 Signal descriptions .......................................................................................................................12

3.1 Input/Output summary ........................................................................................................................................12

3.2 Multiple Input / Output (MIO)...............................................................................................................................13

3.3 Serial Clock (SCK)..................................................................................................................................................13

3.4 Chip Select (CS#)...................................................................................................................................................13

3.5 Serial Input (SI) / IO0.............................................................................................................................................13

3.6 Serial Output (SO) / IO1 ........................................................................................................................................13

3.7 Write Protect (WP#) / IO2......................................................................................................................................14

3.8 IO3 / RESET#..........................................................................................................................................................14

3.9 Voltage Supply (V_CC) .............................................................................................................................................14

3.10 Supply and Signal Ground (V_SS) .........................................................................................................................14

3.11 Not Connected (NC) ............................................................................................................................................14

3.12 Reserved for Future Use (RFU) ...........................................................................................................................15

3.13 Do Not Use (DNU)................................................................................................................................................15

3.14 Block diagrams ...................................................................................................................................................15

4 Signal protocols............................................................................................................................17

4.1 SPI clock modes ....................................................................................................................................................17

4.2 Command Protocol...............................................................................................................................................18

4.3 Interface states .....................................................................................................................................................22

4.4 Configuration Register effects on the interface ..................................................................................................26

4.5 Data protection.....................................................................................................................................................26

5 Electrical specifications.................................................................................................................27

5.1 Absolute maximum ratings ..................................................................................................................................27

5.2 Thermal resistance ...............................................................................................................................................27

5.3 Latchup characteristics ........................................................................................................................................27

5.4 Operating ranges ..................................................................................................................................................28

5.5 Power-up and power-down..................................................................................................................................29

5.6 DC characteristics .................................................................................................................................................31

6 Timing specifications ....................................................................................................................34

6.1 Key to switching waveforms.................................................................................................................................34

6.2 AC test conditions .................................................................................................................................................34

6.3 Reset ......................................................................................................................................................................36

6.4 SDR AC characteristics..........................................................................................................................................39

6.5 DDR AC characteristics .........................................................................................................................................42

7 Physical interface .........................................................................................................................45

7.1 Connection diagrams ...........................................................................................................................................45

7.2 Physical diagrams .................................................................................................................................................46

8 Address space maps ......................................................................................................................48

8.1 Overview................................................................................................................................................................48

8.2 Flash memory array ..............................................................................................................................................48

8.3 ID-CFI address space.............................................................................................................................................49

8.4 JEDEC JESD216 serial flash discoverable parameters (SFDP) space .................................................................49

Datasheet

4 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Table of contents

8.5 OTP address space................................................................................................................................................50

8.6 Error correction code (ECC)..................................................................................................................................51

8.7 Registers................................................................................................................................................................52

9 Data Protection ............................................................................................................................74

9.1 Secure Silicon Region (OTP).................................................................................................................................74

9.2 Write Enable Command........................................................................................................................................75

9.3 Block Protection ...................................................................................................................................................75

9.4 Advanced sector protection .................................................................................................................................77

9.5 Recommended protection process .....................................................................................................................82

10 Commands .................................................................................................................................83

10.1 Command set summary .....................................................................................................................................85

10.2 Identification commands ...................................................................................................................................93

10.3 Register Access commands ................................................................................................................................95

10.4 Read Memory Array commands .......................................................................................................................105

10.5 Program Flash Array Commands .....................................................................................................................113

10.6 Erase Flash Array Commands...........................................................................................................................115

10.7 One Time Program Array Commands ..............................................................................................................124

10.8 Advanced Sector Protection Commands ........................................................................................................125

10.9 Reset Commands ..............................................................................................................................................131

10.10 DPD Commands ..............................................................................................................................................133

11 Data Integrity ........................................................................................................................... 135

11.1 Erase Endurance ...............................................................................................................................................135

11.2 Data Retention ..................................................................................................................................................135

12 Embedded Algorithm Performance Tables .................................................................................. 136

13 Software Interface Reference..................................................................................................... 137

13.1 Serial Flash Discoverable Parameters (SFDP) Address Map ...........................................................................137

13.2 Device ID and Common Flash Interface (ID-CFI) Address Map .......................................................................141

13.3 Initial Delivery State..........................................................................................................................................162

13.4 FS01GS Behavior and Software Modifications ................................................................................................163

14 Ordering Information ................................................................................................................ 166

14.1 Ordering Part Number ......................................................................................................................................166

14.2 Valid Combinations — Standard ......................................................................................................................167

14.3 Valid Combinations — Automotive Grade / AEC-Q100....................................................................................167

Revision history ............................................................................................................................ 168

Datasheet

5 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Overview

1

Overview

1.1

General description

The FS-S Family devices are Flash non-volatile memory products using:

• MIRRORBIT™ technology - that stores two data bits in each memory array transistor

• Eclipse architecture - that dramatically improves program and erase performance

• 65-nm process lithography

The FS-S family connects to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O

or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) or QPI, also

known as quad peripheral interface (QPI) serial commands. This multiple width interface is called SPI Multi-I/O

or MIO. In addition, there are DDR read commands for QIO and QPI that transfer address and read data on both

edges of the clock.

The FS-S Eclipse architecture features a page programming buffer that allows up to 512-bytes to be programmed

in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase

algorithms.

Executing code directly from Flash memory is often called eXecute-In-Place (XIP). By using FS-S family devices at

the higher clock rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can

match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count

dramatically.

The FS-S family products offer high densities coupled with the flexibility and fast performance required by a

variety of mobile or embedded applications. They are an excellent solution for systems with limited space, signal

connections, and power. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing

reprogrammable data.

The S70FS01GS device is a dual die stack of two FS512S die.

1.2

Migration notes

1.2.1

Features comparison

The FS-S family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.

However, the power supply and interface voltages are nominal 1.8 V.

Table 1

SPI families comparison

Parameter

FS-S

65-nm

MIRRORBIT™ Eclipse

2H2015

FL-S

65nm

MIRRORBIT™ Eclipse

2H2011

Technology node

Architecture

Release Date

Density

1Gb

1GB

Bus width

x1, x2, x4

Supply voltage

1.7 V–2.0 V

2.7 V–3.6 V / 1.65 V–3.6 V V_IO

6 MBps (50 MHz)

17 MBps (133 MHz)

26 MBps (104 MHz)

52 MBps (104 MHz)

Normal read speed (SDR)

Fast read speed (SDR)

Dual read speed (SDR)

Quad read speed (SDR)

6 MBps (50 MHz)

16.5 MBps (133 MHz)

33 MBps (133 MHz)

66 MBps (133 MHz)

Notes

1. Only 128 Mb/256 Mb density FL-S devices have 4 KB parameter sector option.

2. 512 Mb/1 Gb FL-S devices support 256 KB sector only.

3. Refer to individual datasheets for further details.

Datasheet

6 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Overview

Table 1

SPI families comparison (Continued)

Parameter

FS-S

80 MBps (80 MHz)

256 B / 512 B

256 KB

FL-S

80 MBps (80 MHz)

256 B / 512 B

256 KB

Quad Read Speed (DDR)

Program Buffer Size

Erase Sector Size

Parameter Sector Size

Sector Erase Rate (typ.)

4 KB (option)

500 KBps

4 KB (option)

500 KBps

0.71 MBps (256B)

1.08 MBps (512B)

1.0 MBps (256B)

1.5 MBps (512B)

Page Programming Rate (typ.)

OTP

1024B

Advanced Sector Protection

Auto Boot Mode

Yes

No

Yes

Erase Suspend/Resume

Program Suspend/Resume

Operating Temperature

Yes

–40 °C to +85 °C / +105 °C / +125 °C

–40 °C to +85 °C / +105 °C

Notes

1. Only 128 Mb/256 Mb density FL-S devices have 4 KB parameter sector option.

2. 512 Mb/1 Gb FL-S devices support 256 KB sector only.

3. Refer to individual datasheets for further details.

1.2.2

Known differences from prior generations

Error reporting

1.2.2.1

The FS-S and FL-S families have error reporting status bits for program and erase operations. These can be set

when there is an internal failure to program or erase, or when there is an attempt to program or erase a protected

sector. In these cases, the program or erase operation did not complete as requested by the command. The

P_ERR or E_ERR bits and the WIP bit will be set to and remain 1 in SR1V. The Clear Status Register command must

be sent to clear the errors and return the device to standby state.

1.2.2.2

Secure Silicon Region (OTP)

The FS-S size and format (address map) of the one time program area is different from FL-K and FL-P generations.

The method for protecting each portion of the OTP area is different. For additional details, see “Secure Silicon

Region (OTP)” on page 74.

1.2.2.3

Configuration Register Freeze Bit

The Configuration Register-1 Freeze Bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] &

SR1V[4:2]), TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S

families the Freeze Bit also locks the state of the configuration register-1 BPNV_O bit (CR1NV[3]), and the Secure

Silicon Region (OTP) area.

1.2.2.4

Sector Erase commands

The command for erasing a 4 KB sector is supported only for use on 4 KB parameter sectors at the top or bottom

of the FS-S device address space.

The command for erasing an 8 KB area (two 4 KB sectors) is not supported.

The command for erasing a 32 KB area (eight 4 KB sectors) is not supported.

1.2.2.5

Deep Power Down (DPD)

The DPD function is supported in the FS-S family devices.

Datasheet

7 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Overview

1.2.2.6

WRR Single Register Write

In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status

Register 1 and clear some bits in Configuration Register 1, including the Quad Mode bit. This could result in

unintended exit from Quad Mode. The FS-S Family only updates Status Register 1 when a single data byte is

provided. The Configuration Register 1 is not modified in this case.

1.2.2.7

Hold Input not supported

In some legacy SPI devices, the IO3 input has an alternate function as a HOLD# input used to pause information

transfer without stopping the serial clock. This function is not supported in the FS-S family.

1.2.2.8

Separate Reset Input not supported

In some legacy SPI devices, a separate hardware RESET# input is supported in packages having more than 8

connections. The FS-S family does not support a separate RESET# input. The FS-S family provides an alternate

function for the IO3 input as a RESET# input. When the CS# signal is HIGH and the IO3/Reset feature is enabled,

the IO3/RESET# input is used to initiate a hardware reset when the input goes LOW.

1.2.2.9

Other legacy commands not supported

• Autoboot Related Commands

• Bank Address Related Commands

• Dual Output Read

• Quad Output Read

• Quad Page Program (QPP) - replaced by Page Program in QPI Mode

• DDR Fast Read

• DDR Dual I/O Read

• Write Register

• Read Configuration Register

• Read Status Register 1

• Read Status Register 2

• Program NV Data Learning Register

• ASP Program

• Password Program

• PPB Erase

• Erase Program Suspend (B0h)

• Erase Program Resume (30h)

Datasheet

8 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Overview

1.2.2.10

New features

The FS-S family introduces new features to Infineon SPI category memories:

• Single 1.8 V power supply for core and I/O voltage.

• Configurable initial read latency (number of dummy cycles) for faster initial access time or higher clock rate

read commands

• QPI (QPI, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions

• JEDEC JESD216 standard, serial flash discoverable parameters (SFDP) that provide device feature and

configuration information.

• Evaluate Erase Status command to determine if the last erase operation on a sector completed successfully.

This command can be used to detect incomplete erase due to power loss or other causes. This command can

be helpful to Flash File System software in file system recovery after a power loss.

• Advanced Sector Protection (ASP) Permanent Protection. A bit is added to the ASP register to provide the option

to make protection of the Persistent Protection Bits (PPB) permanent. Also, when one of the two ASP modes is

selected, all OTP configuration bits in all registers are protected from further programming so that all OTP

configuration settings are made permanent. The OTP address space is not protected by the selection of an ASP

Mode. The Freeze bit (CR1V[0]) may be used to protect the OTP Address Space.

• Single Chip Select (CS#) Dual Die Package (DDP) density option that uses two FS512S devices stacked within

the same package to provide 1Gb of memory. The the two devices share the CS# input to provide a contiguous

1 Gb (128 MB) address space. However, there are some behavior and software differences from the other

members of the FS-S family that are described in “FS01GS Behavior and Software Modifications”on page 163.

1.3

Glossary

• BCD = Binary Coded Decimal. A value in which each 4 bit nibble represents a decimal numeral.

• Command = All information transferred between the host system and memory during one period while CS# is

LOW. This includes the instruction (sometimes called an operation code or opcode) and any required address,

mode bits, latency cycles, or data.

• DDP = Dual Die Package = Two die stacked within the same package to increase the memory capacity of a single

package. Often also referred to as a Multi-Chip Package (MCP)

• DDR = Double Data Rate = When input and output are latched on every edge of SCK.

• ECC = ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP array, each of which

has its own hidden ECC syndrome to enable error correction on each group.

• Flash = The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large

blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.

• High = A signal voltage level ≥ V_IHor a logic level representing a binary one (“1”).

• Instruction = The 8 bit code indicating the function to be performed by a command (sometimes called an

operation code or opcode). The instruction is always the first 8 bits transferred from host system to the memory

in any command.

• Low = A signal voltage level  V_ILor a logic level representing a binary zero (“0”).

• LSb = Least Significant Bit = Generally the right most bit, with the lowest order of magnitude value, within a

group of bits of a register or data value.

• MSb = Most Significant Bit = Generally the left most bit, with the highest order of magnitude value, within a

group of bits of a register or data value.

• N/A = Not applicable. A value is not relevant to situation described.

• Non-volatile = No power is needed to maintain data stored in the memory.

Datasheet

9 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Overview

• OPN = Ordering part number = The alphanumeric string specifying the memory device type, density, package,

factory non-volatile configuration, and so on used to select the desired device.

• Page = 512-byte or 256-byte aligned and length group of data. The size assigned for a page depends on the

Ordering Part Number.

• PCB - Printed circuit board

• Register bit references = Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB:

bit_range_LSB]

• SDR = Single data rate = When input is latched on the rising edge and output on the falling edge of SCK.

• Sector = Erase unit size; depending on device model and sector location this may be 4 KB, 64 KB, or 256 KB

• Write = An operation that changes data within volatile or non-volatile registers bits or non-volatile Flash

memory. When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data

is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same

way that volatile data is modified – as a single operation. The non-volatile data appears to the host system to

be updated by the single write command, without the need for separate commands for erase and reprogram

of adjacent, but unaffected data.

Datasheet

10 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

SPI with multiple input / output (SPI-MIO)

2

SPI with multiple input / output (SPI-MIO)

Many memory devices connect to their host system with separate parallel control, address, and data signals that

require a large number of signal connections and larger package size. The large number of connections increase

power consumption due to so many signals switching and the larger package increases cost.

The FS-S Family reduces the number of signals for connection to the host system by serially transferring all

control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package, reduces

signal switching power, and either reduces the host connection count or frees host connectors for use in

providing other features.

The FS-S family uses the industry standard single bit SPI and also supports optional extension commands for two

bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI multi-I/O or SPI-MIO.

Datasheet

11 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal descriptions

3

Signal descriptions

3.1

Input/Output summary

Table 2

Signal name

SCK

Signal List

Type

Description

Input

I/O

Serial Clock

Chip Select

CS#

SI / IO0

SO / IO1

Serial Input for single bit data commands or IO0 for Dual or Quad commands.

Serial Output for single bit data commands. IO1 for Dual or Quad commands.

I/O

Write Protect when not in Quad Mode (CR1V[1] = 0 and SR1NV[7] = 1).

IO2 when in Quad Mode (CR1V[1] = 1).

The signal has an internal pull-up resistor and may be left unconnected in the

host system if not used for Quad commands or write protection. If write

protection is enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host system is

required to drive WP# HIGH or LOW during a WRAR command.

IO3 in Quad-I/O Mode, when Configuration Register-1 QUAD bit, CR1V[1] = 1, and

CS# is LOW.

RESET# when enabled by CR2V[5] = 1 and not in Quad-I/O Mode, CR1V[1] = 0, or

when enabled in Quad Mode, CR1V[1] = 1 and CS# is HIGH.

The signal has an internal pull-up resistor and may be left unconnected in the

host system if not used for Quad commands or RESET#.

WP# / IO2

I/O

IO3 / RESET#

V_CC

V_SS

Supply

Power Supply.

Ground.

Not Connected. No device internal signal is connected to the package

connector nor is there any future plan to use the connector for a signal. The

connection may safely be used for routing space for a signal on a PCB. However,

NC

Unused

any signal connected to an NC must not have voltage levels higher than V_CC

.

Reserved for Future Use. No device internal signal is currently connected to

the package connector but there is potential future use of the connector for a

RFU

Reserved signal. It is recommended to not use RFU connectors for PCB routing channels

so that the PCB may take advantage of future enhanced features in compatible

footprint devices.

Do Not Use. A device internal signal may be connected to the package

connector. The connection may be used by Cypress for test or other purposes

and is not intended for connection to any host system signal. Any DNU signal

Reserved related function will be inactive when the signal is at V_IL. The signal has an

internal pull-down resistor and may be left unconnected in the host system or

may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to this connection.

DNU

Datasheet

12 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal descriptions

3.2

Multiple Input / Output (MIO)

Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on

the Serial Input (SI) signal. Data may be sent back to the host serially on the Serial Output (SO) signal.

Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal. Address

or data is sent from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,

and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1,

IO2, and IO3.

QPI Mode transfers all instructions, address, and data from the host to the memory as four bit (nibble) groups on

IO0, IO1, IO2, and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2, and IO3.

3.3

Serial Clock (SCK)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data

input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR

commands, and after every edge in DDR commands.

3.4

Chip Select (CS#)

The chip select signal indicates when a command is transferring information to or from the device and the other

signals are relevant for the memory device.

When the CS# signal is at the logic HIGH state, the device is not selected and all input signals are ignored and all

output signals are high impedance If the IO3 / RESET# option is enabled see “IO3 / RESET#” on page 14 for CS#

signal operation. The device will be in the Standby Power Mode, unless an internal embedded operation is in

progress. An embedded operation is indicated by the Status Register-1 Write-In-Progress bit (SR1V[1]) set to 1,

until the operation is completed. Some example embedded operations are: Program, Erase, or Write Registers

(WRAR) operations.

Driving the CS# input to the logic LOW state enables the device, placing it in the Active Power Mode. After

Power-up, a falling edge on CS# is required prior to the start of any command.

3.5

Serial Input (SI) / IO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to

be programmed. Values are latched on the rising edge of serial SCK clock signal.

SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and

data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on

the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

3.6

Serial Output (SO) / IO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the

serial SCK clock signal.

SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be

programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling

edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

Datasheet

13 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal descriptions

3.7

Write Protect (WP#) / IO2

When WP# is driven LOW (V_IL), during a WRAR command and while the Status Register Write Disable (SRWD_NV)

bit of Status Register-1 (SR1NV[7]) is set to a 1, it is not possible to write to Status Register-1 or Configuration

Register-1 related registers. In this situation, a WRAR command is ignored, a WRAR command selecting SR1NV,

SR1V, CR1NV, or CR1V is ignored, and no error is set.

This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the memory

area that are protected by the Block Protection feature are also hardware protected against data modification if

WP# is LOW during a WRAR command with SRWD_NV set to 1.

The WP# function is not available when the Quad Mode is enabled (CR1V[1] = 1). The WP# function is replaced by

IO2 for input and output during Quad Mode for receiving addresses, and data to be programmed (values are

latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,

and on every edge of SCK, in DDR commands).

WP# has an internal pull-up resistance; when unconnected, WP# is at V_IHand may be left unconnected in the host

system if not used for Quad Mode or protection.

3.8

IO3 / RESET#

IO3 is used for input and output during Quad Mode (CR1V[1] = 1) for receiving addresses, and data to be

programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge

of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is enabled

by writing Configuration Register-2 non-volatile bit 5 (CR2V[5] = 1). The input is only treated as RESET# when the

device is not in Quad-I/O Mode, CR1V[1] = 0, or when CS# is HIGH. When Quad I/O Mode is in use, CR1V[1] = 1, and

the device is selected with CS# LOW, the IO3 / RESET# is used only as IO3 for information transfer. When CS# is

HIGH, the IO3 / RESET# is not in use for information transfer and is used as the RESET# input. By conditioning the

reset operation on CS# HIGH during Quad Mode, the reset function remains available during Quad Mode.

When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the

IO3 / RESET# signal is driven LOW. When CS# goes HIGH the IO3 / RESET# input transitions from being IO3 to being

the RESET# input. The reset condition is then detected when CS# remains HIGH and the IO3 / RESET# signal

remains LOW for t_RP. If a reset is not intended, the system is required to actively drive IO3 / Reset# to HIGH along

with CS# being driven HIGH at the end of a transfer of data to the memory. Following transfers of data to the host

system, the memory will drive IO3 HIGH during t_CS. This will ensure that IO3 / Reset is not left floating or being

pulled slowly to HIGH by the internal or an external passive pull-up. Thus, an unintended reset is not triggered by

the IO3 / RESET# not being recognized as HIGH before the end of t_RP

.

The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5] = 0).

The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not

used for Quad Mode or the reset function. The internal pull-up will hold IO3 / Reset HIGH after the host system

has actively driven the signal HIGH and then stops driving the signal.

Note that IO3 / Reset# cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad

I/O Mode as IO3 being driven to or from one selected memory may look like a reset signal to a second

non-selected memory sharing the same IO3 / RESET# signal.

3.9

Voltage Supply (V_CC)

V_CCis the voltage source for all device internal logic. It is the single voltage used for all device internal functions

including read, program, and erase.

3.10

Supply and Signal Ground (V_SS)

V_SSis the common voltage drain and ground reference for the device core, input signal receivers, and output

drivers.

3.11

Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector

for a signal. The connection may safely be used for routing space for a signal on a PCB.

Datasheet

14 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal descriptions

3.12

Reserved for Future Use (RFU)

No device internal signal is currently connected to the package connector but there is potential future use of the

connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take

advantage of future enhanced features in compatible footprint devices.

3.13

Do Not Use (DNU)

A device internal signal may be connected to the package connector. The connection may be used by Cypress for

test or other purposes and is not intended for connection to any host system signal. Any DNU signal related

function will be inactive when the signal is at V_IL. The signal has an internal pull-down resistor and may be left

unconnected in the host system or may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to these connections.

3.14

Block diagrams

RESET#

WP#

RESET#

WP#

SI

SO

SI

SO

SCK

CS2#

CS1#

FS01GS

Flash

FS01GS

Flash

SPI

Bus Master

Figure 1

Bus master and memory devices on the SPI bus - Single bit data path

RESET#

WP#

IO1

IO0

SCK

CS2#

CS1#

FS01GS

Flash

FS01GS

Flash

SPI

Bus Master

Figure 2

Bus master and memory devices on the SPI bus - Dual bit data path

Datasheet

15 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal descriptions

IO3 / RESET#

IO2

RESET# / IO3

IO2

IO1

IO0

SCK

IO1

IO0

SCK

CS1#

FS01GS

Flash

SPI

Bus Master

Figure 3

Bus master and memory devices on the SPI bus - Quad bit data path

Datasheet

16 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

4

Signal protocols

4.1

SPI clock modes

4.1.1

SDR

The FS-S family can be driven by an embedded microcontroller (bus master) in either of the two following

clocking modes.

• Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

• Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the

output data is always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in Standby Mode and not

transferring any data.

• SCK will stay at logic LOW state with CPOL = 0, CPHA = 0

• SCK will stay at logic HIGH state with CPOL = 1, CPHA = 1

POL=0_CPHA=0_SCLK

POL=1_CPHA=1_SCLK

CS#

SI

MSB

SO

MSB

Figure 4

SPI SDR modes supported

Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by

showing SCK as both HIGH and LOW at the fall of CS#. In some cases, a timing diagram may show only Mode 0

with SCK LOW at the fall of CS#. In such a case, mode 3 timing simply means clock is HIGH at the fall of CS# so no

SCK rising edge set up or hold time to the falling edge of CS# is needed for Mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0, the

beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of

SCK because SCK is already LOW at the beginning of a command.

4.1.2

DDR

Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always

latched on the rising edge of clock, the same as in SDR commands. However, the address and input data that

follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is latched on

the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first bit of output

data is driven on the falling edge at the end of the last access latency (dummy) cycle.

SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the

next falling edge of SCK. In mode 0, the beginning of the first SCK cycle in a command is measured from the falling

edge of CS# to the first falling edge of SCK because SCK is already LOW at the beginning of a command.

Datasheet

17 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

CPOL=0_CPHA=0_SCLK

CPOL=1_CPHA=1_SCLK

CS#

Instruction

Address

Mode

Dummy / DLP

Read Data

Transfer_Phase

SI

Inst. 7

Inst. 0

A31 A30

A0

M7

M6

M0

SO

DLP7

DLP0 D0

D1

Figure 5

SPI DDR modes supported

4.2

Command Protocol

All communication between the host system and FS-S family memory devices is in the form of units called

commands.

All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to

be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the

memory, or data transfer from the memory. All instruction, address, and data information is transferred

sequentially between the host system and memory device.

Command protocols are also classified by a numerical nomenclature using three numbers to reference the

transfer width of three command phases:

• instruction

• address and instruction modifier(continuousreadmode bits). FortheS70FS01GS, do not enable the Continuous

Read mode, this will cause bus contention between the two 512 Mb die.

• data

Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI

signal. Data may be sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol

for single bit width instruction, single bit width address and modifier, single bit data.

Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1

or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and

IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad

I/O command protocols.

The FS-S Family also supports a QPI Mode in which all information is transferred in 4-bit width, including the

instruction, address, modifier, and data. This is referenced as a 4-4-4 command protocol.

Commands are structured as follows:

• Each command begins with CS# going LOW and ends with CS# returning HIGH. The memory device is selected

by the host driving the Chip Select (CS#) signal LOW throughout a command.

• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.

• Each command begins with an eight bit (byte) instruction. The instruction selects the type of information

transfer or device operation to be performed. The instruction transfers occur on SCK rising edges. However,

some read commands are modified by a prior read command, such that the instruction is implied from the

earlier command. This is called Continuous Read Mode. For the S70FS01GS, do not enable the Continuous Read

Mode, this will cause bus contention between the two 512 Mb die.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The instruction determines the address space used. The address may be either a

24-bit or a 32-bit, byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands,

or on every SCK edge, in DDR commands.

Datasheet

18 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

• In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent.

Following transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be

done in two bit groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per

(quad) transfer on the IO0-IO3 signals. Within the dual or quad groups, the least significant bit is on IO0. More

significant bits are placed in significance order on each higher numbered IO signal. Single bits or parallel bit

groups are transferred in most to least significant bit order.

• In QPI mode, the width of all transfers is a 4-bit wide (quad) transfer on the IO0–IO3 signals.

• Dual and Quad I/O read instructions send an instruction modifier called Continuous Read Mode bits, following

the address, to indicate whether the next command will be of the same type with an implied, rather than an

explicit, instruction. These mode bits initiate or end the Continuous Read Mode. In Continuous Read Mode, the

next command thus does not provide an instruction byte, only a new address and mode bits. For the S70FS01GS,

do not enable the Continuous Read Mode, this will cause bus contention between the two 512 Mb die.

• The address or mode bits may be followed by write data to be stored in the memory device or by a read latency

period before read data is returned to the host.

• Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles

(also referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from

the outputs on SCK falling edge at the end of the last read latency cycle. The first read data bits are considered

transferred to the host on the following SCK rising edge. Each following transfer occurs on the next SCK rising

edge, in SDR commands, or on every SCK edge, in DDR commands.

• If the command returns read data to the host, the device continues sending data transfers until the host takes

the CS# signal HIGH. The CS# signal can be driven HIGH after any transfer in the read data sequence. This will

terminate the command.

• At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must go

HIGH after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is,

the CS# signal must be driven HIGH when the number of bits after the CS# signal was driven LOW is an exact

multiple of eight bits. If the CS# signal does not go HIGH exactly at the eight bit boundary of the instruction or

write data, the command is rejected and not executed.

• All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The

data bits are shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address

byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address

increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of

commands are accepted during an embedded operation. These are discussed in the individual command

descriptions.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

4.2.1

Command sequence examples

CS#

SCLK

SI

SO

7

6

5

4

3

2

1

0

Phase

Instruction

Figure 6

Standalone Instruction command

Datasheet

19 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

CS#

SCLK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Input Data

Figure 7

Single Bit Wide Input command

CS#

SCLK

SI

7

6

5

4

3

2

1

0

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

Instruction

Data 1

Data 2

Figure 8

Figure 9

Figure 10

Single Bit Wide Output command

CS#

SCLK

SI

SO

7

6

5

4

3

2

1

0

31

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2 1 0

Phase

Address

Instruction

Data 1

Data 2

Single Bit Wide I/O command without latency

CS#

SCLK

SI

SO

7

6

5

4

3

2

1

0

31

1

0

7

6

5

4

3

2

1 0

Phase

Address

Instruction

Dummy Cycles

Data 1

Single Bit Wide I/O command with latency

CS#

SCK

IO0

7

6

5

4

3

2

1

0

30

31

2

3

0

1

6

7

4

5

2

3

0

1

6

4

2

3

0

1

6

4

2

0

1

IO1

7

5

7

5

3

Phase

Instruction

Address

Mode

Dum

Data 1

Data 2

Figure 11

Dual I/O command

Datasheet

20 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

CS#

SCLK

IO0

7

6

5

4

3

2

1

0

28

29

30

31

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

IO1

IO2

IO3

Phase

Address

Instruction

Mode

Dummy

D1

D2

D3

D4

Figure 12

Figure 13

Figure 14

Figure 15

Quad I/O command

CS#

SCLK

IO0

IO1

4

5

6

7

0

1

2

3

28

29

30

31

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

1

2

3

IO2

IO3

Phase

Instruct.

Address Mode

Dummy

D1

D2

D3

D4

Quad I/O Read command in QPI mode

CS#

SCLK

IO0

IO1

7

6

5

4

3

2

1

0

2824201612 8

2925211713 9

4

5

0

1

2

3

4

5

6

7

0

1

2

3

7

6

5

4

3

2

1

0

4

5

6

7

0

4

5

6

7

0

3

0

1

2

3

1

IO2

302622181410 6

312723191511 7

Address

2

3

IO3

Phase

Instruction

Mode Dummy

DLP

D1 D2

DDR Quad I/O Read

CS#

SCLK

IO0

IO1

4

5

6

7

0

28 24 20 16 12

29 25 21 17 13

8

4

0

1

2

3

4

5

6

7

0

1

2

3

7

6

5

4

3

2

1

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

1

2

3

9

5

6

7

4

1

IO2

30 26 22 18 14 10

31 27 23 19 15 11

Address

IO3

Phase

Instruct.

Mode

Dummy

DLP

D1

D2

DDR Quad I/O Read in QPI mode

Additional sequence diagrams, specific to each command, are provided in “Commands” on page 83.

Datasheet

21 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

4.3

Interface states

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 3

Interface states summary

IO3 /

WP# /

IO2

Interface state

V_CC

SCK

CS#

X

SO / IO1 SI / IO0

RESET#

Power-Off

Low Power

Hardware Data Protection

Power-On (Cold) Reset

Hardware (Warm) Reset

Non-Quad Mode

<V_CC(low)

<V_CC(cut-off)

≥V_CC(min)

X

Z

X

HH

X

HL

Hardware (Warm) Reset

Quad Mode

≥V_CC(min)

X

HH

HL

X

Z

X

Interface Standby

Instruction Cycle

(Legacy SPI)

HT

HH

HV

Single Input Cycle

≥V_CC(min)

HT

HL

HH

X

Z

HV

X

Host to Memory Transfer

Single Latency (Dummy)

Cycle

Single Output Cycle

Memory to Host Transfer

MV

X

Dual Input Cycle

≥V_CC(min)

HT

HL

HH

X

HV

X

HV

X

Host to Memory Transfer

Dual Latency (Dummy) Cycle

Dual Output Cycle

Memory to Host Transfer

MV

Quad Input Cycle

≥V_CC(min)

HT

HL

HV

X

HV

X

HV

X

HV

X

Host to Memory Transfer

Quad Latency (Dummy)

Cycle

Quad Output Cycle

Memory to Host Transfer

DDR Quad Input Cycle

Host to Memory Transfer

DDR Latency (Dummy) Cycle

DDR Quad Output Cycle

Memory to Host Transfer

MV

HV

MV

HV

MV

HV

MV

HV

≥V_CC(min)

HT

HL

MV or Z MV or Z MV or Z MV or Z

MV

Datasheet

22 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

Legend

Z = no driver - floating signal,

HL = Host driving V_IL,

HH = Host driving V_IH,

HV = either HL or HH_,

X = HL or HH or Z,

HT= toggling between HL and HH,

ML = Memory driving V_IL,

MH = Memory driving V_IH,

MV = either ML or MH_.

4.3.1

Power-off

When the core supply voltage is at or below the V_{CC (Low)}voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

4.3.2

Low power hardware data protection

When V_CCis less than V_{CC (Cut-off)}the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.3.3

Power-on (Cold) reset

When the core voltage supply remains at or below the V_{CC (Low)}voltage for ≥ t_PDtime, then rises to ≥ V_{CC (Minimum)}

the device will begin its Power On Reset (POR) process. POR continues until the end of t_PU. During t_PU, the device

does not react to external input signals nor drive any outputs. Following the end of t_PUthe device transitions to

the Interface Standby state and can accept commands. For additional information on POR, see “Power on (Cold)

reset” on page 36.

4.3.4

Hardware (Warm) reset

A configuration option is provided to allow IO3 to be used as a hardware reset input when the device is not in

Quad Mode or when it is in Quad Mode and CS# is HIGH. When IO3 / RESET# is driven LOW for t_RPtime, the device

starts the hardware reset process. The process continues for t_RPHtime. Following the end of both t_RPHand the

reset hold time following the rise of RESET# (t_RH) the device transitions to the Interface Standby state and can

accept commands. For additional information on hardware reset, see Note 17.

4.3.5

Interface standby

When CS# is HIGH, the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits

for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a

new command.

While in interface standby state, the memory device draws standby current (I_SB) if no embedded algorithm is in

progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm

when the entire device returns to standby current draw.

The DPD mode is supported by the FS-S Family devices. If the device has been placed in DPD mode by the DPD

(B9h) command, the interface standby current is (I_DPD). The DPD command is accepted only while the device is

not performing an embedded algorithm as indicated by the Status Register-1 Volatile Write In Progress (WIP) bit

being cleared to zero (SR1V[0] = 0). While in DPD mode, the device ignores all commands except the Release from

DPD (RES ABh) command, that will return the device to the Interface Standby state after a delay of t_RES

.

Datasheet

23 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

4.3.6

Instruction cycle (Legacy SPI mode)

When the host drives the MSB of an instruction and CS# goes LOW, on the next rising edge of SCK the device

captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the

device captures the next lower significance bit of the 8 bit instruction. The host keeps CS# LOW, and drives the

Write Protect (WP#) and IO3/RESET signals as needed for the instruction. However, WP# is only relevant during

instruction cycles of a WRAR command and is otherwise ignored. IO3/RESET# is driven HIGH when the device is

not in Quad Mode (CR1V[1] = 0) or QPI Mode (CR2V[6] = 0) and hardware reset is not required.

Each instruction selects the address space that is operated on and the transfer format used during the remainder

of the command. The transfer format may be Single, Dual I/O, Quad I/O, or DDR Quad I/O. The expected next

interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns

CS# HIGH after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface

state in this case is Interface Standby.

4.3.7

Instruction cycle (QPI mode)

In QPI Mode, when CR2V[6] = 1, instructions are transferred 4 bits per cycle. In this mode, instruction cycles are

the same as a quad input cycle (see “Quad input cycle - Host to Memory transfer” on page 25).

4.3.8

Single input cycle - Host to Memory transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the

memory device. The host keeps RESET# HIGH, CS# LOW, and drives SI as needed for the command. The memory

does not drive the Serial Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or

data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly to

Single, Dual, or Quad Output cycle states.

4.3.9

Single latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main Flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR2V[3:0]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW. The Write

Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles or the host may leave SI

floating. The memory does not use any data driven on SI/I/O0 or other I/O signals during the latency cycles. The

memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.

The next interface state depends on the command structure i.e. the number of latency cycles, and whether the

read is single, dual, or quad width.

4.3.10

Single output cycle - Memory to Host transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps

RESET# HIGH, CS# LOW. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal.

The memory drives SO with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to HIGH ending the

command.

4.3.11

Dual input cycle - Host to Memory transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps

RESET# HIGH, CS# LOW. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0 and

SO / IO1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency

cycles needed or Dual Output Cycle if no latency is required.

Datasheet

24 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

4.3.12

Dual latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main Flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR2V[3:0]). During the latency cycles, the host keeps RESET# HIGH, CS# LOW. The Write

Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals during these cycles or the host

may leave SI / IO0 and SO / IO1 floating. The memory does not use any data driven on SI / IO0 and SO / IO1 during

the latency cycles. The host must stop driving SI / IO0 and SO / IO1 on the falling edge at the end of the last latency

cycle. It is recommended that the host stop driving them during all latency cycles so that there is sufficient time

for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the

SI / IO0 and SO / IO1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

4.3.13

Dual output cycle - Memory to Host transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET#

HIGH, CS# LOW. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0 and SO / IO1

signals during the dual output cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to HIGH ending the

command.

4.3.14

Quad input cycle - Host to Memory transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. In QPI Mode, the

Quad I/O Read and Page Program commands transfer four data bits to the memory in each cycle, including the

instruction cycles. The host keeps CS# LOW, and drives the IO signals.

For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle

if there are latency cycles needed or Quad Output Cycle if no latency is required. For QPI Mode Page Program, the

host returns CS# HIGH following the delivery of data to be programmed and the interface returns to standby

state.

4.3.15

Quad latency (Dummy) cycle

Read commands may have zero to several latency cycles during which read data is read from the main Flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR2V[3:0]). During the latency cycles, the host keeps CS# LOW. The host may drive the

IO signals during these cycles or the host may leave the IO floating. The memory does not use any data driven on

IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the end of the last

latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is sufficient

time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This

prevents driver conflict between host and memory when the signal direction changes. The memory does not

drive the IO signals during the latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

4.3.16

Quad output cycle - Memory to Host transfer

The Quad I/O Read returns data to the host four bits in each cycle. The host keeps CS# LOW. The memory drives

data on IO0–IO3 signals during the Quad output cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to HIGH ending the

command.

4.3.17

DDR quad input cycle - Host to Memory transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits

are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps CS# LOW.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

Datasheet

25 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Signal protocols

4.3.18

DDR latency cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main Flash

memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in

the configuration register (CR2V[3:0]). During the latency cycles, the host keeps CS# LOW. The host may not drive

the IO signals during these cycles. So that there is sufficient time for the host drivers to turn off before the memory

begins to drive. This prevents driver conflict between host and memory when the signal direction changes. The

memory has an option to drive all the IO signals with a Data Learning Pattern (DLP) during the last 4 latency

cycles. The DLP option should not be enabled when there are fewer than five latency cycles so that there is at

least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP.

When there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles

of latency.

The next interface state following the last latency cycle is a DDR Single, or Quad Output Cycle, depending on the

instruction.

4.3.19

DDR quad output cycle - Memory to Host transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the

rising edge of SCK and four bits on the falling edge in each cycle. The host keeps CS# LOW.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to HIGH ending the

command.

4.4

Configuration Register effects on the interface

The Configuration Register 2 volatile bits 3 to 0 (CR2V[3:0]) select the variable latency for all array read commands

except Read and Read SDFP (RSFDP). Read always has zero latency cycles. RSFDP always has eight latency cycles.

The variable latency is also used in the OTPR, and RDAR commands.

The configuration register bit1 (CR1V[1]) selects whether Quad Mode is enabled to switch WP# to IO2 function,

RESET# to IO3 function, and thus allow Quad I/O Read and QPI Mode commands. Quad Mode must also be

selected to allow DDR Quad I/O Read commands.

4.5

Data protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the

hardware design. These are described in “Data Protection” on page 74. Other software managed protection

methods are discussed in “Data Protection” on page 74 of this document.

4.5.1

Power-up

When the core supply voltage is at or below the V_{CC (Low)}voltage, the device is considered to be powered off. The

device does not react to external signals, and is prevented from performing any program or erase operation.

Program and erase operations continue to be prevented during the power-on reset (POR) because no command

is accepted until the exit from POR to the Interface Standby state.

4.5.2

Low power

When V_CCis less than V_{CC (Cut-off)}the memory device will ignore commands to ensure that program and erase

operations can not start when the core supply voltage is out of the operating range.

4.5.3

Clock pulse count

The device verifies that all non-volatile memory and register data modifying commands consist of a clock pulse

count that is a multiple of eight bit transfers (byte boundary) before executing them. A command not ending on

an 8 bit (byte) boundary is ignored and no error status is set for the command.

4.5.4

DPD

In the DPD mode, the device responds only to the Release from DPD command (RES ABh). All other commands

are ignored during DPD Mode, thereby protecting the memory from program and erase operations.

Datasheet

26 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5

Electrical specifications

5.1

Absolute maximum ratings

Storage temperature plastic packages

Ambient temperature with power applied

V_CC

Input voltage with respect to Ground (VSS)^[4]

Output short circuit current^[5]

–65 °C to +150 °C

–65 °C to +125 °C

–0.5 V to +2.5 V

–0.5 V to V_CC+ 0.5 V

100 mA

5.2

Thermal resistance

Table 4

Thermal resistance

Parameter

Theta JA

Theta JB

Theta JC

Description

SL3016

ZSZ024

33

Unit

Thermal resistance (Junction to ambient)

Thermal resistance (Junction to board)

Thermal resistance (Junction to case)

39

8

9

11

°C/W

5.3

Latchup characteristics

Table 5

Latchup specification

Description

Min

–1.0

–100

Max

V_CC+ 1.0

+100

Unit

V

Input voltage with respect to V_SSon all input only connections

Input voltage with respect to V_SSon all I/O connections

V_CCCurrent

mA

Notes

4. See “Input signal overshoot” on page 29 for allowed maximums during signal transition.

5. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be

greater than one second.

6. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the device at these or any other conditions above those

indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute

maximum rating conditions for extended periods may affect device reliability.

7. Excludes power supply V_CC. Test conditions: V_CC= 1.8 V, one connection at a time tested, connections not

being tested are at V_SS

.

Datasheet

27 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5.4

Operating ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

5.4.1

Power supply voltages

V_CC

1.7 V to 2.0 V

5.4.2

Temperature ranges

Table 6

Temperature ranges

Spec

Parameter

Symbol

Conditions

Unit

Min

–40

Max

+85

+105

Industrial (I) devices

Industrial Plus (V) devices

°C

Automotive, AEC-Q100 grade 3 (A)

Devices

Automotive, AEC-Q100 grade 2 (B)

Devices

Automotive, AEC-Q100 grade 1 (M)

Devices

–40

+85

+105

+125

°C

Ambient Temperature

T_A

Notes

8. Industrial Plus operating and performance parameters will be determined by device characterization and

may vary from standard industrial temperature range devices as currently shown in this specification.

Datasheet

28 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5.4.3

Input signal overshoot

During DC conditions, input or I/O signals should remain equal to or between V_SSand V_CC. During voltage

transitions, inputs or I/Os may overshoot VSS to –1.0 V or overshoot to V_CC+ 1.0 V, for periods up to 20 ns.

V_SSto V_CC

- 1.0V

< = 20 ns

Figure 16

Maximum negative overshoot waveform

< = 20 ns

V_CC+ 1.0V

V_SSto V_CC

Figure 17

Maximum positive overshoot waveform

5.5

Power-up and power-down

The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on V_CC

until V_CCreaches the correct value as follows:

)

• V_CC(min) at power-up, and then for a further delay of t_PU

• V_SSat power-down

A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and

power-down.

The device ignores all instructions until a time delay of t_PUhas elapsed after the moment that V_CCrises above the

minimum V_CCthreshold (see Figure 18). However, correct operation of the device is not guaranteed if V_CCreturns

below V_CC(min) during t_PU. No command should be sent to the device until the end of t_PU

.

The device draws I_PORduring t_PU. After power-up (t_PU), the device is in Standby Mode, draws CMOS standby

current (I_SB), and the WEL bit is reset.

During power-down or voltage drops below V_CC(cut-off), the voltage must drop below V_CC(low) for a period of t_PD

for the part to initialize correctly on power-up (see Figure 19). If during a voltage drop the V_CCstays above

V_CC(cut-off) the part will stay initialized and will work correctly when V_CCis again above V_CC(min). In the event

Power-on Reset (POR) did not complete correctly after power up, the assertion of the RESET# signal or receiving

a software reset command (RESET) will restart the POR process.

Normal precautions must be taken for supply rail decoupling to stabilize the V_CCsupply at the device. Each device

in a system should have the V_CCrail decoupled by a suitable capacitor close to the package supply connection

(this capacitor is generally of the order of 0.1 µF).

Datasheet

29 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

Table 7

Symbol

_CC(min) V_CC(minimum operation voltage)

_CC(cut-off) V_CC(Cut 0ff where re-initialization is needed)

_CC(low) V_CC(low voltage for initialization to occur)

FS-S power-up / power-down voltage and timing

Parameter

Min

1.7

1.5

0.7

Max

Unit

V

t_PU

t_PD

V_CC(min) to Read operation

V_CC(low) time

300

µs

10.0

V_CC(Max)

V_CC(Min)

tPU

Full Device Access

Time

Figure 18

Power-up

V_CC(Max)

No Device Access Allowed

V_CC(Min)

Device

tPU

Access

Allowe

V_CC(Cut-off)

V_CC(Low)

tPD

Time

Figure 19

Power-down and voltage drop

Datasheet

30 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5.6

DC characteristics

Industrial

5.6.1

Applicable within operating –40 °C to +85 °C range.

Table 8 FS01GS DC characteristics — Industrial

Symbol

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

Test conditions

Min

–0.5

0.7  V_CC

–

Typ^[10]

Max

0.3  V_CC

V_CC+ 0.4

0.2

Unit

V_IL

V_IH

–

V

V_OL

V_OH

I_OL= 0.1 mA

I_OH= –0.1 mA

V_CC– 0.2

–

V

_CC= V_CCMax,

I_LI

Input leakage current

Output leakage current

V_IN= V_IHor V_SS

CS# = V_IH

,

–

±4

µA

V

_CC= V_CCMax,

I_LO

V_IN= V_IHor V_SS

CS# = V_IH

Serial SDR @ 50 MHz

18

25

60

70

25

45

65

90

Active power supply current Serial SDR @ 133 MHz

I_CC1

–

mA

(READ)^[10]

Quad SDR @ 133 MHz

Quad DDR @ 80 MHz

Active power supply current

(Page Program)

Active power supply current

(WRAR)

Active power supply current

(SE)

Active power supply current

(BE)

I_CC2

I_CC3

I_CC4

I_CC5

CS# = V_CC

–

60

100

mA

CS# = V_CC

IO3/RESET#, CS# = V_CC

;

I_SB

Standby current

SI, SCK = V_CCor V_SS

Industrial Temp

,

–

140

200

µA

IO3/RESET#, CS# = V_CC

I_DPD

I_POR

Deep power down current SI, SCK = V_CCor V_SS

Industrial Temp

,

–

16

–

120

160

µA

IO3/RESET#, CS# = V_CC

SI, SCK = V_CCor V_SS

Power on reset current

mA

Notes

9. Typical values are at T_AI= 25 °C and V_CC= 1.8 V.

10.Outputs unconnected during read data return. Output switching current is not included.

Datasheet

31 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5.6.2

Industrial Plus

Applicable within operating –40 °C to +105 °C range.

These values to be adjusted after DE simulation to predict the Industrial Plus capabilities.

Table 9

Symbol

DC characteristics — Industrial Plus

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

Test conditions

Min

–0.5

0.7  V_CC

–

Typ^[11]

Max

0.3  V_CC

V_CC+ 0.4

0.2

Unit

V_IL

V_IH

V_OL

V_OH

–

V

I_OL= 0.1 mA

I_OH= –0.1 mA

V_CC– 0.2

–

V

_CC= V_CCMax,

I_LI

Input leakage current

Output leakage current

V_IN= V_IHor V_SS

CS# = V_IH

,

–

±8

µA

V

_CC= V_CCMax,

I_LO

V_IN= V_IHor V_SS

CS# = V_IH

Serial SDR @ 50 MHz

18

25

60

70

25

45

65

90

Active power supply current Serial SDR @ 133 MHz

I_CC1

–

mA

(READ)^[12]

Quad SDR @ 133 MHz

Quad DDR @ 80 MHz

Active power supply current

(Page Program)

Active power supply current

(WRAR)

Active power supply current

(SE)

Active power supply current

(BE)

I_CC2

I_CC3

CS# = V_CC

–

60

100

mA

I_CC4

I_CC5

CS# = V_CC

IO3/RESET#, CS# = V_CC

;

I

_SB(Indus-

Standby current

SI, SCK = V_CCor V_SS

,

–

140

600

µA

trial Plus)

Industrial Plus Temp

IO3/RESET#, CS#=V_CC

;

I_DPD

Deep power down current SI, SCK = V_CCor V_SS

Industrial Temp

,

–

16

–

300

160

µA

IO3/RESET#, CS#=V_CC

SI, SCK = V_CCor V_SS

I_POR

Power on reset current

mA

Notes

11.Typical values are at T_AI= 25 °C and V_CC= 1.8 V.

12.Outputs unconnected during read data return. Output switching current is not included.

Datasheet

32 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Electrical specifications

5.6.3

Extended

Applicable within operating –40 °C to +125 °C range.

Table 10

Symbol

V_IL

DC characteristics — Extended

Parameter

Test Conditions

Min

–0.5

0.7  V_CC

–

Typ^[13]

Max

0.3  V_CC

V_CC+ 0.4

0.2

Unit

Input low voltage

Input high voltage

Output low voltage

Output high voltage

–

V

V_IH

V_OL

V_OH

I_OL= 0.1 mA

I_OH= –0.1 mA

V_CC– 0.2

–

V

_CC= V_CCMax,

I_LI

Input leakage current

Output leakage current

V_IN= V_IHor V_SS

CS# = V_IH

,

–

±8

µA

V

_CC= V_CCMax,

I_LO

V_IN= V_IHor V_SS

CS# = V_IH

Serial SDR @ 50 MHz

18

25

60

70

25

50

65

90

Active power supply current Serial SDR @ 133 MHz

I_CC1

–

mA

(READ)^[14]

Quad SDR @ 133 MHz

Quad DDR @ 80 MHz

Active power supply current

(Page Program)

Active power supply current

(WRAR)

Active power supply current

(SE)

Active power supply current

(BE)

I_CC2

I_CC3

I_CC4

CS# = V_CC

–

60

100

mA

I_CC5

I_SB

CS# = V_CC

IO3/RESET#, CS# = V_CC

;

(Industrial Standby current

Plus)

SI, SCK = V_CCor V_SS

,

–

140

600

µA

Industrial Plus Temp

IO3/RESET#, CS# = V_CC

I_DPD

I_POR

Deep power down current SI, SCK = V_CCor V_SS

,

–

16

–

500

160

µA

Industrial Temp

IO3/RESET#, CS# = V_CC

SI, SCK = V_CCor V_SS

Power on reset current

mA

Notes

13.Typical values are at T_AI= 25 °C and V_CC= 1.8 V.

14.Outputs unconnected during read data return. Output switching current is not included.

5.6.4

Active power and standby power modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is LOW. When CS# is HIGH, the device

is disabled, but may still be in an Active Power Mode until all program, erase, and write operations have

completed. The device then goes into the Standby Power Mode, and power consumption drops to I_SB

.

The DPD mode is supported by the FS-S Family devices. If the device has been placed in DPD Mode by the DPD

(B9h) command, the interface standby current is (I_DPD). The DPD command is accepted only while the device is

not performing an embedded algorithm as indicated by the Status Register-1 volatile Write In Progress (WIP) bit

being cleared to zero (SR1V[0] = 0). While in DPD Mode, the device ignores all commands except the Release from

DPD (RES ABh) command, that will return the device to the Interface Standby state after a delay of t_RES

.

Datasheet

33 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6

Timing specifications

6.1

Key to switching waveforms

Input

Symbol

Output

Valid at logic high or low

High Impedance

Any change permitted

Logic high Logic low

High Impedance Changing, state unknown Logic high Logic low

Figure 20

Waveform element meanings

6.2

AC test conditions

Device Under

Test

C

L

Figure 21

Test setup

Table 11

Symbol

C_L

AC measurement conditions

Parameter

Load capacitance

Input pulse voltage

Input slew rate

Input rise and fall times

Input timing ref voltage

Output timing ref voltage

Min

–

0.2 × V_CC

0.23

Max

30

0.8 × V_CC

1.25

5

Unit

pF

V

V/ns

ns

V

0.9

0.5 × V_CC

V

Notes

15.Input slew rate measured from input pulse min to max at V_CCmax.

Example: (1.9 V × 0.8) – (1.9 V × 0.2) = 1.14 V; 1.14 V /1.25 V/ns = 0.9 ns rise or fall time.

16.AC characteristics tables assume clock and data signals have the same slew rate (slope).

Datasheet

34 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

Input Levels

Output Levels

V_CC- 0.2V

V_CC+ 0.4V

0.7 x V_CC

Timing Reference Level

0.5 x V_CC

0.3 x V_CC

- 0.5V

0.2V

Figure 22

Input, output, and timing reference levels

6.2.1

Capacitance characteristics

Table 12

Symbol

Capacitance

Parameter

Input capacitance (applies to SCK, CS#,

IO3/RESET#)

Test Conditions

1 MHz

Min

–

Max

Unit

pF

C_IN

16

C_OUT

Output capacitance (applies to All I/O)

1 MHz

–

pF

Note

17.Parameter values are not 100% tested. For more details, refer to the IBIS models.

Datasheet

35 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.3

Reset

6.3.1

Power on (Cold) reset

The device executes a power-on reset (POR) process until a time delay of t_PUhas elapsed after the moment that

V_CCrises above the minimum V_CCthreshold. See Figure 18 and Table 7. The device must not be selected (CS# to

go HIGH with V_CC) during power-up (t_PU), i.e. no commands may be sent to the device until the end of t_PU

.

The IO3 / RESET# signal functions as the RESET# input when CS# is HIGH for more than t_CStime or when Quad

Mode is not enabled CR1V[1] = 0.

RESET# is ignored during POR. If RESET# is LOW during POR and remains LOW through and beyond the end of

t

_PU, CS# must remain HIGH until t_RHafter RESET# returns HIGH. RESET# must return HIGH for greater than t_RS

before returning LOW to initiate a hardware reset.

VCC

tPU

RESET#

If RESET# is low at tPU end

CS# must be high at tPU end

tRH

CS#

Figure 23

Reset LOW at the end of POR

VCC

tPU

RESET#

If RESET# is high at tPU end

tPU

CS#

CS# may stay high or go low at tPU end

Figure 24

Reset HIGH at the end of POR

VCC

tPU

tRS

RESET#

CS#

Figure 25

POR followed by hardware reset

Datasheet

36 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.3.2

IO3 / RESET# input initiated hardware (Warm) reset

The IO3 / RESET# signal functions as the RESET# input when CS# is HIGH for more than t_CStime or when Quad

Mode is not enabled CR1V[1] = 0. The IO3 / RESET# input has an internal pull-up to V_CCand may be left

unconnected if Quad Mode is not used. The t_CSdelay after CS# goes HIGH gives the memory or host system time

to drive IO3 HIGH after its use as a Quad Mode I/O signal while CS# was LOW. The internal pull-up to V_CCwill then

hold IO3 / RESET# HIGH until the host system begins driving IO3 / RESET#. The IO3 / RESET# input is ignored while

CS# remains HIGH during t_CS, to avoid an unintended Reset operation. If CS# is driven LOW to start a new

command, IO3 / RESET# is used as IO3.

When the device is not in Quad Mode or, when CS# is HIGH, and IO3 / RESET# transitions from V_IHto V_ILfor > t_RP

,

following t_CS, the device will reset register states in the same manner as power-on reset but, does not go through

the full reset process that is performed during POR. The hardware reset process requires a period of t_RPHto

complete. If the POR process did not complete correctly for any reason during power-up (t_PU), RESET# going LOW

will initiate the full POR process instead of the hardware reset process and will require t_PUto complete the POR

process.

The RESET command is independent of the state of IO3 / RESET#. If IO3 / RESET# is HIGH or unconnected, and

the RESET instruction is issued, the device will perform software reset.

Additional IO3 RESET# notes:

• IO3 / RESET# must be HIGH for t_RSfollowing t_PUor t_RPH, before going LOW again to initiate a hardware reset.

• When IO3 / RESET# is driven LOW for at least a minimum period of time (t_RP), following t_CS, the device terminates

any operation in progress, makes all outputs high impedance, and ignores all read/write commands for the

duration of t_RPH. The device resets the interface to standby state.

• If Quad mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 LOW during t_CS,

to avoid driver contention on IO3. Immediately following commands that transfer data to the host in Quad Mode,

for example, Quad I/O Read, the memory drives IO3 / Reset HIGH during t_CS,to avoid an unintended Reset

operation. Immediately following commands that transfer data to the memory in Quad Mode, e.g. Page

Program, the host system should drive IO3 / Reset HIGH during t_CS,to avoid an unintended Reset operation.

• If Quad mode is not enabled, and if CS# is LOW at the time IO3 / RESET# is asserted LOW, CS# must return HIGH

during t_RPHbefore it can be asserted LOW again after t_RH

.

Table 13

Parameter

t_RS

Hardware Reset Parameters

Description

Reset Setup - Prior Reset end and RESET# HIGH before RESET# LOW

Reset Pulse Hold - RESET# LOW to CS# LOW

RESET# Pulse Width

Limit

Min

Time Unit

50

35

ns

µs

ns

t_RPH

t_RP

t_RH

200

50

Reset Hold - RESET# HIGH before CS# LOW

Notes

18.IO3 / RESET# LOW is ignored during Power-up (t_PU). If Reset# is asserted during the end of t_PU, the device

will remain in the reset state and t_RHwill determine when CS# may go LOW.

19.If Quad Mode is enabled, IO3 / RESET# LOW is ignored during t_CS

.

20.Sum of t_RPand t_RHmust be equal to or greater than t_RPH

.

Datasheet

37 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

tRP

IO3_RESET#

CS#

Any prior reset

tRPH

tRH

tRS

tRPH

Figure 26

Hardware Reset when Quad mode is not enabled and IO3 / Reset# is enabled

tDIS

tRP

IO3_RESET#

Reset Pulse

tCS

tRH

tRPH

CS#

Prior access using IO3 for data

Figure 27

Hardware Reset when Quad mode and IO3 / Reset# are enabled

Datasheet

38 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.4

SDR AC characteristics

Table 14

AC characteristics

Symbol

Parameter

Min

Max

Unit

F_{SCK, R}SCK clock frequency for READ and 4READ instructions

DC

50

MHz

SCK clock frequency for the following dual and quad

F_{SCK, C}

DC

133

80

MHz

commands: QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR

SCK clock frequency for the following DDR commands:

QIOR, 4QIOR

F_{SCK, D}

P_SCK

_WH, t_CHClock High time

_WL, t_CLClock Low time

_CRT, t_CLCHClock rise time (slew rate)

_CFT, t_CHCLClock fall time (slew rate)

CS# High time (Read instructions)

SCK clock period

1/ F_SCK

50% P_SCK– 5%

0.1

∞

–

t

ns

V/ns

t

0.1

10

20^[25]

50

CS# High time (Read instructions when Reset feature and

t_CS

–

ns

Quad mode are both enabled)

CS# High time (Program/Erase Instructions)

t_CSS

t_CSH

t_SU

CS# Active Setup time (relative to SCK)

CS# Active Hold time (relative to SCK)

Data in Setup time

2

3

2

3

–

ns

t_HD

Data in Hold time

8^[22]

t_V

Clock low to output valid

–

1

ns

6^[23]

–

t_HO

Output Hold time

Output disable time^[24]

Output disable time (when Reset feature and Quad Mode

are both enabled)

WP# Setup time^[21]

WP# Hold time^[21]

CS# High to power-down mode

8

t_DIS

–

ns

20^[25]

t_WPS

t_WPH

t_DPD

20

100

–

3

ns

µs

CS# High to Standby Mode without Electronic Signature

Read

t_RES

–

30

µs

Notes

21.Only applicable as a constraint for WRAR instruction when SRWD is set to a 1.

22.Full V_CCrange & C_L= 30 pF.

23.Full V_CCrange & C_L= 15 pF.

24.Output HI-Z is defined as the point where data is no longer driven.

25.t_CSand t_DISrequire additional time when the Reset feature and Quad Mode are enabled (CR2V[5] = 1 and

CR1V[1] = 1).

26.Tentative AC parameters, subject to device characterization, as DDP has increased I/O capacitance that may

modify values slightly.

Datasheet

39 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.4.1

Clock timing

P_SCK

tCL

tCH

V_{IH min}

V_{CC / 2}

V_{IL max}

tCFT

tCRT

Figure 28

Clock timing

6.4.2

Input / Output timing

tCS

CS#

tCSH

tCSS

SCK

tSU

tHD

MSB IN

SI

LSB IN

SO

Figure 29

SPI single bit input timing

tCS

CS#

SCK

SI

tV

tHO

tDIS

SO

MSB OUT

LSB OUT

Figure 30

SPI single bit output timing

Datasheet

40 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

tCS

CS#

tCSS

tCSH

tCSS

tSU

SCLK

tHD

tV

tHO

tV

tDIS

MSB IN

LSB IN

MSB O.

LSB OUT

IO

Figure 31

SPI SDR MIO timing

CS#

tWPS

WP#

tWPH

SCLK

SI

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Phase

WRR or WRAR Instruction

Input Data

Figure 32

WP# input timing

Datasheet

41 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.5

DDR AC characteristics

Table 15

FS01GS AC characteristics 80MHz operation

Symbol

F_{SCK, R}

P_{SCK, R}

_WH, t_CH

_WL, t_CL

Parameter

Min

DC

12.5

Max

80

∞

–

Unit

MHz

ns

SCK Clock Frequency for DDR READ instruction

SCK Clock Period for DDR READ instruction

Clock High Time

t

50% P_SCK– 5%

Clock Low Time

CS# High Time (Read Instructions)

CS# High Time (Read Instructions when Reset feature is

enabled)

10

20

t_CS

–

ns

t_CSS

t_CSH

t_SU

t_HD

t_V

CS# Active Setup Time (relative to SCK)

CS# Active Hold Time (relative to SCK)

IO in Setup Time

IO in Hold Time

Clock Low to Output Valid

Output Hold Time

2

3

1.5

1

–

6 (1)

–

ns

t_HO

Output Disable Time

Output Disable Time (when Reset feature is enabled)

8

20

t_DIS

–

ns

t_{IO_skew}

t_DPD

First IO to last IO data valid time

CS# High to Power-down Mode

–

400

3

ps

µs

CS# High to Standby Mode without Electronic Signature

Read

t_RES

–

30

µs

Note

27.C_L= 15 pF.

6.5.1

DDR input timing

tCS

CS#

tCSH

tCSS

SCK

tHD

tSU

tHD

tSU

SI_or_IO

SO

MSB IN

LSB IN

Figure 33

SPI DDR input timing

Datasheet

42 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

6.5.2

DDR output timing

tCS

CS#

SCK

tHO

MSB

tV

tDIS

IO's

LSB

Figure 34

SPI DDR output timing

6.5.3

DDR data valid timing using DLP

p_SCK

t_CL

t_CH

SCK

t_{IO_SKEW}

t_V

t_OTT

IO Slow

IO Fast

S.

Slow D1

Slow D2

t_V

Fast D1

Fast D2

t_V_min

t_HO

t_DV

D1

IO_valid

D2

Figure 35

SPI DDR data valid window

Datasheet

43 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Timing specifications

The minimum data valid window (t_DV) and t_Vminimum can be calculated as follows:

[29]

t_DV= Minimum half clock cycle time (t_CLH

t_V_min = t_HO+ t_{IO_SKEW}+ t_OTT

Example:

)

^[28]– t_OTT^[30]– t_{IO_SKEW}

80 MHz clock frequency = 12.5 ns clock period, DDR operations and duty cycle of 45% or higher

t_CLH= 0.45 × PSCK = 0.45 × 12.5 ns = 5.625 ns

Bus impedance of 45 ohm and capacitance of 22 pf, with timing reference of 0.75V_CC,the rise time from 0 to 1 or

fall time 1 to 0 is 1.4^[33]× RC time constant (Tau)^[33]= 1.4 × 0.99 ns = 1.39 ns

t

_OTT= rise time + fall time = 1.39 ns + 1.39 ns = 2.78 ns.

Data valid window

t_DV= t_CLH– t_{IO_SKEW}– t_OTT= 5.625 ns – 400 ps – 2.78 ns = 2.45 ns

t_VMinimum

t_V_min = t_HO+ t_{IO_SKEW}+ t_OTT= 1.0 ns + 400 ps + 2.78 ns = 4.38 ns

Notes

28.t_CLHis the shorter duration of t_CLor t_CH

.

29.t_{O_SKEW}is the maximum difference (delta) between the minimum and maximum t_V(output valid) across all

IO signals.

30.t_OTTis the maximum Output Transition Time from one valid data value to the next valid data value on each

IO. t_OTTis dependent on system level considerations including:

a.Memory device output impedance (drive strength).

b.System level parasitics on the IOs (primarily bus capacitance).

c.Host memory controller input V_IHand V_ILlevels at which 0 to 1 and 1 to 0 transitions are recognized.

d.t_OTTis not a specification tested by Cypress, it is system dependent and must be derived by the system

designer based on the above considerations.

31.t_DVis the data valid window.

32.Tau = R (Output Impedance) x C (Load capacitance).

33.Multiplier of Tau time for voltage to rise to 75% of V_CC

.

Datasheet

44 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Physical interface

7

Physical interface

7.1

7.1.1

Connection diagrams

SOIC 16-lead

Figure 36

16-lead SOIC package, Top view^[34]

7.1.2

BGA 24-ball, 5x5 ball footprint (ZSA024)

Figure 37

24-ball BGA, 5x5 ball footprint (FAB024), Top view^{[35, 36]}

7.1.3

Special handling instructions for FBGA packages

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for

prolonged periods of time.

Notes

34.The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and

hardware reset are not in use.

35.Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use

either package.

36.The RESET# input has an internal pull-up and may be left unconnected in the system if Quad Mode and

hardware reset are not in use.

Datasheet

45 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Physical interface

7.2

Physical diagrams

SOIC 16-lead, 300-mil body width (SL3016)

7.2.1

A-B

C

0.20

0.10

C

D

2X

0.33

C

0.25

0.10

M

C A-B D

C

0.10

C

DIMENSIONS

NOTES:

SYMBOL

MIN.

NOM.

MAX.

2.65

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.

A

A1

A2

b

2.35

0.10

2.05

-

3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER

END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.

D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.

4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS

D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF

THE PLASTIC BODY.

-

0.30

2.55

0.51

0.48

-

0.31

0.27

0.20

-

b1

c

-

0.33

0.30

-

c1

5. DATUMS A AND B TO BE DETERMINED AT DATUM H.

6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED

D

E

10.30 BSC

7.50 BSC

PACKAGE LENGTH.

7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO

0.25 mm FROM THE LEAD TIP.

8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT

MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OF THE LEAD FOOT.

E1

e

1.27 BSC

-

L

1.27

0.40

L1

L2

N

9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1

IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.

10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

1.40 REF

0.25 BSC

16

h

0.25

0°

-

0.75

8°

0

0 1

0 2

5°

15°

-

0°

002-15547 *A

CYPRESS

Company Confidential

TITLE

PACKAGE OUTLINE, 16 LEAD SOIC

Datasheet

46 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Physical interface

7.2.2

Ball grid array 24-ball FBGA 8.0 x 6.0 X 1.2 mm (ZSA024)

NOTES:

DIMENSIONS

SYMBOL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

MIN.

-

NOM.

MAX.

1.20

-

A

A1

D

-

2. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

0.20

-

8.00 BSC

6.00 BSC

4.00 BSC

5

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

E

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE

MD X ME.

D1

E1

MD

ME

n

5

24

6

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

b

0.35

0.40

0.45

eD

eE

SD

SE

1.00 BSC

0.00

7

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE

THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

0.00

"SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALLIZED MARK INDENTATION OR OTHER MEANS.

002-15078 **

CYPRESS

Company Confidential

TITLE

PACKAGE OUTLINE, 24 BALL FBGA

8.0X6.0X1.2 MM ZSA024

DRAWN BY

DATE

Datasheet

47 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

8

Address space maps

8.1

Overview

8.1.1

Extended address

The FS-S family supports 32-bit (4 Byte) addresses to enable higher density devices than allowed by previous

generation (legacy) SPI devices that supported only 24-bit (3 Byte) addresses. A 24-bit, byte resolution, address

can access only 16 MB (128 Mb) maximum density. A 32-bit, byte resolution, address allows direct addressing of

up to a 4 GB (32 GB) address space.

Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit

addresses are enabled in two ways:

• Extended Address Mode — a volatile configuration register bit that changes all legacy commands to expect

32-bits of address supplied from the host system.

• 4 Byte address commands — that perform both legacy and new functions, which always expect 32-bit address.

The default condition for Extended Address Mode, after power-up or reset, is controlled by a non-volatile

configuration bit. The default Extended Address Mode may be set for 24 or 32-bit addresses. This enables legacy

software compatible access to the first 128 Mb of a device or for the device to start directly in 32 bit address mode.

8.1.2

Multiple address spaces

Many commands operate on the main Flash memory array. Some commands operate on address spaces

separate from the main Flash array. Each separate address space uses the full 24 or 32-bit address but may only

define a small portion of the available address space.

8.2

Flash memory array

The main Flash array is divided into erase units called physical sectors of 256 KB. The FS01GS contains two

FS512S devices stacked in a DDP. Both the lower and upper address FS512S devices must be configured to define

the overall sector map of the entire 1 Gb (128 MB) space selected by the CS# for the DDP. The lower address

FS512S may be configured for bottom parameter sectors or uniform sectors. The upper address FS512S may be

configured for top parameters or uniform sectors. When the lower address FS512S is configured for bottom

parameter sectors the upper address FS512S must be configured as uniform sectors. When the upper address

FS512S is configured for top parameter sectors the lower address FS512S must be configured as uniform sectors.

In this way, the overall address space of the DDP may have bottom, or top parameter sectors, or uniform sectors.

No other configurations are supported.

Table 16

S70FS01GS sector address map, bottom 4 KB sectors

Address range

(Byte address)

Sector size (KB)

Sector count

Sector range

Notes

SA00

:

SA7

SA8

SA9

:

00000000h–00000FFFh

:

00007000h–00007FFFh

00008000h–0003FFFFh

00040000h–0007FFFFh

:

4

8

1

Sector Starting

Address

224

256

—

Sector Ending

Address

511

SA519

07FC0000h–07FFFFFFh

Datasheet

48 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

Table 17

S70FS01GS sector address map, top 4 KB sectors

Address range

(Byte address)

Sector size (KB)

Sector count

Sector range

Notes

SA00

:

SA510

SA511

SA512

:

0000000h–003FFFFh

:

07F80000h–07FBFFFFh

07FC0000h–07FF7FFFh

07FF8000h–07FF8FFFh

:

256

224

4

511

1

Sector Starting

Address

—

Sector Ending

Address

8

SA519

07FFF000h–07FFFFFFh

Table 18

S70FS01GS sector address map (Uniform sectors)

Address range

(Byte address)

Sector size (KB)

Sector count

Sector range

Notes

SA00

:

00000000h–0003FFFFh

:

Sector Starting

Address

256

512

—

Sector Ending

Address

SA511

07FC0000h–07FFFFFFh

Note These are condensed tables that use a couple of sectors as references. There are address ranges that are

not explicitly listed. All 4 KB sectors have the pattern XXXX000h–XXXXFFFh. All 256 KB sectors have the pattern

XX00000h–XX3FFFFh, XX40000h–XX7FFFFh, XX80000h–XXCFFFFh, or XXD0000h–XXFFFFFh.

8.3

ID-CFI address space

The RDID command (9Fh) reads information from a separate Flash memory address space for device

identification (ID) and common flash interface (CFI) information. See “Device ID and Common Flash Interface

(ID-CFI) Address Map” on page 141 for the tables defining the contents of the ID-CFI address space. The ID-CFI

address space is programmed by Infineon and read-only for the host system.

8.4

JEDEC JESD216 serial flash discoverable parameters (SFDP) space

The RSFDP command (5Ah) reads information from a separate Flash memory address space for device

identification, feature, and configuration information, in accord with the JEDEC JESD216 standard for Serial

Flash Discoverable Parameters. The ID-CFI address space is incorporated as one of the SFDP parameters. See

“Serial Flash Discoverable Parameters (SFDP) Address Map” on page 137 for the tables defining the contents

of the SFDP address space. The SFDP address space is programmed by Infineon and read-only for the host

system.

Datasheet

49 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

8.5

OTP address space

Each FS-S family memory device has a 1024 byte one time program (OTP) address space that is separate from the

main Flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

In the 32-byte region starting at address zero:

• The 16 lowest address bytes are programmed by Infineon with a 128-bit random number. Only Infineon is able

to program zeros in these bytes. Programming ones in these byte locations is ignored and does not affect the

value programmed by Infineon. Attempting to program any zero in these byte locations will fail and set P_ERR.

• The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently

protect each region from programming. The bytes are erased when shipped from Cypress. After an OTP region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the OTP Lock Bytes.

• The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU

bytes may be programmed by the host system but it must be understood that a future device may use those

bits for protection of a larger OTP space. The bytes are erased when shipped from Cypress.

The remaining regions are erased when shipped from Cypress, and are available for programming of additional

permanent data.

Refer to Figure 38 for a pictorial representation of the OTP memory space.

The OTP memory space is intended for increased system security. OTP values, such as the random number

programmed by Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device

substitution.

The configuration register FREEZE (CR1V[0]) bit protects the entire OTP memory space from programming when

set to ‘1’. This allows trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent

further OTP memory space programming during the remainder of normal power-on system operation.

32 Byte OTP Region 31

32 Byte OTP Region 30

32 Byte OTP Region 29

When programmed to 0, each lock

bit protects its related 32 byte OTP

region from any further

programming

.

32 Byte OTP Region 3

32 Byte OTP Region 2

32 Byte OTP Region 1

32 Byte OTP Region 0

Region 0 Expanded View

...

Reserved

16 Byte Random Number

Lock Bits 31 to 0

Byte 0h

Byte 10h

Byte 1Fh

Figure 38

OTP address space

Datasheet

50 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

Table 19

Region

OTP address map

Byte address range (Hex)

Contents

Initial delivery state (Hex)

Least Significant Byte of

Infineon Programmed

Random Number

000

...

Cypress Programmed

Random Number

...

Most Significant Byte of

Infineon Programmed

Random Number

00F

Region 0

Region Locking Bits

Byte 10 [bit 0] locks region 0

from programming when = 0

...

Byte13 [bit 7] locksregion31

from programming when = 0

010 to 013

All Bytes = FF

Reserved for Future Use

(RFU)

014 to 01F

020 to 03F

040 to 05F

...

All Bytes = FF

Available for User

Programming

Available for User

Programming

Available for User

Programming

Available for User

Programming

Region 1

Region 2

...

Region 31

3E0 to 3FF

8.6

Error correction code (ECC)

Error detection and correction (EDC) is applied to all parts of the Flash address spaces other than registers. An

Error correction code (ECC) is calculated for each group of bytes protected and the ECC is stored in a hidden area

related to the group of bytes. The group of protected bytes and the related ECC are together called an ECC unit.

• ECC is calculated for each 16 byte aligned and length ECC unit

• Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag

• Sector erase resets all ECC disable flags in a sector to the default state (enabled)

• ECC is programmed as part of the standard Program commands operation

• ECC is disabled automatically if multiple programming operations are done on the same ECC unit.

• Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16 byte

ECC unit.

• The ECC disable flag is programmed when ECC is disabled

• To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased

• To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC

is stored for that unit and not disabled.

• The calculation, programming, and disabling of ECC is done automatically as part of programming operations.

The detection and correction if needed is done automatically as part of read operations. The host system sees

only corrected data from a read operation.

• There is a command to read the ECC status for any ECC unit.

Datasheet

51 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

• EDC protects the OTP region - however a second program operation on the same ECC unit will disable ECC

permanently on that ECC unit (OTP), hence an erase operation to re-enable the ECC enable/indicator bit is

prohibited)

8.7

Registers

Registers are small groups of memory cells used to configure how the FS-S Family memory device operates or to

report the status of device operations. The registers are accessed by specific commands. The commands (and

hexadecimal instruction codes) used for each register are noted in each register description.

In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or OTP bits

within the same register. In some configuration options the type of a register bit could change e.g. from

non-volatile to volatile.

The FS-S Family uses separate non-volatile or volatile memory cell groups (areas) to implement the different

register bit types. However, the legacy registers and commands continue to appear and behave as they always

have for legacy software compatibility. There is a non-volatile and a volatile version of each legacy register when

that legacy register has volatile bits or when the command to read the legacy register has zero read latency. When

such a register is read the volatile version of the register is delivered. During Power-On Reset (POR), hardware

reset, or software reset, the non-volatile version of a register is copied to the volatile version to provide the

default state of the volatile register. When non-volatile register bits are written the non-volatile version of the

register is erased and programmed with the new bit values and the volatile version of the register is updated with

the new contents of the non-volatile version. When OTP bits are programmed the non-volatile version of the

register is programmed and the appropriate bits are updated in the volatile version of the register. When volatile

register bits are written, only the volatile version of the register has the appropriate bits updated.

The type for each bit is noted in each register description. The default state shown for each bit refers to the state

after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the

default state is the value of the bit when the device is shipped from Cypress. Non-volatile bits have the same

cycling (erase and program) endurance as the main Flash array.

Datasheet

52 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

8.7.1

Status Register-1

Status Register-1 Non-Volatile (SR1NV)

8.7.1.1

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h)

Table 20

Bits

Status Register-1 Non-Volatile (SR1NV)

Field

Default

state

Function

Type

Description

name

1 = Locks state of SRWD, BP, and

configuration register-1 bits when

WP# is LOW by not executing WRAR

commands that would affect

SR1NV, SR1V, CR1NV, or CR1V.

0 = No protection, even when WP#

is LOW

Provides the default state for the

Programming Error Status. Not

user programmable.

Status Register

Write Disable

Default

7

SRWD_NV

P_ERR_D

Non-Volatile

0

Programming Error

Default

Non-Volatile

Read Only

6

5

0

Provides the default state for the

Erase Error Status. Not user

programmable.

Non-Volatile

Read Only

E_ERR_D Erase Error Default

4

3

BP_NV2

BP_NV1

Protects the selected range of

sectors (Block) from Program or

Erase when the BP bits are

configured as non-volatile

(CR1NV[3] = 0). Programmed to

111b when BP bits are configured

to volatile (CR1NV[3] = 1).- after

which these bits are no longer user

programmable.

Block Protection

Non-Volatile

000b

2

BP_NV0

Provides the default state for the

WEL Status. Not user

Non-Volatile

Read Only

1

0

WEL_D

WIP_D

WEL Default

WIP Default

0

programmable.

Provides the default state for the

WIP Status. Not user

programmable.

Non-Volatile

Read Only

Status Register Write Non-volatile (SRWD_NV) SR1NV[7]: Places the device in the Hardware Protected Mode

when this bit is set to 1 and the WP# input is driven LOW. In this mode, the Write Any Register (WRAR) commands

(that select status register-1 or configuration register-1) are ignored and not accepted for execution, effectively

locking the state of the Status Register-1 and Configuration Register-1 (SR1NV, SR1V, CR1NV, or CR1V) bits, by

making the registers read-only. If WP# is HIGH, Status Register-1 and Configuration Register-1 may be changed

by the WRAR commands. If SRWD_NV is 0, WP# has no effect and Status Register-1 and Configuration Register-1

may be changed by the WRAR commands. WP# has no effect on the writing of any other registers. The SRWD_NV

bit has the same non-volatile endurance as the main Flash array. The SRWD (SR1V[7]) bit serves only as a copy of

the SRWD_NV bit to provide zero read latency.

Program Error Default (P_ERR_D) SR1NV[6]: Provides the default state for the Programming Error Status in

SR1V[6]. This bit is not user programmable.

Erase Error (E_ERR) SR1V[5]: Provides the default state for the Erase Error Status in SR1V[5]. This bit is not user

programmable.

Datasheet

53 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

Block Protection (BP_NV2, BP_NV1, BP_NV0) SR1NV[4:2]: These bits define the main Flash array area to be

software-protected against program and erase commands. The BP bits are selected as either volatile or

non-volatile, depending on the state of the BP non-volatile bit (BPNV_O) in the configuration register CR1NV[3].

When CR1NV[3] = 0 the non-volatile version of the BP bits (SR1NV[4:2]) are used to control Block Protection and

the WRAR command writes SR1NV[4:2] and updates SR1V[4:2] to the same value. When CR1NV[3] = 1 the volatile

version of the BP bits (SR1V[4:2]) are used to control Block Protection and the WRAR command writes SR1V[4:2]

and does not affect SR1NV[4:2]. When one or more of the BP bits is set to 1, the relevant memory area is protected

against program and erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to

0’s. See “Block Protection” on page 75 for a description of how the BP bit values select the memory array area

protected. The non-volatile version of the BP bits have the same non-volatile endurance as the main Flash array.

Write Enable Latch Default (WEL_D) SR1NV[1]: Provides the default state for the WEL Status in SR1V[1]. This bit

is programmed by Cypress and is not user programmable.

Write In Progress Default (WIP_D) SR1NV[0]: Provides the default state for the WIP Status in SR1V[0]. This bit is

programmed by Cypress and is not user programmable.

8.7.1.2

Status Register-1 Volatile (SR1V)

Related Commands: Write Enable (WREN 06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h or 82h),

Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).

Table 21

Bits

Status Register-1 Volatile (SR1V)

Field

Default

state

Function

Type

Description

name

Status Register

Write Disable

Programming Error

Occurred

Volatile

7

6

5

SRWD

P_ERR

E_ERR

Volatile copy of SR1NV[7].

Read Only

Volatile

Read Only

Volatile

Read Only

1 = Error occurred

0 = No Error

1= Error occurred

0 = No Error

Erase Error

Occurred

4

3

BP2

BP1

Protects selected range of sectors (Block)

from Program or Erase when the BP bits

are configured as volatile (CR1NV[3] = 1).

Volatile copy of SR1NV[4:2] when BP bits

are configured as non-volatile. User

writable when BP bits are configured as

volatile.

Block Protection

Volatile

2

BP0

SR1NV

1 = Device accepts Write Registers (WRAR),

program, or erase commands

0 = Device ignores Write Registers (WRAR),

program, or erase commands

1

WEL

Write Enable Latch

Write in Progress

This bit is not affected by WRAR, only

WREN and WRDI commands affect this bit.

1= Device Busy, an embedded operation is

in progress such as program or erase

0 = Ready Device is in Standby Mode and

can accept commands

This bit is not affected by WRAR, it only

provides WIP status.

Volatile

Read Only

0

WIP

Datasheet

54 of 172

002-03833 Rev. *F

2022-05-04

1Gb (128 MB) FS-S Flash

SPI Multi-I/O, 1.8V

Address space maps

Status Register Write (SRWD) SR1V[7]: SRWD is a volatile copy of SR1NV[7]. This bit tracks any changes to the

non-volatile version of this bit.

Program Error (P_ERR) SR1V[6]: The Program Error Bit is used as a program operation success or failure

indication. When the Program Error bit is set to a “1” it indicates that there was an error in the last program

operation. This bit will also be set when the user attempts to program within a protected main memory sector,

or program within a locked OTP region. When the Program Error bit is set to a “1” this bit can be cleared to zero

with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRAR

commands.

Erase Error (E_ERR) SR1V[5]: The Erase Error Bit is used as an Erase operation success or failure indication.

When the Erase Error bit is set to a “1” it indicates that there was an error in the last erase operation. This bit will

also be set when the user attempts to erase an individual protected main memory sector. The Bulk Erase

command will not set E_ERR if a protected sector is found during the command execution. When the Erase Error

bit is set to a “1” this bit can be cleared to zero with the Clear Status Register (CLSR) command. This is a read-only

bit and is not affected by the WRAR commands.

Block Protection (BP2, BP1, BP0) SR1V[4:2]: These bits define the main Flash array area to be