S70GL02GS12FHIV23_技术文档

S70GL02GS

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

General description

The S70GL02GS 2-Gb MIRRORBIT™ flash memory device is fabricated on 65-nm MIRRORBIT™ process technology.

This device offers a fast page access time of 25 ns with a corresponding random access time of 110 ns. It features

a write buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in

faster effective programming time than standard single byte/word programming algorithms. This makes the

device an ideal product for today’s embedded applications that require higher density, better performance and

lower power consumption.

This document contains information for the S70GL02GS device, which is a dual die stack of two S29GL01GS die.

For detailed specifications, please refer to the discrete die datasheet.

Document

Document number

S29GL01GS datasheet

001-98285

Distinctive characteristics

• CMOS 3.0 V core with Versatile I/O™

• Two 1024 Megabit (S29GL01GS) in a single 64-ball Fortified-BGA package (see S29GL01GS datasheet for full

specifications)

• 65-nm MIRRORBIT™ process technology

• Single supply (V_CC) for read / program / erase (2.7 V to 3.6 V)

• Versatile I/O feature

- Wide I/O voltage (VIO): 1.65 V to V_CC

• ×16 data bus

• 16-word/32-byte page read buffer

• 512-byte programming buffer

- Programming in page multiples, up to a maximum of 512 bytes

• Sector erase

- Uniform 128-KB sectors

- S70GL02GS: two thousand forty-eight sectors

• Suspend and Resume commands for Program and Erase operations

• Status Register, data polling, and Ready/Busy pin methods to determine device status

• Advanced sector protection (ASP)

- Volatile and non-volatile protection methods for each sector

• Separate 1024-bye one time program (OTP) array with two lockable regions

- Available in each device Support for common flash interface (CFI)

• WP# input

- Protects first or last sector, or first and last sectors of each device, regardless of sector protection settings

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Performance characteristics

• Temperature range:

- Industrial temperature range (–40°C to +85°C)

- Automotive AEC-Q100 grade 3 (–40°C to +85°C)

- Automotive AEC-Q100 grade 2 (–40°C to +105°C)

• 100,000 erase cycles per sector typical

• 20-year data retention typical

• Packaging options

- 64-ball LSH Fortified BGA, 13 mm  11 mm

Performance characteristics

Maximum read access times (ns) ^[1]

Parameter

2 Gb

Random access time (t

)

110

20

120

30

ACC

Page access time (t

)

PACC

CE# access time (t

)

110

25

120

35

CE

OE# access time (t

)

OE

Typical program and erase rates

Operation

Rate

Buffer Programming (512 bytes)

Sector Erase (128 kbytes)

1.5 MBps

477 KBps

Maximum current consumption

Operation

Current

60 mA

Active read at 5 MHz, 30 pF

Program

Erase

100 mA

200 µA

Standby

Notes

1. Access times are dependent on V_IOoperating ranges. See “Ordering information” on page 21 for further

details.

2. Contact Infineon sales representative for availability.

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Table of contents

General description ...........................................................................................................................1

Distinctive characteristics ..................................................................................................................1

Performance characteristics...............................................................................................................2

Table of contents...............................................................................................................................3

1 Input/output description and logic symbol .......................................................................................4

2 Block diagrams...............................................................................................................................5

3 Connection diagrams ......................................................................................................................7

3.1 Special handling instructions for BGA package ....................................................................................................7

4 Memory map ..................................................................................................................................8

5 Second die access ...........................................................................................................................9

6 Autoselect....................................................................................................................................10

7 Electrical specifications.................................................................................................................11

7.1 Thermal resistance ...............................................................................................................................................11

8 DC characteristics .........................................................................................................................12

9 BGA package capacitance ..............................................................................................................13

10 Device ID and common flash interface (ID-CFI) ASO map.................................................................14

11 Package diagram ........................................................................................................................20

11.1 LSH064 — 64-ball fortified ball grid array, 13 x 11 mm .....................................................................................20

12 Ordering information ..................................................................................................................21

12.1 Recommended combinations............................................................................................................................21

Revision history ..............................................................................................................................23

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Input/output description and logic symbol

1

Input/output description and logic symbol

Table 1 identifies the input and output package connections provided on the device.

Table 1

Symbol

Input/output description

Type

Description

A26–A0

DQ15–DQ0

CE#

Input

I/O

Address lines for GL02GS.

Data input/output.

Chip Enable.

Output Enable.

Write Enable.

Device power supply.

Versatile IO input.

Ground.

Input

Supply

OE#

WE#

V_CC

V_IO

V_SS

Ready/Busy. Indicates whether an Embedded Algorithm is in progress or

complete. At V_IL, the device is actively erasing or programming. At High Z, the

device is in ready.

RY/BY#

RESET#

WP#

Output

Input

Hardware Reset. LOW = device resets and returns to reading array data.

Write Protect/Acceleration Input. At V_IL, disables program and erase functions

in the outermost sectors. At V_HH, accelerates programming; automatically

places device in unlock bypass mode. Should be at V_IHfor all other conditions.

Input

Not Connected. No device internal signal is connected to the package connector

No Connect nor is there any future plan to use the connector for a signal. The connection

may safely be used for routing space for a signal on a printed circuit board (PCB).

NC

Do Not Use. A device internal signal may be connected to the package

connector. The connection may be used by Infineon for test or other purposes

and is not intended for connection to any host system signal. Any DNU signal

Reserved related function will be inactive when the signal is at V_IL. The signal has an

internal pull-down resistor and may be left unconnected in the host system or

may be tied to V_SS. Do not use these connections for PCB signal routing

channels. Do not connect any host system signal to these connections.

DNU

Reserved for Future Use. No device internal signal is currently connected to the

package connector but there is potential future use for the connector for a

No Connect signal. It is recommended to not use RFU connectors for PCB routing channels

so that the PCB may take advantage of future enhanced features in compatible

footprint devices.

RFU

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Block diagrams

2

Block diagrams

A26

A0 to A25

AMAX+1 Ext

A0-A25

VCC

VCCQ

VCC

VIO

VSS

CE#

1 Gb Flash

(Flash 1)

VSSQ

CE#

OE#

WE#

RESET#

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

RY/BY#

WP#

RY/BY#

Amax+1 Ext

A0-A25

VCC

VCCQ

VSS

CE#

VSSQ

1 Gb Flash

(Flash 2)

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

WP#

RY/BY#

Figure 1

2 x GL01GS (Highest and lowest address sectors protected) block diagram

A26

A0 to A25

AMAX+1 Ext

A0-A25

VCC

VCCQ

VCC

VIO

VSS

1 Gb Flash

(Flash 1)

CE#

VSSQ

CE#

OE#

WE#

RESET#

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

RY/BY#

WP#

VIO

RY/BY#

Amax+1 Ext

A0-A25

VCC

VCCQ

VSS

VSSQ

1 Gb Flash

(Flash 2)

CE#

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

WP#

RY/BY#

Figure 2

2 x GL01GS (Lowest address sector protected) block diagram

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Block diagrams

A26

A0 to A25

AMAX+1 Ext

A0-A25

VCC

VCCQ

VCC

VIO

VSS

VSSQ

VSS

1 Gb Flash

(Flash 1)

CE#

OE#

WE#

RESET#

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

RY/BY#

WP#

RY/BY#

Amax+1 Ext

A0-A25

VCC

VCCQ

1 Gb Flash

(Flash 2)

VSS

VSSQ

CE#

OE#

WE#

RESET#

AMAX+1 Int

DQ0-15

VIO

WP#

RY/BY#

Figure 3

2 x GL01GS (Highest address sector protected) block diagram

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Connection diagrams

3

Connection diagrams

3.1

Special handling instructions for BGA package

Special handling is required for flash memory products in BGA packages.

Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package

and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

64-ball fortified BGA

Top view, balls facing down

A8

B8

C8

D8

E8

F8

G8

H8

NC

A22

A23

V_IO

V_SS

A24

A25

A7

B7

C7

D7

E7

F7

G7

H7

V_SS

A13

A12

A14

A15

A16

RFU

DQ15

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

V_CC

WE#

RESET#

A21

A19

DQ5

DQ12

DQ4

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY#

WP#

A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

B1

C1

D1

E1

F1

G1

H1

NC

A26

NC

DNU

V_IO

RFU

NC

Figure 4

Notes

64-ball fortified ball grid array

3. Ball E1, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may

be used by Infineon for test or other purposes and is not intended for connection to any host system signal.

Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be

connected to V_CCor V_SSthrough a series resistor.

4. Balls F7 and G1, Reserved for Future Use (RFU).

5. Balls A1, A8, C1, D1, H1, and H8, No Connect (NC).

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Memory map

4

Memory map

The S70GL02GS consist of uniform 64 Kword (128-KB) sectors organized as shown in Table 2.

Table 2

S70GL02GS sector and memory address map

Uniform sector size

Sector count

Sector range Address range (16-bit)

Notes

SA00

:

0000000h–000FFFFh Sector starting address

:

64 Kword/128 KB

2048

SA2047

7FF0000H–7FFFFFFh

Sector ending address

Note

6. This table has been condensed to show sector-related information for an entire device on a single page.

Sectors and their address ranges that are not explicitly listed (such as SA001–SA2046) have sector starting

and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB

sectors have the pattern xxx0000h–xxxFFFFh.

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Second die access

5

Second die access

The S70GL02GS device is a dual die stack comprising two S29GL01GS dies connected in parallel, but with only

one chip select (CS#) signal. This means that each die receives commands in parallel. The low-address die accepts

commands with A26 = 0, while the high-address die accepts commands with A26 = 1. So, it is necessary to set the

address bit A26 to ‘1’ while sending commands to access the second die of S70GL02GS. You can manage this by

adding the base address for each die to each address argument for each command; the base address for first die

is 0x0 and for the second die is 0x4000000. The following table provides an example.

Table 3

Second die access example

Command sequence to erase first Command sequence to erase first

sector in die 1

sector in die 2

1st unlock cycle

2nd unlock cycle

1st command cycle

2nd command cycle

3rd command cycle

Address 0x555 / Data 0xAA

Address 0x2AA / Data 0x55

Address 0x555 / Data 0x80

Address 0x555 / Data 0xAA

Address 0x2AA / Data 0x55

Address 0x4000555 / Data 0xAA

Address 0x40002AA / Data 0x55

Address 0x4000555 / Data 0x80

Address 0x4000555 / Data 0xAA

Address 0x40002AA / Data 0x55

Sector Address / Sector Erase

command

Address 0x0000000 / Data 0x30

Address 0x4000000 / Data 0x30

No special address manipulation is required for reading the main flash array. While reading you cannot tell that

there are two flash die - only that there is a continuous address space that spans both flash chips.

The special address manipulation is required for writing commands and receiving command response. Many

commands have “unlock cycles” consisting of the 555h/AAh and 2AAh/55h address/data pattern. For these cycles

A26 must be set correctly, so the unlock cycles are accepted by the intended flash die. Some commands also have

address arguments that must be directed to the correct die via A26. These arguments are: Read Address (RA),

Program Address (PA), Sector Address (SA), Write Buffer Location (WBL), PassWord Address (PWA), Don’t Care

(XXX - for single die only)

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Autoselect

6

Autoselect

Table 4 provides the device identification codes for the S70GL02GS. For more information on the autoselect

function, refer to the S29GL-S datasheet.

Table 4

Autoselect addresses in system

Description

Address

Read data (word/byte mode)

Manufacturer ID

Device ID, Word 1

Device ID, Word 2

Device ID, Word 3

(Base) + 00h 0001h

(Base) + 01h 227Eh

(Base) + 0Eh 2248h

(Base) + 0Fh 2201h

For S70GL02GS highest address sector protect:

XX3Fh = Not factory locked

XXBFh = Factory locked

Secure Device Verify

Sector Protect Verify

(Base) + 03h

For S70GL02GS lowest address sector protect:

XX2Fh = Not factory locked

XXAFh = Factory locked

(SA) + 02h xx01h/01h = Locked, xx00h/00h = Unlocked

Datasheet

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001-98296 Rev. *K

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Electrical specifications

7

Electrical specifications

7.1

Thermal resistance

Table 5

Parameter

Thermal resistance

Description

Test condition

LSH064

Unit

Thermal resistance

Theta JA

Theta JB

Theta JC

29.2

°C/W

(Junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance in

accordance with EIA/JESD51, with Still Air (0 m/s).

Thermal resistance

(Junction to board)

11.3

8.4

°C/W

Thermal resistance

(Junction to case)

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

DC characteristics

8

DC characteristics

Table 6

Parameter

DC characteristics

Description

[8]

Test conditions

= V to V , V = V max

Min

–

Typ

Max

±2.0

Unit

µA

I

Input load current

V

+0.04

LI

IN

SS

CC CC

CC

Output leakage current

= V to V , V = V max

–

µA

LO

OUT

SS

CC CC

CC

CE#, RESET#, OE# = V

IH

,

IH

I

V

standby current

–

140

20

200

40

µA

mA

µA

CC4

CC5

CC

V

= V , V = V , V = V max

IO IL SS CC CC

CE# = V , RESET# = V ,

[8, 9]

IH

IL

reset current

V

= V max

CC

V

= V , V = V

SS

,

IH

CC

IO IL

6

12

= V max, t

+ 30 ns

CC

ACC

[10]

I

Automatic Sleep mode

CC6

CC7

V

= V , V = V ,

IO IL SS

IH

CC

200

300

= V max, t

ASSB

CC

RESET# = V

IO,

V

current

CC

CE# = V , OE# = V

,

IO

–

106

160

mA

[8, 13]

IO

during power-up

V

= V max

CC

Notes

7. I_CCactive while Embedded Algorithm is in progress.

8. Not 100% tested.

9. If an embedded operation is in progress at the start of reset, the current consumption will remain at the

embedded operation specification until the embedded operation is stopped by the reset. If no embedded

operation is in progress when reset is started, or following the stopping of an embedded operation, I_CC7will

be drawn during the remainder of t_RPH. After the end of t_RPHthe device will go to standby mode until the next

read or write.

10.Automatic sleep mode enables the lower power mode when addresses remain stable for a designated time.

11.V_IO= 1.65 V to V_CCor 2.7 V to V_CCdepending on the model.

12.V_CC= 3 V and V_IO= 3 V or 1.8 V. When V_IOis at 1.8 V, I/O pins cannot operate at >1.8 V.

13.During power-up there are spikes of current demand, the system needs to be able to supply this current to

insure the part initializes correctly.

14.The recommended pull-up resistor for RY/BY# output is 5 kΩ to 10 kΩ.

15.For all other DC current values, refer to the S29GL-128S_01GS_00 datasheet.

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

BGA package capacitance

9

BGA package capacitance

Table 7

Parameter

C_IN

C_OUT

A26

BGA package capacitance

Description

Input capacitance

Typ

15

10

6

Max

16

11

7

Unit

pF

Output capacitance

Highest order address

Separated control pin

CE#

OE#

WE#

WP#

RESET#

RY/BY#

12

7

11

8

13

8

12

9

5

6

Notes

16.Sampled, not 100% tested.

17.Test conditions TA = 25°C, f = 1.0 MHz.

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

10

Device ID and common flash interface (ID-CFI) ASO map

The device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, sector protection

state, and basic feature set information for the device.

ID-CFI location 02h displays sector protection status for the sector selected by the sector address (SA) used in the

ID-CFI enter command. To read the protection status of more than one sector it is necessary to exit the ID ASO

and enter the ID ASO using the new SA. The access time to read location 02h is always t_ACCand a read of this

location requires CE# to go HIGH before the read and return LOW to initiate the read (asynchronous read access).

Page mode read between location 02h and other ID locations is not supported. Page mode read between ID

locations other than 02h is supported.

Table 8

Description

Manufacture ID

ID (Autoselect) address map

Address

Read data

(SA) + 0000h

(SA) + 0001h

0001h

227Eh

Device ID

Sector protection state (1 = Sector protected, 0 = Sector

unprotected). This protection state is shown only for the SA

selected when entering ID-CFI ASO. Reading other SA provides

undefined data. To read a different SA protection state ASO exit

command must be used and then enter ID-CFI ASO again with the

new SA.

Protection

verification

(SA) + 0002h

For S70GL02GS highest address sector protect:

XX3Fh = Not factory locked

XXBFh = Factory locked

For S70GL02GS lowest address sector protect:

XX2Fh = Not factory locked

XXAFh = Factory locked

DQ15–DQ08 = 1 (Reserved)

DQ7 - Factory locked secure silicon region

1 = Locked

Indicator bits

(SA) + 0003h

0 = Not locked

DQ6 - Customer locked secure silicon region

1 = Locked

0 = Not locked

DQ5 = 1 (Reserved)

DQ4 - WP# Protects

0 = lowest address Sector

1 = highest address Sector

DQ3–DQ0 = 1 (Reserved)

(SA) + 0004h

(SA) + 0005h

(SA) + 0006h

(SA) + 0007h

(SA) + 0008h

(SA) + 0009h

(SA) + 000Ah

(SA) + 000Bh

Reserved

RFU

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

Table 8

ID (Autoselect) address map (Continued)

Description

Address

Read data

Bit 0 - Status Register support

1 = Status Register supported

0 = Status Register not supported

Bit 1 - DQ polling Support

1 = DQ bits polling supported

0 = DQ bits polling not supported

Bit 3–2 - Command set support

11 = reserved

Lower software bits

(SA) + 000Ch

10 = reserved

01 = Reduced Command set

00 = Classic Command set

Bits 4–15 - Reserved = 0

Upper software bits

Device ID

(SA) + 000Dh

(SA) + 000Eh

(SA) + 000Fh

Reserved

2248h = 2 Gb

2201h

Device ID

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

Table 9

CFI query identification string

Word address

Data

Description

(SA) + 0010h

(SA) + 0011h

(SA) + 0012h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

(SA) + 0013h

(SA) + 0014h

0002h

0000h

Primary OEM Command set

(SA) + 0015h

(SA) + 0016h

0040h

0000h

Address for primary extended table

(SA) + 0017h

(SA) + 0018h

0000h

Alternate OEM command set

(00h = none exists)

(SA) + 0019h

(SA) + 001Ah

0000h

Address for alternate OEM extended table

(00h = none exists)

Table 10

Word address

(SA) + 001Bh

CFI system interface string

Data

0027h

0036h

0000h

0008h

Description

V_CCMin. (erase/program) (D7–D4: volts, D3–D0: 100 mV)

(SA) + 001Ch

(SA) + 001Dh

(SA) + 001Eh

(SA) + 001Fh

V

_CCMax. (erase/program) (D7–D4: volts, D3–D0: 100 mV)

_PPMin. voltage (00h = no V_PPpin present)

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single word write 2^Nµs

Typical timeout for max multi-byte program, 2^Nµs

(00h = not supported)

(SA) + 0020h

0009h

(SA) + 0021h

(SA) + 0022h

(SA) + 0023h

(SA) + 0024h

(SA) + 0025h

0008h

0013h (2 Gb)

0001h

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for single word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

0002h

0003h

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical

(00h = not supported)

(SA) + 0026h

0003h

Datasheet

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2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

Table 11

Word address

(SA) + 0027h

CFI device geometry definition

Data

001Ch (2 Gb)

0001h

Description

Device Size = 2^Nbyte

(SA) + 0028h

(SA) + 0029h

(SA) + 002Ah

(SA) + 002Bh

Flash Device Interface Description 0 = x8-only, 1 = ×16-only, 2 = ×8/×16

capable

0000h

Max. number of byte in multi-byte write = 2^N

(00 = not supported)

0009h

0000h

Number of erase block regions within device

1 = Uniform device, 2 = Boot device

(SA) + 002Ch

0001h

(SA) + 002Dh

(SA) + 002Eh

(SA) + 002Fh

(SA) + 0030h

(SA) + 0031h

(SA) + 0032h

(SA) + 0033h

(SA) + 0034h

(SA) + 0035h

(SA) + 0036h

(SA) + 0037h

(SA) + 0038h

(SA) + 0039h

(SA) + 003Ah

(SA) + 003Bh

(SA) + 003Ch

00XXh

000Xh

0000h

000Xh

0000h

Erase block region 1 information (refer to JEDEC JESD68-01 or

JEP137 specifications)

00FFh, 0007h, 0000h, 0002h = 2 Gb

Erase block region 2 information (refer to CFI publication 100)

Erase block region 3 information (refer to CFI publication 100)

Erase block region 4 information (refer to CFI publication 100)

Datasheet

17

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

Table 12

Word address

(SA) + 0040h

CFI primary vendor-specific extended query

Data

0050h

0052h

0049h

0031h

0035h

Description

(SA) + 0041h

(SA) + 0042h

(SA) + 0043h

(SA) + 0044h

Query-unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

Address sensitive unlock (Bits 1–0)

00b = Required

01b = Not required

Process technology (Bits 5–2)

0000b = 0.23 µm floating gate

0001b = 0.17 µm floating gate

0010b = 0.23 µm MIRRORBIT™

0011b = 0.13 µm floating gate

0100b = 0.11 µm MIRRORBIT™

0101b = 0.09 µm floating gate

0110b = 0.09 µm MIRRORBIT™

0111b = 0.065 µm MIRRORBIT™ Eclipse

1000b = 0.065 µm MIRRORBIT™

1001b = 0.045 µm MIRRORBIT™

(SA) + 0045h

001Ch

Erase Suspend

0 = Not supported

1 = Read only

(SA) + 0046h

0002h

2 = Read and write

Sector protect

(SA) + 0047h

(SA) + 0048h

0001h

0000h

00 = Not supported

X = Number of sectors in smallest group

Temporary sector unprotect

00 = Not supported

01 = Supported

Sector protect/unprotect scheme

04 = High voltage method

05 = Software command locking method

08 = Advanced sector protection method

(SA) + 0049h

0008h

Simultaneous operation

00 = Not supported

(SA) + 004Ah

(SA) + 004Bh

0000h

X = Number of banks

Burst mode type

00 = Not supported

01 = Supported

Page mode type

00 = Not supported

01 = 4 word page

02 = 8 word page

03 = 16 word page

(SA) + 004Ch

(SA) + 004Dh

0003h

0000h

ACC (Acceleration) supply minimum

00 = Not supported

D7–D4: Volt

D3–D0: 100 mV

Datasheet

18

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Device ID and common flash interface (ID-CFI)

ASO map

Table 12

CFI primary vendor-specific extended query (Continued)

Word address

Data

Description

ACC (Acceleration) supply maximum

00 = Not supported

D7–D4: Volt

D3–D0: 100 mV

(SA) + 004Eh

0000h

WP# Protection

00h = Flash device without WP Protect (No boot)

01h = Eight 8 KB sectors at top and bottom with WP (Dual boot)

02h = Bottom boot device with WP protect (Bottom boot)

03h = Top boot device with WP protect (Top boot)

04h = Uniform, bottom WP protect (Uniform bottom boot)

05h = Uniform, top WP protect (Uniform top boot)

06h = WP Protect for all sectors

0004h (Bottom)

0005h (Top)

(SA) + 004Fh

(SA) + 0050h

07h = Uniform, top or bottom WP protect

Program Suspend

00 = Not supported

01 = Supported

0001h

Unlock Bypass

(SA) +0051h

(SA) + 0052h

0000h

0009h

00 = Not supported

01 = Supported

Secured silicon sector (Customer OTP area) size 2^N(bytes)

Software features

bit 0: Status Register polling (1 = Supported, 0 = Not supported)

bit 1: DQ polling (1 = Supported, 0 = Not supported)

bit 2: New Program Suspend/Resume commands

(1 = Supported, 0 = Not supported)

bit 3: Word programming (1 = Supported, 0 = Not supported)

bit 4: Bit-field programming (1 = Supported, 0 = Not supported)

bit 5: Autodetect programming (1 = Supported, 0 = Not supported)

bit 6: RFU

bit 7: Multiple writes per line (1 = Supported, 0 = Not supported)

Page Size = 2^Nbytes

Erase Suspend timeout maximum < 2^N(µs)

Program Suspend timeout maximum < 2^N(µs)

Embedded hardware reset timeout maximum < 2^N(µs)

Reset with reset pin

Non-embedded hardware reset timeout maximum < 2^N(µs)

Power-on reset

(SA) + 0053h

008Fh

(SA) + 0054h

(SA) + 0055h

(SA) + 0056h

0005h

0006h

(SA) + 0078h

(SA) + 0079h

0006h

0009h

Datasheet

19

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Package diagram

11

Package diagram

11.1

LSH064 — 64-ball fortified ball grid array, 13 x 11 mm

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

NOM.

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

-

MAX.

1.40

-

A

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

A1

D

0.40

-

13.00 BSC

E

11.00 BSC

7.00 BSC

8

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

8

64

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

0.60

b

0.50

0.70

eD

eE

SD

SE

1.00 BSC

0.50 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

002-13243 **

Figure 5

64-ball FBGA (13.0 × 11.0 × 1.4 mm) package outline, 002-13243

Datasheet

20

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Ordering information

12

Ordering information

12.1

Recommended combinations

Recommended combinations table below list various configurations planned to be available in volume. Table 13

will be updated as new combinations are released. Contact your local Infineon sales representative to confirm

availability of specific configuration not listed or to check on newly released combinations.

Table 13

S29GL-S valid combinations

Ordering part number

(yy = Model number,

x = Packing type)

Speed

(ns)

Package and

temperature

Model

Base OPN

Packing type

number

S70GL02GS11FHI01x

S70GL02GS11FHI02x

S70GL02GS11FHV01x

S70GL02GS11FHV02x

110

120

01, 02

V1, V2

[18]

[19]

S70GL02GS

FHI, FHV

0, 3

S70GL02GS12FHIV1x

S70GL02GS12FHIV2x

S70GL02GS12FHVV1x

S70GL02GS12FHVV2x

Table 14 lists configurations that are automotive grade / AEC-Q100 qualified and are planned to be available in

volume. The table will be updated as new combinations are released. Consult your local sales representative to

confirm availability of specific combinations and to check on newly released combinations.

Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.

Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade

products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full

compliance with ISO/TS-16949 requirements.

AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require

ISO/TS-16949 compliance.

Table 14

Valid combinations — automotive grade / AEC-Q100

Ordering part number

(yy = Model Number,

x = Packing Type)

Speed

(ns)

Package and

temperature

Model

Base OPN

Packing type

number

S70GL02GS11FHA01x

S70GL02GS11FHA02x

S70GL02GS11FHB01x

S70GL02GS11FHB02x

110

120

01, 02

V1, V2

[18]

[19]

S70GL02GS

FHA, FHB

0, 3

S70GL02GS12FHAV1x

S70GL02GS12FHAV2x

S70GL02GS12FHBV1x

S70GL02GS12FHBV2x

Notes

18.BGA package marking omits leading “S70” and packing type designator from ordering part number.

19.Packing Type “0” is standard option.

Datasheet

21

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Ordering information

The ordering part number is formed by a valid combination of the following:

S70GL02GS

12

F

H

I

01

0

Packing type

0 = Tray (standard)

3 = 13” Tape and reel

Model number (V_IOrange, protection when WP# = V_IL

)

01 = V_IO= V_CC= 2.7 V to 3.6 V, highest address sector protected

02 = V_IO= V_CC= 2.7 V to 3.6 V, lowest address sector protected

V1 = V_IO= 1.65 V to V_CC, V_CC= 2.7 V to 3.6 V, highest address sector protected

V2 = V_IO= 1.65 V to V_CC, V_CC= 2.7 V to 3.6 V, lowest address sector protected

Temperature range

I = Industrial (–40°C to +85°C)

A = Automotive, AEC-Q100 grade 3 (–40°C to +85°C)

B = Automotive, AEC-Q100 grade 2 (–40°C to +105°C)

V = Automotive - In cabin (–40°C to +105°C)

Package materials set

H = Low Halogen, Pb-free

Package type

F = Fortified ball grid array, 1.0 mm pitch package (LSH064), 11 mm × 13 mm

Speed option

11 = 110 ns

12 = 120 ns

Device number / description

S70GL02GS

3.0 Volt-Only, 2048 Megabit (128M × 16-bit) Page-Mode flash memory

Manufactured on 65-nm MIRRORBIT™ process technology

Datasheet

22

001-98296 Rev. *K

2022-09-09

2 Gbit (256 MB) GL-T MIRRORBIT™ Flash

Parallel, 3.0 V

Revision history

Document

Date of release

version

Description of changes

Spansion Publication Number: S70GL-S_00

Initial release.

**

2011-05-19

Performance Characteristics: Updated Typical Program and Erase Rates

Ordering Information: Updated model number description of V1 and V2

DC Characteristics: Modified Note 3

*A

2011-07-08

Distinctive Characteristics: Cosmetic changes

Ordering Information: Updated

*B

*C

2011-09-23

2011-12-15

CFI Device Geometry Definition: Data at (SA) + 002Eh modified

Global: Data sheet status changed from Preliminary to Full Production

Performance Characteristics: Updated Sector Erase time

Figure: 64-ball Fortified Ball Grid Array: Added notes

BGA Package Capacitance: Updated

*D

*E

2014-06-27

2015-08-13

Global: Added –40°C to +105°C temperature range

Updated to Cypress template.

General Description: Updated Cypress Document Number as “001-98285” in

the table.

Distinctive Characteristics: Updated link to S29GL01GS datasheet.

Updated to new template.

*F

2016-03-04

Updated Document Title to read as “S70GL02GS 2 Gbit (256 MB) GL-T

MIRRORBIT™ Flash”.

*G

*H

2016-07-08

2017-05-31

Updated to new template.

Updated Cypress Logo and Copyright.

Updated Ordering information:

Updated description.

*I

2017-06-15

2017-08-09

Added Table 14.

Updated details under “Temperature range” in valid combination.

Updated Ordering information:

Updated details under “Device number/description” in valid combination.

Added Second die access.

*J

Updated Document Title to read as “S70GL02GS, 2 Gbit (256 MB) GL-T

MIRRORBIT™ Flash Parallel, 3.0 V”.

Updated Distinctive characteristics:

Updated hyperlinks.

Updated Electrical specifications:

*K

2022-09-09

Added Thermal resistance.

Updated Package diagram:

Updated LSH064 — 64-ball fortified ball grid array, 13 x 11 mm:

Replaced existing spec with 002-13243 **.

Migrated to Infineon template.

Datasheet

23

001-98296 Rev. *K

2022-09-09

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

For further information on the product, technology,

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

Edition 2022-09-09

Published by

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement of

intellectual property rights of any third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Except as otherwise explicitly approved by Infineon

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Technologies in

authorized

a written document signed by

Do you have a question about this

document?

Go to www.infineon.com/support

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference

001-98296 Rev. *K

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	S70GL02GS12FHIV23
厂家：	Infineon
描述：	High Performance Page Mode 内存集成电路闪存
文件：	总24页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S70GL02GS12FHIV23 [INFINEON]

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