S70KL1283DPBHB020 [INFINEON]
128MBit 3.0 V Automotive (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA;
| 型号： | S70KL1283DPBHB020 |
| 厂家： | 
Infineon |
| 描述： | 128MBit 3.0 V Automotive (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA |
| 文件： | 总63页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S70KL1283, S70KS1283
128 Mb HYPERRAM™ self-refresh DRAM
(PSRAM)
Octal xSPI, 1.8 V/3.0 V
Features
• Interface
- xSPI (Octal) interface
- 1.8 V / 3.0 V interface support
• Single ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• Input during write transactions as write data mask
- Optional DDR center-aligned read strobe (DCARS)
• During read transactions RWDS is offset by a second clock, phase shifted from CK
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• Performance, power, and packages
- 200-MHz maximum clock rate
- DDR transfers data on both edges of the clock
- Data throughput up to 400 MBps (3,200 Mbps)
- Configurable burst characteristics
• Linear burst
• Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
• Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear burst across die boundary is
not supported.
- Configurable output drive strength
- Power modes[1]
• Hybrid Sleep mode
• Deep Power Down
- Array refresh
• Partial memory array (1/8, 1/4, 1/2, and so on)
• Full
Note
1. 128-Mb HYPERRAM™ is a stacked-die chip using two 64-Mb dice. Only one die, at a time, can be programmed
to enter hybrid sleep mode or deep power down mode.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Performance summary
- Package
• 24-ball FBGA
- Operating temperature range
• Industrial (I): –40°C to +85°C
• Industrial Plus (V): –40°C to +105°C
• Automotive, AEC-Q100 Grade 3: –40°C to +85°C
• Automotive, AEC-Q100 Grade 2: –40°C to +105°C
• Technology
- 38-nm DRAM
Performance summary
Maximum read rates
Read transaction timings
Value and unit
200 MHz
Maximum clock rate at 1.8 V VCC/VCC
Maximum clock rate at 3.0 V VCC/VCC
Q
Q
200 MHz
Maximum access time, (tACC
)
35 ns
Typical current consumption
Maximum current consumption
Value and unit
50 mA
Burst read or write (linear burst at 200 MHz, 1.8 V)
Burst read or write (linear burst at 200 MHz, 3.0 V)
Standby (CS# = VCC = 3.6 V, 105°C)
60 mA
750 µA
Deep power down (CS# = VCC = 3.6 V, 105°C)
Standby (CS# = VCC = 2.0 V, 105°C)
360 µA
660 µA
Deep power down (CS# = VCC = 2.0 V, 105°C)
330 µA
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Logic block diagram
Logic block diagram
64 Mb HYPERRAM™ - Die 0
CS#
CK/CK#
RWDS
CS#
CK/CK#
RWDS
Memory
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
DQ[7:0]
RESET#
Data Path
64 Mb HYPERRAM™ - Die 1
HyperRAM 2
CS#
CK/CK#
RWDS
Memory
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
RESET#
RESET#
Data Path
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Table of contents
Table of contents
Features ...........................................................................................................................................1
Performance summary ......................................................................................................................2
Logic block diagram ..........................................................................................................................3
Table of contents...............................................................................................................................4
1 General description.........................................................................................................................6
1.1 xSPI (Octal) interface ..............................................................................................................................................6
2 Product overview ...........................................................................................................................9
2.1 xSPI (Octal) interface ..............................................................................................................................................9
3 Signal description.........................................................................................................................10
3.1 Input/output summary.........................................................................................................................................10
4 xSPI (Octal) transaction details......................................................................................................11
4.1 Command/address/data bit assignments...........................................................................................................12
4.2 RESET ENABLE transaction ..................................................................................................................................13
4.3 RESET transaction.................................................................................................................................................13
4.4 READ ID transaction..............................................................................................................................................14
4.5 DEEP POWER DOWN transaction .........................................................................................................................15
4.6 READ transaction ..................................................................................................................................................16
4.7 WRITE transaction.................................................................................................................................................16
4.8 WRITE ENABLE transaction ..................................................................................................................................17
4.9 WRITE DISABLE transaction .................................................................................................................................17
4.10 READ ANY REGISTER transaction .......................................................................................................................18
4.11 WRITE ANY REGISTER transaction......................................................................................................................18
4.12 Data placement during memory READ/WRITE transactions ............................................................................19
4.13 Data placement during register READ/WRITE transactions..............................................................................20
5 Memory space ..............................................................................................................................21
5.1 xSPI (Octal) interface ............................................................................................................................................21
5.2 Density and row boundaries ................................................................................................................................21
6 Register space access ....................................................................................................................22
6.1 xSPI (Octal) interface ............................................................................................................................................22
6.2 Device Identification Registers.............................................................................................................................23
6.3 Device Configuration Registers ............................................................................................................................24
6.3.1 Configuration Register 0 (CR0) ..........................................................................................................................24
6.3.2 Configuration Register 1....................................................................................................................................28
7 Interface states ............................................................................................................................30
8 Power conservation modes............................................................................................................31
8.1 Interface standby..................................................................................................................................................31
8.2 Active clock stop ...................................................................................................................................................31
8.3 Hybrid sleep ..........................................................................................................................................................32
8.4 Deep power down.................................................................................................................................................33
9 Electrical specifications.................................................................................................................34
9.1 Absolute maximum ratings ..................................................................................................................................34
9.2 Input signal overshoot..........................................................................................................................................34
9.3 Latch-up characteristics .......................................................................................................................................35
9.4 Operating ranges ..................................................................................................................................................35
9.4.1 Temperature ranges ..........................................................................................................................................35
9.4.2 Power supply voltages.......................................................................................................................................35
9.5 DC characteristics .................................................................................................................................................36
9.5.1 Capacitance characteristics ..............................................................................................................................40
9.5.2 Thermal resistance ............................................................................................................................................40
9.6 Power-up initialization .........................................................................................................................................41
9.7 Power down ..........................................................................................................................................................42
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Table of contents
9.8 Hardware reset......................................................................................................................................................43
9.9 Software reset .......................................................................................................................................................44
10 Timing specifications ..................................................................................................................45
10.1 Key to switching waveforms...............................................................................................................................45
10.2 AC test conditions ...............................................................................................................................................45
10.3 CLK characteristics .............................................................................................................................................47
10.4 AC characteristics................................................................................................................................................48
10.4.1 Read transactions ............................................................................................................................................48
10.4.2 Write transactions............................................................................................................................................50
11 Physical interface .......................................................................................................................51
11.1 FBGA 24-ball 5 x 5 array footprint ......................................................................................................................51
11.2 Package diagram ................................................................................................................................................52
12 DDR center-aligned read strobe (DCARS) functionality ...................................................................53
12.1 xSPI HYPERRAM™ products with DCARS signal description .............................................................................53
12.2 HYPERRAM™ products with DCARS — FBGA 24-ball, 5 x 5 array footprint .......................................................55
12.3 HYPERRAM™ memory with DCARS timing .........................................................................................................56
13 Ordering information ..................................................................................................................58
13.1 Ordering part number.........................................................................................................................................58
13.2 Valid combinations .............................................................................................................................................59
13.3 Valid combinations – Automotive grade / AEC-Q100........................................................................................59
14 Acronyms ...................................................................................................................................60
15 Document conventions................................................................................................................61
15.1 Units of measure .................................................................................................................................................61
Revision history ..............................................................................................................................62
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
1
General description
The Infineon 128-Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with xSPI (Octal) interface. The
DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the
refresh operations on the DRAM array when the memory is not being actively read or written by the xSPI interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the
host as though the memory uses static cells that retain data without refresh. Hence, the memory is more
accurately described as pseudo static RAM (PSRAM).
Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host
limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The
host must confine the duration of transactions and allow additional initial access latency, at the beginning of a
new transaction, if the memory indicates a refresh operation is needed. The dual-die, 128-Mb HYPERRAM™ chip
supports data transactions with additional (2X) latency only.
1.1
xSPI (Octal) interface
xSPI (Octal) is a SPI-compatible low signal count, DDR interface supporting eight I/Os. The DDR protocol in xSPI
(Octal) transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on
xSPI (Octal) consists of a series of 16-bit wide, one clock cycle data transfers at the internal RAM array with two
corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are
LV-CMOS compatible. Device are available as 1.8 V VCC/VCCQ or 3.0 V VCC/VCCQ (nominal) for array (VCC) and I/O
buffer (VCCQ) supplies, through different ordering part number (OPN).
Each transaction on xSPI (Octal) must include a command whereas address and data are optional. The
transactions are structures as follows:
• Each transaction begins with CS# going LOW and ends with CS# returning HIGH.
• The serial clock (CK) marks the transfer of each bit or group of bits between the host and memory. All transfers
occur on every CK edge (DDR mode).
• Each transaction has a 16-bit command which selects the type of device operation to perform. The 16-bit
command is based on two 8-bit opcodes. The same 8-bit opcode is sent on both edges of the clock.
• A command may be stand-alone or may be followed by address bits to select a memory location in the device
to access data.
• Read transactions require a latency period after the address bits and can be zero to several CK cycles. CK must
continue to toggle during any read transaction latency period. During the command and address parts of a
transaction, the memory indicates that an additional latency period is needed for a required refresh time (tRFH
by driving the RWDS signal to the HIGH state.
)
• Write transactions to registers do not require a latency period.
• Write transactions to the memory array require a latency period after the address bits and can be zero to several
CK cycles. CK must continue to toggle during any write transaction latency period. During the command and
address parts of a transaction, the memory indicates that an additional latency period is needed for a required
refresh time (tRFH) by driving the RWDS signal to the HIGH state.
• In all transactions, command and address bits are shifted in the device with the most significant bits (MSb) first.
The individual data bits within a data byte are shifted in and out of the device MSb first as well. All data bytes
are transferred with the lowest address byte sent out first.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 1
xSPI (Octal) command only transaction (DDR)[2]
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
Write Data
Figure 2
xSPI (Octal) write with no latency transaction (DDR) (Register writes)[3]
Notes
2. The initial latency “low = 1x latency count” is not applicable in dual-die, 128 Mb HYPERRAM™.
3. Write with no latency transaction is used for register writes only.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
General description
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 3
xSPI (Octal) write with 2X latency transaction (DDR) (Memory array writes)[4, 5, 6]
CS#
CK#, CK
Latency C
ount (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 4
xSPI (Octal) read with 2X latency transaction (DDR) (All reads)[4, 7]
Notes
4. The initial latency “low = 1x latency count” is not applicable in dual-die, 128 Mb HYPERRAM™.
5. RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then driven by the host
for data masking.
6. Data DinA and DinA+2 are masked.
7. RWDS is driven by HYPERRAM™ during command and address cycles for 2X latency and then driven again
phase aligned with data.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Product overview
2
Product overview
The 128-Mb HYPERRAM™ device is 1.8 V or 3.0 V array and I/O, synchronous self-refresh dynamic RAM (DRAM). The
HYPERRAM™ device provides an xSPI (Octal) slave interface to the host system. The xSPI (Octal) interface has an
8-bit (1 byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read transactions
provide 16 bits of data during each clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data
from each clock cycle (8 bits on each clock edge).
RESET#
V
CC
V
Q
CC
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
Q
SS
Figure 5
xSPI (Octal) HYPERRAM™ interface[8]
2.1
xSPI (Octal) interface
Read and write transactions require three clock cycles to define the target row/column address and then an initial
access latency of tACC. During the CA part of a transaction, the memory indicates an additional latency for a
required refresh time (tRFH) by driving the RWDS signal to the HIGH state. During a read (or write) transaction,
after the initial data value has been output (or input), additional data can be read from (or written to) the row on
subsequent clock cycles in either a wrapped or linear sequence. When configured in linear burst mode, the device
will automatically fetch the next sequential row from the memory array to support a continuous linear burst.
Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows for
a linear sequential burst operation that can provide a sustained data rate of 400 MBps (1 byte (8 bit data bus) * 2
(data clock edges) * 200 MHz = 400 MBps).
Note
8. CK# is used in differential clock mode, but optional.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Signal description
3
Signal description
3.1
Input/output summary
The xSPI (Octal) HYPERRAM™ signals are shown in Table 1. Active Low signal names have a hash symbol (#) suffix.
Table 1
Symbol
I/O Summary[10]
Type
Description
Chip Select. Bus transactions are initiated with a HIGH to LOW
transition. Bus transactions are terminated with a Low to High
transition. The master device has a separate CS# for each slave.
CS#
Master output,
slave input
Differential Clock. Command, address, and data information is output
with respect to the crossing of the CK and CK# signals. Use of differential
clock is optional.
CK, CK#[9]
DQ[7:0]
Single Ended Clock. CK# is not used, only a single ended CK is used. The
clock is not required to be free-running.
Data Input/Output. Command, address, and data information is trans-
ferred on these signals during read and write transactions.
Read-Write Data Strobe. During the command/address portion of all
bus transactions RWDS is a slave output and indicates whether
additional initial latency is required. Slave output during read data
transfer, data is edge aligned with RWDS. Slave input during data
transfer in write transactions to function as a data mask.
The dual-die, 128-Mb HYPERRAM™ chip supports data transactions with
additional (2X) latency only.
Input/output
RWDS
Hardware RESET. When LOW, the slave device will self initialize and
return to the standby state. RWDS and DQ[7:0] are placed into the
HIGH-Z state when RESET# is LOW. The slave RESET# input includes a
weak pull-up, if RESET# is left unconnected it will be pulled up to the
HIGH state.
Master output, slave
input, internal pull-up
RESET#
VCC
Array Power.
VCC
VSS
Q
Input/Output Power.
Array Ground.
Input/Output Ground.
Reserved for Future Use. May or may not be connected internally, the
signal/ball location should be left unconnected and unused by PCB
routing channel for future compatibility. The signal/ball may be used by
a signal in the future.
Power supply
No connect
VSSQ
RFU
Notes
9. CK# is used in differential clock mode, but optional connection. Tie the CK# input pin to either VccQ or VssQ
if not connected to the host controller, but do not leave it floating.
10.Optional DCARS pinout and pin description are outlined in section “DDR center-aligned read strobe
(DCARS) functionality” on page 53.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4
xSPI (Octal) transaction details
The xSPI (Octal) master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins toggling
while CA words are transferred.
For memory read and write transactions, the xSPI (Octal) master then continues clocking for a number of cycles
defined by the latency count setting in Configuration Register 0 (register write transactions do not require any
latency count). The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is
LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an additional
latency count is inserted. Once these latency clocks have been completed the memory starts to simultaneously
transition the RWDS and output the target data. The dual-die, 128-Mb HYPERRAM™ chip supports data
transactions with additional (2X) latency only.
During the read data transfers, read data is output edge aligned with every transition of RWDS. Data will continue
to be output as long as the host continues to transition the clock while CS# is LOW. Note that burst transactions
should not be so long as to prevent the memory from doing distributed refreshes.
During the write data transfers, write data is center-aligned with the clock edges. The first byte of data in each
word is captured by the memory on the rising edge of CK and the second byte is captured on the falling edge of
CK. RWDS is driven by the host master interface as a data mask. When data is being written and RWDS is HIGH the
byte will be masked and the array will not be altered. When data is being written and RWDS is LOW the data will
be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor
the HYPERRAM™ device are able to indicate a need for latency within the data transfer portion of a write
transaction. The acceptable write data burst length setting is also shown in Configuration Register 0.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential
manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the
burst beyond the last address will provide data from the beginning of the address range. Read transfers can be
ended at any time by bringing CS# HIGH when the clock is idle. The clock is not required to be free-running. The
clock may remain idle while CS# is HIGH.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.1
Command/address/data bit assignments
Table 2
Command set [11, 12, 13, 14, 15]
Address
(bytes)
Latency
Data
Command
Code
CA-Data
Prerequisite
cycles
(bytes)
Software Reset
RESET ENABLE
RESET
0x66
0x99
8-0-0
8-0-0
0
0
0
0
0
0
RESET ENABLE
Identification
READ ID[11]
Power Modes
DEEP POWER DOWN
Read Memory Array
READ (DDR)
Write Memory Aray
WRITE (DDR)
0x9F
0xB9
0xEE
0xDE
8-8-8
8-0-0
8-8-8
8-8-8
4 (0x00)
3–7
0
4
0
4
4
0
3–7
3–7
1 to
1 to
WRITE ENABLE
WRITE ENABLE
Write Enable/Disable
WRITE ENABLE
WRITE DISABLE
Read Registers
READ ANY REGISTER
Write Registers
WRITE ANY REGISTER
0x06
0x04
8-0-0
8-0-0
0
0
0
0
0
0
0x65
0x71
8-8-8
8-8-8
4
4
3–7
0
2
2
Notes
11.The two identification registers contents are read together - identification 0 followed by identification 1.
12.Write Enable provides protection against inadvertent changes to memory or register values. It sets the in-
ternal write enable latch (WEL) which allows write transactions to execute afterwards.
13.Write Disable can be used to disable write transactions from execution. It resets the internal write enable
latch (WEL).
14.The WEL latch stays set to ‘1’ at the end of any successful memory write transaction. After a power down /
power up sequence, or a hardware/software reset, WEL latch is cleared to ‘0’.
15.The internal WEL latch is cleared to ‘0’ at the end of any successful register write transaction.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.2
RESET ENABLE transaction
The RESET ENABLE transaction is required immediately before a RESET transaction. Any transaction other than
RESET following RESET ENABLE will clear the reset enable condition and prevent a later RESET transaction from
being recognized.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 6
RESET ENABLE transaction (DDR)[16]
4.3
RESET transaction
The RESET transaction immediately following a RESET ENABLE will initiate the software reset process.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 7
RESET transaction (DDR)[16]
Note
16.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
4.4
READ ID transaction
The READ ID transaction provides read access to Device Identification Registers 0 and 1. The registers contain the
manufacturer’s identification along with device identification. The read data sequence is as follows.
Table 3
READ ID data sequence
Address space
Byte order
Byte position
Word data bit
DQ
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
A
Register 0
Big-endian
4
3
2
1
B
A
B
0
15
14
13
12
11
10
9
8
7
6
5
Register 1
Big-endian
4
3
2
1
0
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
xSPI (Octal) transaction details
CS#
CK#, CK
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
IDRG 0
[15:8]
IDRG 0
[7:0]
IDRG 1
[15:8]
IDRG 1
[7:0]
0x00
0x00
0x00
0x00
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 8
READ ID with 2X latency transaction (DDR) [17]
4.5
DEEP POWER DOWN transaction
DEEP POWER DOWN transaction brings the device into deep power down state which is the lowest power
consumption state. Writing a ‘0’ to CR0[15] will also bring the device in deep power down State. All register
contents are lost in deep power down state and the device powers-up in its default state.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 9
DEEP POWER DOWN transaction (DDR)[17]
Note
17.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™.
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xSPI (Octal) transaction details
4.6
READ transaction
The READ transaction reads data from the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency C
ount (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 10
READ with 2X latency transaction (DDR)[18, 19]
4.7
WRITE transaction
The WRITE transaction writes data to the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
WRITE ENABLE transaction which sets the WEL latch must be executed before the first WRITE. The WEL latch stays
set to ‘1’ at the end of any successful memory write transaction. It must be reset by WRITE DISABLE transaction
to prevent any inadvertent writes to the memory array.
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 11
WRITE with 2X latency transaction (DDR)[18, 19, 20]
Notes
18.RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then is driven again
phase aligned with data.
19.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™.
20.Data DinA and DinA+2 are masked.
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xSPI (Octal) transaction details
4.8
WRITE ENABLE transaction
The WRITE ENABLE transaction must be executed prior to any transaction that modifies data either in the
memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 12
WRITE ENABLE transaction (DDR)[21]
4.9
WRITE DISABLE transaction
The WRITE DISABLE transaction inhibits writing data either in the memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 13
WRITE DISABLE transaction (DDR)[21]
Note
21.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™.
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xSPI (Octal) transaction details
4.10
READ ANY REGISTER transaction
The READ ANY REGISTER transaction reads all the device registers. It has a latency requirement (dummy cycles)
which allows the device’s internal circuitry enough time to access the addressed register location. During these
latency cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 14
READ ANY REGISTER with 2X latency transaction (DDR)[22, 23]
4.11
WRITE ANY REGISTER transaction
The WRITE ANY REGISTER transaction writes to the device registers. It does not have a latency requirement
(dummy cycles).
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
Write Data
Figure 15
xSPI (Octal) write with no latency transaction (DDR) (Register writes)[23, 24, 25]
Notes
22.RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then driven again phase
aligned with data.
23.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™.
24.Write with no latency transaction is used for register writes only.
25.Data mask on RWDS is not supported.
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xSPI (Octal) transaction details
4.12
Data placement during memory READ/WRITE transactions
Data placement during memory read/write is dependent upon the host. The device will output data (read) as it
was written in (write). Hence both big endian and little endian are supported for the memory array.
Table 4
Data placement during memory READ and WRITE
Address
space
Byte
Byte
Word
DQ
Bit order
order
position data bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
Big-endian
B
When data is being accessed in memory space:
The first byte of each word read or written is the
“A” byte and the second is the “B” byte.
The bits of the word within the A and B bytes
depend on how the data was written. If the word
lower address bits 7–0 are written in the A byte
position and bits 15–8 are written into the B byte
position, or vice versa, they will be read back in
the same order.
Memory
So, memory space can be stored and read in
either little-endian or big-endian order.
A
Little-endian
B
10
9
8
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xSPI (Octal) transaction details
4.13
Data placement during register READ/WRITE transactions
Data placement during register read/write is big endian.
Table 5
Data placement during register READ/WRITE transactions
Address
space
Byte
Byte
Word
DQ
Bit order
order
position data bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When data is being accessed in register space:
During a read transaction on the xSPI (Octal) two
bytes are transferred on each clock cycle. The
upper order byte A (Word[15:8]) is transferred
between the rising and falling edges of RWDS
(edge aligned). The lower order byte B
(Word[7:0]) is transferred between the falling
and rising edges of RWDS.
During a write, the upper order byte A
(Word[15:8]) is transferred on the CK rising edge
and the lower order byte B (Word[7:0]) is
transferred on the CK falling edge.
A
Big-
endian
Register
Therefore, register space is always read and
written in big-endian order because registers
have device dependent fixed bit location and
meaning definitions.
B
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Memory space
5
Memory space
5.1
xSPI (Octal) interface
Table 6
Memory space address map (Byte based - 8 bits with least significant bit A(0) always set to
‘0’)
System byte
Unit type
Count
Address bits
Notes
address bits
A22–A9
Rows within 128-Mb device
Rows within 64-Mb device
Rows within 64-Mb device
Row
16384 (rows)
8192 (rows)
8192 (rows)
1 (row)
35–22
22-10
22 - 10
9–4
A22–A10
A22 - A10
A9–A4
512 (16-bit word) or 1 KB
16 bytes (8 words)
A0 always set to ‘0’
Half-page
16 (byte addresses)
A3–A0
3–0
5.2
Density and row boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used
for the row and column addresses as indicated by the row address bit count and column address bit count fields
in the ID0 register. For example: a 64-Mb HYPERRAM™ device has 10 column address bits and 13 row address bits
for a total of 23 address bits (byte address) = 223 = 8MB (4M words). The 10 column address bits indicate that each
row holds 210 = 512 words = 1KB. The row address bit count indicates there are 8196 rows to be refreshed within
each array refresh interval. The row count is used in calculating the refresh interval.
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Register space access
6
Register space access
6.1
xSPI (Octal) interface
Table 7
Register space address map (address bit A0 always set to ‘0’)
Registers
Address (Byte addressable)
Identification Registers 0 (ID0[15:0]) - Die 0
0x00000000
Identification Registers 0 (ID0[15:0]) - Die 1
Identification Registers 1 (ID1[15:0]) - Die 0
Identification Registers 1 (ID1[15:0]) - Die 1
Configuration Registers 0 (ID0[15:0]) - Die 0
Configuration Registers 0 (ID0[15:0]) - Die 1
Configuration Registers 1 (ID1[15:0]) - Die 0
Configuration Registers 1 (ID1[15:0]) - Die 1
0x00400000
0x00000002
0x00400002
0x00000004
0x00400004
0x00000006
0x00400006
Die Manufacture Information Register
(Registers 0 to Register 17) - die 0
Die Manufacture Information Register
(Registers 0 to Register 17) - die 1
0x00000008, 0x0000000A to 0x0000002A
0x00400008, 0x0040000A to 0x0040002A
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Register space access
6.2
Device Identification Registers
There are two read-only, non-volatile, word registers, that provide information on the device selected when CS#
is LOW. The device information fields identify:
• Manufacturer
• Type
• Density
- Row address bit count
- Column address bit count
Refresh Type
Table 8
Bits
Identification Register 0 (ID0) bit assignments
Function
Settings (Binary)
00b - Die 0
01b - Die 1
[15:14]
Reserved
13
13
Reserved
Reserved
0 - Default
0 - Default
00000 - One row address bit
...
[12:8]
Row address bit count 11111 - Thirty-two row address bits
...
01100 - 64 Mb - Thirteen row address bits (default)
0000 - One column address bits
...
Column address bit
count
[7:4]
[3:0]
1000 - Nine column address bits (default)
...
1111 - Sixteen column address bits
0000 - Reserved
0001 - Cypress (default)
0010 to 1111 - Reserved
Manufacturer
Table 9
Identification Register 1 (ID1) bit assignments
Function
Bits
Settings (Binary)
[15:4]
Reserved
0000_0000_0000 (default)
0001 - HYPERRAM™ 2.0
0000, 0010 to 1111 - Reserved
[3:0]
Device type
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6.3
Device Configuration Registers
Configuration Register 0 (CR0)
6.3.1
Configuration Register 0 (CR0) is used to define the power state and access protocol operating conditions for the
HYPERRAM™ device. Configurable characteristics include:
• Wrapped burst length (16, 32, 64, or 128 byte aligned and length data group)
• Wrapped burst type
- Legacy wrap (sequential access with wrap around within a selected length and aligned group)
- Hybrid wrap (legacy wrap once then linear burst at start of the next sequential group)
• Initial latency
• Variable latency
- Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the
memory will always indicate a refresh latency and delay the read data transfer accordingly. If variable latency
is selected, latency for a refresh is only added when a refresh is required at the same time a new transaction
is starting.
• Output drive strength
• Deep power down (DPD) mode
Table 10
CR0 bit
Configuration Register 0 (CR0) bit assignments
Function
Settings (Binary)
1 - Normal operation (default). HYPERRAM™ will automatically set this
value to ‘1’ after DPD exit
Deep power down
enable
0 - Writing 0 causes the device to enter deep power down
[15]
Only one die of the 128-Mb stack-die HYPERRAM™ can be programmed
to enter DPD mode at a time.
000 - 34 (default)
001 - 115
010 - 67
011 - 46
[14:12]
[11:8]
Drive strength
Reserved
100 - 34
101 - 27
110 - 22
111 - 19
1 - Reserved (default)
Reserved for future use. When writing this register, these bits should be
set to 1 for future compatibility.
0000 - 5 clock latency @ 133 Max frequency
0001 - 6 clock latency @ 166 Max frequency
0010 - 7 clock latency @ 200 MHz/166 MHz Max frequency (default)
0011 - Reserved
[7:4]
Initial latency
0100 - Reserved
...
1101 - Reserved
1110 - 3 clock latency @ 85 Max frequency
1111 - 4 clock latency @ 104 Max frequency
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Register space access
Table 10
CR0 bit
Configuration Register 0 (CR0) bit assignments (continued)
Function
Settings (Binary)
0 - Reserved
1 - Fixed 2 times initial latency (default)
The 128-Mb dual-die stack only supports fixed latency. In fixed latency
mode, when CS# asserted LOW,
[3]
[2]
Fixed latency enable
1. The RWDS signal of each die of dual-die 128-Mb will always drive to
HIGH during CA phase.
2. The RWDS signal of the non-selected die of dual-die 128-Mb will
always drive to Hi-Z after CA phase.
3. The RWDS signal of the selected die of dual-die 128-Mb will drive to L
after CA phase.
0: Wrapped burst sequence to follow hybrid burst sequencing
1: Wrapped burst sequence in legacy wrapped burst manner (default)
Hybrid burst enable
This bit setting is effective only when the “burst type” bit in the
command/address register is set to ‘0’, i.e. CA[45] = ‘0’; otherwise, it is
ignored.
00 - 128 bytes
01 - 64 bytes
[1:0]
Burst length
10 - 16 bytes
11 - 32 bytes (default)
6.3.1.1
Wrapped burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching
the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes
alignment and length. During wrapped transactions, access starts at the CA selected location within the group,
continues to the end of the configured word group aligned boundary, then wraps around to the beginning
location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical
word first instruction or data cache line fill read accesses. Wrapped burst across die boundary is not supported.
6.3.1.2
Hybrid burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing
to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the
transfer is ended by returning CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the
beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access.
The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in
to the cache while the first line is being processed. Hybrid burst across die boundary is not supported.
Table 11
Bit
CR0[2] control of wrapped burst sequence
Default value
Setting details
Hybrid burst enable
CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing
CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner
CR0[2]
1b
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Register space access
Table 12
Example wrapped burst sequences (Addressing)
Wrap
Start
address
(Hex)
Burst type boundary
(Bytes)
Sequence of byte addresses (hex) of data words
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28,
29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B,
128 wrap
once then
linear
Hybrid 128
XXXXXX03 3C, 3D, 3E, 3F, 00, 01, 02
(wrap complete, now linear beyond the end of the initial 128 byte
wrap group)
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
28, 2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00
64 wrap
once then
linear
Hybrid 64
Hybrid 64
XXXXXX02 (wrap complete, now linear beyond the end of the initial 64 byte
wrap group)
40, 42, 44, 46, 48, 4A, 4C, 4E, 50, 52, ...
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24,
64 wrap
once then
linear
26, 28, 2A, 2C
XXXXXX2E
(wrap complete, now linear beyond the end of the initial 64 byte
wrap group)
40, 42, 44, 46, 48, 4A, 4B, 4C, 4D, 4E, 4F, 50, 52, ...
02, 04, 06, 08, 0A, 0C, 0E, 00
16 wrap
once then
linear
(wrap complete, now linear beyond the end of the initial 16 byte
Hybrid 16
Hybrid 16
Hybrid 32
XXXXXX02
wrap group)
10, 12, 14, 16, 18, 1A, ..
0C, 0E, 00, 02, 04, 06, 08, 0A
16 wrap
once then
linear
(wrap complete, now linear beyond the end of the initial 16 byte
XXXXXX0C
wrap group)
10, 12, 14, 16, 18, 1A, ...
0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08
32 wrap
once then
linear
(wrap complete, now linear beyond the end of the initial 32 byte
XXXXXX0A
wrap group)
20, 22, 24, 26, 28, 2A, ...
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
Wrap 64
Wrap 64
64
64
XXXXXX02
28, 2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00, ...
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
XXXXXX2E 00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24,
26, 28, 2A, 2C, 2E, 30, ….
Wrap 16
Wrap 16
Wrap 32
Linear
16
16
32
XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 00, ...
XXXXXX0C 0C, 0E, 00, 02, 04, 06, 08, 0A, ...
XXXXXX0A 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08, ...
Linear burst XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, ...
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Register space access
6.3.1.3
Initial latency
Memory space read and write transactions or register space read transactions require some initial latency to
open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC
depends on the clock input frequency can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of
clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of
200 MHz prior to the host system setting a lower initial latency value that may be more optimal for the system.
In the event a distributed refresh is required at the time a memory space read or write transaction or register
space read transaction begins, the RWDS signal goes High during the CA to indicate that an additional initial
latency is being inserted to allow a refresh operation to complete before opening the selected row.
Register space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA
period. The level of RWDS during the CA period does not affect the placement of register data immediately after
the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed
in the memory array in parallel with the capture of register data.
6.3.1.4
Fixed latency
A Configuration Register Option Bit CR0[3] is provided to make all memory space read and write transactions or
register space read transactions require the same initial latency by always driving RWDS HIGH during the CA to
indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a
distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. Fixed
latency is the default POR or reset configuration.
6.3.1.5
Drive strength
DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration
Register Bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize
the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as
overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid point
of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process
conditions, nominal operating voltage (1.8 V or 3.0 V) and 50°C. The impedance values may vary from the typical
values depending on the process, voltage, and temperature (PVT) conditions. Impedance will increase with
slower process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher
voltage, or lower temperature.
Each system design should evaluate the data signal integrity across the operating voltage and temperature
ranges to select the best drive strength settings for the operating conditions.
6.3.1.6
Deep power down
When the HYPERRAM™ device is not needed for system operation, it may be placed in a very low power consuming
state called deep power down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the
DPD state within tDPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without
refresh) during DPD state. Exiting DPD requires driving CS# LOW then HIGH, POR, or a reset. Only CS# and RESET#
signals are monitored during DPD mode. For additional details, see “Deep power down” on page 33.
Note: The 128-Mb HYPERRAM™ is a stacked-die chip using two 64-Mb dice. Of the two dice, only one die at a time
can be programmed to enter the DPD mode. It is not feasible to program both the dice to enter the DPD mode
together because entering the DPD mode for one die would require CS# HIGH to LOW transition which would
cause to exit the DPD mode in the other die, and vice versa.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Register space access
6.3.2
Configuration Register 1
Configuration Register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the
HYPERRAM™ device. Configurable characteristics include:
• Partial array refresh
• Hybrid sleep state
• Refresh rate
Table 13
CR1 bit
Configuration Register 1 (CR1) bit assignments
Function
Setting (binary)
FFh - Reserved (default)
[15:8]
[7]
Reserved
These bits should always be set to FFh
1 - Linear burst (default)
0 - Wrapped burst
Burst type
1 - Single ended - CK (default)
0 - Differential - CK#, CK
[6]
Master clock type
1 - Causes the device to enter hybrid sleep state
0 - Normal operation (default)
[5]
Hybrid sleep
Only one die of the 128-Mb stack-die HYPERRAM™ can be programmed
to enter hybrid sleep mode at a time.
000 - Full array (default)
001 - Bottom 1/2 array
010 - Bottom 1/4 array
011 - Bottom 1/8 array
100 - None
[4:2]
Partial array refresh
101 - Top 1/2 array
110 - Top 1/4 array
111 - Top 1/8 array
10 - 1 µs tCSM (Industrial Plus temperature range devices)
11 - Reserved
Distributed refresh
interval (read only)
[1:0]
00 - Reserved
01 - 4 µs tCSM (Industrial temperature range devices)
6.3.2.1
Burst type
Two burst types, namely linear and wrapped, are supported in xSPI (Octal) mode by HYPERRAM™. CR1[7] selects
which type to use.
6.3.2.2
Master clock type
Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
• In the single ended clock mode (by default), CK# input is not enabled; hence it may be left either floating or
biased to HIGH or LOW.
• In the differential clock mode (when enabled), the CK# input can’t be left floating. It must be either driven by
the host, or biased to HIGH or LOW.
6.3.2.3
Partial array refresh
The partial array refresh configuration restricts the refresh operation in HYPERRAM™ to a portion of the memory
array specified by CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole
array.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Register space access
6.3.2.4
Hybrid sleep (HS)
When the HYPERRAM™ is not needed for system operation but data in the device needs to be retained, it may be
placed in hybrid sleep state to save more power. Enter hybrid sleep state by writing 1 to CR1[5]. Bringing CS# LOW
will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to
exit hybrid sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can
potentially get lost.
Note: The 128-Mb HYPERRAM™ is a stacked-die chip using two 64-Mb dice. Of the two dice, only one die at a time
can be programmed to enter the HS mode. It is not feasible to program both the dice to enter the HS mode
together because entering the HS mode for one die would require CS# HIGH to LOW transition which would cause
to exit the HS mode in the other die, and vice versa.
6.3.2.5
Distributed refresh interval
The DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading
or writing a location in each row within a specified time limit. The read or write access copies a row of bits to an
internal buffer. At the end of the access the bits in the buffer are written back to the row in memory, thereby
recharging (refreshing) the bits in the row of DRAM memory cells.
HYPERRAM™ devices include self-refresh logic that will refresh rows automatically. The automatic refresh of a
row can only be done when the memory is not being actively read or written by the host system. The refresh logic
waits for the end of any active read or write before doing a refresh, if a refresh is needed at that time. If a new read
or write begins before the refresh is completed, the memory will drive RWDS HIGH during the CA period to
indicate that 2X initial latency time is required at the start of the new access in order to allow the refresh operation
to complete before starting the new access.
The required refresh interval for the entire memory array varies with temperature as shown in Table 14. This is
the time within which all rows must be refreshed. Refresh of all rows could be done as a single batch of accesses
at the beginning of each interval, in groups (burst refresh) of several rows at a time, spread throughout each
interval, or as single row refreshes evenly distributed throughout the interval. The self-refresh logic distributes
single row refresh operations throughout the interval so that the memory is not busy doing a burst of refresh
operations for a long period, such that the burst refresh would delay host access for a long period.
Table 14
Array refresh interval per temperature
Device temperature (°C) Array refresh interval (ms)
Array rows
8192
Recommended tCSM (µs)
85
105
105
64
16
16
4
1
1
8192
8192
The distributed refresh method requires that the host does not do burst transactions that are so long as to
prevent the memory from doing the distributed refreshes when they are needed. This sets an upper limit on the
length of read and write transactions so that the refresh logic can insert a refresh between transactions. This limit
is called the CS# LOW maximum time (tCSM). The tCSM value is determined by the array refresh interval divided by
the number of rows in the array, then reducing this calculation by half to ensure that a distributed refresh interval
cannot be entirely missed by a maximum length host access starting immediately before a distributed refresh is
needed. Because tCSM is set to half the required distributed refresh interval, any series of maximum length host
accesses that delay refresh operations will catch up on refresh operations at twice the rate required by the refresh
interval divided by the number of rows.
The host system is required to respect the tCSM value by ending each transaction before violating tCSM. This can
be done by host memory controller logic splitting long transactions when reaching the tCSM limit, or by host
system hardware or software not performing a single read or write transaction that would be longer than tCSM
.
As noted in Table 14 the array refresh interval is longer at lower temperatures such that tCSM could be increased
to allow longer transactions. The host system can either use the tCSM value from the table for the maximum
operating temperature or, may determine it dynamically by reading the read only CR1[1:0] bits in order to set the
distributed refresh interval prior to every access.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Interface states
7
Interface states
Table 15 describes the required value of each signal for each interface state.
Table 15 Interface states
Interface state
Power-off
V
CC / VCC
< VLKO
Q
CS# CK, CK#
DQ7–DQ0
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
RWDS
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
RESET#
X
X
X
X
X
X
X
X
L
Power-on (cold) reset
Hardware (warm) reset
Interface standby
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
X
H
H
Master output
valid
CA
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
VCC / VCCQ min
L
L
L
L
L
L
T
T
T
T
T
T
Y
L
H
H
H
H
H
H
Read initial access latency
(data bus turn around period)
Write initial access latency
(RWDS turn around period)
HIGH-Z
HIGH-Z
HIGH-Z
Slave output Slave output valid
valid Z or T
Read data transfer
Write data transfer with initial
latency
Master output Master output valid
valid
X or T
Slave output
L or HIGH-Z
Write data transfer without
Master output
valid
initial latency [26]
Master or slave
output valid or
HIGH-Z
Active clock stop [27]
VCC / VCCQ min
L
Idle
Y
H
Deep power down [27]
Hybrid sleep [27]
VCC / VCCQ min
VCC / VCCQ min
H
H
X or T
X or T
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
H
H
Legend
L = VIL
H = VIH
X = either VIL or VIH
Y= either VIL or VIH or VOL or VOH
Z = either VOL or VOH
L/H = rising edge
H/L = falling edge
T = Toggling during information transfer
Idle = CK is LOW and CK# is HIGH
Valid = all bus signals have stable L or H level
Notes
26.Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The
HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is
required. Since master write data immediately follows the CA period the HYPERRAM™ device may continue
to drive RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during Writes with zero
latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written
(full word writes).
27.Active clock stop is described in “Active clock stop” on page 31, DPD is described in “Deep power down”
on page 33, and hybrid sleep is described in “Hybrid sleep” on page 32.
Datasheet
30 of 63
002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8
Power conservation modes
8.1
Interface standby
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CS# = HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.
8.2
Active clock stop
Design note: Active Clock Stop feature is pending device characterization to determine if it will be supported.
The active clock stop state reduces device interface energy consumption to the ICC6 level during the data transfer
portion of a read or write operation. The device automatically enables this state when clock remains stable for
tACC + 30 ns. While in active clock stop state, read data is latched and always driven onto the data bus. ICC6 shown
in “DC characteristics” on page 36.
Active clock stop state helps reduce current consumption when the host system clock has stopped to pause the
data transfer. Even though CS# may be LOW throughout these extended data transfer cycles, the memory device
host interface will go into the active clock stop current level at tACC + 30 ns. This allows the device to transition
into a lower current state if the data transfer is stalled. Active read or write current will resume once the data
transfer is restarted with a toggling clock. The active clock stop state must not be used in violation of the tCSM
limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the active transaction
as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access.
CS#
Clock Stopped
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
DoutA+1
[7:0]
DoutB+1
[7:0]
DQ[7:0]
Output Driven
Read Data
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Figure 16
Active clock stop during read transaction (DDR)
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8.3
Hybrid sleep
In the hybrid sleep (HS) state, the current consumption is reduced (IHS). HS state is entered by writing a 0 to
CR1[5]. The device reduces power within tHSIN time. The data in memory space and register space is retained
during HS state. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 1. Also, POR, or a
hardware reset will cause the device to exit hybrid sleep state. Note that a POR or a hardware reset disables
refresh where the memory core data can potentially get lost. Returning to standby state requires tEXITHS time.
Following the exit from HS due to any of these events, the device is in the same state as entering hybrid sleep.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
tHSIN
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Write Data
CR0 Value
Enter Hybrid Sleep
tHSIN
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
HS
Figure 17
Enter HS transaction[28]
CS#
tCSHS
tEXTHS
Figure 18
Table 16
Exit HS transaction
Hybrid sleep timing parameters
Parameter
tHSIN
tCSHS
Description
Min
–
60
–
Max
3
3000
100
Unit
µs
ns
Hybrid sleep CR1[5] = 1 register write to HS power level
CS# pulse width to exit HS
CS# exit hybrid sleep to standby wakeup time
tEXTHS
µs
Note
28.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™. Write with no
latency transaction is used for register writes only.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Power conservation modes
8.4
Deep power down
In the deep power down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state
is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop.
The data in memory space is lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH
will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state.
Returning to standby state requires tEXTDPD time. Returning to standby state following a POR requires tVCS time,
as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as
following POR.
Note In xSPI (Octal), deep power down transaction or write any register transaction can be used to enter DPD.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
tDPDIN
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Write Data
CR0 Value
Enter Deep Power Down
tDPDIN
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
DPD
Figure 19
Enter DPD transaction[29]
CS#
tCSDPD
tEXTDPD
Figure 20
Table 17
Exit DPD transaction
Deep power down timing parameters
Description
Deep power down CR0[15] = 0 register write to DPD power level
CS# pulse width to exit DPD
Parameter
tDPDIN
tCSDPD
Min
Max
3
3000
150
Unit
µs
ns
–
200
–
tEXTDPD
CS# exit deep power down to standby wakeup time
µs
Note
29.The initial latency “low = 1x latency count” is not applicable in dual-die, 128-Mb HYPERRAM™. Write with no
latency transaction is used for register writes only.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9
Electrical specifications
9.1
Absolute maximum ratings
Storage temperature plastic packages
Ambient temperature with power applied
–65°C to +150°C
–65°C to +115°C
Voltage with respect to ground
All signals[31]
–0.5 V to +(VCC + 0.5 V)
100 mA
Output short circuit current[32]
VCC, VCC
Q
–0.5 V to +4.0 V
9.2
Input signal overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage
transitions, inputs or I/Os may negative overshoot VSS to –1.0 V or positive overshoot to VCC + 1.0 V, for periods
up to 20 ns.
VSSQ to VCC
Q
- 1.0V
20 ns
≤
Figure 21
Maximum negative overshoot waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCC
Q
Figure 22
Maximum positive overshoot waveform
Notes
30.Stresses above those listed under Absolute maximum ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those
indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute
maximum rating conditions for extended periods may affect device reliability.
31.Minimum DC voltage on input or I/O signal is -1.0 V. During voltage transitions, input or I/O signals may
undershoot VSS to -1.0V for periods of up to 20 ns. See Figure 21. Maximum DC voltage on input or I/O signals
is VCC + 1.0 V. During voltage transitions, input or I/O signals may overshoot to VCC + 1.0 V for periods up to
20 ns. See Figure 22.
32.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.3
Table 18
Latch-up characteristics
Latch-up specification[33]
Description
Min
–1.0
–100
Max
VCCQ + 1.0
+100
Unit
V
Input voltage with respect to VSSQ on all input only connections
Input voltage with respect to VSSQ on all I/O connections
VCCQ Current
mA
9.4
Operating ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
9.4.1
Temperature ranges
Table 19
Temperature ranges
Spec
Parameter
Symbol
Device
Unit
Min
Max
85
Industrial (I)
Industrial Plus (V)
Automotive, AEC-Q100 Grade 3 (A)
Automotive, AEC-Q100 Grade 2 (B)
105
85
105
Ambient temperature
TA
–40
°C
9.4.2
Table 20
Power supply voltages
Power supply voltages
Description
Min
1.7
2.7
2.7
Max
2.0
3.6
Unit
1.8 V VCC power supply
V
3.0 V VCC power supply
3.6
Note
33.Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested,
connections not being tested are at VSS
.
Datasheet
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002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.5
DC characteristics
Table 21
DC characteristics (CMOS compatible)
128 Mb
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
Input leakage current
3.0 V device reset signal high
only
V
V
= V to V ,
IN
CC
SS
CC
I
I
I
I
4
LI1
LI2
LI3
LI4
= V max
CC
Input leakage current
1.8 V device reset signal high
only
V
V
= V to V ,
SS CC
IN
CC
4
= V max
CC
–
µA
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
3.0 V device reset signal low
30
30
= V max
[35]
CC
only
Input leakage current
V
V
= V to V ,
SS CC
IN
CC
1.8 V device reset signal low
= V max
[35]
CC
only
CS# = V , @ 200 MHz,
CC
IL
50
56
V
= 2.0 V
CS# = V , @ 166 MHz,
IL
I
I
V
V
active read current
active write current
CC1
CC2
CC
CC
V
= 3.6 V
CC
CS# = VSS, @ 200 MHz,
= 3.6 V
60
V
CC
30
160
–
mA
CS# = V , @ 200 MHz,
IL
50
V
= 2.0 V
CC
CS# = V , @ 166 MHz,
IL
56
V
= 3.6 V
CC
CS# = V , @ 200 MHz,
SS
= 3.6 V
60
V
–
CC
CS# = V , V = 2.0 V;
CC CC
440
420
410
400
420
410
400
500
480
450
440
full array
CS# = V , V = 2.0 V;
CC CC
bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/4 array
V
standby current
CS# = V , V = 2.0 V;
CC
CC CC
(–40°C to +85°C)
bottom 1/8 array
CS# = V , V = 2.0 V;
CC CC
top 1/2 array
CS# = V , V = 2.0 V;
CC CC
I
µA
CC4I
top 1/4 array
CS# = V , V = 2.0 V;
CC CC
top 1/8 array
CS# = V , V = 3.6 V;
CC CC
180
–
full array
CS# = V , V = 3.6 V;
CC CC
bottom 1/2 array
V
standby current
CC
(–40°C to +85°C)
CS# = V , V = 3.6 V;
CC CC
bottom 1/4 array
CS# = V , V = 3.6 V;
CC CC
bottom 1/8 array
Notes
34.Not 100% tested.
35.Only one of the two-die 128 Mb chip can enter DPD mode, while the other die remains in standby mode. RESET# LOW
initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Datasheet
36 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
Table 21
DC characteristics (CMOS compatible) (continued)
128 Mb
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
CS# = V , V = 3.6 V;
CC CC
480
top 1/2 array
V
standby current
CS# = V , V = 3.6 V;
CC
CC CC
–
450
440
660
630
615
600
630
615
600
750
720
675
660
720
675
660
1.5
ICC4I
(–40°C to +85°C)
top 1/4 array
CS# = V , V = 3.6 V;
CC CC
top 1/8 array
CS# = V , V = 2.0 V;
CC CC
160
full array
CS# = V , V = 2.0 V;
CC CC
bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/4 array
V
standby current
CS# = V , V = 2.0 V;
CC
CC CC
(–40°C to +105°C)
bottom 1/8 array
–
CS# = V , V = 2.0 V;
CC CC
top 1/2 array
CS# = V , V = 2.0 V;
CC CC
top 1/4 array
µA
CS# = V , V = 2.0 V;
CC CC
top 1/8 array
I
CC4P
CS# = V , V = 3.6 V;
CC CC
–
180
full array
CS# = V , V = 3.6 V;
CC CC
bottom 1/2 array
CS# = V , V = 3.6 V;
CC CC
bottom 1/4 array
V
standby current
CS# = V , V = 3.6 V;
CC
CC CC
(–40°C to +105°C)
bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
–
top 1/2 array
CS# = V , V = 3.6 V;
CC CC
top 1/4 array
CS# = V , V = 3.6 V;
CC CC
top 1/8 array
CS# = V , RESET# = V ,
IH
IL
I
I
I
I
Reset current
CC5
V
= V max
CC
CC
Active clock stop current
(–40°C to +85°C)
CS# = V , RESET# = V ,
IL IH
13
CC6I
CC6IP
CC7
V
= V max
CC
CC
10
–
mA
Active clock stop current
(–40°C to +105°C)
CS# = V , RESET# = V ,
IL IH
19
V
= V max
CC
CC
CS# = V , V = V max,
[34]
IH CC
CCQ
CC
V
current during power up
70
CC
V
= V
= 2.0 V or 3.6 V
CC
Notes
34.Not 100% tested.
35.Only one of the two-die 128 Mb chip can enter DPD mode, while the other die remains in standby mode. RESET# LOW
initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Datasheet
37 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
Table 21
Parameter
[35]
DC characteristics (CMOS compatible) (continued)
128 Mb
Description
Test conditions
CS# = V , V = V max
Unit
[34]
Min
Typ
Max
Deep power down current
(–40°C to +85°C)
I
I
I
I
250
DPD
DPD
DPD
IH CC
CC
Deep power down current 3.0 V
[35]
[35]
[35]
CS# = V , V = 3.6 V
220
330
360
420
370
330
310
370
330
310
480
430
370
340
430
370
340
630
570
510
460
570
IH CC
(40 °C to +85 °C)
–
Deep power down current
(–40°C to +105°C)
CS# = V , V = V max
IH CC
CC
Deep power down current 3.0 V
CS# = V , V = 3.6 V
DPD
IH CC
(40 °C to +105 °C)
CS# = V , V = 2.0 V;
CC CC
105
full array
CS# = V , V = 2.0 V;
CC CC
bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/4 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/8 array
–
115
–
CS# = V , V = 2.0 V;
CC CC
top 1/2 array
CS# = V , V = 2.0 V;
CC CC
top 1/4 array
CS# = V , V = 2.0 V;
CC CC
top 1/8 array
CS# = V , V = 3.6 V;
CC CC
–
µA
full array
CS# = V , V = 3.6 V;
CC CC
bottom 1/2 array
Hybrid sleep current
(–40°C to +85°C)
CS# = V , V = 3.6 V;
[35]
HS
CC CC
I
bottom 1/4 array
CS# = V , V = 3.6 V;
CC CC
bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
top 1/2 array
CS# = V , V = 3.6 V;
CC CC
top 1/4 array
CS# = V , V = 3.6 V;
CC CC
top 1/8 array
CS# = V , V = 2.0 V;
CC CC
185
–
full array
CS# = V , V = 2.0 V;
CC CC
bottom 1/2 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/4 array
CS# = V , V = 2.0 V;
CC CC
bottom 1/8 array
CS# = V , V = 2.0 V;
CC CC
top 1/2 array
Notes
34.Not 100% tested.
35.Only one of the two-die 128 Mb chip can enter DPD mode, while the other die remains in standby mode. RESET# LOW
initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
Table 21
DC characteristics (CMOS compatible) (continued)
128 Mb
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
CS# = V , V = 2.0 V;
CC CC
–
–
510
top 1/4 array
Hybrid sleep current
(–40°C to +85°C)
CS# = V , V = 2.0 V;
CC CC
460
690
630
550
520
630
550
520
top 1/8 array
CS# = V , V = 3.6 V;
CC CC
215
full array
CS# = V , V = 3.6 V;
CC CC
bottom 1/2 array
CS# = V , V = 3.6 V;
[35]
CC CC
I
–
µA
HS
bottom 1/4 array
Hybrid sleep current
(–40°C to +105°C)
CS# = V , V = 3.6 V;
CC CC
bottom 1/8 array
CS# = V , V = 3.6 V;
CC CC
top 1/2 array
–
CS# = V , V = 3.6 V;
CC CC
top 1/4 array
CS# = V , V = 3.6 V;
CC CC
top 1/8 array
V
V
V
V
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.15 × V
0.35 × V
1.15 × V
0.20
IL
CCQ
CCQ
CCQ
–
0.70 × V
–
IH
CCQ
V
I
I
= 100 µA for DQ[7:0]
= 100 µA for DQ[7:0]
OL
OL
V
– 0.20
CCQ
–
OH
OH
Notes
34.Not 100% tested.
35.Only one of the two-die 128 Mb chip can enter DPD mode, while the other die remains in standby mode. RESET# LOW
initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.5.1
Table 22
Capacitance characteristics
1.8 V capacitive characteristics[36, 37, 38]
128 Mb
Max
6
0.50
6
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
CI
CID
CO
pF
CIO
CIOD
6
0.50
IO capacitance delta (DQx)
Table 23
3.0 V capacitive characteristics[36, 37, 38]
Description
128 Mb
Max
6
0.50
6
Parameter
Unit
Input capacitance (CK, CK#, CS#)
CI
CID
CO
CIO
CIOD
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
pF
6
0.50
IO capacitance delta (DQx)
9.5.2
Thermal resistance
Table 24
Thermal resistance
24-ball FBGA
Parameter[39]
Description
Test conditions
Unit
package
Thermal resistance
Test conditions follow standard
test methods and procedures for
measuringthermalimpedance,per
EIA/JESD51.
JA
JC
54
(junction to ambient)
°C/W
Thermal resistance
(junction to case)
25.5
Notes
36.These values are guaranteed by design and are tested on a sample basis only.
37.Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector
network analyzer. VCC, VCCQ are applied and all other signals (except the signal under test) floating. DQ’s
should be in the high impedance state.
38.Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance values
to allow for signal propagation time matching in the system. The capacitance value for CS# is not as critical
because there are no critical timings between CS# going active (LOW) and data being presented on the DQs
bus.
39.This parameter is guaranteed by characterization; not tested in production.
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.6
Power-up initialization
HYPERRAM™ products include an on-chip voltage sensor used to launch the power-up initialization process. VCC
and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC(min),
the device will require tVCS time to complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min)
is reached during power-up, and then CS# must remain high for a further delay of tVCS . A simple pull-up resistor
from VCCQ to chip select (CS#) can be used to insure safe and proper power-up.
If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period
is used primarily to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 23
Power-up with RESET# HIGH
Vcc_VccQ
CS#
VCC Minimum
Device
Access Allowed
tVCS
RESET#
Figure 24
Power-up with RESET# LOW
Table 25
Power up and reset parameters[40, 41, 42]
Description
Parameter
Min
1.7
2.7
–
Max
2.0
3.6
Unit
V
1.8 V VCC power supply
3.0 V VCC power supply
VCC and VCCQ minimum and RESET# HIGH to first access
VCC
tVCS
150
µs
Notes
40.Bus transactions (read and write) are not allowed during the power-up reset time (tVCS).
41.VCCQ must be the same voltage as VCC
.
42.VCC ramp rate may be non-linear.
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.7
Power down
HYPERRAM™ devices are considered to be powered-off when the array power supply (VCC) drops below the VCC
lock-out voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or
equal to VCC. At the VLKO level, the HYPERRAM™ device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC VCCQ).
During power-down or voltage drops below VLKO, the array power supply voltages must also drop below VCC reset
(VRST) for a power down period (tPD) for the part to initialize correctly when the power supply again rises to VCC
minimum. See Figure 25.
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is
again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no
assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the
device is properly initialized.
V
(Max)
(Min)
CC
V
CC
No Device Access Allowed
V
CC
Device Access
Allowed
t
VCS
V
LKO
V
RST
t
PD
Time
Figure 25
Power down or voltage drop
The following section describes HYPERRAM™ device dependent aspects of power down specifications.
Table 26
Symbol
VCC
VLKO
VRST
tPD
1.8 V power-down voltage and timing[43]
Parameter
Min
1.7
1.5
0.7
50
Max
2.0
Unit
V
VCC power supply
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC VRST
–
µs
Table 27
3.0 V power-down voltage and timing[43]
Parameter
Symbol
Min
2.7
2.4
0.7
50
Max
3.6
Unit
V
VCC
VCC power supply
VLKO
VRST
tPD
VCC lock-out below which re-initialization is required
VCC low Voltage needed to ensure initialization will occur
Duration of VCC VRST
–
µs
Note
43.VCC ramp rate can be non-linear.
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.8
Hardware reset
The RESET# input provides a hardware method of returning the device to the standby state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws
CMOS standby current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not
allowed.
A hardware reset will do the following:
• Cause the Configuration Registers to return to their default values
• Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
• Force the device to exit the hybrid sleep state
• Force the device to exit the deep power down state
After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped
during RESET# LOW, and the self-refresh row counter is reset to its default value, some rows may not be refreshed
within the required array refresh interval per Table 14. This may result in the loss of DRAM array data during or
immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware
reset and reload any required data.
tRP
RESET#
tRH
tRPH
CS#
Figure 26
Hardware reset timing diagram
Power-up and reset parameters
Table 28
Parameter
tRP
Description
Min
200
400
Max
Unit
RESET# pulse width
tRH
tRPH
Time between RESET# (HIGH) and CS# (LOW)
RESET# LOW to CS# LOW
–
ns
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Electrical specifications
9.9
Software reset
The software reset provides a software method of returning the device to the standby state. During tSR the device
will draw ICC5 current.
A software reset will do the following:
• Cause the Configuration Registers to return to their default values
• Halt self-refresh operation during the software reset process - memory array data is considered as invalid
After software reset finishes, the self-refresh operation will resume. Because self-refresh operation is stopped,
and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required
array refresh interval per Table 14. This may result in the loss of DRAM array data during or immediately following
a software reset. The host system should assume DRAM array data is lost after a software reset and reload any
required data.
Table 29
Parameter
tSR
Software reset timing
Description
Min
–
Max
400
Unit
ns
Software reset transaction CS# HIGH to device in standby
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10
Timing specifications
The following section describes HYPERRAM™ device dependent aspects of timing specifications.
10.1
Key to switching waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
Figure 27
Switching waveforms
10.2
AC test conditions
Device
Under
Test
CL
Figure 28
Table 30
Test setup
Test specification[44]
Parameter
All speeds
15
Units
pF
Output load capacitance, CL
Minimum input rise and fall slew rates (1.8 V)[45]
Minimum input rise and fall slew rates (3.0 V)[45]
Input pulse levels
1.13
2.06
0.0–VCCQ
V/ns
Input timing measurement reference levels
Output timing measurement reference levels
V
VCCQ/2
VccQ
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Vss
Figure 29
Notes
Input waveforms and measurement levels[46]
44.Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#.
45.All AC timings assume this input slew rate.
46.Input timings for the differential CK/CK# pair are measured from clock crossings.
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
tCK
VCCQ
CK, CK#
VT
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
IL(max)
VT
RWDS
V
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VT
DQ[7:0]
VSSQ
Figure 30
DDR input timing reference level
tSCK
VCCQ
RWDS
VT
VSSQ
VCCQ
tDSS
tDSH
VOH(min)
OL(max)
VT
DQ[7:0]
V
VSSQ
Figure 31
DDR output timing reference level
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10.3
CLK characteristics
t
CK
t
t
CKHP
CKHP
CK#
V
IX (Max)
VCCQ / 2
V
IX (Min)
CK
Figure 32
Table 31
CK period
Clock characteristics
Clock timings[47, 48, 49]
Parameter[50, 51]
200 MHz
166 MHz
Symbol
Unit
Min
5
Max
–
Min
6
Max
–
tCK
ns
CK half period - duty cycle
tCKHP
0.45
0.55
0.45
0.55
tCK
CK half period at frequency
Min = 0.45 tCK Min
Max = 0.55 tCK Min
tCKHP
2.25
2.75
2.7
3.3
ns
Table 32
Clock AC/DC electrical characteristics[52, 53]
Parameter
Symbol
VIN
VID(DC)
VID(AC)
VIX
Min
–0.3
VCCQ × 0.4
VCCQ × 0.6
VCCQ × 0.4
Max
Unit
DC input voltage
VCCQ + 0.3
VCCQ + 0.6
VCCQ + 0.6
VCCQ × 0.6
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
V
Notes
47.Clock jitter of ±5% is permitted
48.Minimum frequency (maximum tCK) is dependent upon maximum CS# Low time (tCSM), initial latency, and
burst length.
49.CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially).
50.CK# is only used on the 1.8 V device and is shown as a dashed waveform.
51.The 3-V device uses a single-ended clock input.
52.VID is the magnitude of the difference between the input level on CK and the input level on CK#.
53.The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC
level of VCCQ.
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10.4
AC characteristics
10.4.1
Read transactions
Table 33
HYPERRAM™ specific read timing parameters
200 MHz
166 MHz
Parameter
Symbol
Unit
Min
Max
Min
Max
Chip select high between transactions - 1.8 V
Chip select high between transactions - 3.0 V
HYPERRAM™ read-write recovery time - 1.8 V
HYPERRAM™ read-write recovery time - 3.0 V
Chip select setup to next CK rising edge
Data strobe valid - 1.8 V
tCSHI
6
6
–
–
tRWR
tCSS
tDSV
35
4.0
–
36
3
5.0
6.5
12
12
–
Data strobe valid - 3.0 V
Input setup - 1.8 V
tIS
Input setup - 3.0 V
0.5
0.6
Input hold - 1.8 V
tIH
Input hold - 3.0 V
–
–
HYPERRAM™ read initial access time - 1.8 V
HYPERRAM™ read initial access time- 3.0 V
Clock to DQs low Z
tACC
tDQLZ
tCKD
35
0
36
0
CK transition to DQ valid - 1.8 V
CK transition to DQ valid - 3.0 V
CK transition to DQ invalid - 1.8 V
CK transition to DQ invalid - 3.0 V
5.0
6.5
4.2
5.7
5.5
7
ns
1
1
0
0
4.6
5.6
tCKDI
0.5
0.5
Data Valid (tDV min = the lesser of: tCKHP min –
tCKD max + tCKDI max or tCKHP min – tCKD min +
tCKDI min) - 1.8 V
1.8
[54, 55]
tDV
1.45
–
–
–
Data Valid (tDV min = the lesser of: tCKHP min –
tCKD max + tCKDI max or tCKHP min – tCKD min +
tCKDI min) - 3.0 V
1.3
1
CK transition to RWDS valid - 1.8 V
CK transition to RWDS valid - 3.0 V
RWDS transition to DQ valid - 1.8 V
RWDS transition to DQ valid - 3.0 V
RWDS transition to DQ invalid - 1.8 V
RWDS transition to DQ invalid - 3.0 V
Chip select hold after CK falling edge
5.0
6.5
5.5
7
tCKDS
tDSS
tDSH
tCSH
–0.4
0
+0.4
–
–0.45
0
+0.45
–
Notes
54.Refer to Figure 35 for data valid timing.
55.The tDV timing calculation is provided for reference only, not to determine the spec limit. The spec limit is
guaranteed by testing.
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
Table 33
HYPERRAM™ specific read timing parameters (continued)
200 MHz
166 MHz
Parameter
Symbol
tDSZ
Unit
Min
Max
Min
Max
Chip select inactive to RWDS high-Z - 1.8 V
Chip select inactive to RWDS high-Z - 3.0 V
Chip select inactive to DQ high-Z - 1.8 V
Chip select inactive to DQ high-Z - 3.0 V
Refresh time - 1.8 V
5.0
6.5
5
6
7
6
7
–
–
tOZ
6.5
ns
tRFH
35
1
–
36
1
–
Refresh time - 3.0 V
CK transition to RWDS Low @ CA phase @ Read
- 1.8 V
5.5
7
5.5
7
tCKDSR
CK transition to RWDS Low @ CA phase @ Read
- 3.0 V
tCSHI
CS#
tCSS
tRWR=Read Write Recovery
tCSH
Additional latency
tACC
tCSS
CK#, CK
RWDS
tDSZ
4 cycle latency 1
4 cycle latency 2
tCKDS
tDSV
High: 2X Latency Count
tCKDSR
tOZ
tDSS
tDQLZ
tCKD
tIS
tIH
tDSH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
RWDS and Data
are edge aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
Figure 33
Read timing parameters - With additional latency
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Timing specifications
10.4.2
Write transactions
Table 34
Write timing parameters
200 MHz
166 MHz
Parameter
Symbol
Unit
Min
Max
Min
Max
Read-write recovery time
Access time
Refresh time
tRWR
tACC
tRFH
tCSM
tCSM
tDMV
35
–
36
–
ns
Chip select maximum low time (85°C)
Chip select maximum low time (105°C)
RWDS data mask valid
4
1
–
4
1
–
–
0
–
0
µs
CS#
tCSH
tRWR=Read Write Recovery
Additional Latency
tCSS
CK#, CK
tIS
tIH
tDSV
4 cycle latency 1
tDSZ
tDMV
High: 2X Latency Count
RWDS
tIS
tIS tIH
tIH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
CK and Data
Are center aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0]
and RWDS
Figure 34
Write timing parameters - With additional latency
CS#
tCKHP
tCSHS tCSS
CK
CK#
tDSZ
tOZ
tCKDS
RWDS
tDSS
tCKD
tCKDI
tDV
tDQLZ
tCKD
tDSH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
Figure 35
Notes
Data valid timing[56, 57, 58]
56.tCKD and tCKDI parameters define the beginning and end position of data valid period.
57.tDSS and tDSH define how early or late DQ may transition relative to RWDS. This is a potential skew between
the CK to DQ delay tCKD and CK to RWDS delay tCKDS
.
58.Since DQ and RWDS are the same output types, the tCKD, and tCKDS values track together (vary by the same
ratio).
Datasheet
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Physical interface
11
Physical interface
11.1
FBGA 24-ball 5 x 5 array footprint
HYPERRAM™ devices are provided in Fortified Ball Grid Array (FBGA), 1 mm pitch, 24-ball, 5 x 5 ball array footprint,
with 6mm x 8mm body.
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
RFU
RFU
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Figure 36
24-ball FBGA, 6 x 8 mm, 5 x 5 ball footprint, top view
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Physical interface
11.2
Package diagram
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
DIMENSIONS
SYMBOL
MIN.
-
NOM.
MAX.
1.00
-
A
-
-
2. ALL DIMENSIONS ARE IN MILLIMETERS.
A1
D
0.20
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D1
E1
MD
ME
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
5
24
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
b
0.35
0.45
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
JEDEC SPECIFICATION NO. REF: N/A
10.
002-15550 *A
Figure 37
24-ball BGA (8.0 mm × 6.0 mm × 1.0 mm) package outline, 002-15550
Datasheet
52 of 63
002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
12
DDR center-aligned read strobe (DCARS) functionality
The HYPERRAM™ device offers an optional feature that enables independent skewing (phase shifting) of the
RWDS signal with respect to the read data outputs. This feature is provided in certain devices, based on the
ordering part number (OPN).
When the DCARS feature is provided, a second differential phase shifted clock input PSC/PSC# is used as the
reference for RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase shifted
90 degrees to place the RWDS edges centered within the DQ signals valid data window. However, other degrees
of phase shift between CK/CK# and PSC/PSC# may be used to optimize the position of RWDS edges within the DQ
signals valid data window so that RWDS provides the desired amount of data setup and hold time in relation to
RWDS edges.
PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven LOW and HIGH respectively or,
both may be driven LOW during write transactions.
The PSC/PSC# is used in xSPI (Octal) devices. If single-ended mode is selected, then PSC# must be driven LOW
but must not be left floating (leakage concerns).
12.1
xSPI HYPERRAM™ products with DCARS signal description
RESET#
VCC
VCCQ
CS#
CK
DQ[7:0]
RWDS
CK#
PSC
PSC#
VSS
VSSQ
Figure 38
xSPI product with DCARS signal diagram
Datasheet
53 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
Table 35
Symbol
Signal description
Type
Description
Chip Select. xSPI transactions are initiated with a HIGH to LOW transition.
xSPI transactions are terminated with a LOW to HIGH transition.
CS#
Differential Clock. Command, address, and data information is output with
respect to the crossing of the CK and CK# signals. Use of differential clock is
optional.
Single Ended Clock. CK# is not used, only a single ended CK is used. The
clock is not required to be free-running.
CK, CK#
Input
Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS
signal with respect to the CK/CK# inputs. If the CK/CK# (differential mode) is
configured, then PSC/PSC# are used. Otherwise, only PSC is used (single
ended).
PSC (and PSC#) may be driven HIGH and LOW respectively or both may be
driven LOW during write transactions.
PSC, PSC#
Read-Write Data Strobe. Data bytes output during read transactions are
aligned with RWDS based on the phase shift from CK, CK# to PSC, PSC#. PSC,
PSC# cause the transitions of RWDS, thus the phase shift from CK, CK# to
PSC, PSC# is used to place RWDS edges within the data valid window. RWDS
is an input during write transactions to function as a data mask. At the
beginning of all bus transactions RWDS is an output and indicates whether
additional initial latency count is required.
RWDS
Output
The dual-die, 128-Mb HyperRAM chip supports data transactions with
additional (2X) latency only.
Data Input/Output. CA/data information is transferred on these DQs during
DQ[7:0]
Input/output
Input
read and write transactions.
Hardware RESET. When LOW, the device will self initialize and return to the
idle state. RWDS and DQ[7:0] are placed into the HIGH-Z state when RESET#
is LOW. RESET# includes a weak pull-up, if RESET# is left unconnected it will
be pulled up to the HIGH state.
RESET#
VCC
Array Power.
V
CCQ
VSS
SSQ
Input/Output Power.
Array Ground.
Input/Output Ground.
Power supply
V
Datasheet
54 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
12.2
HYPERRAM™ products with DCARS — FBGA 24-ball, 5 x 5 array footprint
1
2
3
4
RESET#
Vcc
5
A
B
C
D
E
RFU
PSC
PSC#
DQ4
VssQ
RFU
CK
CS#
Vss
CK#
VssQ
VccQ
DQ7
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
DQ2
DQ3
VccQ
Figure 39
24-ball FBGA, 5 x 5 ball footprint, top view
Datasheet
55 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
12.3
HYPERRAM™ memory with DCARS timing
The illustrations and parameters shown here are only those needed to define the DCARS feature and show the
relationship between the phase shifted clock, RWDS, and data.
2X initial latency
Figure 40
HYPERRAM™ memory DCARS timing diagram[59, 60, 61, 62]
Notes
59.Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new
transaction is initiated.
60.The memory drives RWDS during read transactions.
61.This example demonstrates a latency code setting of four clocks and no additional initial latency required.
62.The initial latency “low = 1x latency count” is not applicable in dual-die, 128 Mb HYPERRAM™.
Datasheet
56 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
DDR center-aligned read strobe (DCARS) functionality
CS#
tCKHP
tCSH
tCSS
CK,CK#
PSC,PSC#
tPSCRWDS
tDSZ
tIS
tIH
RWDS
tCKDI
tCKD
tDQLZ
tDV
tOZ
tCKD
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
RWDS and Data are driven by the memory
Figure 41
Table 36
DCARS data valid timing[63, 64, 65, 66]
DCARS read timing
200 MHz
166 MHz
Parameter
Symbol
Unit
Min
Max
Min
Max
Input setup - CK/CK# setup w.r.t
PSC/PSC# (edge to edge)
tIS
tIH
0.5
–
0.6
–
CK half period - duty cycle (edge to edge)
ns
HYPERRAM™ PSC transition to RWDS
transition
tPSCRWDS
–
5
–
6.5
Time delta between CK to DQ valid and
tPSCRWDS - tCKD
–1.0
+0.5
–1.0
+0.5
PSC to RWDS[67]
Notes
63.Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new
transaction is initiated.
64.This figure shows a closer view of the data transfer portion of Figure 38 in order to more clearly show the
Data Valid period as affected by clock jitter and clock to output delay uncertainty.
65.The delay (phase shift) from CK to PSC is controlled by the xSPI master interface (host) and is generally
between 40 and 140 degrees in order to place the RWDS edge within the data valid window with sufficient
set-up and hold time of data to RWDS. The requirements for data set-up and hold time to RWDS are
determined by the xSPI master interface design and are not addressed by the xSPI slave timing parameters.
66.The xSPI timing parameters of tCKD, and tCKDI define the beginning and end position of the data valid period.
The tCKD and tCKDI values track together (vary by the same ratio) because RWDS and Data are outputs from
the same device under the same voltage and temperature conditions.
67.Sampled, not 100% tested.
Datasheet
57 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Ordering information
13
Ordering information
13.1
Ordering part number
The ordering part number is formed by a valid combination of the following:
S70KS
S70KL 128
3
DP
B
H
I
02
0
Packing type
0 = Tray
3 = 13" Tape and reel
Model number (additional ordering options)
02 = Standard 6 × 8 × 1.0 mm package (VAA024)
03 = DDR center-aligned read strobe (DCARS) 6 × 8 × 1.0 mm package (VAA024)
Temperature range/grade
I = Industrial (-40°C to +85°C)
V = Industrial Plus (-40°C to +105°C)
A = Automotive, AEC-Q100 grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 grade 2 (-40°C to +105°C)
Package materials
H = Halogen-Free, Lead (Pb)-free
Package type
B = 24-ball BGA, 1.00 mm pitch (5 × 5 ball footprint)
Speed
GA = 200 MHz DDR
DP = 166 MHz DDR
Device technology
2 = 38-nm DRAM process technology - HYPERBUS™
3 = 38-nm DRAM process technology - Octal
Density
128 = 128 Mb
Device family
S70KS 1.8 V-only, HYPERRAM™ self-refresh DRAM
S70KL 3.0 V-only, HYPERRAM™ self-refresh DRAM
Datasheet
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002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Ordering information
13.2
Valid combinations
The recommended combinations table lists configurations planned to be available in volume. Table 37 will be
updated as new combinations are released. Contact your local sales representative to confirm availability of
specific combinations and to check on newly released combinations.
Table 37
Valid combinations – Standard
Package,
Device
family
Model Packing
Density Technology Speed material, and
temperature
Ordering part number
Package marking
number
type
0
3
0
3
0
3
0
3
S70KL1283DPBHI020
S70KL1283DPBHI023
S70KL1283GABHI020
S70KL1283GABHI023
S70KL1283DPBHV020
S70KL1283GABHI023
S70KL1283GABHV020
S70KL1283GABHV023
7KL1283DPHI02
7KL1283DPHI02
7KL1283GAHI02
7KL1283GAHI02
7KL1283DPHV02
7KL1283GAHI02
7KL1283GAHV02
7KL1283GAHV02
DP
BHI
GA
S70KL
128
128
3
02
DP
GA
BHV
0
3
0
3
S70KS1283GABHI020
S70KS1283GABHI023
S70KS1283GABHV020
S70KS1283GABHV023
7KS1283GAHI02
7KS1283GAHI02
7KS1283GAHV02
7KS1283GAHV02
BHI
S70KS
3
GA
02
BHV
13.3
Valid combinations – Automotive grade / AEC-Q100
Table 38 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in
volume. The table will be updated as new combinations are released. Consult your local sales representative to
confirm availability of specific combinations and to check on newly released combinations.
Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade
products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full
compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require
ISO/TS-16949 compliance.
Table 38
Valid combinations – Automotive grade / AEC-Q100
Package,
Device
family
Model Packing
Density Technology Speed material, and
Ordering part number
Package marking
number
type
temperature
3
3
3
3
3
3
0
3
0
3
0
3
S70KL1283DPBHA020
S70KL1283DPBHA023
S70KL1283DPBHB020
S70KL1283DPBHB023
S70KL1283GABHB020
S70KL1283GABHB023
7KL1283DPHA02
7KL1283DPHA02
7KL1283DPHB02
7KL1283DPHB02
7KL1283GABHB02
7KL1283GABHB02
BHA
DP
GA
S70KL
128
128
02
BHB
3
3
3
3
0
3
0
3
S70KS1283GABHA020
S70KS1283GABHA023
S70KS1283GABHB020
S70KS1283GABHB023
7KS1283GAHA02
7KS1283GAHA02
7KL1283GABHB02
7KS1283GAHB02
BHA
BHB
S70KS
GA
02
Datasheet
59 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Acronyms
14
Acronyms
Table 39
Acronyms used in this document
Description
Acronym
CMOS
DCARS
DDR
complementary metal oxide semiconductor
DDR Center-Aligned Read Strobe
double data rate
DPD
deep power down
DRAM
HS
dynamic RAM
hybrid sleep
MSb
most significant bit
POR
power-on reset
PSRAM
PVT
RWDS
SPI
pseudo static RAM
process, voltage, and temperature
read-write data strobe
serial peripheral interface
expanded serial peripheral interface
xSPI
Datasheet
60 of 63
002-29418 Rev. *A
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128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Document conventions
15
Document conventions
15.1
Table 40
Units of measure
Units of measure
Unit of measure
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
Symbol
°C
MHz
µA
µs
mA
mm
ns
nanosecond
ohm
%
percent
pF
V
picofarad
volt
W
watt
Datasheet
61 of 63
002-29418 Rev. *A
2022-04-19
128 Mb HYPERRAM™ self-refresh DRAM (PSRAM)
Octal xSPI, 1.8 V/3.0 V
Revision history
Revision history
Document
Date of release
Description of changes
version
**
2020-02-07
New datasheet.
Migrated to Infineon template.
Configuration Register 1: Updated description.
Interface states: Updated Table 15. Updated Note 27.
Hybrid sleep: Updated Table 16.
DC characteristics: Updated Table 21.
Added Thermal resistance.
AC test conditions: Added Figure 30 and Figure 31.
Read transactions: Updated Table 33. Added Notes 54, 55 and referred
these notes in tDV parameter in Table 33. Removed figure “Read Timing
Diagram”. Updated Figure 33.
*A
2022-04-19
Write transactions: Updated Figure 34 and Figure 35.
Added Notes 56, 57, 58 and referred the same notes in Figure 35.
Valid combinations: Updated part numbers in Table 37. Deleted Table 38.
Valid combinations - DCARS and Table 40. Valid combinations – DCARS
automotive grade / AEC-Q100.
Datasheet
62 of 63
002-29418 Rev. *A
2022-04-19
Please read the Important Notice and Warnings at the end of this document
Trademarks
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IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-04-19
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
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is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
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document?
Go to www.infineon.com/support
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Technologies, Infineon Technologies’ products may
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Document reference
002-29418 Rev. *A
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
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