S71KS512SC0BHV000 [INFINEON]

Multi-chip Package Solutions;


型号：	S71KS512SC0BHV000
厂家：	Infineon
描述：	Multi-chip Package Solutions
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中文：	中文翻译
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S71KS512SC0

S71KL256SC0

S71KL512SC0

SUPPLEMENT

HyperFlash™ and HyperRAM™

Multi-Chip Package 1.8V/3V

HyperFlash™ and HyperRAM™ Multi-Chip Package

3 V

Distinctive Characteristics

■ HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP)

■ Optional Signals

❐ 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM

❐ Reset

(S71KS512SC0)

❐ INT# output to generate external interrupt

• Busy to Ready Transition

❐ RSTO# Output to generate system level Power-On Reset

(POR)

❐ 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM

(S71KL512SC0)

❐ 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM

(S71KL256SC0)

• User configurable RSTO# Low period

❐ FBGA 24-ball, 6  8  1.0 mm package

■ High Performance

❐ Double-Data Rate (DDR)

• Two data transfers per clock

❐ Up to 166-MHz clock rate (333 MB/s) at 1.8V V_CC

❐ Up to 100-MHz clock rate (200 MB/s) at 3.0V V_CC

■ HyperBus Interface

❐ 1.8V I/O, 12 bus signals

• Differential clock (CK/CK#)

❐ 3.0V I/O, 11 bus signals

• Single ended clock (CK)

❐ Chip Select (CS#)

❐ 8-bit data bus (DQ[7:0])

❐ Read-Write Data Strobe (RWDS)

• Bidirectional Data Strobe/Mask

• Output at the start of all transactions to indicate refresh

latency

• Output during read transactions as Read Data Strobe

• Input during write transactions as Write Data Mask (Hyper-

RAM only)

Cypress Semiconductor Corporation

Document Number: 002-03902 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 23, 2017

S71KS512SC0

S71KL256SC0

S71KL512SC0

SUPPLEMENT

Contents

General Description .........................................................3

HyperBus MCP Family with HyperFlash

Ordering Part Numbers ..................................................11

Valid Combinations - Standard ..................................11

Valid Combinations — Automotive Grade /

and HyperRAM ............................................................3

HyperBus MCP 3 V Signal Descriptions .........................4

HyperBus MCP Block Diagram .......................................5

Physical Interface .............................................................6

HyperBus MCP — FBGA 24-Ball,

5x5 Array Footprint ......................................................6

Physical Diagram ........................................................7

Electrical Specifications ..................................................8

Absolute Maximum Ratings .........................................8

DC Characteristics ......................................................8

AEC-Q100 .................................................................12

Document History Page .................................................13

Sales, Solutions, and Legal Information ......................14

Worldwide Sales and Design Support .......................14

Products ....................................................................14

PSoC® Solutions ......................................................14

Cypress Developer Community .................................14

Technical Support .....................................................14

Document Number: 002-03902 Rev. *D

Page 2 of 14

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General Description

This supplementary datasheet provides MCP device related information for a HyperBus MCP family, incorporating both HyperFlash

and HyperRAM memories. The document describes how the features, operation, and ordering options of the related memories have

been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document

modifies any information on the same topics established by the documents listed in Table 1 and should be used in conjunction with

those documents. This document may also contain information that was not previously covered by the listed documents. The infor-

mation is intended for hardware system designers and software developers of applications, operating systems, or tools.

Table 1. Affected Documents/Related Documents

Title

Cypress Publication Number

HyperBus™ Specification Low Signal Count, High Performance DDR Bus

001-99253

S26KL512S / S26KS512S / S26KL256S / S26KS256S / S26KL128S / S26KS128S, 512 MBIT

(64 MBYTE), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V HyperFlash^TMFamily

001-99198

001-97964

S27KL0641, S27KS0641, S71KL1281, S71KS1281: HyperRAM™ Self-Refresh DRAM 3.0V/

1.8V 64/128 Mbit (8/16 Mbyte)

HyperBus MCP Family with HyperFlash and HyperRAM

For systems needing both Flash and self-refresh DRAM, the HyperBus products family includes MCP devices that combine

HyperFlash and HyperRAM in a single package. AHyperBus MCP reduces board space and Printed Circuit Board (PCB) signal routing

congestion while also maintaining or improving signal integrity over separately packaged memory configurations.

The HyperBus MCP family offers 1.8V/3V interface HyperFlash densities of 512 Mb (64 Mbyte) and 256 Mb (32 Mbyte) in

combination with HyperRAM 64 Mb (8 Mbyte).

This supplemental datasheet addresses only the MCP related differences from the HyperBus Specification and the individual

HyperFlash and HyperRAM datasheets. For all other information related to the individual memories in the MCP, refer to the

HyperBus, HyperFlash, and HyperRAM datasheets.

Document Number: 002-03902 Rev. *D

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HyperBus MCP 3 V Signal Descriptions

Figure 1. HyperBus MCP Signal Diagram

RESET#

CS1#

CS2#

DQ[7:0]

RWDS

CK#

INT#

RSTO#

Table 2. Signal Descriptions

Symbol

Type

Description

Chip Select 1: Chip Select for the HyperFlash memory. HyperBus transactions are initiated

with a High to Low transition. HyperBus transactions are terminated with a Low to High

transition.

CS1#

Input

Chip Select 2: Chip Select for the HyperRAM memory. HyperBus transactions are initiated

with a High to Low transition. HyperBus transactions are terminated with a Low to High

transition.

CS2#

Single-ended Clock 3.0V: Command-Address/Data information is input or output with respect

to the edges of the CK.

Note: Single-ended clock is available on 3.0V devices only.

Differential Clock 1.8V: Command-Address/Data information is input or output with respect to

the crossing edges of the CK/CK# pair.

Note: Differential clock is available on 1.8V devices only.

CK/CK#

Read-Write Data Strobe: Output data during read transactions are edge aligned with RWDS.

RWDS is an input during write transactions to function as a HyperRAM data mask. At the

beginning of all bus transactions RWDS is an output and indicates whether additional initial

latency count is required.

RWDS

Output

1 = Additional latency count

0 = No additional latency count

Data Input/Output: Command-Address/Data information is transferred on these DQs during

Read and Write transactions.

DQ[7:0]

INT#

Input/Output

INT Output (Optional): When Low, the HyperFlash device is indicating that an internal event

Output (open drain) has occurred. This signal is intended to be used as a system level interrupt for the device to

indicate that an on-chip event has occurred. INT# is an open-drain output.

Hardware RESET (Optional): When Low, the HyperFlash memory will self initialize and return

to the idle state.

RWDS and DQ[7:0] is placed into the High-Z state when RESET# is Low. RESET# includes

a weak pull-up, if RESET# is left unconnected it will be pulled up to the High state.

RESET# is not connected to the HyperRAM.

RESET#

RSTO#

Input

RSTO# Output (Optional): RSTO# is an open-drain output used to indicate when a POR is

occurring within the HyperFlash memory and can be used as a system level reset signal. Upon

completion of the internal POR the RSTO# signal will transition from Low to high impedance

after a user defined timeout period has elapsed. Upon transition to the high impedance state

the external pull-up resistance will pull RSTO# High and the device immediately is placed into

the Idle state.

Output (open drain)

Power Supply

Core Power

Input/Output Power

Core Ground

Input/Output Ground

Document Number: 002-03902 Rev. *D

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HyperBus MCP Block Diagram

Figure 2. HyperBus Connections Including Optional Signals

MCP

Master

Slave 0

HyperFlash

CS1#

CS0#

CS#

CK#

DQ[7:0]

RWDS

DQ[7:0]

RWDS

RESET#

RSTO#

INT#

RESET#

RSTO#

INT#

CS2#

CS1#

Slave 1

HyperRAM

CS#

CK#

DQ[7:0]

RWDS

Note

1. CK# is for 1.8V devices only.

Document Number: 002-03902 Rev. *D

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Physical Interface

HyperBus MCP — FBGA 24-Ball, 5x5 Array Footprint

Figure 3. 24-Ball FBGA, 6 x 8 mm, 5 x 5 Ball Footprint (Top View)

RSTO#

INT#

RFU

CS2# RESET#

CK#

V_SS

V_CC

V_SS

CS1#

DQ1

DQ6

RFU

DQ4

RWDS DQ2

V_CC

DQ0

DQ5

DQ3

DQ7

V_SSQ

V_CCQ

Notes

2. C2 and A3 are chip select (CS#) signals 1 and 2 used for HyperFlash and HyperRAM devices respectively.

3. and V are internally connected.

SSQ

4. CK# (B1) is RFU in 3.0V devices

Document Number: 002-03902 Rev. *D

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Physical Diagram

Figure 4. ELA024 — FBGA 24-Ball 6 x 8 x 1 mm

NOTES:

DIMENSIONS

SYMBOL

MIN.

NOM.

MAX.

1.00

1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

0.20

3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

8.00 BSC

"e" REPRESENTS THE SOLDER BALL GRID PITCH.

6.00 BSC

4.00 BSC

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE

POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

0.40

0.35

0.45

1.00 BSC

0.00 BSC

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION

OR OTHER MEANS.

JEDEC SPECIFICATION NO. REF: N/A

10.

CYPRESS

Company Confidential

TITLE

PACKAGE OUTLINE, 24 BALL BGA

8.0X6.0X1.0 MM VAA024/ELA024/E2A024

DRAWN BY

KOTA

DATE

THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS

SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS

MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.

SPEC NO.

REV

30-AUG-16

PACKAGE

CODE(S)

002-15550

SCALE :

TO FIT

VAA024 ELA024 E2A024

APPROVED BY

BESY

DATE

30-AUG-16

SHEET

Document Number: 002-03902 Rev. *D

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Electrical Specifications

For the general description of the HyperBus interface electrical

specifications, refer to the HyperBus Specification. The following

section describes HyperFlash device dependent aspects of

electrical specifications.

■ Program or erase current will be that of the HyperFlash device.

Note however, that program and erase operations are long time

frame events that extend beyond the duration of a HyperFlash

chip select period. Thus, if the HyperRAM is selected for read

or write during an on going HyperFlash program or erase

operation, the active current will be the sum of the HyperFlash

program or erase operation and the HyperRAM read or write

current.

Absolute Maximum Ratings

Ambient Temperature with Power Applied: 65 °C to +105 °C

DC Characteristics

■ Standby current, when neither memory is selected and no

embedded flash operation is in progress, is the sum of the

memory standby currents.

Only one memory may have its chip select active (Low) at any

point in time. For each of the conditions below refer to the Hyper-

Flash and HyperRAM datasheets for the most accurate infor-

mation:

■ Deep Power Down (DPD) current, is the sum of the memory

DPD currents.

■ Active core read or write current will be that of the selected

device plus the standby current of the non-selected device. But,

the added standby current is generally not significant as it is

less than 300 A.

■ Power On Reset (POR) current is the sum of the memory

standby currents.

■ Input leakage current is the sum of the memory input leakage

currents.

■ Active IO read current will be that of the selected device.

For reference purpose, Table 3 aids in the estimation of the

above operating conditions current consumption. However, refer

to the HyperFlash and HyperRAM datasheets for the most

accurate information.

■ Active clock stop current will be that of the selected device plus

the standby current of the non-selected device. But, the added

standby current is generally not significant as it is less than

300 A.

Document Number: 002-03902 Rev. *D

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Table 3. 3.0V DC Characteristics (CMOS Compatible)

Parameter Description

Test Conditions

Min

Typ^[6]

Max Unit

V_IN= V_SSto V_CC

V_CC= V_CCmax

I_LI

Input Leakage Current



±4.0

±2.0

µA

_OUT= V_SSto V_CC

_CC= V_CCmax

I_LO

Output Leakage Current



80.2

130.2

CS# = V_IL, @100 MHz,

V_CC= 3.6V

100.3 mA

180.3 mA

V_CCActive Read Current - HyperFlash reading

(core current only, IO switching current is not

included)

I_CC1HF

CS# = V_IL, @166 MHz,

V_CC= 1.95V

CS# = V_IL, @100 MHz,

100

35.3

60.3

35.3

60.3

135

160

135

160

V_CCQ = 3.6V, C_LOAD= 20 pF

V_CCQ Active Read Current of IOs - HyperFlash

reading

I_IO1HF

CS# = V_IL, @166 MHz,

V_CCQ = 1.95V, C_LOAD= 20 pF

CS# = V_IL, @100 MHz,

V_CC= 3.6V

20.1

15.1

I_CC1HR

V_CCActive Read Current - HyperRAM reading

V_CCActive Write Current - HyperRAM writing

CS# = V_IL, @166 MHz,

V_CC= 1.95V

CS# = V_IL, @100 MHz,

V_CC= 3.6V

I_CC2HR

CS# = V_IL, @166 MHz,

V_CC= 1.95V

CS# = V_IL, @100 MHz,

V_CC= 3.6V

V_CCActive Read Current - HyperFlash embedded

operation plus HyperRAM reading^[6]

I_CC1HFHR

CS# = V_IL, @166 MHz,

V_CC= 1.95V

CS# = V_IL, @100 MHz,

V_CC= 3.6V

V_CCActive Write Current - HyperFlash embedded

operation plus HyperRAM writing^[6]

I_CC2HFHR

CS# = V_IL, @166 MHz,

V_CC= 1.95V

I_CC3P

I_CC3E

V_CCActive Program Current^{[5, 6]}

V_CCActive Erase Current^{[5, 6]}

V_CC= V_CCmax



100

V_CCStandby Current for Industrial Temperature (– CS#, RESET# = V_CC

I_CC4I

I_CC4IC

I_CC5



160

300

600

µA

40 °C to +85 °C)

V_CC= V_CCmax

V_CCStandby Current for Industrial Plus

Temperature (–40 °C to +105 °C)

CS#, RESET# = V_CC

V_CC= V_CCmax

CS# = V_IH,RESET# = V_SS

V_CC= V_CCmax (1.8V/3.0V)

V_CCReset Current

V_IH= V_CC, V_IL= V_SS

I_CC6

Active Clock Stop Mode^[7]

V_CCCurrent during Power-Up (POR)

11.3

100

V_CC= 1.95V/3.6V

CS# = X, V_CC= V_CCmax

(1.95V/3.6V)

I_CC7

135

Notes

6. Not 100% tested.

7. Active Clock Stop Mode enables the lower power mode when the CK signals remain stable for t

active while Embedded Algorithm is in progress.

+ 30 ns

for 85 °C and 105 °C).

ACC

DPD

8. Typical I values are measured at t = 25 °C and V = V = 1.8V/3.0V (not applicable to I

CCQ

Document Number: 002-03902 Rev. *D

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Table 3. 3.0V DC Characteristics (CMOS Compatible) (Continued)

Parameter

Description

Test Conditions

Min



Typ^[6]

34.1

36.6

37.4

Max Unit

Deep Power-Down Current 512/64 Mb @ 25°C

Deep Power-Down Current 512/64 Mb @ 85°C

Deep Power-Down Current 512/64 Mb @ 105°C

112

120

340

µA

CS#, RESET#,



V_CC= V_CCmax (1.95V/3.6V)

HyperFlash in Standby



Deep Power-Down Current (all other densities) @

25°C



34.1

37.4

112

140

340

µA

Deep Power-Down Current (all other densities) @

85°C

HyperRAM in Deep Power

Down

Deep Power-Down Current (all other densities) @

105°C

I_DPD

Deep Power-Down Current 512/64 Mb @ 25°C

Deep Power-Down Current 512/64 Mb @ 85°C

Deep Power-Down Current 512/64 Mb @ 105°C

143

165

230

218

250

350

µA

CS#, RESET#,

V_CC= V_CCmax (1.95V/3.6V)

Deep Power-Down Current (all other densities) @

25°C

HyperFlash in Deep Power

Down

138

139

140

206

210

215

µA

Deep Power-Down Current (all other densities) @

85°C

HyperRAM in Standby

Deep Power-Down Current (all other densities) @

105°C

Notes

6. Not 100% tested.

7. Active Clock Stop Mode enables the lower power mode when the CK signals remain stable for t

active while Embedded Algorithm is in progress.

+ 30 ns

for 85 °C and 105 °C).

ACC

DPD

8. Typical I values are measured at t = 25 °C and V = V = 1.8V/3.0V (not applicable to I

CCQ

Table 4. 1.8V/3.0V Capacitive Characteristics

Description

Parameter

Min

Max

Unit

Input Capacitance (CK, CK#)^[7,8,9]

6.0

10.0

10.5

10.0

10.5

1.0

S71KL/S512SC0

S71KL/S256SC0

S71KL/S512SC0

S71KL/S256SC0

Output Capacitance (RWDS)^[7,8,9]

8.0

—

I/O Pin Capacitance (DQx)^[7,8,9]

CIO

I/O Pin Capacitance Delta (DQx)^[7,8,9]

INT#, RSTO# Pin Capacitance, RST#^[7,8,9]

CIOD

COP

—

8.0

Notes

9. These values are guaranteed by design and are tested on a sample basis only.

10. Pin capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. V

Q are applied and all other pins

CC, CC

(except the pin under test) floating. DQs should be in the High Impedance state.

11. The capacitance values for the CK, CK#, RWDS and DQx pins must have similar capacitance values to allow for signal propagation time matching in the system. The

capacitance value for CS# is not as critical because there are no critical timings between CS# going active (Low) and data being presented on the DQs bus.

Document Number: 002-03902 Rev. *D

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Ordering Part Numbers

The ordering part number is formed by a valid combination of the following:

S71KL

512

Packing Type

0 = Tray

3 = 13” Tape and Reel

Model Number (Additional Ordering Options)

00 = 100/166 MHz FBGA, 24-ball, 6 x 8 x 1.0 mm package (ELA024) 3.0V/1.8V

Temperature Range

I = Industrial (–40 °C to +85 °C)

V = Industrial Plus (–40 °C to +105 °C)

A = Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)

B = Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)

Package Materials

H = Low-Halogen, Lead (Pb)-free

Package Type

B = 24-ball FBGA 6 x 8 mm package, 1.00 mm pitch

HyperRAM Density

C0 = 64 Mb

HyperFlash Device Technology

S = 65 nm MirrorBit Process Technology

HyperFlash Density

256 = 256 Mb

512 = 512 Mb

Device Family

S71KL — Cypress HyperBus MCP, 3.0V-Only

S71KS — Cypress HyperBus MCP, 1.8V-Only

Valid Combinations - Standard

Table 5 lists configurations planned to be available in volume. The table will be updated as new combinations are released. Contact

your local sales representative to confirm availability of specific combinations and to check on newly released combinations.

Table 5. Valid Standard Combinations

Package

HyperRAM

Density

Temperature Model Packing

Ordering Part Number

(x = Packing Type)

Device Number

and

Material

Package Marking

Range

Number

Type

S71KL256SC0BHI00x

S71KL256SC0BHV00x

S71KL512SC0BHI00x

S71KL512SC0BHV00x

S71KS512SC0BHI00x

S71KS512SC0BHV00x

1KL256SC0HI00

1KL256SC0HV00

1KL512SC0HI00

1K5L12SC0HV00

1KS512SC0HI00

1KS512SC0HV00

S71KL256S

S71KL512S

S71KS512S

Note

I, V

0, 3

I, V

0, 3

12. FBGA package marking omits the leading S7, the package type character and packing type character from the ordering part number from the ordering part number.

Document Number: 002-03902 Rev. *D

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Valid Combinations — Automotive Grade / AEC-Q100

Table 6 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table

will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific

combinations and to check on newly released combinations.

Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.

Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in

combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with

ISO/TS-16949 requirements.

AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949

compliance.

Table 6. Valid Combinations — Automotive Grade / AEC-Q100

Package

HyperRAM

Density

Temperature Model Packing

Ordering Part Number

(x = Packing Type)

Device Number

and

Material

Package Marking

Range

Number Type

S71KL256S

A, B

0, 3

S71KL256SC0BHA00x

S71KL256SC0BHB00x

S71KL512SC0BHA00x

S71KL512SC0BHB00x

S71KS512SC0BHA00x

S71KS512SC0BHB00x

1KL256SC0HA00

1KL256SC0HB00

1KL512SC0HA00

1KL512SC0HB00

1KS512SC0HA00

1KS512SC0HB00

S71KL512S

S71KS512S

A, B

Note

FBGA package marking omits the leading S7, the package type character and packing type character from the ordering part number from the ordering part number.

Document Number: 002-03902 Rev. *D

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Document History Page

Document Title: S71KS512SC0, S71KL256SC0, S71KL512SC0, HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V

Document Number: 002-03902

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

5023814

MAMC

11/23/2015 Initial release.

Updated HyperBus MCP 3 V Signal Descriptions:

Updated Table 2:

Updated details in “Description” column corresponding to RESET# pin.

Updated HyperBus MCP Block Diagram.

Updated Physical Interface:

Updated HyperBus MCP — FBGA 24-Ball, 5x5 Array Footprint:

Added Note 2.

Updated Physical Diagram:

07/07/2016 Added Figure 4.

5188954

RYSU

Updated Electrical Specifications:

Updated DC Characteristics:

Updated Table 3:

Changed typical value of I_CC5parameter from 20 mA to 10 mA.

Changed maximum value of I_CC5parameter from 40 mA to 20 mA.

Updated Table 4:

Updated values of all parameters.

Updated to new template.

Updated Document Title to read as “S71KL512SC0, HyperFlash™ and

HyperRAM™ Multi-Chip Package 3V”.

Removed part number “S71KL256SC0” related information in all instances

across the document.

Removed 256 Mb density related information in all instances across the

document.

Updated Ordering Part Numbers:

Added Automotive, AEC-Q100 Grade 3 and Automotive, AEC-Q100 Grade 2

Temperature Range details.

5442136

RYSU

09/27/2016

Removed 128 Mb, 256 Mb details.

Updated Valid Combinations - Standard:

Removed S71KL256S and its corresponding details.

Added Valid Combinations — Automotive Grade / AEC-Q100.

Updated to new template.

Updated Document Title to read as “S71KL256SC0/S71KL512SC0,

HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V”.

Added part number “S71KL256SC0” related information in all instances across

the document.

Added 256 Mb density related information in all instances across the document.

Updated Electrical Specifications:

Updated DC Characteristics:

12/20/2016 Updated Table 4:

Added values corresponding to S71KL256SC0.

5560279

5635102

RYSU

Updated Ordering Part Numbers:

Added 256 Mb details.

Updated Valid Combinations - Standard:

Added S71KL256S and its corresponding details.

Updated Valid Combinations — Automotive Grade / AEC-Q100:

Added S71KL256S and its corresponding details.

Added S71KS512S and its corresponding details.

Updated Sales and Copyright information.

SZZX

02/23/2017

Document Number: 002-03902 Rev. *D

Page 13 of 14

S71KS512SC0

S71KL256SC0

S71KL512SC0

SUPPLEMENT

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-03902 Rev. *D

Revised February 23, 2017

Page 14 of 14

S71KS512SC0BHV000 [INFINEON]

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