SAB-C502-LP_技术文档

Microcomputer Components

8-Bit CMOS Microcontroller

C502

Data Sheet 08.94

8-Bit CMOS Microcontroller

C502

Preliminary

● Fully compatible to standard 8051 microcontroller

● Versions for 12 / 20 MHz operating frequency

● 16 K × 8 ROM (SAB-C502-2R only)

● 256 × 8 RAM

● 256 × 8 XRAM (additional on-chip RAM)

● Eight datapointers for indirect addressing of program and external data memory

(including XRAM)

● Four 8-bit ports

● Three 16 -bit Timers / Counters (Timer 2 with Up/Down Counter feature)

● USART with programmable 10-bit Baudrate-Generator

● Six interrupt sources, two priority levels

● Programmable 15-bit Watchdog Timer

● Oscillator Watchdog

● Fast Power On Reset

● Power Saving Modes

● P-DIP-40 package and P-LCC-44 package

● Temperature ranges:

SAB-C502

SAF-C502

T_A: 0 ˚C to 70 ˚C

T_A: – 40 ˚C to 85 ˚C

SAB-C502

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08.94

C502

The SAB-C502-L/C502-2R described in this document is compatible with the SAB 80C52 and can

be used for all present SAB 80C52 applications.

The SAB-C502-2R contains a non-volatile 16 K × 8 read-only program memory, a volatile 256 × 8

read/write data memory, four ports, three 16-bit timers/counters, a six source, two priority level

interrupt structure, a serial port and versatile fail save mechanisms. The SAB-C502-L/C502-2R

incorporates 256 × 8 additional on-chip RAM called XRAM. For higher performance eight

datapointers are implemented. The SAB-C502-L is identical, except that it lacks the program

memory on chip. Therefore the term SAB-C502 refers to both versions within this specification

unless otherwise noted.

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C502

Ordering Information

Type

Ordering

Code

Package

Description

(8-Bit CMOS microcontroller)

SAB-C502-LN

SAB-C502-LP

Q67120-C838 P-LCC-44 for external memory 12 MHz

Q67120-C889 P-DIP-40

SAB-C502-2RN

SAB-C502-2RP

Q67120-C839 P-LCC-44 with mask-programmable ROM,

Q67120-C890 P-DIP-40

12 MHz

SAB-C502-L20N

SAB-C502-L20P

Q67120-C885 P-LCC-44 for external memory 20 MHz

Q67120-C891 P-DIP-40

SAB-C502-2R20N

SAB-C502-2R20P

Q67120-C884 P-LCC-44 with mask-programmable ROM,

Q67120-C892 P-DIP-40

Q67120-C883 P-LCC-44 for external ROM, 12 MHz,

Q67120-C893 P-DIP-40 ext. temp. – 40 ˚C to 85 ˚C

Q67120-C886 P-LCC-44 with mask-programmable ROM,

Q67120-C894 P-DIP-40 12 MHz, ext. temp. – 40 ˚C to 85 ˚C

Q67120-C887 P-LCC-44 for external memory, 20 MHz,

Q67120-C895 P-DIP-40 ext. temp. – 40 ˚C to 85 ˚C

Q67120-C888 P-LCC-44 with mask-programmable ROM,

Q67120-C896 P-DIP-40 20 MHz, ext. temp. – 40 ˚C to 85 ˚C

20 MHz

SAF-C502-LN

SAF-C502-LP

SAF-C502-2RN

SAF-C502-2RP

SAF-C502-L20N

SAF-C502-L20P

SAF-C502-2R20N

SAF-C502-2R20P

Note: Extended temperature range – 40 ˚C to 110 ˚C (SAH-C502) on request.

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C502

Pin Configuration

(top view)

(P-LCC-44)

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C502

Pin Configuration

(top view)

(P-DIP-40)

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C502

Logic Symbol

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C502

Pin Definitions and Functions

Symbol

Pin Number

P-LCC-44 P-DIP-40

I/O*) Function

P1.7 – P1.0

9–2

8–1

I

Port 1

is a bidirectional I/O port with internal pull-up

resistors. Port 1 pins that have 1s written to

them are pulled high by the internal pull-up

resistors, and in that state can be used as

inputs. As inputs, port 1 pins being externally

pulled low will source current (I_IL, in the DC

characteristics) because of the internal pull-up

resistors. Port 1 also contains the timer 2 pins

as secondary function. The output latch corre-

sponding to a secondary function must be pro-

grammed to a one (1) for that function to

operate.

The secondary functions are assigned to the

pins of port 1, as follows:

2

3

1

2

P1.0 T2

Input to counter 2

P1.1 T2EX Capture - Reload trigger of

timer 2 / Up-Down count

*) I = Input

O = Output

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C502

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

P-LCC-44 P-DIP-40

11, 13–19 10–17

I/O*) Function

P3.0 – P3.7

I/O

Port 3

is a bidirectional I/O port with internal pull-up

resistors. Port 3 pins that have 1s written to

them are pulled high by the internal pull-up

resistors, and in that state can be used as

inputs. As inputs, port 3 pins being externally

pulled low will source current (I_IL, in the DC

characteristics) because of the internal pull-up

resistors. Port 3 also contains the interrupt,

timer, serial port 0 and external memory strobe

pins that are used by various options. The out-

put latch corresponding to a secondary func-

tion must be programmed to a one (1) for that

function to operate.

The secondary functions are assigned to the

pins of port 3, as follows:

11

13

10

11

P3.0 R×D receiver data input

(asynchronous) or data input/

output (synchronous) of serial

interface 0

P3.1 T×D transmitter data output

(asynchronous) or clock output

(synchronous) of the serial

interface 0

14

15

12

13

P3.2 INT0 interrupt 0 input/timer 0 gate

control

P3.3 INT1 interrupt 1 input/timer 1 gate

control

16

17

18

14

15

16

P3.4 T0

P3.5 T1

P3.6 WR

counter 0 input

counter 1 input

the write control signal latches

the data byte from port 0 into the

external data memory

the read control signal enables

the external data memory to

port 0

19

20

17

18

P3.7 RD

XTAL2

–

XTAL2

Output of the inverting oscillator amplifier

*)I = Input

O = Output

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C502

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

I/O*) Function

P-LCC-44 P-DIP-40

XTAL1

21

19

–

XTAL1

Input to the inverting oscillator amplifier and

input to the internal clock generator circuits.

To drive the device from an external clock

source, XTAL1 should be driven, while XTAL2

is left unconnected. There are no requirements

on the duty cycle of the external clock signal,

since the input to the internal clocking circuitry

is divided down by a divide-by-two flip-flop.

Minimum and maximum high and low times as

well as rise fall times specified in the AC

characteristics must be observed.

P2.0 – P2.7

24–31

21–28

I/O

Port 2

ia a bidirectional I/O port with internal pull-up

resistors. Port 2 pins that have 1s written to

them are pulled high by the internal pull-up

resistors, and in that state can be used as

inputs. As inputs, port 2 pins being externally

pulled low will source current (I_IL, in the DC

characteristics) because of the internal pull-up

resistors. Port 2 emits the high-order address

byte during fetches from external program

memory and during accesses to external data

memory that use 16-bit addresses (MOVX

@DPTR). In this application it uses strong

internal pull-up resistors when issuing 1s.

During accesses to external data memory that

use 8-bit addresses (MOVX @Ri), port 2

issues the contents of the P2 special function

register.

PSEN

32

29

O

The Program Store Enable

output is a control signal that enables the

external program memory to the bus during

external fetch operations. It is activated every

six oscillator periodes except during external

data memory accesses. Remains high during

internal program execution.

*) I = Input

O = Output

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C502

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

I/O*) Function

P-LCC-44 P-DIP-40

RESET

10

33

35

9

I

RESET

A high level on this pin for two machine cycles

while the oscillator is running resets the

device. An internal diffused resistor to V_SS

permits power-on reset using only an external

capacitor to V_CC.

ALE

EA

30

31

O

The Address Latch Enable

output is used for latching the low-byte of the

address into external memory during normal

operation. It is activated every six oscillator

periodes except during an external data

memory access.

I

External Access Enable

When held at high level, instructions are

fetched from the internal ROM (SAB-C502-2R

only) when the PC is less than 4000 . When

H

held at low level, the SAB-C502 fetches all

instructions from external program memory.

For the SAB-C502-L this pin must be tied low.

P0.0 – P0.7

43–36

39–32

I/O

Port 0

is an 8-bit open-drain bidirectional I/O port.

Port 0 pins that have 1s written to them float,

and in that state can be used as high-

impedance inputs. Port 0 is also the

multiplexed low-order address and data bus

during accesses to external program or data

memory. In this application it uses strong

internal pull-up resistors when issuing 1s.

Port 0 also outputs the code bytes during

program verification in the SAB-C502-2R.

External pull-up resistors are required during

program verification.

V_SS

22

44

20

40

–

Circuit ground potential

Supply terminal for all operating modes

No connection

V_CC

N.C.

1, 12,

23, 34

*) I = Input

O = Output

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C502

Functional Description

The SAB-C502 is fully compatible to the standard 8051 microcontroller family.

It is compatible with the SAB 80C52. While maintaining all architectural and operational

characteristics of the SAB 80C52 the SAB-C502 incorporates some enhancements in the Timer2

and Fail Save Mechanism Unit.

Figure 1 shows a block diagram of the SAB-C502.

Figure 1

Block Diagram of the SAB-C502

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C502

CPU

The SAB-C502 is efficient both as a controller and as an arithmetic processor. It has extensive

facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of

program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and

15 % three-byte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1.0 µs

(18 MHz : 667 ns).

Special Function Register PSW

MSB

7

LSB

0

Bit No.

6

5

4

3

2

1

Addr. D0

CY

AC

F0

RS1

RS0

OV

F1

P

PSW

H

Bit

CY

AC

F0

Function

Carry Flag

Auxiliary Carry Flag (for BCD operations)

General Purpose Flag

RS1

RS0

Register Bank select control bits

0

1

0

1

0

1

Bank 0 selected, data address 00 - 07

H

Bank 1 selected, data address 08 - 0F

H

Bank 2 selected, data address 10 - 17

Bank 3 selected, data address 18 - 1F

H

OV

F1

P

Overflow Flag

General Purpose Flag

Parity Flag.

Set/cleared by hardware each instruction cycle to indicate an odd/

even number of “one” bits in the accumulator, i.e. even parity.

Reset value of PSW is 00H.

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C502

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the

special function register area.

The 36 special function register (SFR) include pointers and registers that provide an interface

between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits

within the SFR area.

All SFRs are listed in table 1, table 2 and table 3. In table 1 they are organized in numeric order

of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the

SAB-C502. Table 3 illustrates the contents of the SFRs.

Table 1

Special Function Register in Numeric Order of their Addresses

Address

Register

Contents

Address

Register

Contents

after Reset

80

H

P0 ¹⁾

SP

DPL

FF

H

98

H

SCON¹⁾

SBUF

00

H

2)

XX

81

H

07

H

99

H

2)

XX

82

H

00

H

00

H

9A

H

reserved

H

2)

XX

83

H

DPH

9B

H

2)

XX

84

H

reserved

WDTREL

PCON

9C

H

2)

XX

85

H

9D

H

2)

XX

86

H

00

H

000X0000

9E

H

2)

B

2)

XX

87

H

9F

H

1)

88

H

TCON

TMOD

TL0

00

H

A0

H

P2 ¹⁾

FF

H

2)

XX

89

H

00

H

A1

H

reserved

H

2)

XX

8A

H

00

H

A2

H

2)

XX

8B

H

TL1

TH0

TH1

00

H

A3

H

2)

XX

8C

H

00

H

A4

H

2)

XX

8D

H

00

A5

H

2)

XX

2)

XX

8E

H

reserved

A6

H

2)

XX

2)

XX

8F

H

A7

H

2)

90

H

P1 ¹⁾

FF

H

A8

H

IE¹⁾

reserved

SRELL

reserved

0X000000

B

2)

91

H

XPAGE

DPSEL

reserved

XCON

reserved

00

H

A9

H

XX

H

2)

92

H

XXXXX000

AA

H

D9

B

2)

XX

93

H

XX

F8

AB

H

2)

XX

94

H

AC

H

2)

XX

2)

XX

95

H

AD

H

2)

XX

2)

XX

96

H

AE

H

2)

XX

2)

XX

97

H

AF

H

¹⁾: Bit-addressable Special Function Register

²⁾: X means that the value is indeterminate and the location is reserved

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C502

Table 1

Special Function Register in Numeric Order of their Addresses (cont’d)

Address

Register

Contents

Address

Register

Contents

after Reset

2)

B0

H

P3¹⁾

FF

H

D8

H

BAUD

0XXXXXXX

B

2)

XX

B1

H

SYSCON

reserved

XXXXXX01

D9

H

reserved

B

H

2)

XX

2)

XX

B2

H

DA

H

2)

XX

2)

XX

B3

H

DB

H

2)

XX

2)

XX

B4

H

DC

H

2)

XX

2)

XX

B5

H

DD

H

2)

XX

2)

XX

N6

H

DE

H

2)

XX

2)

XX

B7

H

DF

H

2)

B8

H

IP¹⁾

reserved

SRELH

reserved

X0000000

E0

H

ACC ¹⁾

00

B

H

2)

XX

B9

H

XX

E1

H

reserved

H

2)

XX

BA

H

XXXXXX11

E2

H

B

H

2)

XX

BB

H

XX

E3

H

2)

XX

2)

XX

BC

H

E4

H

2)

XX

2)

XX

BD

H

E5

H

2)

XX

2)

XX

BE

H

E6

H

2)

XX

2)

XX

BF

H

E7

H

2)

XX

C0

H

WDCON¹⁾

reserved

XXXX0000

E8

H

reserved

B

H

2)

XX

C1

H

XX

E9

H

2)

XX

C2

H

EA

H

2)

XX

C3

H

EB

H

2)

XX

C4

H

EC

H

2)

XX

C5

H

ED

H

2)

XX

C6

H

EE

H

2)

XX

C7

H

EF

H

C8

H

T2CON¹⁾

T2MOD

RC2L

RC2H

TL2

TH2

reserved

00

F0

H

B¹⁾

00

H

2)

XX

C9

H

XXXXXXX0

F1

H

reserved

B

H

2)

XX

CA

H

00

H

00

H

F2

H

2)

XX

CB

H

F3

H

2)

XX

CC

H

F4

H

2)

XX

CD

H

00

F5

H

2)

XX

2)

XX

CE

H

F6

H

2)

XX

2)

XX

CF

H

F7

H

2)

XX

D0

H

PSW¹⁾

00

F8

H

reserved

H

2)

XX

2)

XX

D1

H

reserved

F9

H

2)

XX

2)

XX

D2

H

FA

H

2)

XX

2)

XX

D3

H

FB

H

2)

XX

2)

XX

D4

H

FC

H

2)

XX

2)

XX

D5

H

FD

H

2)

XX

2)

XX

D6

H

FE

H

2)

XX

2)

XX

D7

H

FF

H

¹⁾: Bit-addressable Special Function Register

²⁾: X means that the value is indeterminate and the location is reserved

Semiconductor Group

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C502

Table 2

Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents

after Reset

1)

E0

CPU

ACC

B

Accumulator

B-Register

00

H

1)

F0

00

H

DPH

DPL

DPSEL

PSW

SP

Data Pointer, High Byte

Data Pointer, Low Byte

Data pointer select register

Program Status Word Register

Stack Pointer

83

00

H

82

H

00

H

3)

B

92

XXXX X000

H

1)

D0

00

07

H

81

H

1)

A8

3)

Interrupt

System

IE

IP

Interrupt Enable Register

Interrupt Priority Register

0X00 0000

X000 0000

H

B

1)

B8

3)

H

1)

80

Ports

P0

P1

P2

P3

Port 0

Port 1

Port 2

Port 3

FF

H

1)

90

FF

H

1)

A0

FF

H

1)

B0

FF

H

XRAM

XPAGE

XCON

Page addr. reg. for XRAM

XRAM startaddress (highbyte)

91

H

00

H

94

H

F8

H

3)

SYSCON XRAM control register

B1

H

XXXX XX01

B

Serial

Channels

PCON²⁾

SBUF

SCON

SRELL

SRELH

BAUD

Power Control Register

Serial Channel Buffer Reg.

Serial Channel Control Reg.

Baudrate Generator Reloadvalue, Lowbyte

Baudrate Generator Reloadvalue, Highbyte BA

87

H

00

H

3)

XX

99

H

1)

98

00

H

AA

D9

H

3)

XXXX XX11

0XXX XXXX

H

B

1)

Baudrate Generator Enable Bit

D8

1)

Timer 0/

Timer 1

TCON

TH0

TH1

TL0

TL1

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88

8C

8D

8A

00

H

00

H

00

H

00

H

8B

89

00

H

TMOD

00

H

1)

Timer 2

T2CON

T2MOD

RC2L

RC2H

TH2

Timer 2 Control Register

Timer 2 Mode Register

Timer 2, Reload Capture Register, Low Byte CA

Timer 2, Reload Capture Register, High Byte CB

Timer 2, High Byte

Timer 2, Low Byte

C8

00

H

XXXX XXX0

H

3)

B

C9

H

00

H

00

H

CD

00

H

TL2

CC

00

H

1)

3)

Watchdog WDCON Watchdog Timer Control Register

WDTREL Watchdog Timer Reload Reg.

C0

XXXX 0000

H

B

86

00

H

Pow. Sav. PCON²⁾

Modes

Power Control Register

87

000X 0000

3)

H

B

¹⁾: Bit-addressable special function registers

²⁾: This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

³⁾: X means that the value is indeterminate and the location is reserved

Semiconductor Group

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C502

Table 3

Contents of SFR’s, SFR’s in Numeric Order

Address Register

Bit 7

6

5

4

3

2

1

0

80

81

82

83

86

87

88

89

P0

SP

H

DPL

DPH

WDTREL

PCON

TCON

TMOD

TL0

SMOD

TF1

PDS

TR1

C/T

IDLS

TF0

M1

–

GF1

IE1

GF0

IT1

PDE

IE0

M1

IDLE

IT0

TR0

M0

GATE

C/T

M0

8A

8B

8C

8D

90

H

TL1

TH0

TH1

P1

H

91

92

94

98

99

XPAGE

DPSEL

XCON

SCON

SBUF

P2

–

.2

.1

TI

.0

SM0

SM1

SM2

REN

TB8

RB8

RI

A0

A8

H

IE

EA

–

ET2

ES

ET1

EX1

ET0

EX0

AA

SRELL

H

bit and byte addressable

not bit addressable

– = reserved

Semiconductor Group

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C502

Table 3

Contents of SFRs, SFRs in Numeric Order (cont’d)

Address Register

Bit 7

6

5

4

3

2

1

0

B0

B1

B8

P3

SYSCON

IP

H

–

XMAP1 XMAP0

PADC

PT2

PS

PT1

PX1

PT0

PX0

BA

C0

C8

C9

SRELH

WDCON

T2CON

T2MOD

RC2L

RC2H

TL2

H

–

OWDS

WDTS

WDT

SWDT

CP/RL2

DCEN

TF2

–

EXF2

–

RCLK

–

TCLK

–

EXEN2

–

TR2

–

C/T2

–

CA

CB

CC

CD

D0

H

TH2

PSW

CY

BD

AC

–

F0

–

RS1

–

RS0

–

OV

–

F1

–

P

–

H

D8

E0

F0

BAUD

ACC

B

H

bit and byte addressable

not bit addressable

– = reserved

Semiconductor Group

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C502

Timer/Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4:

Table 4

Timer/Counter 0 and 1 Operating Modes

Mode Description

TMOD

Gate C/T M1

Input Clock

internal external

(max)

M0

0

8-bit timer/counter with a

X

0

f_{OSC 12 × 32}

/

f_OSC/_{24 × 32}

divide-by-32 prescaler

1

2

16-bit timer/counter

X

0

1

0

f_{OSC 12}

/

f_{OSC 24}

/

8-bit timer/counter with

8-bit auto-reload

f_{OSC 12}

/

f_{OSC 24}

/

3

Timer/counter 0 used as one

8-bit timer/counter and one

8-bit timer

X

1

f_{OSC 12}

/

f_OSC/₂₄

Timer 1 stops

In “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count

rate is f_OSC/12.

In “counter” function the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a

falling edge the max. count rate is f_OSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the

input clock logic.

Figure 2

Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group

18

C502

Timer 2

Timer 2 is a 16-bit Timer/Counter with up/down count feature. It can operate either as timer or as an

event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in

table 5.

Table 5

Timer/Counter 2 Operating Modes

T2CON

T2MOD T2CON

Input Clock

external

P1.1/

T2EX

R×CLK

Mode

Remarks

CP/

or

TR2

internal

RL2

(P1.0/T2)

DCEN

EXEN

T×CLK

16-bit

Auto-

reload

0

1

0

X

reload upon

overflow

reload trigger

(falling edge)

Down counting

Up counting

0

1

↓

max

_OSC/24

f

_OSC/12

f

0

1

X

0

1

16-bit

Cap-

ture

0

1

X

0

X

16-bit Timer/

Counter (only

up-counting)

capture TH2,

TL2 → RC2H,

RC2L

max

_OSC/24

f_OSC/12

0

1

X

1

↓

Baud

Rate

Gene-

rator

1

X

1

X

0

1

X

no overflow

interrupt

request (TF2)

extra external

interrupt

max

_OSC/24

f

_OSC/2

↓

(“Timer 2”)

off

X

0

X

Timer 2 stops

–

Note: ↓ =

falling edge

Semiconductor Group

19

C502

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three

asynchronous modes) as illustrated in table 6. Figure 3 illustrates the block diagram of Baudrate

generation for the serial interface.

Table 6

USART Operating Modes

SCON

Baudrate

Description

Mode

SM0

SM1

0

1

0

f

_OSC/12

Serial data enters and exits through R×D.

T×D outputs the shift clock. 8-bit are

transmitted/received (LSB first)

1

2

3

1

0

1

Timer 1/2 overflow rate

or

Baudrate Generator

8-bit UART

10 bits are transmitted (through T×D) or

received (R×D)

f

_OSC/32 or f_OSC/64

9-bit UART

11 bits are transmitted (T×D) or

received (R×D)

Timer 1/2 overflow rate

or

Baudrate Generator

9-bit UART

Like mode 2 except the variable

baud rate

Figure 3

Block Diagram of Baud Rate Generation for Serial Interface

Semiconductor Group

20

C502

The possible baudrate can be calculated using the formulas given in table 7.

Table 7

Baudrates

Baud Rate

Interface Mode

Baudrate

derived from

Oscillator

0

2

f

_OSC/12

(2^SMOD× f_OSC)/64

Timer 1 (16-bit timer)

(8-bit timer with

1,3

(2^SMOD× timer 1 overflow rate)/32

(2^SMOD× f_OSC)/(32 × 12 × (256-TH1))

8-bit autoreload)

Timer 2

1,3

f

_OSC/(32 × (65536-(RC2H, RC2L))

Baudrate

(2^SMOD× f_OSC)/(64 × (2¹⁰-SREL))

Generator

The internal baudrate generator consists of a free running 10-bit timer with f_OSC/2 input frequency.

The internal baudrate generator is selected by setting bit BD in SFR BAUD.

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21

C502

Additional On-Chip RAM - XRAM

The SAB-C502 contains another 256byte of On-Chip RAM additional to the 256bytes internal RAM.

This RAM is called XRAM (‘eXtended RAM’) in this document.

The additional ON-Chip RAM is logically located in the external data memory range. The highbyte

of the XRAM address range startaddress is programmable by SFR XCON (94 ). The reset value of

H

XCON is 0F8 (that is, XRAM address range F800H … F8FF ).

H

The contents of the XRAM is not affected by a reset. After power up the contents is undefined, while

it remains unchanged during and after reset as long as the power supply is not turned off. The

XRAM is controlled by SFR SYSCON as shown in table 8.

Table 8

Control of the XRAM

SFR SYSCON

Description

XMAP1

XMAP0

0

1

Resetvalue. Access to XRAM is disabled. When cleared it can

be set again only by a reset

0

1

0

XRAM enabled

XRAM enabled. The signals RD and WR are activated during

accesses to XRAM

Because of the XRAM is used in the same way as external data memory the same instruction types

must be used for accessing the XRAM. A general overview gives table 9.

Table 9

Accessing the XRAM

Instruction

using

Instruction

Remarks

DPTR

MOVX A @DPTR

MOVX @ DPTR,A

Normally the use of these instructions would use a

physically external memory. However, in the SAB-C502

the XRAM is accessed if it is enabled.

R0/R1

(page mode)

MOVX A, @Ri

MOVX@Ri,A

Normally Port 2 serves as page register. However, the

distinction, whether Port 2 is as general purpose I/O or

as “page address” is made by the external design.

Hence a special SFR XPAGE is implemented the serve

the same function for the XRAM as Port 2 for external

data memory.

Note: When writing the page address (in page mode) at Port2 the value is also written in XPAGE.

However when writing XPAGE the value at PORT2 is not changed!

The behaviour of Port0/Port2 and RD/WR during MOVX accesses is shown in table 10.

Semiconductor Group

22

C502

Eight Datapointers for Faster External Bus Access

The SAB-C502 contains a set of eight 16-bit-Datapointer (DPTR) from which the actual DPTR can

be selected.

This means that the user’s program may keep up to eight 16-bit addresses resident in these

registers, but only one register at the time is selected to be the datapointer. Thus the DPTR in turn

is accessed (or selected) via indirect addressing. This indirect addressing is done through a special

function register (SFR) called DPSEL (data pointer select register, Bits 0 to 2). All instructions of the

SAB-C502 which handle the DPTR therefore affect only one of the eight pointers which is

addressed by DPSEL at that very moment.

A 3-bit field in SFR DPSEL points to the currently used DPTRx:

DPSEL

.2

selected

DPTR

.1

.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

Semiconductor Group

24

C502

Interrupt System

The SAB-C502 provides 6 interrupt sources with two priority levels. Figure 4 gives a general

overview of the interrupt sources and illustrates the request and control flags.

Figure 4

Interrupt Request Sources

Semiconductor Group

25

C502

Table 11

Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags)

Vector

Vector Address

IE0

TF0

IE1

TF1

RI + TI

TF2 + EXF2

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port interrupt

Timer 2 interrupt

0003

H

000B

H

0013

H

001B

H

0023

H

002B

H

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-

priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is

serviced. If requests of the same priority are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority

structure determined by the polling sequence as shown in table 12.

Table 12

Interrupt Priority-within-Level

Interrupt Source

Priority

External Interrupt 0,

IE0

High

Timer 0 Interrupt,

External Interrupt 1,

Timer 1 Interrupt,

Serial Channel,

TF0

IE1

TF1

RI or TI

TF2 or EXF2

↓

Timer 2 Interrupt,

Low

Semiconductor Group

26

C502

Fail Safe Mechanisms

The SAB-C502 offers enhanced fail safe mechanisms, which allow an automatic recovery from

software upset or hardware failure.

1) Watchdog Timer (15 bit, WDT)

2) Oscillator Watchdog (OWD)

1) Watchdog Timer (WDT)

The Watchdog Timer in the SAB-C502 is a 15-bit timer, which is incremented by a count rate of

either f_CYCLE/2 or f_CYCLE/32 (f_CYCLE= f_OSC/12). That is, the machine clock is divided by a series of

arrangement of two prescalers, a divide-by-two and a divide-by-16 prescaler. The latter is enabled

by setting bit WDTREL.7.

Figure 5 shows the block diagram of the programmable Watchdog Timer.

Figure 5

Block Diagram of the Programmable Watchdog Timer

Semiconductor Group

27

C502

– Starting and refreshing the WDT

Table 13 gives an overview how to start and refresh the WDT. The mentioned bits are located in

SFR WDCON.

Table 13

Starting and Refreshing the WDT

Function

Example

Remarks

Starting WD

SETB

SWDT

Cannot be stopped during active mode of the

device. WDT is halted during idle mode, power

down mode or the oscillator watchdog reset is

active.

Refreshing WD

SETB

WDT

SWDT

Double instruction sequence

(setting bit WDT and SWDT consecutively) to

increase system security.

– Watchdog reset and watchdog status flag (WDTS)

If the software fails to clear the watchdog in time, an internally generated watchdog reset is

entered at the counter state 7FFC . The duration of the reset signal then depends on the

H

prescaler selection (either 8 or 128 cycles). This internal reset differs from an external one in so

far as the Watchdog Timer is not disabled and bit WDTS (SFR WDCON) is set. The WDTS is a

flip-flop, which is set by a Watchdog Timer reset and can be cleared by an external hardware

reset. Bit WDTS allows the software to examine from which source the reset was activated. The

bit WDTS can also be cleared by software.

Semiconductor Group

28

C502

2) Oscillator Watchdog (OWD)

The OWD consists of an internal RC oscillator which provides the reference frequency for the

comparison with the frequency of the on-chip oscillator.

Figure 6 shows the block diagram of the oscillator watchdog unit while table 14 shows the effect

when the OWD becomes activ/inactiv.

Note: The OWD is always enabled!

Figure 6

Functional Block Diagram of the Oscillator Watchdog

Table 14

Effects of the OWD

Conditions

Effect

f_OSC< f_RC/5

Switch input of internal clock system to RC oscillator output

Activating internal reset at the same time (reset sequence is clocked by

RC-oscillator).

Exception from effects of a Hardware Reset:

Watchdog Timer Status Flag, WDTS is not reset

Oscillator Watchdog Status Flag, OWDS is set

f_OSC> f_RC/5

Input of internal clock system is f_OSC/2.

When failure condition (f_OSC< f_RC/5) disappears the part executes a

final reset phase of typ. 1 ms in order to allow the external oscillator to

stabilize.

Semiconductor Group

29

C502

Fast Internal Resest after Power-On

The SAB-C502 can use the oscillator watchdog unit for a fast internal resert procedure after power-

on.

Normally members of the 8051 family enter their default reset state not before the on-chip oscillator

starts. The reason is that the external reset signal must be internally synchronized and processed

in order to bring the device into the correct reset state. Especially if a crystal is used the start up

timed of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an

undefined state which could have severe effects e.g. to actuators connected to port pins.

In the SAB-C502 the oscillator watchdog unit avoids this situation. After power-on the oscillator

watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 µs). In the

following the watchdog circuitry detects a failure condition for the on-chip oscillator this has not yet

started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the on-chip

oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as a clock

source for the chip rather than the on-chip oscillator’s 16 output. This allows correct resetting of the

part and brings also all ports to the defined state.

Delay between power-on and correct reset state:

Typ: 18 µs

Max: 34 µs

Semiconductor Group

30

C502

Power Saving Modes

Two power down modes are available, the Idle Mode and the Power Down Mode.

The bits PDE, PDS and IDLE, IDLS select the Power Down mode or the idle mode, respectively. If

the Power Down mode and the idle mode are set at the same time, Power Down takes precedence.

Table 15 gives a general overview of the power saving modes.

Table 15

Entering and Leaving the Power Saving Modes

Mode

Entering

Example

Leaving by

Remarks

Idle mode

ORL PCON, #01H – enabled interrupt

ORL PCON, #20H – Hardware Reset

CPU is gated off

CPU status registers maintain

their data.

Peripherals are active

Double instruction sequence

Power Down

Mode

ORL PCON, #02H Hardware Reset

ORL PCON, #40H

Oscillators are stopped. Contents

of on-chip RAM and SFR’s are

maintained (leaving Power

Down Mode means redefinition

of SFR’s contents.)

Double instruction sequence

In the Power Down mode of operation, V_CCcan be reduced to minimize power consumption. It must

be ensured, however, that V_CCis not reduced before the Power Down mode is invoked, and that V_CC

is restored to its normal operating level, before the Power Down mode is terminated. The reset

signal that terminates the Power Down mode also restarts the oscillator. The reset should not be

activated before V_CCis restored to its normal operating level and must be held active long enough

to allow the oscillator to restart and stabilize (similar to power-on reset).

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31

C502

Absolute Maximum Ratings

Ambient temperature under bias (T_A) ..............................................................– 40 ˚C to + 85 ˚C

Storage temperature (T_ST) ...............................................................................– 65 ˚C to + 150 ˚C

Voltage on V_CCpins with respect to ground (V_SS) ............................................– 0.5 V to 6.5 V

Voltage on any pin with respect to ground (V_SS)..............................................– 0.5 V to V_CC+ 0.5 V

Input current on any pin during overload condition..........................................– 10 mA to + 10 mA

Absolute sum of all input currents during overload condition ..........................| 100 mA |

Power dissipation.............................................................................................TBD

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for longer

periods may affect device reliability. During overload conditions (V_IN> V_CCor V_IN< V_SS) the

Voltage on V_CCpins with respect to ground (V_SS) must not exceed the values defined by the

absolute maximum ratings.

Semiconductor Group

32

C502

DC Characteristics

_CC= 5 V + 10 %, – 15 %; V_SS= 0 V;

V

T_A= 0 to + 70 ˚C for the SAB-C502

T_A= – 40 to + 85 ˚C for the SAF-C502

Parameter

Symbol

Limit Values

max.

Unit Test Condition

min.

Input low voltage

(except EA, RESET)

V_IL

– 0.5

0.2 V_CC

– 0.1

V

–

Input low voltage (EA)

V_IL1

V_IL2

V_IH

0.2 V_CC

– 0.3

Input low voltage (RESET)

0.2 V_CC

+ 0.1

Input high voltage

0.2 V_CC

V_CC+ 0.5

(except EA, RESET, XTAL1)

+ 0.9

Input high voltage to XTAL1

V_IH1

0.7 V_CC

V

_CC+ 0.5

V

Input high voltage to RESET, EA V_IH2

0.6 V_CC

V

–

Output low voltage (ports 2, 3)

V_OL

–

0.45

I_OL= 1.6 mA¹⁾

I_OL= 3.2 mA¹⁾

Output low voltage

(port 0, ALE, PSEN)

V_OL1

Output high voltage (ports 2, 3) V_OH

2.4

0.9 V_CC

–

V

I

_OH= – 80 µA

_OH= – 10 µA

Output high voltage (port 0 in

V_OH1

2.4

0.9 V_CC

–

I

_OH= – 800 µA²⁾,

_OH= – 80 µA²⁾

external bus mode, ALE, PSEN)

Logic 0 input current

(ports 1, 2, 3)

I_IL

– 10

– 65

–

– 50

– 650

± 1

µA V_IN= 0.45 V

Logical 1-to-0 transition current I_TL

(ports 1, 2, 3)

µA V_IN= 2 V

Input leakage current

(port 0, EA, P1)

I_LI

µA 0.45 < V_IN< V_CC

Pin capacitance

C_IO

–

10

pF

f_C= 1 MHz,

T_A= 25 ˚C

Power supply current:

Active mode, 12 MHz⁷⁾

Idle mode, 12 MHz⁷⁾

Active mode, 20 MHz⁷⁾

Idle mode, 20 MHz⁷⁾

Power Down Mode

I_CC

I_PD

–

23.3

7.4

33.9

10.6

50

mA

µA

V

_CC= 5 V,⁴⁾

_CC= 5 V,⁵⁾

_CC= 5 V,⁴⁾

_CC= 5 V,⁵⁾

_CC= 2 … 5.5 V,³⁾

Semiconductor Group

33

C502

1)

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLof ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,

or use an address latch with a schmitt-trigger strobe input.

2)

3)

4)

Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall bellow the

0.9 V_CCspecification when the address lines are stabilizing.

I

_PD(Power Down Mode) is measured under following conditions:

EA = Port0 = V_CC; RESET = V_SS; XTAL2 = N.C.; XTAL1 = V_SS; all other pins are disconnected.

I_CC(active mode) is measured with:

XTAL1 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_CC– 0.5 V; XTAL2 = N.C.;

EA = Port0 = RESET = V_CC; all other pins are disconnected. I_CCwould be slightly higher if a crystal oscillator

is used (appr. 1 mA).

5)

7)

I

_CC(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_CC– 0.5 V; XTAL2 = N.C.;

RESET = EA = V_SS; Port0 = V_CC; all other pins are disconnected;

I_{CC max}at other frequencies is given by:

active mode:

idle mode:

I

_{CC max}= 1.32 x f_OSC+ 7.48

_{CC max}= 0.40 x f_OSC+ 2.62

where f_OSCis the oscillator frequency in MHz. I_CCvalues are given in mA and measured at V_CC= 5 V.

Semiconductor Group

34

C502

AC Characteristics for SAB-C502-L / C502-2R

_CC= 5 V + 10 %, – 15 %; V_SS= 0 V

V

T_A= 0 ˚C to + 70 ˚C

T_A= – 40 ˚C to + 85 ˚C

for the SAB-C502

for the SAF-C502

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 12 MHz

Unit

12 MHz

Clock

min. max. min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

127

43

30

–

2t_CLCL– 40

–

ns

Address setup to ALE

Address hold after ALE

ALE low to valid instr in

ALE to PSEN

–

t

_CLCL– 40

_CLCL– 53

–

t

–

233

–

4t_CLCL– 100

t_LLPL

t_PLPH

t_PLIV

58

215

–

t_CLCL– 25

–

PSEN pulse width

PSEN to valid instr in

–

3t_CLCL– 35

–

150

–

0

–

3t_CLCL– 100

Input instruction hold after PSEN t_PXIX

0

–

*)

Input instruction float after PSEN t_PXIZ

–

63

–

t_CLCL– 20

*)

Address valid after PSEN

Address to valid instr in

Address float to PSEN

t_PXAV

t_AVIV

t_AZPL

75

–

t_CLCL– 8

–

302

–

0

5t_CLCL– 115

0

–

*) Interfacing the SAB-C502-L/C502-2R to devices with float times up to 75 ns is permissible. This limited bus

contention will not cause any damage to port 0 Drivers.

Semiconductor Group

35

C502

AC Characteristics for SAB-C502-L / C502-2R

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 12 MHz

Unit

12 MHz

Clock

min. max. min.

max.

RD pulse width

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

400

30

–

6t_CLCL– 100

–

ns

WR pulse width

–

Address hold after ALE

RD to valid data in

–

t_CLCL– 53

–

252

–

5t_CLCL– 165

–

Data hold after RD

0

Data float after RD

–

97

517

585

300

–

2t_CLCL– 70

8t_CLCL– 150

9t_CLCL– 165

3t_CLCL+ 50

–

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

–

200

203

43

33

433

33

–

3t_CLCL– 50

4t_CLCL– 130

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

Address float after RD

123

–

t

_CLCL– 40

_CLCL– 50

t_CLCL+ 40

t

–

0

–

7t_CLCL– 150

t_CLCL– 50

–

0

–

Semiconductor Group

36

C502

External Clock Drive

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 12 MHz

min.

83.3

20

–

max.

Oscillator period

High time

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

285.7

ns

t

_CLCL– t_CLCX

_CLCL– t_CHCX

Low time

t

Rise time

20

Fall time

–

Semiconductor Group

37

C502

AC Characteristics for SAB-C502-L20 / C502-2R20

_CC= 5 V + 10 %, – 15 %; V_SS= 0 V

V

T_A= 0 ˚C to + 70 ˚C

T_A= – 40 ˚C to + 85 ˚C

for the SAB-C502

for the SAF-C502

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 20 MHz

Unit

20 MHz

Clock

min. max. min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

60

20

–

2t_CLCL– 40

–

ns

Address setup to ALE

Address hold after ALE

ALE low to valid instr in

ALE to PSEN

–

t

_CLCL– 30

–

t

–

100

–

4t_CLCL– 100

t_LLPL

t_PLPH

t_PLIV

25

115

–

t_CLCL– 25

–

PSEN pulse width

PSEN to valid instr in

–

3t_CLCL– 35

–

75

–

0

–

3t_CLCL– 75

Input instruction hold after PSEN t_PXIX

0

–

*)

Input instruction float after PSEN t_PXIZ

–

40

–

t_CLCL– 10

*)

Address valid after PSEN

Address to valid instr in

Address float to PSEN

t_PXAV

t_AVIV

t_AZPL

47

–

t_CLCL– 3

–

190

–

0

5t_CLCL– 60

0

–

*) Interfacing the SAB-C502-L20/C502-2R20 to devices with float times up to 45 ns is permissible. This limited

bus contention will not cause any damage to port 0 Drivers.

Semiconductor Group

38

C502

AC Characteristics for SAB-C502-L20 / C502-2R20

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/t_CLCL= 3.5 MHz to 20 MHz

Unit

18 MHz

Clock

min. max. min.

max.

RD pulse width

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

200

20

–

6t_CLCL– 100

–

ns

WR pulse width

–

Address hold after ALE

RD to valid data in

–

t_CLCL– 30

–

155

–

5t_CLCL– 95

–

Data hold after RD

0

Data float after RD

–

76

250

285

200

–

2t_CLCL– 24

8t_CLCL– 150

9t_CLCL– 165

3t_CLCL+ 50

–

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

–

100

70

20

5

3t_CLCL– 50

4t_CLCL– 130

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

Address float after RD

80

–

t

_CLCL– 30

_CLCL– 45

t_CLCL+ 30

t

–

0

200

10

–

7t_CLCL– 150

t_CLCL– 40

–

0

–

Semiconductor Group

39

C502

External Clock Drive

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 20 MHz

min.

50

12

–

max.

Oscillator period

High time

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

285.7

ns

t

_CLCL– t_CLCX

_CLCL– t_CHCX

Low time

t

Rise time

12

Fall time

–

Figure 7

Program Memory Read Cycle

Semiconductor Group

40

C502

Figure 8

Data Memory Read Cycle

Semiconductor Group

41

C502

Figure 9

Data Memory Write Cycle

Semiconductor Group

42

C502

ROM Verification Characteristics for SAB-C502-2R

ROM Verification Mode 1

Parameter

Symbol

Limit Values

max.

Unit

min.

Address to valid data

ENABLE to valid data

Data float after ENABLE

Oscillator frequency

t_AVQV

t_ELQV

–

0

4

48t_CLCL

6

ns

t_EHQZ

1/t_CLCL

ns

MHz

Figure 10

ROM Verification Mode 1

Semiconductor Group

43

C502

AC Inputs during testing are driven at V_CC– 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing

measurements are made at V_IHminfor a logic ‘1’ and V_ILmaxfor a logic ‘0’.

Figure 11

AC Testing: Input, Output Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/ V_OLlevel occurs.

I_OL/ I_OH≥ ± 20 mA.

Figure 12

AC Testing: Float Waveforms

Figure 13

External Clock Cycle

Semiconductor Group

44

C502

Figure 14

Recommended Oscillator Circuits

Semiconductor Group

45


型号：	SAB-C502-LP
厂家：	Infineon
描述：	8-Bit CMOS Microcontroller 8位CMOS微控制器微控制器
文件：	总46页 (文件大小：568K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAB-C502-LP [INFINEON]

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