SAB80C516-16_技术文档

Microcomputer Components

8-Bit CMOS Single-Chip Microcontroller

SAB 80C515 / SAB 80C535

Data Sheet 02.96

High-Performance

8-Bit CMOS Single-Chip Microcontroller

SAB 80C515/80C535

Preliminary

SAB 80C515/80C515-16

SAB 80C535/80C535-16

CMOS microcontroller with factory mask-programmable ROM

CMOS microcontroller for external ROM

● 8 K × 8 ROM (SAB 80C515 only)

● 256 × 8 RAM

● Six 8-bit I/O ports, one input port for

digital or analog input

● Boolean processor

● Most instructions execute in 1 µs (750 ns)

● 4 µs (3 µs) multiply and divide

● External memory expandable up to

128 Kbytes

● Three 16-bit timer/counters

● Highly flexible reload, capture, compare

● Backwardly compatible with SAB 8051

● Functionally compatible with SAB 80515

capabilities

● Full-duplex serial channel

● Idle and power-down mode

● Twelve interrupt vectors, four priority

● Plastic leaded chip carrier package:

levels

P-LCC-68

● 8-bit A/D converter with 8 multiplexed

inputs and programmable internal

reference voltages

● Plastic Metric Quad Flat Package

P-MQFP-80

● Two temperature ranges available:

● 16-bit watchdog timer

0 to 70 ˚C

(for 12, 16, 20 MHz)

– 40 to 85 ˚C (for 12, 16 MHz)

The SAB 80C515/80C535 is a powerful member of the Siemens SAB 8051 family

of 8-bit microcontrollers. It is designed in Siemens ACMOS technology and is functionally

compatible with the SAB 80515/80535 devices designed in MYMOS technology.

The SAB 80C515/80C535 is a stand-alone, high-performance single-chip microcontroller

based on the SAB 8051/80C51 architecture. While maintaining all the SAB 80C51 operating

characteristics, the SAB 80C515/80C535 incorporates several enhancements which

significantly increase design flexibility and overall system performance.

In addition, the low-power properties of Siemens ACMOS technology allow applications where

power consumption and dissipation are critical. Furthermore, the SAB 80C515/80C535 has

two software-selectable modes of reduced activity for further power reduction: idle and power-

down mode.

The SAB 80C535 is identical with the SAB 80C515 except that it lacks the on-chip program

memory. The SAB 80C515/80C535 is supplied in a 68-pin plastic leaded chip carrier package

(P-LCC-68) or in a plastic metric quad flat package (P-MQFP-80).

There are versions for 12, 16 and 20 MHz operation and for 16 MHz operation and for extended

temperature ranges – 40 to 85 ˚C. Versions for extended temperature range – 40 to + 110 ˚C

are available on request.

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02.96

SAB 80C515/80C535

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SAB 80C515/80C535

Ordering Information

Type

Ordering

Code

Package

Description

8-Bit CMOS Microcontroller

SAB 80C515-N

Q67120-DXXXX P-LCC-68

with mask-programmable ROM,

12 MHz

SAB 80C535-N

Q67120-C0508

P-LCC-68

for external memory, 12 MHz

SAB 80C515-N-T40/85

Q67120-DXXXX P-LCC-68

with mask-programmable ROM,

12 MHz

ext. temperature – 40 to + 85 ˚C

SAB 80C535-N-T40/85

SAB 80C515-16-N

SAB 80C535-16-N

Q67120-C0510

P-LCC-68

for external memory, 12 MHz

ext. temperature – 40 to + 85 ˚C

Q67120-DXXXX P-LCC-68

with mask-programmable ROM,

16 MHz

Q67120-C0509

Q67120-C0562

P-LCC-68

for external memory, 16 MHz

SAB 80C535-16-N-

T40/85

for external memory, 16 MHz

ext. temperature – 40 to + 85 ˚C

SAB 80C535-20-N

SAB 80C535-M

SAB 80C515-M

Q67120-C0778

Q67120-C0857

P-LCC-68

for external memory, 20 MHz

P-MQFP-80 for external memory, 12 MHz

Q67120-DXXXX P-MQFP-80 with mask-programmable ROM,

12 MHz

SAB 80C535-M-T40/85

SAB 80C515-M-T40/85

Q67120-C0937

P-MQFP-80 for external memory, 12 MHz

ext. temperature – 40 to + 85 ˚C

Q67120-DXXXX P-MQFP-80 with mask-programmable ROM,

12 MHz

ext. temperature – 40 to + 85 ˚C

Notes: Versions for extended temperature range – 40 to + 110 ˚C on request.

The ordering number of ROM types (DXXXX extension) is defined after program release

(verification) of the customer.

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SAB 80C515/80C535

Pin Configuration

(top view)

P-LCC-68

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SAB 80C515/80C535

Pin Configuration

(top view)

P-MQFP-80

80

75

70

65

61

RESET

N.C.

VAREF

1

5

60

55

50

P5.7

P0.7 / AD7

P0.6 / AD6

P0.5 / AD5

P0.4 / AD4

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

N.C.

EA

ALE

PSEN

VAGND

P6.7 / AIN7

P6.6 / AIN6

P6.5 / AIN5

P6.4 / AIN4

P6.3 / AIN3

P6.2 / AIN2

P6.1 / AIN1

P6.0 / AIN0

N.C.

SAB 80C535 / 80C515

10

15

20

P-MQFP-80

Package

N.C.

P3.0 / RXD0

P3.1 / TXD0

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

N.C.

45

41

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P3.5 / T1

21

25

30

35

40

N.C. pins must not be connected.

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SAB 80C515/80C535

Logic Symbol

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SAB 80C515/80C535

Pin Definitions and Functions

Symbol

Input (I)

Function

Port 4

P-LCC-68 P-MQFP-80 Output (O)

P4.0-P4.7 1-3, 5-9

72-74,

76-80

I/O

is an 8-bit bidirectional I/O port with

internal pullup resistors. Port 4 pins that

have 1’s written to them are pulled high by

the internal pullup resistors, and in that

state can be used as inputs. As inputs,

port 4 pins being externally pulled low will

source current (I _,in the DC

I L

characteristics) because of the internal

pullup resistors.

PE

4

75

I

Power saving mode enable

A low level on this pin enables the use of

the power saving modes (idle mode and

power-down mode). When PE is held on

high level it is impossible to enter the

power saving modes.

RESET

10

1

Reset pin

A low level on this pin for the duration of

two machine cycles while the oscillator is

running resets the SAB 80C515. A small

internal pullup resistor permits power-on

reset using only a capacitor connected

to V

.

SS

V

11

12

3

Reference voltage for the A/D converter

Reference ground for the A/D converter

AREF

4

AGND

P6.7-P6.0 13-20

5-12

Port 6

is an 8-bit undirectional input port. Port

pins can be used for digital input if voltage

levels simultaneously meet the

specifications for high/low input voltages

and for the eight multiplexed analog inputs

of the A/D converter.

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SAB 80C515/80C535

Pin Definitions and Functions (cont’d)

Symbol

Input (I)

Function

Port 3

P-LCC-68 P-MQFP-80 Output (O)

P3.0-P3.7 21-28

15-22

I/O

is an 8-bit bidirectional I/O port with

internal pullup resistors. Port 3 pins that

have1's written to them are pulled high by

the internal pullup resistors, and in that

state can be used as inputs. As inputs,

port 3 pins being externally pulled low will

source current (I_IL, in the DC

characteristics) because of the internal

pullup resistors. Port 3 also contains the

interrupt, timer, serial port and external

memory strobe pins that are used by

various options. The output latch

corresponding to a secondary function

must be programmed to a one (1) for that

function to operate. The secondary

functions are assigned to the pins of port

3, as follows:

– R×D (P3.0): serial port's receiver data

input (asynchronous) or data input/

output (synchronous)

– T×D (P3.1): serial port's transmitter data

output

(asynchronous) or clock output

(synchronous)

– INT0 (P3.2): interrupt 0 input/timer 0

gate control input

– INT1 (P3.3): interrupt 1 input/timer 1

gate control input

– T0 (P3.4): counter 0 input

– T1 (P3.5): counter 1 input

– WR (P3.6): the write control signal

latches the data byte from port 0 into the

external data memory

– RD (P3.7): the read control signal

enables the external data memory to

port 0

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SAB 80C515/80C535

Pin Definitions and Functions (cont’d)

Symbol

Input (I)

Function

Port 1

P-LCC-68 P-MQFP-80 Output (O)

P1.7-P1.0 29-36

24-31

I/O

is an 8-bit bidirectional I/O port with

internal pullup resistors. Port 1 pins that

have 1's written to them are pulled high by

the internal pullup resistors, and in that

state can be used as inputs. As inputs,

port 1 pins being externally pulled low will

source current (I_{I L}in the DC

characteristics) because of the internal

pullup resistors. The port is used for the

low-order address byte during program

verification. Port 1 also contains the

interrupt, timer, clock, capture and

compare pins that are used by various

options. The output latch corresponding to

a secondary function must be

programmed to a one (1) for that function

to operate (except when used for the

compare functions). The secondary

functions are assigned to the port 1 pins

as follows:

– INT3/CC0 (P1.0): interrupt 3 input/

compare 0 output/capture 0 input

– INT4/CC1 (P1.1): interrupt 4 input/

compare 1 output/capture 1 input

– INT5/CC2 (P1.2): interrupt 5 input/

compare 2 output/capture 2 input

– INT6/CC3 (P1.3): interrupt 6 input/

compare 3 output/capture 3 input

– INT2 (P1.4): interrupt 2 input

– T2EX (P1.5): timer 2 external reload

trigger input

– CLKOUT (P1.6): system clock output

– T2 (P1.7): counter 2 input

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SAB 80C515/80C535

Pin Definitions and Functions (cont’d)

Symbol

Input (I)

Function

XTAL2

P-LCC-68 P-MQFP-80 Output (O)

XTAL2

XTAL1

39

40

36

37

Input to the inverting oscillator amplifier

and input to the internal clock generator

circuits.

XTAL1

Output of the inverting oscillator amplifier.

To drive the device from an external clock

source, XTAL2 should be driven, while

XTAL1 is left unconnected. There are no

requirements on the duty cycle of the

external clock signal, since the input to the

internal clocking circuitry is divided down

by a divide-by-two flip-flop. Minimum and

maximum high and low times and rise/fall

times specified in the AC characteristics

must be observed.

P2.0-P2.7 41-48

38-45

I/O

Port 2

is an 8-bit bidirectional I/O port with

internal pullup resistors. Port 2 pins that

have 1's written to them are pulled high by

the internal pullup resistors, and in that

state can be used as inputs. As inputs,

port 2 pins being externally pulled low will

source current (I _{I L,}in the DC

characteristics) because of the internal

pullup resistors.

Port 2 emits the high-order address byte

during fetches from external program

memory and during accesses to external

data memory that use 16-bit addresses

(MOVX@DPTR). In this application it

uses strong internal pullup resistors when

issuing 1's. During accesses to external

data memory that use 8-bit addresses

(MOVX@Ri), port 2 issues the contents of

the P2 special function register.

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SAB 80C515/80C535

Pin Definitions and Functions (cont’d)

Symbol

Input (I)

Function

P-LCC-68 P-MQFP-80 Output (O)

PSEN

49

47

O

The Program store enable

output is a control signal that enables the

external program memory to the bus

during external fetch operations. It is

activated every six oscillator periods,

except during external data memory

accesses. The signal remains high during

internal program execution.

ALE

EA

50

51

48

49

O

The Address latch enable

output is used for latching the address into

external memory during normal operation.

It is activated every six oscillator periods,

except during an external data memory

access.

I

External access enable

When held high, the SAB 80C515

executes instructions from the internal

ROM as long as the PC is less than 8192.

When held low, the SAB 80C515 fetches

all instructions from external program

memory. For the SAB 80C535 this pin

must be tied low.

P0.0-P0.7 52-59

52-59

I/O

Port 0

is an 8-bit open-drain bidirectional I/O

port.

Port 0 pins that have 1's written to them

float, and in that state can be used as

high-impedance inputs.

Port 0 is also the multiplexed low-order

address and data bus during accesses to

external program and data memory. In

this application it uses strong internal

pullup resistors when issuing 1's.

Port 0 also outputs the code bytes during

program verification in the SAB 80C515.

External pullup resistors are required

during program verification.

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SAB 80C515/80C535

Pin Definitions and Functions (cont’d)

Symbol

Input (I)

Function

P-LCC-68 P-MQFP-80 Output (O)

P5.7-P5.0 60-67 60-67 I/O

Port 5 is an 8-bit bidirectional I/O port with

internal pullup resistors. Port 5 pins that

have 1's written to them are pulled high by

the internal pullup resistors, and in that

state can be used as inputs. As inputs,

port 5 pins being externally pulled low will

source current

(I in the DC characteristics) because of

IL

the internal pullup resistors.

V

37

33

–

Supply voltage

CC

during normal, idle, and power-down

operation. Internally connected to pin 68.

V

38

68

34

69

–

Ground (0 V)

SS

CC

Supply voltage

during normal, idle, and power-down

operation. Internally connected to pin 37.

N. C.

–

2, 13, 14,

23, 32, 35,

46, 50, 51,

68, 70, 71

–

Not connected

These pins of the P-MQFP-80 package

must not be connected

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SAB 80C515/80C535

Figure 1

Block Diagram

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SAB 80C515/80C535

Functional Description

The members of the SAB 80515 family of microcontrollers are:

– SAB 80C515:

Microcontroller, designed in Siemens ACMOS technology, with

8 Kbyte factory mask-programmable ROM

ROM-less version of the SAB 80C515

Microcontroller, designed in Siemens MYMOS technology, with

8 Kbyte factory mask-programmable ROM

– SAB 80C535:

– SAB 80515:

– SAB 80535:

ROM-less version of the SAB 80515

The SAB 80C535 is identical to the SAB 80C515, except that it lacks the on-chip ROM.

In this data sheet the term "SAB 80C515" is used to refer to both the SAB 80C515 and

SAB 80C535, unless otherwise noted.

Principles of Architecture

The architecture of the SAB 80C515 is based on the SAB 8051/SAB 80C51 microcontroller

family. The following features of the SAB 80C515 are fully compatible with the SAB 80C51

features:

– Instruction set

– External memory expansion interface (port 0 and port 2)

– Full-duplex serial port

– Timer/counter 0 and 1

– Alternate functions on port 3

– The lower 128 bytes of internal RAM and the lower 4 Kbytes of internal ROM

The SAB 80C515 additionally contains 128 bytes of internal RAM and 4 Kbytes of internal

ROM, which results in a total of 256 bytes of RAM and 8 Kbytes of ROM on-chip.

The SAB 80C515 has a new 16-bit timer/counter with a 2:1 prescaler, reload mode, compare

and capture capability. It also contains at 16-bit watchdog timer, an 8-bit A/D converter with pro-

grammable reference voltages, two additional quasi-bidirectional 8-bit ports, one 8-bit input

port for analog or digital signals, and a programmable clock output (f

/12).

OSC

Furthermore, the SAB 80C515 has a powerful interrupt structure with 12 vectors and 4 pro-

grammable priority levels.

Figure 1 shows a block diagram of the SAB 80C515.

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SAB 80C515/80C535

CPU

The SAB 80C515 is efficient both as a controller and as an arithmetic processor. It has

extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities.

Efficient use of program memory results from an instruction set consisting of 44 % one-byte,

41 % two-byte, and 15 % three-byte instructions. With a 12 MHz crystal, 58 % of the

instructions execute in 1.0 µs.

Memory Organization

The SAB 80C515 manipulates operands in the four memory address spaces described below:

Figure 1 illustrates the memory address spaces of the SAB 80C515.

Program Memory

The SAB 80C515 has 8 Kbyte of on-chip ROM, while the SAB 80C535 has no internal ROM.

The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high,

the SAB 80C515 executes out of internal ROM unless the address exceeds 1FFF . Locations

H

2000 through 0FFFF are then fetched from the external program memory. If the EA pin is

H

held now, the SAB 80C515 fetches all instructions from the external program memory. Since

the SAB 80C535 has no internal ROM, pin EA must be tied low when using this component.

Data Memory

The data memory address space consists of an internal and an external memory space. The

internal data memory is divided into three physically separate and distinct blocks:

the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function

register (SRF) area. While the upper 128 bytes of data memory and the SFR area share the

same address locations, they are accessed through different addressing modes. The lower

128 bytes of data memory can be accessed through direct or register indirect addressing; the

upper 128 bytes of RAM can be accessed through register indirect addressing; the special

function registers are accessible through direct addressing.

Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy loca-

tions 0 through 1F in the lower RAM area. The next 16 bytes, locations 20 through 2F , con-

H

tain 128 directly addressable bit locations. The stack can be located anywhere in the internal

data memory address space, and the stack depth can be expanded up to 256 bytes.

The external data memory can be expanded up to 64 Kbytes and can be accessed by instruc-

tions that use a 16-bit or an 8-bit address.

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SAB 80C515/80C535

Figure 2

Memory Address Spaces

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SAB 80C515/80C535

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside

in the special function register area. The special function registers include arithmetic registers,

pointers, and registers that provide an interface between the CPU and the on-chip peripherals.

There are also 128 directly addressable bits within the SFR area. All special function registers

are listed in table 1 and table 2.

In table 1 they are organized in numeric order of their addresses. In table 3 they are organized

in groups which refer to the functional blocks of the SAB 80C515.

Table 1

Special Function Register

Address

Register

Contents

Address

Register

Contents

after Reset

1)

P0 ¹⁾

SP

DPL

DPH

reserved

PCON

SCON

SBUF

80

0FF

98

00

H

2)

XX

81

07

99

H

2)

XX

82

00

9A

9B

9C

9D

9E

9F

reserved

H

2)

XX

83

00

H

2)

XX

84

H

2)

XX

85

H

2)

86

XX

H

2)

87

000X 0000

H

B

H

TCON ¹⁾

TMOD

TL0

TL1

TH0

TH1

reserved

P2 ¹⁾

88

00

A0

0FF

H

2)

89

A1

XX

reserved

H

8A

8B

8C

8D

8E

8F

A2

XX

H

A3

XX

H

A4

XX

H

A5

XX

H

2)

XX

A6

XX

H

A7

XX

H

P1 ¹⁾

IEN0 ¹⁾

IP0

90

0FF

A8

00

H

2)

91

XX

A9

X000 0000

reserved

H

B

2)

XX

92

XX

AA

AB

AC

AD

reserved

H

2)

XX

93

XX

H

2)

XX

94

XX

H

2)

XX

95

XX

H

2)

XX

96

XX

AE

H

2)

XX

97

XX

AF

H

1)

Bit-addressable Special Function Register

X means that the value is indeterminate and the location is reserved

2)

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SAB 80C515/80C535

Table 1

Special Function Register (cont’d)

Address

Register

Contents

Address

Register

Contents

after Reset

B0

P3 ¹⁾

0FF

D0

PSW ¹⁾

00

H

2)

B1

B2

B3

B4

B5

B6

B7

reserved

XX

D1

D2

D3

D4

D5

D6

D7

reserved

XX

H

2)

B8

IEN1 ¹⁾

IP1

00

D8

D9

DA

DB

DC

DD

ADCON¹⁾

ADDAT

DAPR

00X0 0000

B

H

2)

B9

XX00 0000

00

H

B

H

2

BA

BB

BC

BD

BS

BF

reserved

XX

)

H

2

2)

P6

XX

H

reserved

H

DE

DF

2)

1)

C0

C1

C2

C3

C4

C5

C6

C7

IRCON ¹⁾

CCEN

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

00

E0

ACC

00

H

2)

00

E1

E2

E3

E4

E5

E6

E7

reserved

XX

H

C8H

C9

T2CON ¹⁾

reserved

CRCL

CRCH

TL2

TH2

reserved

00

XX

E8

E9

EA

EB

EC

ED

P4 ¹⁾

0FF

H

2)

reserved

XX

H

CA

CB

00

XX

H

CC

CD

H

2)

CE

CF

EE

EF

H

1)

Bit-addressable Special Function Register

X means that the value is indeterminate and the location is reserved

2)

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SAB 80C515/80C535

Table 1

Special Function Register (cont’d)

Address

Register

Contents

Address

Register

Contents

after Reset

1)

F0

F1

F2

F3

F4

F5

F6

F7

B

00

F8

F9

FA

FB

FC

FD

P5

0FF

H

2)

reserved

XX

reserved

XX

H

2)

H

FE

FF

1)

Bit-addressable Special Function Register

X means that the value is indeterminate and the location is reserved

2)

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SAB 80C515/80C535

Table 2

Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents

after Reset

1)

CPU

ACC

B

DPH

DPL

PSW

SP

Accumulator

B-Register

Data Pointer, High Byte

Data Pointer, Low Byte

Program Status Word Register

Stack Pointer

0E0

0F0

00

07

H

83

82

H

1)

0D0

H

81

H

2)

A/D-

Converter

ADCON

ADDAT

DAPR

A/D Converter Control Register

A/D Converter Data Register

D/A Converter Program Register

0D8

0D9

0DA

00X0 0000

H

B

00

H

1)

Interrupt

System

EN0

IEN1

IP0

IP1

IRCON

TCON ²⁾

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

Interrupt Priority Register 1

Interrupt Request Control Register 0C0

Timer Control Register

0A8

0B8

0A9

0B9

00

H

2)

X000 0000

XX00 0000

B

1)

3)

H

B

1)

88

00

H

T2CON ²⁾Timer 2 Control Register

0C8

00

H

Compare/

Capture-

Unit

CCEN

CCH1

CCH2

CCH3

CCL1

CCL2

CCL3

CRCH

CRCL

TH2

Comp./Capture Enable Reg.

Comp./Capture Reg. 1, High Byte

Comp./Capture Reg. 2, High Byte

Comp./Capture Reg. 3, High Byte

Comp./Capture Reg. 1, Low Byte

Comp./Capture Reg. 2, Low Byte

Comp./Capture Reg. 3, Low Byte

Com./Rel./Capt. Reg. High Byte

Com./Rel./Capt. Reg. Low Byte

Timer 2, High Byte

0C1

0C3

0C5

0C7

0C2

0C4

0C6

0CB

0CA

0CD

0CC

00

H

(CCU)

H

TL2

T2CON

Timer 2, Low Byte

Timer 2 Control Register

H

1)

0C8

H

1)

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong

to other functional blocks.

2)

3)

X means that the value is indeterminate and the location is reserved

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SAB 80C515/80C535

Table 2

Special Function Registers- Functional Blocks (cont’d)

Block

Symbol

Name

Address

Contents

after Reset

1)

Ports

P0

P1

P2

P3

P4

P5

P6

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

80

90

0A0

0B0

0E8

0F8

0DB

0FF

H

1)

H

Port 6, Analog/Digital Input

H

2)

Pow.Sav.M PCON

odes

Power Control Register

87

000X 0000

H

B

1)

2)

ADCON ²⁾

PCON ²⁾

SBUF

Serial

Channels

A/D Converter Control Reg.

Power Control Register

Serial Channel Buffer Reg.

Serial Channel Control Reg.

0D8

00X0 0000

000X 0000

H

B

87

99

98

H

3)

0XX

H

1)

00

SCON

H

Timer 0/

Timer 1

TCON

TH0

TH1

TL0

TL1

Timer Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88

00

H

8C

8D

H

8A

8B

89

TMOD

1)

IEN0 ²⁾

IEN1 ²⁾

IP0 ²⁾

Watchdog

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

Interrupt Priority Register 1

0A8

0B8

0A9

00

H

2)

3)

X000 0000

XX00 0000

H

B

IP1 ²⁾

0B9

B

1)

Bit-addressable special function registers

This special function register is listed repeatedly since some bits of it also belong

to other functional blocks.

2)

3)

X means that the value is indeterminate and the location is reserved

Semiconductor Group

21

SAB 80C515/80C535

I/O Ports

The SAB 80C515 has six 8-bit I/O ports and one 8-bit input port. Port 0 is an open-drain

bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pullup

resistors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source

current when externally pulled low. Port 0 will float when configured as input.

Port 0 and port 2 can be used to expand the program and data memory externally. During an

access to external memory, port 0 emits the low-order address byte and reads/writes the data

byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain

port, but uses a strong internal pullup FET. Ports 1 and 3 are provided for several alternate

functions, as listed below:

Port Symbol

Function

P1.0 INT3/CC0 External interrupt 3 input, compare 0 output, capture 0 input

P1.1 INT4/CC1 External interrupt 4 input, compare 1 output, capture 1 input

P1.2 INT5/CC2 External interrupt 5 input, compare 2 output, capture 2 input

P1.3 INT6/CC3 External interrupt 6 input, compare 3 output, capture 3 input

P1.4 INT2

P1.5 T2EX

External interrupt 2 input

Timer 2 external reload trigger input

P1.6 CLKOUT System clock output

P1.7 T2

Timer 2 external count or gate input

P3.0 R×D

Serial port’s receiver data input (asynchronous) or data input/output

(synchronous)

P3.1 T×D

Serial port’s transmitter data output (asynchronous) or clock output

(synchronous)

P3.2 INT0

P3.3 INT1

P3.4 T0

External interrupt 0 input, timer 0 gate control

External interrupt 1 input, timer 1 gate control

Timer 0 external counter input

P3.5 T1

Timer 1 external counter input

P3.6 WR

P3.7 RD

External data memory write strobe

External data memory read strobe

The SAB 80C515 has dual-purpose input port. As the ANx lines in the SAB 80515 (NMOS

version), the eight port lines at port 6 can be used as analog inputs. But if the input voltages at

port 6 meet the specified digital input levels (V an d V ), the port can also be used as digital

IL

IH

input port. Reading the special function register P6 allows the user to input the digital values

currently applied to the port pins. It is not necessary to select these modes by software; the

voltages applied at port 6 pins can be converted to digital values using the A/D converter and

at the same time the pins can be read via SFR P6.

It must be noted, however, that the results in port P6 bits will be indeterminate if the levels at

the corresponding pins are not within their respective V /V specifications. Furthermore, it is

IL IH

not possible to use port P6 as output lines. Special function register P6 is located at address

0DB .

H

Semiconductor Group

22

SAB 80C515/80C535

Timer/Counters

The SAB 80C515 contains three 16-bit timers/counters which are useful in many applications

for timing and counting. The input clock for each timer/counter is 1/12 of the oscillator frequency

in the timer operation or can be taken from an external clock source for the counter operation

(maximum count rate is 1/24 of the oscillator frequency).

– Timer/Counter 0 and 1

These timers/counters can operate in four modes:

Mode 0: 8-bit timer/counter with 32:1 prescaler

Mode 1: 16-bit timer/counter

Mode 2: 8-bit timer/counter with 8-bit auto-reload

Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer;

Timer/counter 1 in this mode holds its count.

External inputs INT0 and INT1 can be programmed to function as a gate for

timer/counters 0 and 1 to facilitate pulse width measurements.

– Timer/Counter 2

Timer/counter 2 of the SAB 80C515 is a 16-bit timer/counter with several additional features. It

offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions.

Corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one

of them can be used to perform a 16-bit reload on a timer overflow or external event. Each of

these registers corresponds to a pin of port 1 for capture input/compare output.

Figure 3 shows a block diagram of timer/counter 2.

Reload

A 16-bit reload can be performed with the 16-bit CRC register consisting of CRCL and CRCH.

There are two modes from which to select:

Mode 0: Reload is caused by a timer 2 overflow (auto-reload).

Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5), which

can also request an interrupt.

Capture

This feature permits saving the actual timer/counter contents into a selected register

upon an external event or a software write operation. Two modes are provided to latch

the current 16-bit value in timer 2 registers TL2 and TH2 into a dedicated capture register:

Mode 0: Capture is performed in response to a transition at the corresponding port 1 pins

CC0 to CC3.

Mode 1: Write operation into the low-order byte of the dedicated capture register causes

the timer 2 contents to be latched into this register.

Semiconductor Group

23

SAB 80C515/80C535

Compare

In the compare mode, the 16-bit values stored in the dedicated compare registers are

compared to the contents of the timer 2 registers. If the count value in the timer 2

registers matches one of the stored values, an appropriate output signal is generated and an

interrupt is requested. Two compare modes are provided:

Mode 0: Upon a match the output signal changes from low to high. It goes back to a low

level when timer 2 overflows.

Mode 1: The transition of the output signal can be determined by software.

A timer 2 overflow causes no output change

Figure 3

Block Diagram of Timer/Counter 2

Semiconductor Group

24

SAB 80C515/80C535

Serial Port

The serial port of the SAB 80C515 enables full duplex communication between microcontrol-

lers or between microcontroller and peripheral devices.

The serial port can operate in 4 modes:

Mode 0: Shift register mode. Serial data enters and exits through R×D. T×D outputs the

shift clock. 8-bits are transmitted/received: 8 data bits (LSB first).

The baud rate is fixed at 1/12 of the oscillator frequency.

Mode 1: 10-bits are transmitted (through R×D) or received (through T×D): a start bit (0),

8 data bits (LSB first), and a stop bit (1). The baud rate is variable.

Mode 2: 11-bits are transmitted (through R×D) or received (through T×D): a start bit (0),

8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1).

The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency.

Mode 3: 11-bits are transmitted (through T×D) or received (through R×D): a start bit (0),

8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). Mode 3

is identical to mode 2 except for the baud rate. The baud rate in mode 3 is variable.

The variable baud rates in modes 1 and 3 can be generated by timer 1 or an internal

baud rate generator.

A/D Converter

The 8-bit A/D converter of the SAB 80C515 has eight multiplexed analog inputs (Port 6) and

uses the successive approximation method.

There are three characteristic time frames in a conversion cycle (see A/D converter

characteristics): the conversion time t_C, which is the time required for one conversion; the

sample time t which is included in the conversion time and is measured from the start of the

S

conversion; the load time t , which in turn is part of the sample time and also is measured from

L

the conversion start.

Within the load time t , the analog input capacitance C must be loaded to the analog inpult

L

I

voltage level. For the rest of the sample time t , after the load time has passed, the selected

S

analog input must be held constant. During the rest of the conversion time t the conversion

C

itself is actually performed. Conversion can be programmed to be single or continuous; at the

end of a conversion an interrupt can be generated.

A unique feature is the capability of internal reference voltage programming. The internal

reference voltages V

and V

for the A/D converter both are programmable to one

IntAREF

IntAGND

of 16 steps with respect to the external reference voltages. This feature permits a conversion

with a smaller internal reference voltage range to gain a higher resolution.

In addition, the internal reference voltages can easily be adapted by software to the desired

analog input voltage range.

Figure 4 shows a block diagram of the A/D converter.

Semiconductor Group

25

SAB 80C515/80C535

Figure 4

Block Diagram of the A/D Converter

Semiconductor Group

26

SAB 80C515/80C535

Interrupt Structure

The SAB 80C515 has 12 interrupt vectors with the following vector addresses and request

flags:

Table 3

Interrupt Sources and Vectors

Source (Request Flags)

Vector Address

0003

Vector

IE0

TF0

IE1

TF1

RI + TI

TF2 + EXF2

IADC

IEX2

IEX3

IEX4

IEX5

IEX6

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port interrupt

Timer 2 interrupt

A/D converter interrupt

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

H

000B

H

0013

001B

H

0023

002B

H

0043

H

004B

H

0053

005B

H

0063

006B

H

Each interrupt vector can be individually enabled/disabled. The minimum response time to an

interrupt request is more than 3 machine cycles and less than 9 machine cycles.

Figure 5 shows the interrupt request sources.

External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)

at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering

on a negative or a positive transition. The external interrupts 3 or 6 are combined with the

corresponding alternate functions compare (output) and capture (input) on port 1.

For programming of the priority levels the interrupt vectors are combined to pairs. Each pair can

be programmed individually to one of four priority levels by setting or clearing one bit in the

special function register IP0 and one in IP1.

Figure 6 shows the priority level structure.

Semiconductor Group

27

SAB 80C515/80C535

Figure 5

Interrupt Request Sources

Semiconductor Group

28

SAB 80C515/80C535

Figure 6

Interrupt Priority Level Structure

Semiconductor Group

29

SAB 80C515/80C535

Watchdog Timer

This feature is provided as a means of graceful recovery from a software upset. After an

external reset, the watchdog timer is cleared and stopped. It can be started and cleared by

software, but it cannot be stopped during active mode of the device. If the software fails to clear

the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 MHz oscillator

frequency is used), an internal reset will be initiated. The reset cause (external reset or reset

caused by the watchdog) can be examined by software. To clear the watchdog, two bits in two

different special function registers must be set by two consecutive instructions (bits IEN0.6 and

IEN1.6). This is done to prevent the watchdog from being cleared by unexpected opcodes.

It must be noted, however, that the watchdog timer is halted during the idle mode and power-

down mode of the processor (see section "Power Saving Modes" below).

Therefore, it is possible to use the idle mode in combination with the watchdog timer function.

But even the watchdog timer cannot reset the device when one of the power saving modes has

been is entered accidentally.

For these reasons several precautions are taken against unintentional entering of the power-

down or idle mode (see below).

Power Saving Modes

The ACMOS technology of the SAB 80C515 allows two new power saving modes of the device:

The idle mode and the power-down mode. These modes replace the power-down supply mode

via pin V of the SAB 80515 (NMOS). The SAB 80C515 is supplied via

PD

pins V also during idle and power-down operation.

CC

However, there are applications where unintentional entering of these power saving modes

must be absolutely avoided. Such critical applications often use the watchdog timer to prevent

the system from program upsets. Then accidental entering of the power saving modes would

even stop the watchdog timer and would circumvent the watchdog timer's task of system

protection.

Thus, the SAB 80C515 has an extra pin that allows it to disable both of the power saving

modes. When pin PE is held high, idle mode and power-down mode are completely disabled

and the instruction sequences that are used for entering these modes (see below) will NOT

affect the normal operations of the device. When PE is held low, the use of the idle mode and

power-down mode is possible as described in the following sections.

Pin PE has a weak internal pullup resistor. Thus, when left open, the power saving modes are

disabled.

The Special Function Register PCON

In the NMOS version SAB 80515 the SFR PCON (address 87 ) contains only bit SMOD; in the

H

CMOS version SAB 80C515 there are more bits used (see table 4).

The bits PDE, PDS and IDLE, IDLS select the power-down mode or the idle mode, respectively,

when the use of the power saving modes is enabled by pin PE (see next page).

Semiconductor Group

30

SAB 80C515/80C535

If the power-down mode and the idle mode are set at the same time, power-down takes prece-

dence.

Furthermore, register PCON contains two general purpose flags. For example, the flag bits

GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation

or during an idle. Then an instruction that activates Idle can also set one or both flag bits. When

idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.

The reset value of PCON is 000X0000 .

B

Table 4

SFR PCON (87H)

SMOD

7

PDS

6

IDLS

5

–

4

GF1

3

GF0

2

PDE

1

IDLE

0

87H

Symbol

Position

Function

SMOD

PCON.7

When set, the baud rate of the serial channel in mode 1, 2,

3 is doubled.

PDS

IDLS

PCON.6

Power-down start bit. The instruction that sets the PDS flag

bit is the last instruction before entering the power-down

mode.

PCON.5

Idle start bit. The instruction that sets the IDLS flag bit is the

last instruction before entering the idle mode.

–

PCON.4

PCON.3

PCON.2

PCON.1

Reserved

GF1

GF0

PDE

General purpose flag

Power-down enable bit. When set, starting of the power-

down mode is enabled.

IDLE

PCON.0

Idle mode enable bit. When set, starting of the idle mode is

enabled.

Idle Mode

In the idle mode the oscillator of the SAB 80C515 continues to run, but the CPU is gated off

from the clock signal. However, the interrupt system, the serial port, the A/D converter, and all

timers with the exception of the watchdog timer are further provided with the clock. The CPU

status is preserved in its entirety: the stack pointer, program counter, program status word,

accumulator, and all other registers maintain their data during idle mode.

The reduction of power consumption, which can be achieved by this feature depends on the

number of peripherals running.

Semiconductor Group

31

SAB 80C515/80C535

If all timers are stopped and the A/D converter and the serial interface are not running, the

maximum power reduction can be achieved. This state is also the test condition for the idle

mode I (see DC characteristics, note 5).

CC

So the user has to take care which peripheral should continue to run and which has to be

stopped during idle mode. Also the state of all port pins – either the pins controlled by their

latches or controlled by their secondary functions – depends on the status of the controller

when entering idle mode.

Normally the port pins hold the logical state they had at the time idle mode was activated. If

some pins are programmed to serve their alternate functions they still continue to output during

idle mode if the assigned function is on. This applies to the compare outputs as well as to the

clock output signal or to the serial interface in case it cannot finish reception or transmission

during normal operation. The control signals ALE and PSEN hold at logic high levels (see

table 5).

Table 5

Status of External Pins During Idle and Power-Down Mode

Last instruction executed from

internal code memory

Last instruction executed from

external code memory

Outputs

ALE

Idle

Power-down

Low

Idle

Power-down

Low

High

Data

High

Float

PSEN

Low

PORT 0

PORT 1

Data

Float

Data/alternate

outputs

Data/last

output

Data/alternate

outputs

Data/last

output

PORT 2

PORT 3

Data

Address

Data

Data/alternate

outputs

Data/last

output

Data/alternate

outputs

Data/last

output

PORT 4

PORT 5

Data

As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture

or reload operation can be triggered, the timers can be used to count external events, and

external interrupts will be detected.

The idle mode is a useful feature which makes it possible to "freeze" the processor's status –

either for a predefined time, or until an external event reverts the controller to normal operation,

as discussed below. The watchdog timer is the only peripheral which is automatically stopped

during idle mode. If it were not disabled on entering idle mode, the watchdog timer would reset

the controller, thus abandoning the idle mode.

Semiconductor Group

32

SAB 80C515/80C535

When idle mode is used, pin PE must be held on low level. The idle mode is then entered by

two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not

set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not

set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and

IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after

being set. If one of these register bits is read the value that appears is 0 (see table 4). This

double instruction is implemented to minimize the chance of an unintentional entering of the

idle mode which would leave the watchdog timer’s task of system protection without effect.

Note that PCON is not a bit-addressable register, so the above mentioned sequence for

entering the idle mode is obtained by byte-handling instructions, as shown in the following

example:

ORL

PCON,#00000001

;Set bit IDLE, bit IDLS must not be set

;Set bit IDLS, bit IDLE must not be set

B

PCON,#00100000

The instruction that sets bit IDLS is the last instruction executed before going into idle mode.

There are two ways to terminate the idle mode:

– The idle mode can be terminated by activating any enable interrupt. This interrupt will

be serviced and normally the instruction to be executed following the RETI instruction

will be the one following the instruction that sets the bit IDLS.

– The other way to terminate the idle mode, is a hardware reset. Since the oscillator

is still running, the hardware reset must be held active only for two machine cycles

for a complete reset.

Power-Down Mode

In the power-down mode, the on-chip oscillator is stopped. Therefore all functions are stopped;

only the contents of the on-chip RAM and the SFR's are maintained.The port pins controlled by

their port latches output the values that are held by their SFR's.

The port pins which serve the alternate output functions show the values they had at the end

of the last cycle of the instruction which initiated the power-down mode; when the clockout

signal (CLKOUT, P1.6) is enabled, it will stop at low level. ALE and PSEN hold at logic low

level (see table 5).

To enter the power-down mode the pin PE must be on low level. The power-down mode then

is entered by two consecutive instructions. The first instruction has to set the flag bit PDE

(PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit

PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent

setting of both bits, PDE and PDS, does not initiate the power-down mode. Bits PDE and PDS

will automatically be cleared after having been set and the value shown by reading one of these

bits is always 0 (see table 4). This double instruction is implemented to minimize the chance of

unintentionally entering the power-down mode which could possibly "freeze" the chip's activity

in an undesired status.

Semiconductor Group

33

SAB 80C515/80C535

Note that PCON is not a bit-addressable register, so the above mentioned sequence for

entering the power-down mode is obtained by byte-handling instructions, as shown in the

following example:

ORL

PCON,#00000010

;Set bit PDE, bit PDS must not be set

;Set bit PDS, bit PDE must not be set

B

PCON,#01000000

The instruction that sets bit PDS is the last instruction executed before going into

power-down mode.

The only exit from power-down mode is a hardware reset. Reset will redefine all SFR's, but will

not change the contents of the internal RAM.

In the power-down mode of operation, V can be reduced to minimize power consumption. It

CC

must be ensured, however, that V is not reduced before the power- down mode is invoked,

CC

and that V

is restored to its normal operating level, before the power-down mode is

CC

terminated. The reset signal that terminates the power-down mode also restarts the oscillator.

The reset should not be activated before V is restored to its normal operating level and must

CC

be held active long enough to allow the oscillator to restart and stabilize (similar to power-on

reset).

Differences in Pin Assignments of the SAB 80C515 and SAB 80515

Since the SAB 80C515 is designed in CMOS technology, this device requires no V pin, be-

B B

cause the die's substrate is internally connected to V .

CC

Furthermore, the RAM backup power supply via pin V is replaced by the software- controlled

PD

power-down mode and power supply via V .

CC

Therefore, pins V

and V

of the NMOS version SAB 80515 are used for other functions in

PD

B B

the SAB 80C515.

Pin 4 (the former pin V ) is the new PE pin which enables the use of the power saving modes.

PD

Pin 37 (the former pin V ) becomes an additional V pin. Thus, it is possible to insert a

BB

CC

decoupling capacitor between pin 37 (V ) and pin 38 (V ) very close to the device, thereby

CC

SS

avoiding long wiring and reducing the voltage distortion resulting from high dynamic current

peaks.

There is a difference between the NMOS and CMOS version concerning the clock circuitry.

When the device is driven from an external source, pin XTAL2 must be driven by the clock

signal; pin XTAL1, however, must be left open in the SAB 80C515 (must be tied low in the

NMOS version). When using the oscillator with a crystal there is no difference in the circuitry.

Thus, due to its pin compatibility the SAB 80C515 normally substitutes any SAB 80515 without

redesign of the user’s printed circuit board, but the user has to take care that the two V pins

CC

are hardwired on-chip. In any case, it is recommended that power is supplied on both V pins

CC

of the SAB 80C515 to improve the power supply to the chip.

If the power saving modes are to be used, pin PE must be tied low, otherwise these modes are

disabled.

Semiconductor Group

34

SAB 80C515/80C535

Instruction Set

The SAB 80C515 / 83C535 has the same instruction set as the industry standard 8051 micro-

controller.

A pocket guide is available which contains the complete instruction set in functional and hexa-

decimal order. Furtheron it provides helpful information about Special Function Registers, In-

terrupt Vectors and Assembler Directives.

Literature Information

Title

Ordering No.

Microcontroller Family SAB 8051 Pocket Guide

B158-H6579-X-X-7600

Semiconductor Group

35

SAB 80C515/80C535

Absolute Maximum Ratings

Ambient temperature under bias

SAB 80C515

0 to 70 °C

SAB 80C515-T3

Storage temperature

– 40 to 85 °C

– 65 to 150 °C

– 0.5 to 6.5 V

Voltage on V

pins with respect to ground (V )

CC

SS

Voltage on any pin with respect to ground (V )

– 0.5 to V + 0.5 V

SS

CC

Input current on any pin during overload condition

Absolute sum of all input currents during overload condition

Power disipation

– 10 mA to + 10 mA

|100 mA|

2 W

Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for longer

periods may affect device reliability. During overload conditions (V > V or V < V )

I N

CC

I N

SS

the Voltage on V pins with respect to ground (V ) must not exeed the values defined

CC

SS

by the absolute maximum ratings.

DC Characteristics

= 5 V ± 10 %; V = 0 V

V

CC

SS

T = 0 to 70 °C for the SAB 80C515/80C535

A

T = – 40 to 85 °C for the SAB 80C515/80C535-T3

A

Parameter

Symbol

Limit values

Unit Test condition

min.

max.

V

–

Input low voltage (except EA)

Input low voltage (EA)

V

– 0.5

0.2 V

– 0.1

I L

CC

– 0.5

0.2 V

I L1

I H

CC

– 0.3

Input high voltage

(except RESET and XTAL²⁾

0.2 V

+ 0.9

V

CC

+ 0.5

CC

Input high voltage to XTAL2

0.7 V

0.6 V

–

V

CC

+ 0.5

I H1

I H2

Input high voltage to RESET

V

CC

+ 0.5

I

= 1.6 mA ¹⁾

Output low voltage, ports

1, 2, 3, 4, 5

V

– 0.45

V

OL

Notes see page 38.

Semiconductor Group

36

SAB 80C515/80C535

DC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit Test condition

min.

max.

–

Output low voltage, port 0,

ALE, PSEN

V

0.45

V

I

= 3.2 mA 1)

OL1

OH

OL

–

Output high voltage, ports

1, 2, 3, 4, 5

2.4

0.9 V_{C C}

V

I

= – 80 µA

= – 10 µA

OH

–

Output high voltage (port 0 in

external bus mode, ALE,

PSEN)

2.4

0.9 V_{C C}

V

I

= – 400 µA

= – 40 µA ²⁾

OH1

OH

Logic 0 input current, ports 1, 2, I

3, 4, 5

– 10

– 70

µA

V_IN= 0.45 V

IL

Input low current to RESET for

reset

I

– 100

IL2

Input low current (XTAL2)

Input low current (PE)

I

–

– 15

– 20

– 650

µA

V_IN= 0.45 V

I L3

I L4

TL

–

Logical 1-to-0 transition current, I

– 65

V = 2 V

IN

ports 1, 2, 3, 4, 5

Input leakage current

(port 0, port 6, AN0-7, EA)

I

–

± 1

µA

0.45 < V < V

I N CC

L I

Pin capacitance

C

10

pF

f = 1 MHz,

C

I O

T = 25 ˚C

A

Power-supply current:

Active mode, 12 MHz ⁶⁾

Idle mode, 12 MHz ⁶⁾

Active mode, 16 MHz ⁶⁾

Idle mode, 16 MHz ⁶⁾

Power-down mode

– I

–

35

13

46

17

50

mA

µA

4)

5)

4)

5)

CC

PD

V

= 5 V

CC

3)

= 2 V to 5.5 V

Notes see page 38.

Semiconductor Group

37

SAB 80C515/80C535

Notes for page 36 and 37:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be

superimposed on the V of ALE and ports 1, 3, 4 and 5. The noise is due to external bus

OL

capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0

transitions during bus operation.

In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may

exceed 0.8 V.

Then, it may be desirable to qualify ALE with a Schmitttrigger, or use an address latch

with a Schmitttrigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to

momentarily fall below the 0.9 V specification when the address bits are stabilizing.

CC

3) Power-down I is measured with: EA = Port 0 = Port 6 = V ;

CC

XTAL1 = N.C.; XTAL2 = V ; RESET = V ; V

= V ; all other pins are disconnected.

SS

CC AGND

4) I (active mode) is measured with: XTAL2 driven with the clock signal according

CC

to the figure below; XTAL1 = N.C.; EA = Port 0 = Port 6 = V ; RESET = V ; all other

CC

SS

pins are disconnected. I might be slightly higher if a crystal oscillator is used.

CC

5) I (idle mode) is measured with: XTAL2 driven with the clock signal according to the

CC

figure below; XTAL1 = N.C.; EA = V ; Port 0 = Port 6 V ; RESET = V ; all other pins are

SS

CC

disconnected; all on-chip peripherals are disabled.

6) I at other frequencies is given by:

CC

Active mode: I

(mA) = 2.67 × f

(MHz) + 3.00

OSC

CC max

Idle mode: I

(mA) = 0.88 × f

(MHz) + 2.50

OSC

CC max

where f

is the oscillator frequency in MHz.

OSC

I

is given in mA and measured at V = 5 V (see also notes 4 and 5)

CC

CC max

Semiconductor Group

38

SAB 80C515/80C535

A/D Converter Characteristics

V

= 5 V ± 10 %; V = 0 V; V

= V ± 5 %; V

= V ± 0.2 V;

AGND SS

CC

SS

AREF

CC

–V

≥ 1 V;

T = 0 to 70 ˚C for SAB 80C515/80C535

I ntAREF

IntAGND

A

T = – 40 to 85 ˚C for SAB 80C515/80C535-T40/85

A

Parameter

Symbol

Limit values

Unit

Test condition

min.

typ.

max.

–

9)

7)

Analog input voltage

V

C

V

– 0.2

V

AREF

+ 0.2

V

AINPUT

I

AGND

Analog input

capacitance

–

25

45

pF

Load time

t

–

2 t

7 t

µs

–

L

CY

Sample time

(incl. load time)

S

C

Conversion time

(incl. sample time)

t

–

13 t

µs

–

CY

TUE

Total unadjusted

error

± 1

± 2

LSB

V

=

I ntAREF

= V

AREF

CC

=

I ntAGND

= V 7)

AGND

SS

8)

V

supply current

I

–

5

mA

mV

AREF

REF

Internal reference error

V

± 30

I nt REFERR

7)

The output impedance of the analog source must be low enough to assure full loading

of the sample capacitance (C ) during load time (t_L) . After charging of the internal

I

capacitance (C_I) in the load time (t_L) the analog input must be held constant for the rest

of the sample time (t )

S

8)

9)

The differential impedance r of the analog reference voltage source must be less than

D

1 kΩ at reference supply voltage.

Exceeding these limit values at one or more input channels will cause additional

current which is sinked / sourced at these channels. This may also affect the accuracy

of other channels which are operated within these specifications.

Semiconductor Group

39

SAB 80C515/80C535

AC Characteristics

= 5 V ± 10%; V = 0 V (C_Lfor Port 0, ALE and PSEN outputs = 100 pF;

V

CC

SS

C for all outputs = 80 pF);

T = 0 to 70 ˚C for SAB 80C515/80C535

L

A

T = – 40 to 85 ˚C for SAB 80C515/80C535-T40/85

A

Parameter

Symbol

Limit values

Unit

12 MHz clock

Variable clock

= 3.5 MHz to 12 MHz

1/t

CLCL

min.

max.

min.

max.

Program Memory Characteristics

ALE pulse width

t

127

–

2 t

– 40

C LCL

–

ns

LHLL

AVLL

LLAX

LLIV

Address setup to ALE

Address hold after ALE

53

48

–

t

– 30

–

C LCL

–

– 35

–

ALE to valid instruction

in

233

–

4 t

– 100 ns

CLCL

C LCL

ALE to PSEN

t

58

215

–

t

– 25

–

ns

LLPL

PLPH

PLIV

C LCL

PSEN pulse width

3 t

– 35

C LCL

PSEN to valid instruction t

in

150

–

3 t

– 100 ns

–

Input instruction hold

after PSEN

t

0

ns

PXIX

1)

–

Input instruction float

after PSEN

–

63

t

– 20

C LCL

ns

PXIZ

)

1

Address valid after

PSEN

75

–

t

– 8

C LCL

PXAV

A VIV

A ZPL

–

Address to valid instruc- t

tion in

302

–

5 t

– 115 ns

ns

C LCL

–

Address float to PSEN

t

0

1)

Interfacing the SAB 80C515 to devices with float times up to 75 ns is permissible.

This limited bus contention will not cause any damage to port 0 drivers.

Semiconductor Group

40

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter Symbol

Limit values

Unit

12 MHz clock

Variable clock

1/t

= 3.5 MHz to 12 MHz

CLCL

min.

max.

min.

max.

External Data Memory Characteristics

–

RD pulse width

t

400

132

–

6 t

2 t

–

– 100

ns

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

CLCL

–

WR pulse width

–

– 100

– 35

–

Address hold after ALE

RD to valid data in

DATA hold after RD

Data float after RD

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

252

–

5 t

– 165 ns

CLCL

0

–

ns

–

97

2 t

8 t

9 t

3 t

– 70

CLCL

–

517

585

300

123

– 150 ns

– 165 ns

–

AVDV

LLWL

WHLH

200

43

3 t

– 50

+ 50

+ 40

ns

CLCL

WR or RD high to ALE

high

t

– 40

t

CLCL

Address valid to WR

t

203

33

–

4 t

– 130

–

ns

AVWL

QVWX

Data valid to WR

transition

t

– 50

CLCL

Data setup before WR

Data hold after WR

t

288

13

–

0

7 t

– 150

– 50

–

0

ns

QVWH

WHQX

RLAZ

t

CLCL

Address float after RD

–

Semiconductor Group

41

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit

Variable clock

Frequ. = 3.5 MHz to 12 MHz

min.

max.

External Clock Drive

Oscillator period

Oscillator frequency

High time

t

83.3

0.5

20

–

285

12

–

ns

CLCL

1/t

MHz

ns

CLCL

t

CHCX

–

Low time

ns

CLCX

CLCH

CHCL

Rise time

20

ns

–

Fall time

ns

External Clock Cycle

Semiconductor Group

42

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit

12 MHz clock

Variable clock

1/t

= 3.5 MHz to 12 MHz

CLCL

min.

max.

min.

max.

System Clock Timing

ALE to CLKOUT

t

543

–

7 t

2 t

– 40

–

ns

LLSH

SHSL

SLSH

SLLH

CLCL

CLKOUT high time

CLKOUT low time

127

793

43

–

10 t

– 40

CLCL

CLKOUT low to ALE

high

123

t

– 40

t

+ 40

CLCL

System Clock Timing

Semiconductor Group

43

SAB 80C515/80C535

AC Characteristics for SAB 80C515-16/80C535-16

= 5 V ± 10 %; V = 0 V (C_Lfor Port 0, ALE and PSEN outputs = 100 pF;

V

CC

SS

C_Lfor all outputs = 80 pF)

T = 0 to 70 ˚C for SAB 80C515-16/80C535-16

A

T = – 40 to 85 ˚C for SAB 80C515-16/80C535-16-T40/85

A

Parameter

Symbol

Limit values

Unit

16 MHz clock

Variable clock

= 3.5 MHz to 16 MHz

1/t

CLCL

min.

max.

min.

max.

Program Memory Characteristics

–

ALE pulse width

t

85

2 t

– 40

C LC L

ns

LHLL

AVLL

LLAX

LLIV

–

Address setup to ALE

Address hold after ALE

33

28

–

t

– 30

CLCL

–

– 35

–

ALE to valid instruction

in

150

4 t

– 100 ns

CLCL

–

ALE to PSEN

t

38

153

–

t

– 25

ns

LLPL

PLPH

PLIV

CLCL

PSEN pulse width

3 t

– 35

CLCL

–

PSEN to valid instruction t

88

3 t

– 100 ns

in

–

Input instruction hold

after

PSEN

t

0

ns

PXIX

–

Input instruction float

1)

43

t

– 20

CLCL

ns

PXIZ

after

PSEN

)

1

Address valid after

PSEN

t

55

t

– 8

ns

– 115 ns

ns

PXAV

AVIV

AZPL

CLCL

–

Address to valid

instruction in

198

5 t

CLCL

–

Address float to PSEN

0

1)

Interfacing the SAB 80C515-16 to devices with float times up to 55 ns is permissible.

This limited bus contention will not cause any damage to port 0 drivers.

Semiconductor Group

44

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter Symbol

Limit values

Unit

16 MHz clock

Variable clock

= 3.5 MHz to 16 MHz

1/t

CLCL

min.

max.

min.

max.

External Data Memory Characteristics

RDpulse width

t

275

90

–

6 t

2 t

–

– 100

–

ns

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

–

– 100

– 35

–

Address hold after ALE

RD to valid data in

Data hold after RD

Data ﬂoat after RD

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

148

–

5 t

–

– 165 ns

ns

CLCL

0

–

55

–

2 t

– 70

ns

CLCL

–

350

398

238

103

–

8t

– 150

–

9 t

– 165 ns

AVDV

LLWL

WHLH

CLCL

138

23

3 t

– 50

3 t

+ 50

ns

CLCL

WR or RD high to ALE

high

t

– 40

t

+ 40

CLCL

Address valid to WR

t

120

13

–

4 t

– 130

–

ns

AVWL

QVWX

Data valid to WR transi-

tion

t

– 50

CLCL

Data setup before WR

Data hold after WR

t

288

13

–

0

7 t

– 150

– 50

–

0

ns

QVWH

WHQX

RLAZ

t

CLCL

Address ﬂoat after RD

–

Semiconductor Group

45

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit

Variable clock

Frequ. = 3.5 MHz to 16 MHz

min.

max.

External Clock Drive

Oscillator period

Oscillator frequency

High time

t

62.5

0.5

15

–

285

16

–

ns

CLCL

1/t

MHz

ns

CLCL

t

CHCX

–

Low time

ns

CLCX

CLCH

CHCL

Rise time

15

ns

–

Fall time

ns

External Clock Cycle

Semiconductor Group

46

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit

16 MHz clock

Variable clock

= 3.5 MHz to 16 MHz

1/t

CLCL

min.

max.

min.

max.

System Clock Timing

ALE to CLK OUT

t

398

–

7 t

2 t

– 40

–

ns

LLSH

SHSL

SLSH

SLLH

CLCL

CLK OUT high time

CLK OUT low time

85

–

– 40

CLCL

585

23

–

10 t

CLCL

CLK OUT low to ALE

high

103

t

– 40

t

+ 40

CLCL

System Clock Timing

Semiconductor Group

47

SAB 80C515/80C535

AC Characteristics for SAB 80C515-20 / 80C535-20

= 5 V ± 10 %; V = 0 V T = 0 ˚C to + 70 ˚C

V

CC

SS

A

(C for port 0, ALE and PSEN outputs = 100 pF; C for all other outputs = 80 pF)

L

Parameter

Symbol

Limit values

Unit

20 MHz

clock

Variable clock

= 3.5 MHz to 20 MHz

1/t

CLCL

min. max.

min.

max.

Program Memory Characteristics

ALE pulse width

t

60

20

–

2 t

– 40

–

ns

LHLL

AVLL

LLAX

LLIV

CLCL

Address setup to ALE

Address hold after ALE

ALE low to valid instr in

ALE to PSEN

–

t

– 30

–

CLCL

–

– 30

–

100

–

4 t

–

– 100 ns

CLCL

25

115

–

t

– 25

ns

LLPL

PLPH

PLIV

PXIX

CLCL

PSEN pulse width

PSEN to valid instr in

–

3 t

–

– 35

–

CLCL

75

–

3 t

–

– 75

CLCL

Input instruction hold

after PSEN

0

)

Input instruction float

after PSEN

t

*

–

40

–

t

– 10

CLCL

ns

PXIZ

)

Address valid after PSEN t

*

47

–

t

– 3

CLCL

–

ns

PXAV

AVIV

AZPL

Address to valid instr in

Address float to PSEN

t

190

–

0

5 t

–

– 60

CLCL

0

)

* Interfacing the SAB 80C515 / 80C535 microcontrollers to devices with float times up to 45 ns is permissible.

This limited bus contention will not cause any damage to port 0 drivers.

Semiconductor Group

48

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Unit

20 MHz

clock

Variable clock

1/t

= 3.5 MHz to 20 MHz

CLCL

min. max.

min.

max.

External Data Memory Characteristics

RD pulse width

t

200

65

–

6 t

2 t

–

– 100 –

ns

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

–

Address hold after ALE

RD to valid data in

Data hold after RD

Data float after RD

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

– 35

–

155

–

5 t

–

– 95

CLCL

0

–

40

250

285

200

–

2 t

8 t

9 t

3 t

– 60

CLCL

–

– 150 ns

– 165 ns

–

AVDV

LLWL

AVWL

WHLH

100

70

20

3 t

4 t

– 50

+ 50

ns

CLCL

Address valid to WR or RD t

– 130 –

CLCL

WR or RD high to ALE

high

t

80

t

– 30

t

+ 30

CLCL

Data valid to WR transition

Data setup before WR

Data hold after WR

t

5

–

0

t

– 45

–

ns

QVWX

QVWH

WHQX

RLAZ

CLCL

200

10

–

7 t

CLCL

– 150 –

t

– 40

–

0

CLCL

Address float after RD

–

Semiconductor Group

49

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit Values

Variable clock

Unit

1/t

= 3.5 MHz to 20 MHz

CLCL

min.

max.

External Clock Drive

Oscillator period

High time

t

50

12

–

285

ns

CLCL

CHCX

CLCX

CLCH

CHCL

t

– t

CLCL

CLCX

CHCX

Low time

t

Rise time

12

Fall time

–

External Clock Cycle

Semiconductor Group

50

SAB 80C515/80C535

AC Characteristics (cont’d)

Parameter

Symbol

Limit values

Variable clock

Unit

20 MHz

clock

1/t

= 3.5 MHz to 20 MHz

CLCL

min. max.

min.

max.

System Clock Timing

ALE to CLKOUT

t

310

60

–

7 t

2 t

– 40

–

ns

LLSH

SHSL

SLSH

SLLH

CLCL

CLKOUT high time

CLKOUT low time

–

– 40

460

10

–

10 t

– 40 –

CLCL

CLKOUT low to ALE high

90

t

– 40

t

+ 40

CLCL

External Clock Cycle

Semiconductor Group

51

SAB 80C515/80C535

ROM Verification Characteristics

T = 25 ˚C ± 5 ˚C; V = 5 V ± 10 %; V

= 0 V

A

CC

SS

Parameter

Symbol

Limit values

Unit

min.

max.

ROM Verification

–

Address to valid data

ENABLE to valid data

t

48 t

6

ns

AVQV

ELQV

EHOZ

CLCL

–

ns

Data float after ENABLE t

0

4

–

ns

Oscillator frequency

Address to valid data

1/t

MHz

ns

CLCL1

t

48 t

AVQV

CLCL

ROM Verification

Semiconductor Group

52

SAB 80C515/80C535

Waveforms

Program Memory Read Cycle

Data Memory Read Cycle

Semiconductor Group

53

SAB 80C515/80C535

AC inputs during testing are driven at V_{C C}– 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at V_{IH min}for a logic '1' and V_{IL max}for a logic '0'.

Data Memory Write Cycle

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and

begins to float when a 100 mV deviation from the load voltage V_{O H}/V _{O L}occurs. I_{O L}/I _{O H}≥ ± 20 mA.

Recommended Oscillator Circuits

Semiconductor Group

54

SAB 80C515/80C535

AC Testing: Input, Output Waveforms

AC Testing: Float Waveforms

Semiconductor Group

55


型号：	SAB80C516-16
厂家：	Infineon
描述：	8-Bit CMOS Single-Chip Microcontroller 8位CMOS单芯片微控制器微控制器
文件：	总56页 (文件大小：667K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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