SAFC501 [INFINEON]
8-Bit CMOS Microcontroller; 8位CMOS微控制器
| 型号： | SAFC501 |
| 厂家： | 
Infineon |
| 描述： | 8-Bit CMOS Microcontroller |
| 文件： | 总48页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microcomputer Components
8-Bit CMOS Microcontroller
C501
Data Sheet 04.97
C501 Data Sheet
Revision History :
1997-04-01
Previous Releases :
11.92, 11.93, 08.94, 08.95, 10.96
Subjects (changes since last revision)
Page
Page
(previous (new
version)
general
version)
C501G-1E OTP version included
4
5
4
5
Ordering information resorted and C501G-1E types added
Table with literature hints added
5-7
11
5-7
11
Pin configuration logic symbol for pins EA/Vpp and ALE/PROG updated
Pin description for ALE/PROG and EA/Vpp completed
8, 9, 10
8, 9, 10 Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi-
bidirectional”
13
14
-
13
14
15
Block diagram updated for C501G-1E
New design of register (PSW) description
“Memory organization” added
15-18
17
-
-
41
-
16-18
17
25-28
31
41
43, 44
Actualized design of the SFR tables
Reset value of T2CON corrected
Description for the C501-1E OTP version added
DC characteristics for C501-1E added
Timing “External Clock Drive” now behind “Data Memory Cycle”
AC characteristics for C501-1E added
Edition 1997-04-01
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.
1
A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2
Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
8-Bit CMOS Microcontroller
C501
Preliminary
• Fully compatible to standard 8051 microcontroller
• Versions for 12/24/40 MHz operating frequency
• Program memory : completely external (C501-L)
8K × 8 ROM (C501-1R)
8K × 8 OTP memory (C501-1E)
• 256 × 8 RAM
• Four 8-bit ports
• Three 16-bit timers / counters (timer 2 with up/down counter feature)
• USART
• Six interrupt sources, two priority levels
• Power saving modes
• Quick Pulse programming algorithm (C501-1E only)
• 2-Level program memory lock (C501-1E only)
• P-DIP-40, P-LCC-44, and P-MQFP-44 package
• Temperature ranges :
SAB-C501
SAF-C501
TA : 0 ˚C to 70 ˚C
TA : – 40 ˚C to 85 ˚C
Power
Saving
Modes
RAM
256 x 8
Port 0
Port 1
Port 2
Port 3
Ι
Ι
Ι
Ι
/O
/O
/O
/O
T0
T1
USART
T2
CPU
8K x 8 ROM (C501-1R)
8K x 8 OTP (C501-1E)
MCA03238
Figure 1
C501G Functional Units
Semiconductor Group
3
1997-04-01
C501
The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/
write data memory, four ports, three 16-bit timers counters, a seven source, two priority level
interrupt structure and a serial port. The C501-L is identical, except that it lacks the program
memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip.
The term C501 refers to all versions within this specification unless otherwise noted. Further, the
term C501 refers to all versions which are available in the different temperature ranges, marked with
SAB-C501... or SAF-C501.... .
Ordering Information
Type
Ordering Code Package
Description
(8-Bit CMOS microcontroller)
SAB-C501G-LN
SAB-C501G-LP
SAB-C501G-LM
Q67120-C969
Q67120-C968
Q67127-C970
P-LCC-44
P-DIP-40
P-MQFP-44
for external memory (12 MHz)
for external memory (24 MHz)
for external memory (40 MHz)
for external memory (24 MHz)
SAB-C501G-L24N
SAB-C501G-L24P
SAB-C501G-L24M
Q67120-C1001 P-LCC-44
Q67120-C999 P-DIP-40
Q67127-C1014 P-MQFP-44
SAB-C501G-L40N
SAB-C501G-L40P
SAB-C501G-L40M
Q67120-C1002 P-LCC-44
Q67120-C1000 P-DIP-40
Q67127-C1009 P-MQFP-44
SAF-C501G-L24N
SAF-C501G-L24P
Q67120-C1011 P-LCC-44
Q67120-C1010 P-MQFP-44 ext. temp. – 40 ˚C to 85 ˚C
SAB-C501G-1RN
SAB-C501G-1RP
SAB-C501G-1RM
Q67120-DXXX P-LCC-44
Q67120-DXXX P-DIP-40
Q67127-DXXX P-MQFP-44
with mask-programmable ROM (12 MHz)
SAB-C501G-1R24N Q67120-DXXX P-LCC-44
SAB-C501G-1R24P Q67120-DXXX P-DIP-40
SAB-C501G-1R24M Q67127-DXXX P-MQFP-44
with mask-programmable ROM (24 MHz)
with mask-programmable ROM (40 MHz)
SAB-C501G-1R40N Q67120-DXXX P-LCC-44
SAB-C501G-1R40P Q67120-DXXX P-DIP-40
SAB-C501G-1R40M Q67127-DXXX P-MQFP-44
SAF-C501G-1R24N Q67120-DXXX P-LCC-44
SAF-C501G-1R24P Q67120-DXXX P-DIP-40
with mask-programmable ROM (24 MHz)
ext. temp. – 40 ˚C to 85 ˚C
SAB-C501G-1EN
SAB-C501G-1EP
Q67120-C1054 P-LCC-44
Q67120-C1056 P-DIP-40
with OTP memory (12 MHz)
SAF-C501G-1EN
SAF-C501G-1EP
Q67120-C2002 P-LCC-44
Q67120-C2003 P-DIP-40
with OTP memory (12 MHz))
ext. temp. – 40 ˚C to 85 ˚C
SAB-C501G-1E24N Q67120-C2005 P-LCC-44
SAB-C501G-1E24P Q67120-C2006 P-DIP-40
with OTP memory (24 MHz)
SAF-C501G-1E24N Q67120-C2008 P-LCC-44
SAF-C501G-1E24P Q67120-C2009 P-DIP-40
with OTP memory (24 MHz))
ext. temp. – 40 ˚C to 85 ˚C
Semiconductor Group
4
1997-04-01
C501
Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request.
The ordering number of ROM types (DXXX extensions) is defined after program release
(verification) of the customer.
Additional Literature
For further information about the C501 the following literature is available :
Title
Ordering Number
C501 8-Bit CMOS Microcontroller User’s Manual
B158-H6723-X-X-7600
B158-H6987-X-X-7600
C500 Microcontroller Family
Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide
B158-H6986-X-X-7600
V
6
5
4
3
2
1 44 43 42 41 40
P1.5
P1.6
7
8
39
38
37
36
35
34
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
P1.7
9
RESET
RxD/P3.0
N.C.
10
11
12
13
14
15
16
17
C501
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
MCP03214
V
Figure 2
Pin Configuration P-LCC-44 Package (Top view)
Semiconductor Group
5
1997-04-01
C501
T2/P1.0
T2EX/P1.1
P1.2
1
40
39
VCC
2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
3
38
P1.3
4
37
P1.4
5
36
P1.5
6
35
P1.6
7
34
P1.7
8
33
RESET
RxD/P3.0
TxD/P3.1
INT0/P3.2
9
32
10
11
12
13
14
15
16
17
18
19
20
31
C501
30
ALE/PROG
PSEN
29
28
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
27
26
25
24
23
XTAL1
22
21
P2.0/A8
VSS
MCP03215
Figure 3
Pin Configuration P-DIP-40 Package (top view)
Semiconductor Group
6
1997-04-01
C501
V
33 32 31 30 29 28 27 26 25 24 23
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
N.C.
P1.0/T2
P1.1/T2EX
P1.2
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
N.C.
VSS
XTAL1
C501
XTAL2
RD/P3.7
WR/P3.6
P1.3
P1.4
1
2
3
4
5
6
7
8
9 10 11
MCP03216
Figure 4
Pin Configuration P-MQFP-44 Package (top view)
VCC
VSS
Port 0
8-Bit Digital Ι /O
XTAL1
XTAL2
Port 1
8-Bit Digital Ι /O
RESET
C501
Port 2
8-Bit Digital Ι /O
EA/
VPP
ALE/PROG
PSEN
Port 3
8-Bit Digital Ι /O
MCL03217
Figure 5
Logic Symbol
Semiconductor Group
7
1997-04-01
C501
Table 1
Pin Definitions and Functions
Symbol
Pin Number
P-LCC-44 P-DIP-40 P-MQFP-44
I/O*) Function
P1.0 – P1.7 2–9
1–8
40–44,
1–3,
I/O
Port 1
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 1 pins that
have 1s written to them are pulled high by
the internal pullup resistors, and in that
state can be used as inputs. As inputs,
port 1 pins being externally pulled low will
source current (IIL, in the DC character-
istics) because of the internal pull-up
resistors. Port 1 also contains the timer 2
pins as secondary function. The output
latch corresponding to a secondary
function must be pro-grammed to a one
(1) for that function to operate.
The secondary functions are assigned to
the pins of port 1, as follows:
2
3
1
2
40
41
P1.0 T2
Input to counter 2
P1.1 T2EX Capture - Reload trigger of
timer 2 / Up-Down count
*) I = Input
O = Output
Semiconductor Group
8
1997-04-01
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
P3.0 – P3.7 11,
13–19
10–17
5, 7–13
I/O
Port 3
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 3 pins that
have 1s written to them are pulled high by
the internal pull-up resistors, and in that
state they can be used as inputs. As
inputs, port 3 pins being externally pulled
low will source current (IIL, in the DC
characteristics) because of the internal
pull-up resistors. Port 3 also contains the
interrupt, timer, serial port 0 and external
memory strobe pins which are used by
various options. The output latch
corresponding to a secondary function
must be programmed to a one (1) for that
function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
11
13
10
11
5
7
P3.0 R×D receiver data input (asyn-
chronous) or data input
output (synchronous) of
serial interface 0
P3.1 T×D transmitter data output
(asynchronous) or clock
output (synchronous) of
the serial interface 0
14
15
12
13
8
9
P3.2 INT0 interrupt 0 input/timer 0
gate control
P3.3 INT1 interrupt 1 input/timer 1
gate control
16
17
18
14
15
16
10
11
12
P3.4 T0
P3.5 T1
P3.6 WR
counter 0 input
counter 1 input
the write control signal lat-
ches the data byte from
port 0 into the external
data memory
19
17
13
P3.7 RD
the read control signal
enables the external data
memory to port 0
*) I = Input
O = Output
Semiconductor Group
9
1997-04-01
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
XTAL2
20
18
14
–
–
XTAL2
Output of the inverting oscillator
amplifier.
XTAL1
21
19
15
XTAL1
Input to the inverting oscillator amplifier
and input to the internal clock generator
circuits.
To drive the device from an external
clock source, XTAL1 should be driven,
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, since the input
to the internal clocking circuitry is divided
down by a divide-by-two flip-flop.
Minimum and maximum high and low
times as well as rise fall times specified
in the AC characteristics must be
observed.
P2.0 – P2.7 24–31
21–28
18–25
I/O
Port 2
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high
by the internal pull-up resistors, and in
that state they can be used as inputs. As
inputs, port 2 pins being externally pulled
low will source current (IIL, in the DC
characteristics) because of the internal
pull-up resistors. Port 2 emits the high-
order address byte during fetches from
external program memory and during
accesses to external data memory that
use 16-bit addresses (MOVX @DPTR).
In this application it uses strong internal
pull-up resistors when issuing 1s. During
accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port
2 issues the contents of the P2 special
function register.
*) I = Input
O = Output
Semiconductor Group
10
1997-04-01
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
PSEN
32
29
26
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus
during external fetch operations. It is
activated every six oscillator periods
except during external data memory
accesses. Remains high during internal
program execution.
RESET
10
9
4
I
RESET
A high level on this pin for two machine
cycles while the oscillator is running
resets the device. An internal diffused
resistor to VSS permits power-on reset
using only an external capacitor to VCC.
ALE/PROG 33
30
27
I/O
The Address Latch Enable
output is used for latching the low-byte of
the address into external memory during
normal operation. It is activated every six
oscillator periods except during an
external data memory access.
For the C501-1E this pin is also the
program pulse input (PROG) during OTP
memory programming.
EA/VPP
35
31
29
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (C501-1R
and C501-1E) when the PC is less than
2000 . When held at low level, the C501
H
fetches all instructions from external
program memory. For the C501-L this
pin must be tied low.
This pin also receives the programming
supply voltage VPP during OTP memory
programming (C501-1E) only).
*) I = Input
O = Output
Semiconductor Group
11
1997-04-01
C501
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
P0.0 – P0.7 43–36
39–32
37–30
I/O
Port 0
is an 8-bit open-drain bidirectional I/O
port. Port 0 pins that have 1s written to
them float, and in that state can be used
as high-impedance inputs. Port 0 is also
the multiplexed low-order address and
data bus during accesses to external
program or data memory. In this
application it uses strong internal pull-up
resistors when issuing 1s.
Port 0 also outputs the code bytes during
program verification in the C501-1R and
C501-1E. External pull-up resistors are
required during program verification.
VSS
22
44
20
40
–
16
38
–
–
–
Circuit ground potential
Supply terminal for all operating modes
No connection
VCC
N.C.
1, 12,
6, 17,
23, 34
28, 39
*) I = Input
O = Output
Semiconductor Group
12
1997-04-01
C501
Functional Description
The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational
characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the
timer 2 unit.
Figure 6 shows a block diagram of the C501.
C501
VCC
C501-1R : ROM
C501-1E : OTP
RAM
VSS
XTAL1
XTAL2
8K x 8
256 x 8
OSC & Timing
CPU
RESET
ALE/PROG
PSEN
Port 0
8-Bit Digit. Ι /O
Timer 0
Timer 1
Timer 2
Port 0
Port 1
Port 2
Port 3
EA/VPP
Port 1
8-Bit Digit. Ι /O
Port 2
8-Bit Digit. Ι /O
Interrupt Unit
Port 3
8-Bit Digit. Ι /O
Serial Channel
(USART)
MCB03219
Figure 6
Block Diagram of the C501
Semiconductor Group
13
1997-04-01
C501
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs
24 MHz: 500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0 )
H
Reset Value : 00
H
Bit No. MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
H
H
H
H
H
H
H
H
D0
CY
AC
F0
RS1
RS0
OV
F1
P
PSW
H
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
F0
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1
RS0
Function
Bank 0 selected, data address 00 -07
0
0
1
1
0
1
0
1
H
H
Bank 1 selected, data address 08 -0F
H
H
Bank 2 selected, data address 10 -17
H
H
Bank 3 selected, data address 18 -1F
H
H
OV
Overflow Flag
Used by arithmetic instruction.
General Purpose Flag
Parity Flag
F1
P
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
14
1997-04-01
C501
Memory Organization
The C501 CPU manipulates data and operands in the following four address spaces:
– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128 byte special function register area
Figure 7 illustrates the memory address spaces of the C501.
FFFF
FFFF
H
H
External
External
Indirect
Address
Direct
Address
FF
80
FF
80
H
H
H
H
Special
Function
Register
Internal
RAM
2000
H
7F
H
1FFF
H
H
Internal
(EA = 1)
External
(EA = 0)
Internal
RAM
0000
0000
00
H
H
"Code Space"
"Data Space"
"Internal Data Space"
MCD03224
Figure 7
C501 Memory Map
Semiconductor Group
15
1997-04-01
C501
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 27 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits
0-2 are 0 (e.g. 80 , 88 , 90 , 98 , ..., F8 , FF ) are bitaddressable.
H
H
H
H
H
H
The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Semiconductor Group
16
1997-04-01
C501
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address Contents after
Reset
1)
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0
F0
83
82
00
00
00
00
00
07
H
H
H
H
H
H
H
1)
H
H
H
1)
D0
H
81
H
1)
1)
3)
3)
Interrupt
System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8
B8
0X000000
XX000000
H
H
B
B
1)
1)
1)
1)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80
90
A0
B0
FF
H
H
H
H
H
FF
H
FF
H
FF
H
3)
Serial
Channel
PCON 2)
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
87
99
98
0XXX0000
H
H
H
B
3)
XX
00
H
H
1)
1)
Timer 0 / TCON
Timer 1
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88
00
H
H
TH0
TH1
TL0
TL1
TMOD
8C
8D
8A
00
H
H
H
H
H
00
H
00
H
8B
89
00
H
00
H
H
1)
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, High Byte CB
Timer 2 Reload/Capture Register, Low Byt CA
Timer 2 High Byte
Timer 2 Low Byte
C8
C9
00
H
XXXXXXX0
H
H
H
H
H
H
3)
B
00
H
00
H
CD
CC
00
H
TL2
00
H
3)
Pow.Sav. PCON 2)
Modes
Power Control Register
87
0XXX0000
H
B
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
Semiconductor Group
17
1997-04-01
C501
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register Content Bit 7
after
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1)
Reset
2)
80
81
82
83
87
P0
FF
07
.7
.7
.7
.7
.6
.6
.6
.6
.5
.5
.5
.5
–
.4
.4
.4
.4
–
.3
.2
.1
.0
H
H
H
H
H
H
SP
.3
.2
.1
.0
H
H
H
DPL
DPH
PCON
00
00
.3
.2
.1
.0
.3
.2
.1
.0
0XXX- SMOD –
0000
GF1
GF0
PDE
IDLE
B
2)
88
89
TCON
TMOD
TL0
00
00
00
00
00
00
TF1
TR1
TF0
M1
.5
TR0
M0
.4
IE1
IT1
IE0
M1
.1
IT0
M0
.0
H
H
H
H
H
H
H
H
GATE C/T
GATE C/T
8A
.7
.6
.3
.2
H
H
8B
TL1
.7
.6
.5
.4
.3
.2
.1
.0
8C
8D
90
TH0
TH1
P1
.7
.6
.5
.4
.3
.2
.1
.0
H
H
.7
.6
.5
.4
.3
.2
.1
.0
2)
FF
00
.7
.6
.5
.4
.3
.2
.1
.0
H
H
H
H
2)
98
99
SCON
SBUF
P2
SM0
.7
SM1
.6
SM2
.5
REN
.4
TB8
.3
RB8
.2
TI
RI
.0
H
XX
.1
H
2)
2)
A0
A8
FF
.7
.6
.5
.4
.3
.2
.1
.0
H
H
H
IE
0X00-
0000
EA
–
ET2
ES
ET1
EX1
ET0
EX0
B
2)
2)
B0
B8
P3
IP
FF
RD
–
WR
–
T1
T0
INT1
PT1
INT0
PX1
TxD
PT0
RxD
PX0
H
H
H
XX00.
0000
PT2
PS
B
2)
C8
C9
T2CON 00
TF2
–
EXF2 RCLK TCLK EXEN2 TR2
C/T2
–
CP/RL2
DCEN
H
H
T2MOD XXXX-
XXX0
–
–
–
–
–
H
B
CA
CB
RC2L
RC2H
TL2
00
00
00
00
00
00
00
.7
.7
.7
.7
CY
.7
.7
.6
.6
.6
.6
AC
.6
.6
.5
.5
.5
.5
F0
.5
.5
.4
.3
.2
.1
.1
.1
.1
F1
.1
.1
.0
.0
.0
.0
P
H
H
H
H
H
H
H
H
H
.4
.3
.2
CC
CD
D0
.4
.3
.2
H
TH2
PSW
ACC
B
.4
.3
.2
H
2)
RS1
.4
RS0
.3
OV
.2
H
2)
E0
F0
.0
.0
H
2)
.4
.3
.2
H
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
Semiconductor Group
18
1997-04-01
C501
Timer / Counter 0 and 1
Timer/counter 0 and 1 can be used in four operating modes as listed in table 4.
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode Description
TMOD
Gate C/T M1
Input Clock
internal external (max)
M0
0
8-bit timer/counter with a
X
X
0
0
fOSC 12 × 32
/
fOSC/24 × 32
divide-by-32 prescaler
1
2
16-bit timer/counter
X
X
X
X
1
0
1
0
fOSC 12
/
fOSC 24
/
8-bit timer/counter with
8-bit autoreload
fOSC 12
/
fOSC 24
/
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
X
X
1
1
fOSC 12
/
fOSC/24
Timer 1 stops
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INTO and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the
input clock logic.
f OSC
f OSC/12
÷
12
C/T
TMOD
0
1
P3.4/T0
P3.5/T1
max f OSC/24
Timer 0/1
Input Clock
TR 0/1
TCON
Control
&
Gate
=1
TMOD
_
<
1
P3.2/INT0
P3.3/INT1
MCS01768
Figure 8
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
19
1997-04-01
C501
Timer 2
Timer 2 is a 16-bit timer/counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Table 5
Timer/Counter 2 Operating Modes
T2CON
T2MOD T2CON
Input Clock
external
P1.1/
T2EX
R×CLK
Mode
Remarks
CP/
or
TR2
internal
RL2
(P1.0/T2)
DCEN
EXEN
T×CLK
16-bit
Auto-
reload
0
0
0
1
1
0
0
X
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
0
0
1
↓
max
OSC/24
f
OSC/12
f
f
f
0
0
0
0
1
1
1
1
X
X
0
1
16-bit
Cap-
ture
0
1
1
X
0
X
16 bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
max
OSC/24
fOSC/12
0
1
1
X
1
↓
Baud
Rate
Gene-
rator
1
1
X
X
1
1
X
X
0
1
X
no overflow
interrupt
request (TF2)
extra external
interrupt
max
OSC/24
f
OSC/2
↓
(“Timer 2”)
off
X
X
0
X
X
X
Timer 2 stops
–
–
Note: ↓ =
falling edge
Semiconductor Group
20
1997-04-01
C501
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 7.
Table 6
USART Operating Modes
SCON
Baudrate
Description
Mode
SM0
SM1
0
0
0
1
1
0
f
OSC/12
Serial data enters and exits through R×D.
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
1
2
3
1
0
1
Timer 1/2 overflow rate
8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
f
OSC/32 or fOSC/64
9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
Timer 1/2 overflow rate
9-bit UART
Like mode 2 except the variable baud rate
Table 7
Formulas for Calculating Baudrates
Baud Rate
Interface Mode
Baudrate
derived from
Oscillator
0
2
fOSC/12
(2SMOD × fOSC) / 64
Timer 1 (16-bit timer)
(8-bit timer with
1,3
1,3
(2SMOD × timer 1 overflow rate) /32
(2SMOD × fOSC) / (32 × 12 × (256-TH1))
8-bit autoreload)
Timer 2
1,3
fOSC / (32 × (65536-(RC2H, RC2L))
Semiconductor Group
21
1997-04-01
C501
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of
the interrupt sources and illustrates the request and control flags.
High Priority
Low Priority
Timer 0 Overflow
TF0
TCON.5
ET0
IE.1
PT0
IP.1
Timer 1 Overflow
Timer 2 Overflow
TF1
TCON.7
TCON.0
ET1
IE.3
PT1
IP.3
TF2
T2CON.7
_
<
1
P1.1/
T2EX
EXF2
T2CON.6
ET2
IE.5
PT2
IP.5
EXEN2
T2CON.3
RI
SCON.0
_
<
1
USART
TI
ES
PS
SCON.1
IE.4
IP.4
P3.2/
INT0
IE0
TCON.1
IT0
EX0
IE.0
PX0
IP.0
TCON.0
P3.3/
INT1
IE1
TCON.3
IT1
EX1
IE.2
EA
PX1
IP.2
TCON.2
IE.7
MCS01783
Figure 9
Interrupt Request Sources
Semiconductor Group
22
1997-04-01
C501
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
0003
H
000B
H
0013
H
001B
H
0023
H
002B
H
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-
priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 9
Interrupt Priority-Within-Level
Interrupt Source
Priority
External Interrupt 0,
IE0
High
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Serial Channel,
TF0
IE1
TF1
RI + TI
TF2 + EXF2
↓
Timer 2 Interrupt,
Low
Semiconductor Group
23
1997-04-01
C501
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode,
respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down
mode takes precedence. Table 10 gives a general overview of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
– enabled interrupt
– Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power-Down
Mode
ORL PCON, #02H
Hardware Reset
Oscillator is stopped, contents
of on-chip RAM and SFR’s are
maintained (leaving Power
Down Mode means redefinition
of SFR contents).
In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC
is restored to its normal operating level, before the Power Down mode is terminated. The reset
signal that terminates the Power Down mode also restarts the oscillator. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long enough
to allow the oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
24
1997-04-01
C501
OTP Operation
TM 1)
The C501-1E is programmed by usng a modified Quick-Pulse Programming
algorithm. It differs
from older methods in the value used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and
used by a programming system to identify the device. The signature bytes identify the manufacturer
of the device.
Table 11 shows the logic levels for reading the signature byte, and for programming the program
memory, the encryption table, and the security bits. The circuit configuration and waveforms for
quick-pulse programming are shown in figures 10 to 12.
Table 11
OTP Programming Modes
Mode
RESET PSEN
ALE/
EA/VPP P2.7
P2.6
P3.7
P3.6
PROG
Read signature
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data
Verify code data
VPP
1
Progam encryption table
Program security bit 1
Program security bit 2
VPP
VPP
VPP
Notes :
1. “0” = valid low for that pin, “1” = valid high for that pin.
2. VPP = 12.75 V ± 0.25V
3. VCC = 5 V ± 10% during programming and verification.
4. ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for
100 µs (± 10 µs) and high for a minimum of 10 µs.
1)
Quick-Pulse ProgrammingTM is a trademark phrase of Intel Corporation
Semiconductor Group
25
1997-04-01
C501
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in figure 10. Note that the C501-
1E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the OTP memory location to be programmed is applied to port 1 and 2 as shown in
figure 10. The code byte to be programmed into that location is applied to port 0. RESET, PSEN
and pins of port 2 and 3 specified in table 11 are held at the “Program code data“ levels. The ALE/
PROG signal is pulsed low 25 times as shown in figure 11.
For programming of the encryption table, the 25 pulse programming sequence must be repeated for
addresses 0 through 1F , using the “Program encrytion table“ levels. After the encryption table is
H
programmed, verification cycles will produce only encrypted data.
For programming of the security bits, the 25 pulse programming sequence must be repeat using the
“Program security bit“ levels. After one security bit is programmed, further programming of the code
memory and encryption table is disabled. However, the other security bit can still be programmed.
Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level. for any
amount of time. Even a narrow glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches and overshoots.
Program Verification
If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for
program verification. The address of the OTP program memory locations to be read is applied to
ports 1 and 2 as shown in figure 12. The other pins are held at the “Verify code data“ levels
indicated in table 11. The contents of the address location will be emitted on port 0. External pullups
are required on port 0 for this operation.
If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR
of the program byte with one of the encryption bytes. The user will have to know the encryption
table contents in order to correctly decode the verification data. The encryption table itself cannot be
read out.
Reading the SIgnature Bytes
The signature bytes are read by the same procedure as a normal verification of loctions 30 and
H
31 , except that P3.6 and P3.7 need to be pulled to a logic low. The values are :
H
30 = E0 indicates manufacturer
H
H
31 = 71 indicates C501-1E
H
H
Semiconductor Group
26
1997-04-01
C501
+5 V
A0 - A7
1
Port 1
VCC
C501-1E
RESET
Programming
Data
Port 0
1
1
P3.6
P3.7
V
EA/
+12.75 V
PP
25 x 100µs
ALE/PROG
PSEN
P2.7
Low Pulses
0
XTAL2
4 - 6 MHz
1
0
P2.6
XTAL1
VSS
P2.0 - P2.4
A8 - A12
MCS03232
Figure 10
C501-1E OTP Memory Programming Configuration
25 Pulses
ALE/PROG
ALE/PROG
10
µ
s min.
µ
µ
1
0
MCT03234
Figure 11
C501-1E ALE/PROG Waveform
Semiconductor Group
27
1997-04-01
C501
+5 V
A0 - A7
1
Port 1
VCC
C501-1E
10 kΩ
RESET
1
1
P3.6
P3.7
Programming
Data
Port 0
V
EA/
1
PP
XTAL2
ALE/PROG
PSEN
P2.7
1
0
4 - 6 MHz
0 Enable
0
P2.6
XTAL1
VSS
P2.0 - P2.4
A8 - A12
MCS03235
Figure 12
C501-1E OTP Memory Verification
Semiconductor Group
28
1997-04-01
C501
Absolute Maximum Ratings
Ambient temperature under bias (TA) ......................................................... – 40 to 85 °C
Storage temperature (Tstg) .......................................................................... – 65 °C to 150 °C
Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V
Input current on any pin during overload condition..................................... – 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
29
1997-04-01
C501
DC Characteristics for C501-L / C501-1R
VCC = 5 V + 10 %, – 15 %; VSS = 0 V;
TA = 0 ˚C to 70 ˚C
for the SAB-C501
TA = – 40 ˚C to 85 ˚C for the SAF-C501
Parameter
Symbol
Limit Values
max.
Unit Test Condition
min.
Input low voltage (except EA, VIL
– 0.5
0.2 VCC – 0.1 V
–
RESET)
Input low voltage (EA)
VIL 1
– 0.5
– 0.5
0.2 VCC – 0.3 V
0.2 VCC + 0.1 V
–
–
–
Input low voltage (RESET)
VIL 2
VIH
Input high voltage (except
XTAL1, EA, RESET)
0.2 VCC + 0.9 VCC + 0.5
V
Input high voltage to XTAL1 VIH 1
0.7 VCC
0.6 VCC
VCC + 0.5
VCC + 0.5
V
V
Input high voltage to EA,
RESET
VIH 2
–
Output low voltage
(ports 1, 2, 3)
VOL
–
–
0.45
0.45
V
V
V
V
IOL = 1.6 mA1)
IOL = 3.2 mA1)
Output low voltage
(port 0, ALE, PSEN)
VOL 1
VOH
Output high voltage
(ports 1, 2, 3)
2.4
0.9 VCC
–
–
I
I
OH = – 80 µA,
OH = – 10 µA
Output high voltage
(port 0 in external bus mode,
ALE, PSEN)
VOH 1
2.4
0.9 VCC
–
–
I
I
OH = – 800 µA 2),
OH = – 80 µA2)
Logic 0 input current
(ports 1, 2, 3)
IIL
– 10
– 65
–
– 50
– 650
± 1
µA VIN = 0.45 V
µA VIN = 2 V
Logical 1-to-0 transition
current (ports 1, 2, 3)
ITL
ILI
Input leakage current
(port 0, EA)
µA 0.45 < VIN < VCC
Pin capacitance
CIO
–
10
pF
fC = 1 MHz,
TA = 25 ˚C
Power supply current:
Active mode, 12 MHz 7) ICC
–
–
–
–
–
–
–
21
4.8
mA VCC = 5 V, 4)
mA VCC = 5 V, 5)
mA VCC = 5 V, 4)
mA VCC = 5 V, 5)
mA VCC = 5 V, 4)
mA VCC = 5 V, 5)
µA VCC = 2 … 5.5 V 3)
Idle mode, 12 MHz 7)
Active mode, 24 MHz 7) ICC
Idle mode, 24 MHz 7)
ICC
36.2
8.2
56.5
12.7
50
ICC
Active mode, 40 MHz 7) ICC
Idle mode, 40 MHz 7)
Power Down Mode
ICC
IPD
Notes see page 32.
Semiconductor Group
30
1997-04-01
C501
DC Characteristics for C501-1E
VCC = 5 V + 10 %, – 15 %; VSS = 0 V;
TA = 0 ˚C to 70 ˚C
for the SAB-C501
TA = – 40 ˚C to 85 ˚C for the SAF-C501
Parameter
Symbol
Limit Values
max.
Unit Test Condition
min.
Input low voltage (except
VIL
– 0.5
0.2 VCC – 0.1 V
–
EA/V , RESET)
PP
Input low voltage (EA/V )
VIL 1
VIL 2
VIH
– 0.5
– 0.5
0.1 VCC – 0.1 V
0.2 VCC + 0.1 V
–
–
–
PP
Input low voltage (RESET)
Input high voltage (except
0.2 VCC + 0.9 VCC + 0.5
V
XTAL1, EA/V , RESET)
PP
Input high voltage to XTAL1 VIH 1
0.7 VCC
0.6 VCC
VCC + 0.5
VCC + 0.5
V
V
Input high voltage to EA/V , VIH 2
–
PP
RESET
Output low voltage
(ports 1, 2, 3)
VOL
–
–
0.45
0.45
V
V
V
V
IOL = 1.6 mA1)
IOL = 3.2 mA1)
Output low voltage
(port 0, ALE/PROG, PSEN)
VOL 1
VOH
Output high voltage
(ports 1, 2, 3)
2.4
0.9 VCC
–
–
I
I
OH = – 80 µA,
OH = – 10 µA
Output high voltage
(port 0 in external bus mode,
ALE/PROG, PSEN)
VOH 1
2.4
0.9 VCC
–
–
I
I
OH = – 800 µA 2),
OH = – 80 µA2)
Logic 0 input current
(ports 1, 2, 3)
IIL
– 10
– 65
–
– 50
– 650
± 1
µA VIN = 0.45 V
µA VIN = 2 V
Logical 1-to-0 transition
current (ports 1, 2, 3)
ITL
ILI
Input leakage current
µA 0.45 < VIN < VCC
(port 0, EA/V )
PP
Pin capacitance
CIO
–
10
pF
fC = 1 MHz,
TA = 25 ˚C
Power supply current:
Active mode, 12 MHz 7) ICC
–
–
–
–
–
21
18
36.2
20
50
mA VCC = 5 V, 4)
mA VCC = 5 V, 5)
mA VCC = 5 V, 4)
mA VCC = 5 V, 5)
µA VCC = 2 … 5.5 V 3)
Idle mode, 12 MHz 7)
ICC
Active mode, 24 MHz 7) ICC
Idle mode, 24 MHz 7)
Power Down Mode
ICC
IPD
Notes see next page.
Semiconductor Group
31
1997-04-01
C501
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
3)
4)
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the
0.9 VCC specification when the address lines are stabilizing.
I
PD (Power Down Mode) is measured under following conditions:
EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.
ICC (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET= VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is
used (appr. 1 mA).
5)
7)
I
CC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VCC; all other pins are disconnected;
ICC max at other frequencies is given by:
active mode:
idle mode:
I
CC = 1.27 x fOSC + 5.73
ICC = 0.28 x fOSC + 1.45 (C501-L and C501-1R only)
where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
Semiconductor Group
32
1997-04-01
C501
AC Characteristics for C501-L / C501-1R / C501-1E
VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C
TA = – 40 ˚C to 85 ˚C for the SAF-C501
for the SAB-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
Unit
12 MHz
Clock
min. max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
127
43
30
–
–
2tCLCL – 40
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
CLCL – 40
CLCL – 53
–
–
t
–
233
–
–
4tCLCL – 100
tLLPL
tPLPH
tPLIV
58
215
–
tCLCL – 25
–
PSEN pulse width
PSEN to valid instr in
–
3tCLCL – 35
–
150
–
–
0
–
3tCLCL – 100
Input instruction hold after PSEN tPXIX
0
–
*)
Input instruction float after PSEN tPXIZ
–
63
–
tCLCL – 20
*)
Address valid after PSEN
Address to valid instr in
Address float to PSEN
tPXAV
tAVIV
tAZPL
75
–
tCLCL – 8
–
302
–
–
0
5tCLCL – 115
0
–
*) Interfacing the C501 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group
33
1997-04-01
C501
AC Characteristics for C501-L / C501-1R / C501-1E (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
Unit
12 MHz
Clock
min. max. min.
max.
RD pulse width
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
400
400
30
–
–
6tCLCL – 100
6tCLCL – 100
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR pulse width
–
–
Address hold after ALE
RD to valid data in
–
tCLCL – 53
–
252
–
–
5tCLCL – 165
–
Data hold after RD
0
0
Data float after RD
–
97
517
585
300
–
–
2tCLCL – 70
8tCLCL – 150
9tCLCL – 165
3tCLCL + 50
–
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
–
200
203
43
33
433
33
–
3tCLCL – 50
4tCLCL – 130
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
123
–
t
CLCL – 40
CLCL – 50
tCLCL + 40
t
–
–
–
0
–
7tCLCL – 150
CLCL – 50
–
t
0
–
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Variable Clock
Unit
Freq. = 3.5 MHz to 12 MHz
min.
83.3
20
20
–
max.
Oscillator period
High time
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
285.7
ns
ns
ns
ns
ns
t
CLCL – tCLCX
CLCL – tCHCX
Low time
t
Rise time
20
20
Fall time
–
Semiconductor Group
34
1997-04-01
C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24
VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C
TA = – 40 ˚C to 85 ˚C for the SAF-C501
for the SAB-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 24 MHz
Unit
24 MHz
Clock
min. max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
43
17
17
–
–
2tCLCL – 40
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
CLCL – 25
CLCL – 25
–
–
t
–
80
–
–
4tCLCL – 87
tLLPL
tPLPH
tPLIV
22
95
–
tCLCL – 20
–
PSEN pulse width
PSEN to valid instr in
–
3tCLCL – 30
–
60
–
–
0
–
3tCLCL – 65
Input instruction hold after PSEN tPXIX
0
–
*)
Input instruction float after PSEN tPXIZ
–
32
–
tCLCL – 10
*)
Address valid after PSEN
Address to valid instr in
Address float to PSEN
tPXAV
tAVIV
tAZPL
37
–
tCLCL – 5
–
148
–
–
0
5tCLCL – 60
0
–
*) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group
35
1997-04-01
C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 24 MHz
Unit
24 MHz
Clock
min. max. min.
max.
RD pulse width
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
180
180
15
–
–
6tCLCL – 70
6tCLCL – 70
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR pulse width
–
–
Address hold after ALE
RD to valid data in
–
tCLCL – 27
–
118
–
–
5tCLCL – 90
–
Data hold after RD
0
0
Data float after RD
–
63
200
220
175
–
–
2tCLCL – 20
8tCLCL – 133
9tCLCL – 155
3tCLCL + 50
–
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
–
75
67
17
5
3tCLCL – 50
4tCLCL – 97
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
67
–
t
CLCL – 25
CLCL – 37
tCLCL + 25
t
–
–
–
0
170
15
–
–
7tCLCL – 122
CLCL – 27
–
t
0
–
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Variable Clock
Unit
Freq. = 3.5 MHz to 24 MHz
min.
41.7
12
12
–
max.
Oscillator period
High time
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
285.7
ns
ns
ns
ns
ns
t
CLCL – tCLCX
CLCL – tCHCX
Low time
t
Rise time
12
12
Fall time
–
Semiconductor Group
36
1997-04-01
C501
AC Characteristics for C501-L40 / C501-1R40
VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C
for the SAB-C501
TA = – 40 ˚C to 85 ˚C for the SAF-C501
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 40 MHz
Unit
40 MHz
Clock
min. max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
35
10
10
–
–
2 tCLCL– 15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
CLCL– 15
CLCL– 15
–
–
t
–
55
–
–
4 tCLCL– 45
tLLPL
tPLPH
tPLIV
10
60
–
tCLCL– 15
–
PSEN pulse width
PSEN to valid instr in
–
3 tCLCL– 15
–
25
–
–
0
–
3 tCLCL– 50
Input instruction hold after PSEN tPXIX
0
–
*)
Input instruction float after PSEN tPXIZ
–
20
–
tCLCL– 5
*)
Address valid after PSEN
Address to valid instr in
Address float to PSEN
tPXAV
tAVIV
tAZPL
20
–
tCLCL– 5
–
65
–
–
5 tCLCL– 60
– 5
– 5
–
*) Interfacing the C501 to devices with float times up to 25ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group
37
1997-04-01
C501
AC Characteristics for C501-L40 / C501-1R40 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
Variable Clock
1/tCLCL = 3.5 MHz to 40 MHz
Unit
40 MHz
Clock
min. max. min.
max.
RD pulse width
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
120
120
10
–
–
6 tCLCL– 30
6 tCLCL– 30
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR pulse width
–
–
Address hold after ALE
RD to valid data in
–
tCLCL– 15
–
75
–
–
5 tCLCL– 50
–
Data hold after RD
0
0
Data float after RD
–
38
150
150
90
–
–
2 tCLCL– 12
8 tCLCL– 50
9 tCLCL– 75
3 tCLCL+ 15
–
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
–
60
70
10
5
3 tCLCL– 15
4 tCLCL– 30
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
40
–
t
CLCL– 15
CLCL– 20
tCLCL+ 15
t
–
–
–
0
125
5
–
7 tCLCL– 50
CLCL– 20
–
t
–
0
–
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Variable Clock
Unit
Freq. = 3.5 MHz to 40 MHz
min.
25
10
10
–
max.
Oscillator period
High time
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
285.7
ns
ns
ns
ns
ns
t
CLCL – tCLCX
CLCL – tCHCX
Low time
t
Rise time
10
10
Fall time
–
Semiconductor Group
38
1997-04-01
C501
t LHLL
ALE
PSEN
Port 0
Port 2
t AVLL
t PLPH
t LLPL
t
LLIV
t
PLIV
t AZPL
t LLAX
t
PXAV
PXIZ
t
t PXIX
A0 - A7
Instr.IN
A0 - A7
t
AVIV
A8 - A15
A8 - A15
MCT00096
Figure 13
Program Memory Read Cycle
Semiconductor Group
39
1997-04-01
C501
tWHLH
ALE
PSEN
RD
t LLDV
t LLWL
t RLRH
t RLDV
t AVLL
tRHDZ
t LLAX2
t RLAZ
tRHDX
A0 - A7 from
Ri or DPL
A0 - A7
from PCL
Instr.
IN
Port 0
Data IN
tAVWL
t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 14
Data Memory Read Cycle
Semiconductor Group
40
1997-04-01
C501
tWHLH
ALE
PSEN
WR
t LLWL
t WLWH
tQVWX
t AVLL
tWHQX
t LLAX2
tQVWH
A0 - A7 from
Ri or DPL
A0 - A7
from PCL
Instr.IN
Port 0
Port 2
Data OUT
tAVWL
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Figure 15
Data Memory Write Cycle
tCLCL
V
CC- 0.5V
0.45V
0.7 VCC
0.2 VCC- 0.1
tCLCX
tCHCX
MCT00033
tCHCL
tCLCH
Figure 16
External Clock Drive at XTAL2
Semiconductor Group
41
1997-04-01
C501
ROM Verification Characteristics for C501-1R
ROM Verification Mode 1
Parameter
Symbol
Limit Values
max.
Unit
min.
Address to valid data
ENABLE to valid data
Data float after ENABLE
Oscillator frequency
tAVQV
tELQV
–
–
0
4
48tCLCL
48tCLCL
48tCLCL
6
ns
ns
tEHQZ
1/tCLCL
ns
MHz
P1.0 - P1.7
P2.0 - P2.4
Address
t AVQV
Port 0
Data OUT
t ELQV
tEHQZ
P2.7
ENABLE
MCT00049
V
Address: P1.0 - P1.7 = A0 - A7
P2.0 - P2.4 = A8 - A12
Inputs: P2.5 - P2.6, PSEN =
VSS
ALE, EA =
RESET =
V IH
P0.0 - P0.7 = D0 - D7
Data:
SS
Figure 17
ROM Verification Mode 1
Semiconductor Group
42
1997-04-01
C501
OTP Programming and Verification Characteristics
VCC = 5 V ± 10%, VSS = 0 V, TA = 21 ˚C to + 27 ˚C
Parameter
Symbol
Limit Values
Unit
min.
12.5
–
max.
13.0
50
Programming supply voltage
Programming supply current
Oscillator frequency
VPP
V
IPP
mA
MHz
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
µs
1 / tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHGL
4
6
Address setup to ALE/PROG low
Address hold after ALE/PROG
Data setup to ALE/PROG low
Data hold after ALE/PROG
P2.7 (ENABLE) high to VPP
48 tCLCL
48 tCLCL
48 tCLCL
48 tCLCL
48 tCLCL
10
–
–
–
–
–
VPP setup to ALE/PROG low
–
VPP hold after ALE/PROG low
ALE/PROG width
10
–
90
110
Address to data valid
–
48 tCLCL
48 tCLCL
48 tCLCL
–
ENABLE low to data valid
Data float after ENABLE
ALE/PROG high to ALE/PROG low
–
0
10
Semiconductor Group
43
1997-04-01
C501
Programming
Address
Verification
Address
P1.0 - P1.7
P2.0 - P2.4
t AVQV
Port 0
Data
Data
t DVGL
t AVGL
t GHDX
t GHAX
ALE/PROG
t GHGL
t GHSL
t GLGH
t SHGL
Logic 1
EA/VPP
Logic 0
t EHSH
t ELQV
t EHQZ
P2.7
ENABLE
MCT03237
Figure 18
C501-1E OTP Memory Program/Read Cycle
Semiconductor Group
44
1997-04-01
C501
VCC -0.5 V
0.2 VCC+0.9
0.2 VCC -0.1
Test Points
0.45 V
MCT00039
AC Inputs during testing are driven at VCC – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing
measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.
Figure 19
AC Testing: Input, Output Waveforms
-0.1 V
VOH
VLoad +0.1 V
Timing Reference
Points
VLoad
-0.1 V
VLoad
V
OL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH / VOL level occurs.
IOL / IOH ≥ ± 20 mA.
Figure 20
AC Testing: Float Waveforms
Crystal Oscillator Mode
C
Driving from External Source
N.C.
XTAL2
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
3.5 - 40 MHz
C
External Oscillator
Signal
XTAL1
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
C = 20 pF 10 pF
MCS02452
(incl. stray capacitance)
Note: During programming and verification of the C501-1E OTP memory
a clock signal of 4-6 MHz must be applied to the device.
Figure 21
Recommended Oscillator Circuits
Semiconductor Group
45
1997-04-01
C501
Package Outlines
Plastic Package, P-DIP-40 for C501G-L / C501G-1R
(Plastic Dual in-Line Package)
Figure 22
P-DIP-40 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
Semiconductor Group
46
1997-04-01
C501
Plastic Package, P-LCC-44 – SMD for C501G-L / C501G-1R / C501G-1E
(Plastic Leaded Chip-Carrier)
Figure 23
P-LCC-44 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
47
1997-04-01
C501
Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-1R
(Plastic Metric Quad Flat Package)
Figure 24
P-MQFP-44 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
48
1997-04-01
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