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SAFC504 [INFINEON]

8-Bit Single-Chip Microcontroller; 8位单芯片微控制器
SAFC504
型号： SAFC504
厂家： Infineon    Infineon
描述：

8-Bit Single-Chip Microcontroller
8位单芯片微控制器

微控制器
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中文：  中文翻译
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Data Sheet, May 2000  
C504  
8-Bit Single-Chip Microcontroller  
Microcontrollers  
N e v e r s t o p t h i n k i n g .  
Edition 2000-05  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
D-81541 München, Germany  
© Infineon Technologies AG 2000.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as warranted  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Infineon Technologies is an approved CECC manufacturer.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address  
list).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
Data Sheet, May 2000  
C504  
8-Bit Single-Chip Microcontroller  
Microcontrollers  
N e v e r s t o p t h i n k i n g .  
C504  
Revision History:  
2000-05  
Previous Version:  
1996-05  
Page  
Subjects (major changes since last revision)  
OTP Memory Operation is added.  
35 - 40  
41  
Table on Version Byte Content is added.  
AC Characteristics of Programming Mode is added.  
VCC is replaced by VDD.  
57 - 60  
several  
several  
Specification for SAH-C504 is removed  
Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation  
licensed to Infineon Technologies.  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
mcdocu.comments@infineon.com  
8-Bit Single-Chip Microcontroller  
C500 Family  
C504  
C504  
• Fully compatible to standard 8051 microcontroller  
• Up to 40 MHz external operating frequency  
• 16 Kbyte on-chip program memory  
– C504-2R: ROM version (with optional ROM protection)  
– C504-2E: programmable OTP version  
– C504-L: without on-chip program memory  
• 256 byte on-chip RAM  
• 256 byte on-chip XRAM  
• Four 8-bit ports  
– 2 ports with mixed analog/digital I/O capability  
• Three 16-bit timers/counters  
– Timer 2 with up/down counter feature  
Further features are listed next page.  
Oscillator Watchdog  
XRAM  
256 x 8  
RAM  
256 x 8  
Port 0  
Port 1  
Port 2  
Port 3  
I/O  
10-Bit ADC  
Timer 2  
8-Bit Digital I/O  
4-Bit Analog Inputs  
T0  
T1  
16-Bit  
Capture/Compare  
Unit  
8-Bit  
USART  
C500  
Core  
I/O  
10-Bit Compare Unit  
ROM/OTP  
16 k x 8  
8-Bit Digital I/O  
4-Bit Analog Inputs  
Watchdog Timer  
MCB02589  
Figure 1  
C504 Functional Units  
Data Sheet  
1
2000-05  
C504  
• Capture/compare unit for PWM signal generation and signal capturing  
– 3-channel, 16-bit capture/compare unit  
– 1-channel, 10-bit compare unit  
• Full duplex serial interface (USART)  
• 10-bit A/D Converter with 8 multiplexed inputs  
• Twelve interrupt sources with two priority levels  
• On-chip emulation support logic (Enhanced Hooks TechnologyTM)  
• Programmable 15-bit Watchdog Timer  
• Oscillator Watchdog  
• Fast Power On Reset  
• Power Saving Modes  
– Idle mode  
– Power-down mode with wake-up capability through INT0  
• M-QFP-44 package  
• Temperature ranges: SAB-C504 TA: 0 to 70 °C  
SAF-C504 TA: – 40 to 85 °C  
SAK-C504 TA: – 40 to 125 °C  
(max. operating frequency: 24 MHz)  
Ordering Information  
The ordering code for Infineon Technologies microcontrollers provides an exact  
reference to the required product. This ordering code indentifies:  
• The derivative itself, i.e. its function set  
• the specified temperature range  
• the package and the type of delivery  
For the available ordering codes for the C504, please refer to the “Product Information  
Microcontrollers” which summarizes all available microcontroller variants.  
Note: The ordering codes for the Mask-ROM versions are defined for each product after  
verification of the respective ROM code.  
Data Sheet  
2
2000-05  
C504  
VDD  
VSS  
VAREF  
VAGND  
Port 0  
8-Bit Digital I/O  
XTAL1  
XTAL2  
Port 1  
8-Bit Digital I/O/  
4-Bit Analog Inputs  
C504  
RESET  
EA  
Port 2  
8-Bit Digital I/O  
ALE  
PSEN  
Port 3  
8-Bit Digital I/O/  
4-Bit Analog Inputs  
CTRAP  
COUT3  
MCL02590  
Figure 2  
Logic Symbol  
Data Sheet  
3
2000-05  
C504  
33 32 31 30 29 28 27 26 25 24 23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
P0.3 / AD3  
P0.2 / AD2  
P0.1 / AD1  
P0.0 / AD0  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
P2.4 / A12  
P2.3 / A11  
P2.2 / A10  
P2.1 / A9  
P2.0 / A8  
C504-LM  
C504-2RM  
C504-2EM  
V
AREF  
V
V
GND  
DD  
V
P1.0 / AN0 / T2  
P1.1 / AN1 / T2EX  
P1.2 / AN2 / CC0  
P1.3 / AN3 / COUT0  
P1.4 / CC1  
SS  
XTAL1  
XTAL2  
P3.7 / RD  
P3.6 / WR / INT2  
1
2
3
4
5
6
7
8
9 10 11  
MCP02532  
Figure 3  
Pin Configuration (top view)  
Data Sheet  
4
2000-05  
C504  
Table 1  
Symbol  
Pin Definitions and Functions  
Pin Number I/O1) Function  
(P-MQFP-44)  
P1.0 - P1.7 40 - 44,  
1 - 3  
I/O Port 1  
is an 8-bit bidirectional port. Port 1 pins can be used  
for digital input/output. P1.0 - P1.3 can also be used  
as analog inputs of the A/D converter. As secondary  
digital functions, Port 1 contains the Timer 2 pins  
and the Capture/Compare inputs/outputs. Port 1  
pins are assigned to be used as analog inputs via  
the register P1ANA.  
The functions are assigned to the pins of Port 1 as  
follows:  
40  
41  
P1.0 / AN0 / T2  
Analog input channel 0 /  
input to Timer 2  
P1.1 / AN1 / T2EX Analog input channel 1 /  
capture/reloadtriggerofTimer  
2 up-down count  
42  
43  
P1.2 / AN2 / CC0  
Analog input channel 2 /  
input/output of capture/  
compare channel 0  
P1.3 / AN3 / COUT0 Analog input channel 3 /  
output of capture/compare  
channel 0  
44  
1
P1.4 / CC1  
Input/output of capture/  
compare channel 1  
Output of capture/compare  
channel 1  
Input/output of capture/  
compare channel 2  
Output of capture/compare  
channel 2  
P1.5 / COUT1  
P1.6 / CC2  
2
3
P1.7 / COUT2  
RESET  
4
I
RESET  
A high level on this pin for two machine cycles while  
the oscillator is running resets the device. An  
internal diffused resistor to VSS permits power-on  
reset using only an external capacitor to VDD.  
Data Sheet  
5
2000-05  
C504  
Table 1  
Symbol  
Pin Definitions and Functions (cont’d)  
Pin Number I/O1) Function  
(P-MQFP-44)  
P3.0 - P3.7 5, 7 - 13  
I/O Port 3  
is an 8-bit bidirectional port. P3.0 (R×D) and P3.1  
(T×D) operate as defined for the C501. P3.2 to P3.7  
contain the external interrupt inputs, timer inputs,  
and four of the analog inputs of the A/D converter.  
Port 3 pins are assigned to be used as analog inputs  
via the bits of SFR P3ANA. P3.6/WR can be  
assigned as a third interrupt input.  
The functions are assigned to the pins of port 3 as  
follows:  
5
7
8
9
P3.0 / RxD  
Receiver data input (asynch.) or  
data input/output (synch.) of  
serial interface  
Transmitter data output  
(asynch.) or clock output  
(synch.) of serial interface  
P3.1 / TxD  
P3.2 / AN4 / INT0 Analog input channel 4 /  
external interrupt 0 input /  
Timer 0 gate control input  
P3.3 / AN5 / INT1 Analog input channel 5 /  
external interrupt 1 input /  
Timer 1 gate control input  
10  
11  
12  
P3.4 / AN6 / T0  
P3.5 / AN7 / T1  
Analog input channel 6 / Timer 0  
counter input  
Analog input channel 7 / Timer 1  
counter input  
P3.6 / WR / INT2 WR control output; latches the  
data byte from port 0 into the  
external data memory /  
external interrupt 2 input  
13  
P3.7 / RD  
RD control output; enables the  
external data memory  
Data Sheet  
6
2000-05  
C504  
Table 1  
Symbol  
Pin Definitions and Functions (cont’d)  
Pin Number I/O1) Function  
(P-MQFP-44)  
CTRAP  
6
I
CCU Trap Input  
With CTRAP = low, the compare outputs of the  
CAPCOM unit are switched to the logic level as  
defined in the COINI register (if they are enabled by  
the bits in SFR TRCON). CTRAP is an input pin with  
an internal pullup resistor. For power saving  
reasons, the signal source which drives the CTRAP  
input should be at high or floating level during  
power-down mode.  
XTAL2  
14  
–
–
XTAL2  
Output of the inverting oscillator amplifier.  
XTAL1  
15  
XTAL1  
Input to the inverting oscillator amplifier and input to  
the internal clock generator circuits.  
To drive the device from an external clock source,  
XTAL1 should be driven, while XTAL2 is left  
unconnected. There are no requirements on the  
duty cycle of the external clock signal, since the  
input to the internal clocking circuitry is divided down  
by a divide-by-two flip-flop. Minimum and maximum  
high and low times as well as rise/fall times specified  
in the AC characteristics must be observed.  
P2.0 - P2.7 18-25  
I/O Port 2  
is a bidirectional I/O port with internal pullup  
resistors. Port 2 pins that have “1”s written to them  
are pulled high by the internal pullup resistors, and  
in that state can be used as inputs. As inputs, Port 2  
pins being externally pulled low will source current  
(IIL, in the DC characteristics) because of the  
internal pullup resistors. Port 2 emits the high-order  
address byte during fetches from external program  
memory and during accesses to external data  
memorythatuse16-bitaddresses(MOVX@DPTR).  
In this application it uses strong internal pullup  
resistors when issuing “1”s. During accesses to  
external data memory that use 8-bit addresses  
(MOVX @Ri), Port 2 issues the contents of the P2  
special function register.  
Data Sheet  
7
2000-05  
C504  
Table 1  
Symbol  
Pin Definitions and Functions (cont’d)  
Pin Number I/O1) Function  
(P-MQFP-44)  
PSEN  
26  
O
The Program Store Enable  
output is a control signal that enables the external  
program memory to the bus during external fetch  
operations. It is activated every six oscillator periods  
except during external data memory accesses.  
Remains high during internal program execution.  
ALE  
27  
O
The Address Latch Enable  
output is used for latching the low-byte of the  
address into external memory during normal  
operation. It is activated every six oscillator periods  
except during an external data memory access.  
When instructions are executed from internal ROM  
(EA = 1) the ALE generation can be disabled by  
clearing bit EALE in SFR SYSCON.  
COUT3  
EA  
28  
29  
O
I
10-Bit compare channel output  
This pin is used for the output signal of the 10-bit  
Compare Timer 2 unit. COUT3 can be disabled and  
set to a high or low state.  
External Access Enable  
When held at high level, instructions are fetched  
from the internal ROM (C504-2R only) when the PC  
is less than 4000H. When held at low level, the C504  
fetches all instructions from external program  
memory.  
For the C504-L, this pin must be tied low.  
P0.0 - P0.7 37 - 30  
I/O Port 0  
is an 8-bit open-drain bidirectional I/O port. Port 0  
pins that have “1”s written to them float; and in that  
state, can be used as high-impedance inputs. Port 0  
is also the multiplexed low-order address and data  
bus during accesses to external program or data  
memory. In this application, it uses strong internal  
pullup resistors when issuing “1” s.  
Port 0 also outputs the code bytes during program  
verification in the C504-2R. External pullup resistors  
are required during program (ROM) verification.  
VAREF  
38  
–
Reference voltage for the A/D converter.  
Data Sheet  
8
2000-05  
C504  
Table 1  
Symbol  
Pin Definitions and Functions (cont’d)  
Pin Number I/O1) Function  
(P-MQFP-44)  
VAGND  
VSS  
39  
16  
17  
–
–
–
Reference ground for the A/D converter.  
Ground (0 V)  
VDD  
Power Supply (+ 5 V)  
1) I = Input,  
O = Output  
Data Sheet  
9
2000-05  
C504  
VDD  
VSS  
Oscillator Watchdog  
OSC & Timing  
XRAM  
256 x 8  
RAM  
256 x 8  
ROM/OTP  
16 k x 8  
XTAL1  
XTAL2  
CPU  
Timer 0  
RESET  
ALE  
Port 0  
8-Bit Digital I/O  
Port 0  
Port 1  
Port 2  
Port 3  
PSEN  
EA  
Port 1  
8-Bit Digital I/O  
4-Bit Analog Inputs  
Timer 1  
Port 2  
8-Bit Digital I/O  
Timer 2  
Port 3  
8-Bit Digital I/O  
4-Bit Analog Inputs  
Interrupt Unit  
USART  
COUT3  
CTRAP  
Capture/Compare Unit  
A/D Converter 10-Bit  
VAREF  
VAGND  
Emulation  
Support  
Logic  
S & H  
MUX  
MCB02591  
Figure 4  
Block Diagram of the C504  
Data Sheet  
10  
2000-05  
C504  
CPU  
The C504 is efficient both as a controller and as an arithmetic processor. It has extensive  
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient  
use of program memory results from an instruction set consisting of 44% one-byte, 41%  
two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions  
are executed in 1.0 µs (24 MHz: 500 ns, 40 MHz: 300 ns).  
Special Function Register PSW (Address D0H)  
Reset Value: 00H  
Bit No. MSB  
LSB  
D7H  
CY  
D6H  
AC  
D5H  
F0  
D4H  
RS1  
D3H  
RS0  
D2H  
OV  
D1H  
F1  
D0H  
P
D0H  
PSW  
Bit  
Function  
CY  
Carry Flag  
Used by arithmetic instructions.  
AC  
Auxiliary Carry Flag  
Used by instructions which execute BCD operations.  
F0  
General Purpose Flag 0  
RS1  
RS0  
Register Bank Select Control bits  
These bits are used to select one of the four register banks.  
RS1  
RS0  
Function  
0
0
1
1
0
1
0
1
Bank 0 selected, data address 00H-07H  
Bank 1 selected, data address 08H-0FH  
Bank 2 selected, data address 10H-17H  
Bank 3 selected, data address 18H-1FH  
OV  
Overflow Flag  
Used by arithmetic instruction.  
F1  
P
General Purpose Flag 1  
Parity Flag  
Set/cleared by hardware after each instruction to indicate an odd/  
even number of “one” bits in the accumulator.  
Data Sheet  
11  
2000-05  
C504  
Memory Organization  
The C504 CPU manipulates operands in the following four address spaces:  
– up to 64 Kbyte of program memory: 16K ROM for C504-2R  
16K OTP for C504-2E  
– up to 64 Kbyte of external data memory  
– 256 bytes of internal data memory  
– 256 bytes of internal XRAM data memory  
– a 128 byte special function register area  
Figure 5 illustrates the memory address spaces of the C504.  
FFFF  
FFFF  
FF00  
H
H
H
Internal  
XRAM  
FEFF  
H
External  
Indirect  
Address  
Direct  
Address  
FF  
80  
FF  
H
H
Special  
Function  
Register  
Internal  
RAM  
External  
4000  
H
80  
H
H
3FFF  
0000  
7F  
H
H
H
Internal  
(EA = 1)  
External  
(EA = 0)  
Internal  
RAM  
0000  
00  
H
H
"Code Space"  
"Data Space"  
"Internal Data Space"  
MCD02592  
Figure 5  
C504 Memory Map  
Data Sheet  
12  
2000-05  
C504  
Reset and System Clock Operation  
The reset input is an active high input. An internal Schmitt trigger is used at the input for  
noise rejection. Since the reset is synchronized internally, the RESET pin must be held  
high for at least two machine cycles (24 oscillator periods) while the oscillator is running.  
During reset, pins ALE and PSEN are configured as inputs and should not be stimulated  
externally. (An external stimulation at these lines during reset activates several test  
modes which are reserved for test purposes. This, in turn, may cause unpredictable  
output operations at several port pins).  
At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up  
reset with an external capacitor only. An automatic reset can be obtained when VDD is  
applied by connecting the reset pin to VDD via a capacitor. After VDD has been turned on,  
the capacitor must hold the voltage level at the reset pin for a specific time to effect a  
complete reset.  
The time required for a reset operation is the oscillator start-up time and the time for  
2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This  
requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations  
apply if the reset signal is generated externally (Figure 6b). In each case, it must be  
assured that the oscillator has started up properly and that at least two machine cycles  
have passed before the reset signal goes inactive.  
Figure 6 shows the possible reset circuitries.  
a)  
b)  
&
RESET  
RESET  
+
C504  
C504  
c)  
RESET  
+
C504  
MCS03352  
Figure 6  
Reset Circuitries  
Data Sheet  
13  
2000-05  
C504  
Figure 7 shows the recommended oscillator circuit for the C504, while Figure 8 shows  
the circuit for using an external clock source.  
C
XTAL2  
3.5 - 40  
C504  
MHz  
C
XTAL1  
C = 20 pF 10 pF for crystal operation  
MCS03353  
Figure 7  
Recommended Oscillator Circuit  
C504  
V
DD  
XTAL2  
N.C.  
External  
Clock  
XTAL1  
Signal  
MCS03355  
Figure 8  
External Clock Source  
Data Sheet  
14  
2000-05  
C504  
Enhanced Hooks Emulation Concept  
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new,  
innovative way to control the execution of C500 MCUs and to gain extensive information  
on the internal operation of the controllers. Emulation of on-chip ROM based programs  
is possible, too.  
Each production chip has built-in logic for the support of the Enhanced Hooks Emulation  
Concept. Therefore, no costly bond-out chips are necessary for emulation. This also  
ensure that emulation and production chips are identical.  
The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows  
the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the  
design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a  
compatible C500 are able to emulate all operating modes of the different versions of the  
C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of  
operation. It is also able to operate in single step mode and to read the SFRs after a  
break.  
ICE-System Interface  
to Emulation Hardware  
RESET  
SYSCON  
PCON  
RSYSCON  
RPCON  
EA  
ALE  
EH-IC  
TCON  
RTCON  
PSEN  
C500  
MCU  
Enhanced Hooks  
Interface Circuit  
Port 0  
Port 2  
Optional  
I/O Ports  
Port 3 Port 1  
RPort 2 RPort 0  
TEA TALE TPSEN  
MCS02647  
Target System Interface  
Figure 9  
Basic C500 MCU Enhanced Hooks Concept Configuration  
Port 0, Port 2 and some of the control lines of the C500 based MCU are used by  
Enhanced Hooks Emulation Concept to control the operation of the device during  
emulation and to transfer informations about the program execution and data transfer  
between the external emulation hardware (ICE-system) and the C500 MCU.  
Data Sheet  
15  
2000-05  
C504  
Special Function Registers  
All registers, except the program counter and the four general purpose register banks,  
reside in the special function register area.  
The 63 special function registers (SFR) include pointers and registers that provide an  
interface between the CPU and the other on-chip peripherals. All SFRs with addresses  
where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F0H, F8H) are bit-addressable.  
The SFRs of the C504 are listed in Table 2 and Table 3. In Table 2, they are organized  
in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents  
of the SFRs in numeric order of their addresses.  
Data Sheet  
16  
2000-05  
C504  
Table 2  
Block  
Special Function Registers - Functional Blocks  
Symbol Name Addr.  
Contents  
after  
Reset  
1)  
CPU  
ACC  
B
DPH  
DPL  
PSW  
SP  
Accumulator  
B-Register  
Data Pointer, High Byte  
Data Pointer, Low Byte  
Program Status Word Register  
Stack Pointer  
E0H1)  
00H  
00H  
00H  
00H  
00H  
07H  
F0H  
83H  
82H 1)  
D0H  
81H  
3)  
SYSCON System Control Register  
B1H  
XX10XXX0B  
1)  
3)  
Interrupt  
System  
IEN0  
IEN1  
CCIE2)  
IP0  
IP1  
ITCON  
Interrupt Enable Register 0  
Interrupt Enable Register 1  
Capture/Compare Interrupt Enable Reg.  
Interrupt Priority Register 0  
Interrupt Priority Register 1  
A8H  
0X000000B3)  
XX000000B  
00H  
A9H  
D6H1)  
B8H  
B9H  
9AH  
3)  
XX000000B3)  
XX000000B  
00101010B  
Interrupt Trigger Condition Register  
1)  
Ports  
P0  
P1  
Port 0  
Port 1  
80H1)  
FFH  
FFH  
XXXX1111B  
FFH  
FFH  
XX1111XXB  
90H1) 4)  
90H 1)  
A0H1)  
B0H1) 4)  
B0H  
3)  
P1ANA2) Port 1 Analog Input Selection Register  
P2  
P3  
Port 2  
Port 3  
3)  
P3ANA2) Port 3 Analog Input Selection Register  
1)  
3)  
A/D-  
Converter  
ADCON0 A/D Converter Control Register 0  
ADCON1 A/D Converter Control Register 1  
ADDATH A/D Converter Data Register High Byte  
ADDATL A/D Converter Data Register Low Byte  
P1ANA2) Port 1 Analog Input Selection Register  
P3ANA2) Port 3 Analog Input Selection Register  
D8H  
XX000000B 3)  
01XXX000B  
00H  
DCH  
D9H  
DAH  
3)  
00XXXXXXB  
1) 4)  
3)  
90H 1) 4)  
XXXX1111B3)  
B0H  
XX1111XXB  
Serial  
Channels  
PCON2) Power Control Register  
87H  
000X0000B  
XXH  
00H  
3)  
SBUF  
SCON  
Serial Channel Buffer Register  
Serial Channel Control Register  
99H1)  
98H  
1)  
Timer 0/  
Timer 1  
TCON  
TH0  
TH1  
TL0  
TL1  
Timer 0/1 Control Register  
Timer 0, High Byte  
Timer 1, High Byte  
Timer 0, Low Byte  
Timer 1, Low Byte  
Timer Mode Register  
88H  
00H  
00H  
00H  
00H  
00H  
00H  
8CH  
8DH  
8AH  
8BH  
89H  
TMOD  
1) Bit-addressable special function registers  
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.  
3) X means that the value is undefined and the location is reserved  
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.  
Data Sheet  
17  
2000-05  
C504  
Table 2  
Block  
Special Function Registers - Functional Blocks (cont’d)  
Symbol Name  
Addr.  
Contents  
after  
Reset  
1)  
Timer 2  
T2CON Timer 2 Control Register  
T2MOD Timer 2 Mode Register  
C8H  
C9H  
00H  
XXXXXXX0B  
3)  
RC2H  
RC2L  
TH2  
Timer 2 Reload Capture Register, High Byte CBH  
Timer 2 Reload Capture Register, Low Byte CAH  
00H  
00H  
00H  
00H  
Timer 2 High Byte  
Timer 2 Low Byte  
CDH  
CCH  
TL2  
Capture /  
Compare  
Unit  
CT1CON Compare timer 1 control register  
E1H  
DEH  
DFH  
E6H  
E7H  
E3H  
E4H  
E2H  
CFH  
C2H  
C3H  
C4H  
C5H  
C6H  
C7H  
00010000B  
00H  
00H  
00H  
00H  
00H  
00H  
FFH  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
CCPL  
CCPH  
Compare timer 1 period register, low byte  
Compare timer 1 period register, high byte  
CT1OFL Compare timer 1 offset register, low byte  
CT1OFH Compare timer 1 offset register, high byte  
CMSEL0 Capture/compare mode select register 0  
CMSEL1 Capture/compare mode select register 1  
COINI  
Compare output initialization register  
TRCON Trap enable control register  
CCL0  
CCH0  
CCL1  
CCH1  
CCL2  
CCH2  
CCIR  
CCIE2)  
Capture/compare register 0, low byte  
Capture/compare register 0, high byte  
Capture/compare register 1, low byte  
Capture/compare register 1, high byte  
Capture/compare register 2, low byte  
Capture/compare register 2, high byte  
Capture/compare interrupt request flag reg. E5H  
Capture/compare interrupt enable register  
D6H  
C1H  
D2H  
D3H  
CT2CON Compare timer 2 control register  
00010000B  
00H  
XXXXXX00B  
00H  
CP2L  
CP2H  
CMP2L  
Compare timer 2 period register, low byte  
Compare timer 2 period register, high byte  
Compare timer 2 compare register, low byte D4H  
3)  
3)  
CMP2H Compare timer 2 compare register, high byte D5H  
BCON Block commutation control register D7H  
XXXXXX00B  
00H  
1)  
3)  
Watchdog  
Timer  
WDCON Watchdog Timer Control Register  
WDTREL Watchdog Timer Reload Register  
C0H  
86H  
XXXX0000B  
00H  
3)  
Power  
Saving  
Mode  
PCON2) Power Control Register  
PCON1 Power Control Register 1  
87H1) 4)  
000X0000B  
3)  
88H  
0XXXXXXXB  
1) Bit-addressable special function registers  
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.  
3) X means that the value is undefined and the location is reserved  
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.  
Data Sheet  
18  
2000-05  
C504  
Table 3  
Contents of the SFRs, SFRs in Numeric Order of their Addresses  
Addr Register Content Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
after  
Reset1)  
2)  
80H  
81H  
82H  
83H  
86H  
P0  
FFH  
07H  
00H  
00H  
.7  
.7  
.7  
.7  
.6  
.6  
.6  
.6  
.6  
.5  
.5  
.5  
.5  
.5  
.4  
.4  
.4  
.4  
.4  
.3  
.3  
.3  
.3  
.3  
.2  
.2  
.2  
.2  
.2  
.1  
.1  
.1  
.1  
.1  
.0  
.0  
.0  
.0  
.0  
SP  
DPL  
DPH  
WDTREL 00H  
WDT  
PSEL  
87H  
PCON  
000X-  
SMOD PDS  
IDLS  
–
GF1  
GF0  
PDE  
IDLE  
0000B  
2)  
88H  
88H  
TCON  
00H  
TF1 TR1  
TF0  
–
TR0  
–
IE1  
–
IT1  
–
IE0  
–
IT0  
–
1)3)  
PCON1 0XXX- EWPD –  
XXXXB  
89H  
TMOD  
TL0  
TL1  
TH0  
TH1  
P1  
00H  
00H  
00H  
00H  
00H  
FFH  
GATE C/T  
M1  
.5  
.5  
.5  
.5  
.5  
–
M0  
.4  
.4  
.4  
.4  
.4  
–
GATE C/T  
M1  
.1  
M0  
.0  
8AH  
8BH  
8CH  
8DH  
.7  
.7  
.7  
.7  
.7  
–
.6  
.6  
.6  
.6  
.6  
–
.3  
.3  
.3  
.3  
.3  
.2  
.2  
.2  
.2  
.2  
.1  
.0  
.1  
.0  
.1  
.0  
2)  
90H  
90H  
T2EX T2  
2)3)  
2)  
P1ANA XXXX-  
1111B  
EAN3 EAN2 EAN1 EAN0  
98H  
99H  
SCON  
SBUF  
ITCON  
00H  
SM0  
.7  
SM1  
.6  
SM2  
.5  
REN  
.4  
TB8  
.3  
RB8  
.2  
TI  
.1  
RI  
.0  
XXH  
9AH  
0010-  
1010B  
IT2  
IE2  
I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR  
2)  
2)  
A0H  
A8H  
P2  
FFH  
.7  
.6  
–
.5  
.4  
.3  
.2  
.1  
.0  
IEN0  
0X00-  
0000B  
EA  
ET2  
ES  
ET1  
EX1  
ET0  
EX0  
A9H  
IEN1  
XX00-  
0000B  
–
–
ECT1 ECCM ECT2 ECEM EX2  
EADC  
1) X means that the value is undefined and the location is reserved  
2) Bit-addressable special function registers  
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.  
Data Sheet  
19  
2000-05  
C504  
Table 3  
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)  
Addr Register Content Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
after  
Reset1)  
2)  
B0H  
B0H  
P3  
FFH  
RD  
WR  
T1  
T0  
INT1  
INT0  
TxD  
RxD  
2)3)  
P3ANA XX11-  
11XXB  
–
–
EAN7 EAN6 EAN5 EAN4  
–
–
B1H  
B8H  
B9H  
C0H  
C1H  
SYSCON XX10-  
XXX0B  
–
–
–
–
–
–
–
–
EALE RMAP –  
PT2 PS PT1  
–
–
XMAP  
PX0  
2)  
IP0  
XX00-  
0000B  
PX1  
PT0  
IP1  
XX00-  
0000B  
PCT1 PCCM PCT2 PCEM PX2  
OWDS WDTS WDT  
PADC  
SWDT  
2)  
WDCON XXXX-  
0000B  
–
–
CT2CON 0001-  
0000B  
CT2P ECT2O STE2 CT2  
RES  
CT2R CLK2 CLK1 CLK0  
C2H  
C3H  
C4H  
C5H  
C6H  
C7H  
C8H  
CCL0  
CCH0  
CCL1  
CCH1  
CCL2  
CCH2  
00H  
00H  
00H  
00H  
00H  
00H  
.7  
.6  
.6  
.6  
.6  
.6  
.6  
.5  
.5  
.5  
.5  
.5  
.5  
.4  
.4  
.4  
.4  
.4  
.4  
.3  
.3  
.3  
.3  
.3  
.3  
.2  
.2  
.2  
.2  
.2  
.2  
.1  
.0  
.0  
.0  
.0  
.0  
.0  
.7  
.1  
.7  
.1  
.7  
.1  
.7  
.1  
.7  
.1  
2)  
T2CON 00H  
TF2  
EXF2 RCLK TCLK EXEN2 TR2  
C/T2  
CP/  
RL2  
C9H  
T2MOD XXXX-  
XXX0B  
–
–
–
–
–
–
–
DCEN  
CAH RC2L  
CBH RC2H  
CCH TL2  
CDH TH2  
00H  
00H  
00H  
00H  
.7  
.7  
.7  
.7  
.6  
.6  
.6  
.6  
.5  
.5  
.5  
.5  
.4  
.4  
.4  
.4  
.3  
.3  
.3  
.3  
.2  
.2  
.2  
.2  
.1  
.1  
.1  
.1  
.0  
.0  
.0  
.0  
CFH  
TRCON 00H  
TRPEN TRF  
TREN5 TREN4 TREN3 TREN2 TREN1 TREN0  
1) X means that the value is undefined and the location is reserved  
2) Bit-addressable special function registers  
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.  
Data Sheet  
20  
2000-05  
C504  
Table 3  
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)  
Addr Register Content Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
after  
Reset1)  
2)  
D0H  
D2H  
D3H  
PSW  
CP2L  
CP2H  
00H  
00H  
CY  
.7  
AC  
.6  
F0  
.5  
–
RS1  
.4  
RS0  
.3  
OV  
.2  
F1  
.1  
P
.0  
.0  
XXXX.  
XX00B  
–
–
–
–
–
.1  
D4H  
D5H  
CMP2L 00H  
.7  
–
.6  
–
.5  
–
.4  
–
.3  
–
.2  
–
.1  
.1  
.0  
.0  
CMP2H XXXX.  
XX00B  
D6H  
D7H  
D8H  
D9H  
CCIE  
00H  
ECTP ECTC CC2  
FEN  
CC2  
REN  
CC1  
FEN  
CC1  
REN  
CC0  
FEN  
CC0  
REN  
BCON  
00H  
BCMP PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0  
BCEM  
2)  
ADCON0 XX00-  
0000B  
–
–
IADC  
BSY  
ADM  
MX2  
MX1  
MX0  
ADDATH 00H  
.9  
.1  
.8  
.0  
.7  
–
.6  
–
.5  
–
.4  
–
.3  
–
.2  
–
DAH ADDATL 00XX-  
XXXXB  
DCH ADCON1 01XX-  
X000B  
ADCL1 ADCL0 –  
–
–
MX2  
MX1  
MX0  
DEH CCPL  
00H  
00H  
00H  
.7  
.6  
.6  
.6  
.5  
.5  
.5  
.4  
.4  
.4  
.3  
.3  
.3  
.2  
.2  
.2  
.1  
.1  
.1  
.0  
.0  
.0  
DFH  
CCPH  
ACC  
.7  
2)  
E0H  
E1H  
.7  
CT1CON 0001-  
0000B  
CTM  
ETRP STE1 CT1  
RES  
CT1R CLK2 CLK1 CLK0  
E2H  
E3H  
E4H  
COINI  
FFH  
COUT COUTX COUT CC2I  
3I 2I  
COUT CC1I  
1I  
COUT CC0I  
0I  
I
CMSEL0 00H  
CMSEL1 00H  
CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL  
13  
12  
11  
10  
03  
CMSEL CMSEL CMSEL CMSEL  
23 22 21 20  
CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R  
02  
01  
00  
0
0
0
0
E5H  
E6H  
E7H  
CCIR  
00H  
CT1OFL 00H  
CT1OFH 00H  
.7  
.7  
.7  
.6  
.6  
.6  
.5  
.5  
.5  
.4  
.4  
.4  
.3  
.3  
.3  
.2  
.2  
.2  
.1  
.1  
.1  
.0  
.0  
.0  
2)  
F0H  
B
00H  
1) X means that the value is undefined and the location is reserved  
2) Bit-addressable special function registers  
Data Sheet  
21  
2000-05  
C504  
Timer/Counter 0 and 1  
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4.  
Table 4  
Timer/Counter 0 and 1 Operating Modes  
TMOD  
Gate C/T M1 M0 internal  
Mode Description  
Input Clock  
external  
(max.)  
OSC/12 × 32 fOSC/24 × 32  
0
8-bit timer/counter with a  
X
X
0
0
f
divide-by-32 prescaler  
1
2
16-bit timer/counter  
X
X
X
X
1
0
1
0
f
f
OSC/12  
OSC/12  
f
f
OSC/24  
OSC/24  
8-bit timer/counter with  
8-bit auto-reload  
3
Timer/counter 0 used as one X  
8-bit timer/counter and one  
8-bit timer  
X
1
1
f
OSC/12  
f
OSC/24  
Timer 1 stops  
In the “timer” function (C/T = ‘0’), the register is incremented every machine cycle.  
Therefore the count rate is fOSC/12.  
In the “counter” function the register is incremented in response to a 1-to-0 transition at  
its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine  
cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and  
INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width  
measurements. Figure 10 illustrates the input clock logic.  
f OSC  
f OSC/12  
÷
12  
C/T  
TMOD  
0
1
P3.4/T0  
P3.5/T1  
max f OSC/24  
Timer 0/1  
Input Clock  
TR 0/1  
TCON  
Control  
&
Gate  
=1  
TMOD  
_
<
1
P3.2/INT0  
P3.3/INT1  
MCS01768  
Figure 10  
Timer/Counter 0 and 1 Input Clock Logic  
Data Sheet  
22  
2000-05  
C504  
Timer/Counter 2  
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as  
a timer or as an event counter. This is selected by bit C/T2 of SFR T2CON. It has three  
operating modes as shown in Table 5.  
Table 5  
Mode  
Timer/Counter 2 Operating Modes  
T2CON  
T2MOD T2CON P1.1/ Remarks  
Input Clock  
T2EX  
R×CLK CP/ TR2  
internal external  
(P1.0/T2)  
or  
RL2  
DCEN  
EXEN  
T×CLK  
16-bit  
Auto-  
reload  
0
0
0
1
1
0
0
X
reload upon  
overflow  
reload trigger  
(falling edge)  
Down counting  
Up counting  
fOSC/12 max  
fOSC/24  
0
0
1
↓
0
0
0
0
1
1
1
1
X
X
0
1
16-bit  
Cap-  
ture  
0
1
1
X
0
X
16 bit Timer/  
Counter (only  
up-counting)  
capture TH2,  
TL2 → RC2H,  
RC2L  
fOSC/12 max  
fOSC/24  
0
1
1
X
1
↓
Baud  
Rate  
Gene-  
rator  
1
1
X
X
1
1
X
X
0
1
X
no overflow  
interrupt  
request (TF2)  
extra external  
interrupt  
fOSC/2  
max  
fOSC/24  
↓
(“Timer 2”)  
off  
X
X
0
X
X
X
Timer 2 stops  
–
–
Note: ↓ =  
falling edge  
Data Sheet  
23  
2000-05  
C504  
Capture/Compare Unit  
The Capture/Compare Unit (CCU) of the C504 consists of a 16-bit 3-channel capture/  
compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare  
mode, the CAPCOM unit provides two output signals per channel, which can have  
inverted signal polarity and non-overlapping pulse transitions. The COMP unit can  
generate a single PWM output signal and is further used to modulate the CAPCOM  
output signals. In capture mode, the value of the Compare Timer 1 is stored in the  
capture registers if a signal transition occurs at the pins CCx. Figure 11 shows the block  
diagram of the CCU.  
Figure 11  
Block Diagram of the CCU  
Data Sheet  
24  
2000-05  
C504  
The Compare Timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit  
timers; each of which has a count rate with a maximum of fOSC/2 up to fOSC/256. The  
compare timer operations with its possible compare output signal waveforms are shown  
in Figure 12.  
Compare Timer 1 in Operating Mode 0  
a) Standard PWM (Edge Aligned)  
b) Standard PWM (Single Edge Aligned)  
with programmable dead time ( t )  
OFF  
Period  
Value  
Period  
Value  
Compare  
Value  
Compare  
Value  
Offset  
0000  
H
t
OFF  
CC  
CC  
COUT  
COUT  
Compare Timer 1 in Operating Mode 1  
c) Symetrical PWM (Center Aligned)  
d) Symetrical PWM (Center Aligned)  
with programmable dead time ( t  
)
OFF  
Period  
Value  
Period  
Value  
Compare  
Value  
Compare  
Value  
Offset  
0000  
CC  
H
t
t
OFF  
OFF  
CC  
COINI=0  
COINI=0  
COUT  
COINI=1  
COUT  
COINI=1  
MCT03356  
: Interrupts can be generated  
Figure 12  
Basic Operating Modes of the CAPCOM Unit  
Compare Timer 1 can be programmed for both operating modes while Compare Timer 2  
works only in operating mode 0 with one output signal of selectable polarity at the pin  
COUT3.  
Data Sheet  
25  
2000-05  
C504  
Serial Interface (USART)  
The serial port is full duplex and can operate in four modes (one synchronous mode,  
three asynchronous modes) as illustrated in Table 6. The possible baud rates can be  
calculated using the formulas given in Table 6.  
Table 6  
Mode  
USART Operating Modes  
SCON Baud Rate  
SM0 SM1  
Description  
0
1
2
3
0
0
1
1
0
1
0
1
f
OSC/12  
Serial data enters and exits through  
R×D. T×D outputs the shift clock. 8-bit  
are transmitted/received (LSB first)  
Timer 1/2 overflow rate 8-bit UART  
10 bits are transmitted (through T×D)  
or received (R×D)  
f
OSC/32 or fOSC/64  
9-bit UART  
11 bits are transmitted (T×D) or  
received (R×D)  
Timer 1/2 overflow rate 9-bit UART  
Like mode 2 except the variable baud  
rate  
Timer 2  
Overflow  
Timer 1  
Overflow  
PCON.7  
(SMOD)  
T2CON  
SM0 / SM1  
Mode 1, 3  
(RCLK, TCLK)  
Baud  
Rate  
Clock  
Phase 2  
CLK  
0
0
1
2
(=  
/2)  
f
OSC  
Mode 2  
1
MCB02414  
Figure 13  
Baud Rate Generation for the Serial Interface  
Data Sheet  
26  
2000-05  
C504  
The possible baud rates can be calculated using the formulas given in Table 7.  
Table 7  
Formulas for Calculating Baud Rates  
Source of  
Baud Rate  
Operating Mode  
Baud Rate  
Oscillator  
0
2
fOSC/12  
(2SMOD × fOSC)/64  
Timer 1  
(16-bit timer)  
(8-bit timer with  
8-bit auto-reload)  
1, 3  
1, 3  
(2SMOD × timer 1 overflow rate)/32  
(2SMOD × fOSC)/(32 × 12 × (256-TH1))  
Timer 2  
1, 3  
fOSC/(32 × (65536-(RC2H, RC2L))  
Data Sheet  
27  
2000-05  
C504  
10-Bit A/D Converter  
The C504 has a high performance 8-channel 10-bit A/D converter using successive  
approximation technique for the conversion of analog input voltages. Figure 14 shows  
the block diagram of the A/D Converter.  
Internal  
Bus  
IEN1 (A9  
)
H
-
-
ECT1 ECCM ECT2 ECEM EX2 EADC  
P1ANA (90  
)
H
-
-
-
-
EAN3 EAN2 EAN1 EAN0  
P3ANA (B0  
)
H
-
-
EAN7 EAN6 EAN5 EAN4  
-
-
ADCON1 (DC  
)
H
ADCL1 ADCL0  
-
-
-
MX2  
MX2  
MX1  
MX0  
ADCON0 (D8  
)
H
-
-
IADC  
BSY  
ADM  
MX1  
MX0  
ADDATH ADDATL  
(D9  
)
(DA )  
H
H
Single/  
Continuous  
Mode  
.2  
-
-
-
-
-
-
.3  
.4  
.5  
.6  
.7  
.8  
Port 1/3  
f OSC /2  
MUX  
S & H  
A/D Converter  
LSB  
.1  
Clock  
Prescaler  
÷ 32, 16, 8, 4  
MSB  
Conversion Clock fADC  
Input Clock f IN  
VAREF  
VAGND  
Start of  
Conversion  
Write to  
ADDATL  
Internal  
Bus  
Shaded bit locations are not used in ADC-functions.  
MCB02616  
Figure 14  
A/D Converter Block Diagram  
Data Sheet  
28  
2000-05  
C504  
The A/D Converter uses two clock signals for operation: the conversion clock fADC (= 1/  
t
ADC) and the input clock fIN (= 1/tIN). Both clock signals are derived from the C504 system  
clock fOSC which is applied at the XTAL pins. The duration of an A/D conversion is a  
multiple of the period of the fIN clock signal. The table in Figure 15 shows the prescaler  
ratios and the resulting A/D conversion times which must be selected for typical system  
clock rates.  
MCUSystemClock  
fIN  
Prescaler  
fADC  
A/D  
Conversion  
Time [µs]  
Rate (fOSC  
)
[MHz]  
[MHz]  
Ratio  
ADCL1 ADCL0  
3.5 MHz  
12 MHz  
16 MHz  
24 MHz  
32 MHz  
40 MHz  
1.75  
6
÷ 4  
÷ 4  
÷ 4  
÷ 8  
÷ 8  
÷ 16  
0
0
0
0
0
1
0
0
0
1
1
0
.438  
1.5  
2
48 × tIN = 27.4  
48 × tIN = 8  
48 × tIN = 6  
96 × tIN = 8  
96 × tIN = 6  
192 × tIN = 9.6  
8
12  
16  
20  
1.5  
2
1.25  
Figure 15  
A/D Converter Clock Selection  
The analog inputs are located at Port 1 and Port 3 (4 lines on each port). The  
corresponding Port 1 and Port 3 pins have a port structure, which allows the pins to be  
used either as digital I/Os or analog inputs. The analog input function of these mixed  
digital/analog port lines is selected via the registers P1ANA and P3ANA.  
Data Sheet  
29  
2000-05  
C504  
Interrupt System  
The C504 provides 12 interrupt sources with two priority levels. Figures 16 and 17 give  
a general overview of the interrupt sources and illustrate the interrupt request and control  
flags.  
Figure 16  
Interrupt Request Sources (Part 1)  
Data Sheet  
30  
2000-05  
C504  
Low Priority  
High Priority  
_
<
1
P3.6/WR/INT2  
IE2  
004B  
H
IT2  
ITCON.6  
EX2  
PX2  
ITCON.4  
ITCON.5  
ITCON.7  
IEN1.1  
IP1.1  
_
<
1
CC0R  
CC0REN  
CCIE0.0  
CCIR.0  
P1.2/AN2/CC0  
CC0F  
CC0FEN  
CCIE0.1  
CCIR.1  
CC1R  
CC1REN  
CCIE0.2  
CCIR.2  
P1.4/CC1  
0063  
H
ECCM  
IEN1.4  
PCCM  
IP1.4  
CC1F  
CC1FEN  
CCIE0.3  
CCIR.3  
CC2R  
CC2REN  
CCIE0.4  
CCIR.4  
P1.6/CC2  
CC2F  
CC2FEN  
CCIE0.5  
CCIR.5  
CT1FP  
CCIR.7  
ECTP  
Compare Timer 1  
Interrupt  
_
<
1
CCIE.7  
006B  
005B  
H
ECT1  
PCT1  
IP1.5  
CT1FC  
CCIR.6  
IEN1.5  
ECTC  
CCIE.6  
Compare Timer 2  
Interrupt  
CT2P  
H
H
CT2CON.7  
ECT2  
PCT2  
IP1.3  
TRF  
IEN1.3  
TRCON.6  
ETRP  
CCU Emergency  
Interrupt  
_
<
1
CT1CON.6  
0053  
EA  
ECEM  
IEN1.2  
PCEM  
IP1.2  
BCERR  
BCON.3  
Bit addressable  
EBCE  
Request Flag is  
cleared by hardware  
BCON.4  
MCB02596  
IEN0.7  
Figure 17  
Interrupt Request Sources (Part 2)  
Data Sheet  
31  
2000-05  
C504  
Table 8  
Interrupt Vector Addresses  
Request Flags  
Interrupt Source  
Vector Address  
IE0  
TF0  
IE1  
TF1  
RI + TI  
TF2 + EXF2  
IADC  
IE2  
TRF, BCERR  
CT2P  
External interrupt 0  
Timer 0 interrupt  
External interrupt 1  
Timer 1 interrupt  
Serial port interrupt  
Timer 2 interrupt  
A/D converter interrupt  
External interrupt 2  
CAPCOM emergency interrupt  
Compare timer 2 interrupt  
0003H  
000BH  
0013H  
001BH  
0023H  
002BH  
0043H  
004BH  
0053H  
005BH  
0063H  
006BH  
007BH  
CC0F-CC2F, CC0R-CC2R Capture/compare match interrupt  
CT1FP, CT1FC  
–
Compare timer 1 interrupt  
Power-down interrupt  
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by  
another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other  
interrupt sources.  
If two requests of different priority level are received simultaneously, the request of  
higher priority is serviced. If requests of the same priority are received simultaneously,  
an internal polling sequence determines which request is serviced. Thus within each  
priority level there is a second priority structure determined by the polling sequence as  
shown in Table 9.  
Table 9  
Interrupt Source Structure  
Interrupt Source  
High Priority  
Priority  
Low Priority  
External Interrupt 0  
Timer 0 Interrupt  
External Interrupt 1  
Timer 1 Interrupt  
Serial Channel  
A/D Converter  
External Interrupt 2  
CCU Emergency Interrupt  
Compare Timer 2 Interrupt  
Capture/Compare Match Interrupt  
Compare Timer 1 Interrupt  
High  
Low  
Timer 2 Interrupt  
Data Sheet  
32  
2000-05  
C504  
Fail Save Mechanisms  
The C504 offers enhanced fail save mechanisms, which allow an automatic recovery  
from software or hardware failure.  
– a programmable 15-bit Watchdog Timer  
– Oscillator Watchdog  
Programmable Watchdog Timer  
The Watchdog Timer in the C504 is a 15-bit timer, which is incremented by a count rate  
of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). Only the upper 7 bits of the 15-bit  
watchdog timer count value can be programmed. Figure 18 shows the block diagram of  
the programmable Watchdog Timer.  
Figure 18  
Block Diagram of the Programmable Watchdog Timer  
The Watchdog Timer can be started by software (bit SWDT in SFR WDCON), but it  
cannot be stopped during active mode of the device. If the software fails to refresh the  
running Watchdog Timer, an internal reset will be initiated. The reset cause (external  
reset or reset caused by the watchdog) can be examined by software (status flag WDTS  
in SFR WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT  
and SWDT (both in SFR WDCON) consecutively.  
This double instruction sequence has been implemented to increase system security.  
It must be noted, however, that the Watchdog Timer is halted during the idle mode and  
power down mode of the processor.  
Data Sheet  
33  
2000-05  
C504  
Oscillator Watchdog  
The Oscillator Watchdog of the C504 serves for three functions:  
– Monitoring of the on-chip oscillator’s function  
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the  
frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC  
oscillator and the C504 is brought into reset. If the failure condition disappears, the  
C504 executes a final reset phase of typically 1 ms in order to allow the oscillator  
to stabilize; then, the Oscillator Watchdog reset is released and the part starts  
program execution again.  
– Fast internal reset after power-on  
The oscillator watchdog unit provides a clock supply for the reset before the on-chip  
oscillator has started. The Oscillator Watchdog unit also works identically to the  
monitoring function.  
– Control of external wake-up from software power-down mode  
When the software power-down mode is terminated by a low level at pin P3.2/INT0,  
the Oscillator Watchdog unit ensures that the microcontroller resumes operation  
(execution of the power-down wake-up interrupt) with the nominal clock rate. In the  
power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both  
oscillators are started again when power-down mode is released. When the on-chip  
oscillator has a higher frequency than the RC oscillator, the microcontroller starts  
operation after a final delay of typically 1 ms in order to allow the on-chip oscillator  
to stabilize.  
Data Sheet  
34  
2000-05  
C504  
Figure 19  
Block Diagram of the Oscillator Watchdog  
Power Saving Modes  
The C504 provides two power saving modes, the idle mode and the power down mode.  
– In the idle mode, the oscillator of the C504 continues to run, but the CPU is gated  
off from the clock signal. However, the interrupt system, the serial port, the A/D  
Converter, and all timers with the exception of the Watchdog Timer, are further  
provided with the clock. The CPU status is preserved in its entirety: the stack  
pointer, program counter, program status word, accumulator, and all other registers  
maintain their data during idle mode.  
– In the power down mode, the RC oscillator and the on-chip oscillator which  
operates with the XTAL pins are both stopped. Therefore all functions of the  
microcontroller are stopped and only the contents of the on-chip RAM, XRAM and  
the SFRs are maintained. The port pins, which are controlled by their port latches,  
output the values that are held by their SFRs.  
Table 10 gives a general overview of the entry and exit procedures of the power saving  
modes.  
Data Sheet  
35  
2000-05  
C504  
Table 10  
Mode  
Power Saving Modes Overview  
Entering  
Leaving by  
Remarks  
(2-Instruction  
Example)  
Idle mode  
ORL PCON, #01H  
ORL PCON, #20H  
Occurrence of any CPU clock is stopped;  
enabled interrupt  
CPU maintains their data;  
peripheral units are active  
(if enabled) and provided  
with clock.  
Hardware Reset  
Power  
With external wake-up Hardware Reset  
Oscillator is stopped;  
Down mode capability from power  
down enabled  
Contents of on-chip RAM  
and SFRs are maintained.  
P3.2/INT0goes low  
for at least  
10 µs.  
ORL SYSCON,#10H  
ORL PCON1,#80H  
ANL SYSCON,#0EFH  
It is desired that the  
pin be held at high  
level during the  
power down mode  
entry and up to the  
wake-up.  
ORL PCON,#02H  
ORL PCON,#40H  
With external wake-up Hardware Reset  
capability from power  
down disabled  
ORL PCON,#02H  
ORL PCON,#40H  
If a power saving mode is terminated through an interrupt, including the external wake-  
up via P3.2/INT0, the microcontroller state (CPU, ports, peripherals) remains preserved.  
If it is terminated by a hardware reset, the microcontroller is reset to its default state.  
In the power down mode of operation, VDD can be reduced to minimize power  
consumption. It must be ensured, however, that VDD is not reduced before the power  
down mode is invoked, and that VDD is restored to its normal operating level, before the  
power down mode is terminated.  
Data Sheet  
36  
2000-05  
C504  
OTP Memory Operation (C504-2E only)  
The C504-2E is the OTP version of the C504 microcontroller with a 16Kbyte one-time  
programmable (OTP) program memory. Fast programming cycles are achieved (1 byte  
in 100 µs) with the C504-2E. Several levels of OTP memory protection can be selected  
as well.  
To program the device, the C504-2E must be put into the programming mode. Typically,  
this is not done in-system, but in a special programming hardware. In the programming  
mode, the C504-2E operates as a slave device similar to an EPROM standalone  
memory device and must be controlled with address/data information, control lines, and  
an external 11.5 V programming voltage.  
Figure 20 shows the pins of the C504-2E which are required for controlling of the OTP  
programming mode.  
V
V
SS  
DD  
P2.0 - 7  
PALE  
Port 2  
Port 0  
P0.0 - 7  
EA /  
V
PMSEL0  
PMSEL1  
PP  
PROG  
PRD  
C504-2E  
RESET  
PSEN  
XTAL1  
XTAL2  
PSEL  
MCS03360  
Figure 20  
C504-2E Programming Mode Configuration  
Data Sheet  
37  
2000-05  
C504  
Pin Configuration in Programming Mode  
V
33 32 31 30 29 28 27 26 25 24 23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
D3  
D2  
D1  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
A4 / A12  
A3 / A11  
A2 / A10  
A1 / A9  
D0  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
A0 / A8  
C504-2E  
V
DD  
V
SS  
XTAL1  
XTAL2  
N.C.  
N.C.  
1
2
3
4
5
6
7
8
9 10 11  
MCP03361  
Figure 21  
Pin Configuration of the C504-2E in Programming Mode (top view)  
Data Sheet  
38  
2000-05  
C504  
Pin Definitions  
Table 11 contains the functional description of all C504-2E pins which are required for  
OTP memory programming.  
Table 11  
Pin Definitions and Functions of the C504-2E  
in Programming Mode  
Symbol Pin No.  
P-MQFP-44  
I/O Function  
RESET  
4
I
Reset  
This input must be at static “1” (active) level throughout  
the entire programming mode.  
PMSEL0 5  
PMSEL1 7  
I
I
Programming mode selection pins  
These pins are used to select the different access  
modes in programming mode. PMSEL1,0 must satisfy a  
setup time to the rising edge of PALE. When the logic  
level of PMSEL1,0 is changed, PALE must be at low  
level.  
PMSEL1 PMSEL0 Access Mode  
0
0
1
1
0
1
0
1
Reserved  
Read version bytes  
Program/read lock bits  
Program/read OTP memory  
byte  
PSEL  
PRD  
8
9
I
I
Basic programming mode select  
This input is used for the basic programming mode  
selection and must be switched according to Figure 22.  
Programming mode read strobe  
This input is used for read access control for OTP  
memory read, version byte read, and lock bit read  
operations.  
PALE  
10  
14  
I
Programming address latch enable  
PALE is used to latch the high address lines. The high  
address lines must satisfy a setup and hold time to/from  
the falling edge of PALE. PALE must be at low level  
when the logic level of PMSEL1,0 is changed.  
XTAL2  
O
XTAL2  
Output of the inverting oscillator amplifier.  
Data Sheet  
39  
2000-05  
C504  
Table 11  
Pin Definitions and Functions of the C504-2E  
in Programming Mode (cont’d)  
Symbol Pin No.  
P-MQFP-44  
15  
I/O Function  
XTAL1  
VSS  
I
XTAL1  
Input to the oscillator amplifier.  
16  
–
–
I
Ground (0 V)  
must be applied in programming mode.  
VDD  
17  
Power Supply (+ 5 V)  
must be applied in programming mode.  
P2.0 -  
P2.7  
18 - 25  
Address lines  
P2.0 - P2.7 are used as multiplexed address input lines  
A0 - A7 and A8 - A13. A8 - A13 must be latched with  
PALE.  
PSEN  
PROG  
26  
27  
I
I
Program store enable  
This input must be at static “0” level during the whole  
programming mode.  
Programming mode write strobe  
This input is used in programming mode as a write  
strobe for OTP memory program and lock bit write  
operations. During basic programming mode selection,  
a low level must be applied to PROG.  
EA/VPP  
29  
–
Programming Voltage  
This pin must be held at 11.5 V (VPP) during  
programming of an OTP memory byte or lock bit. During  
an OTP memory read operation, this pin must be at VIH.  
This pin is also used for basic programming mode  
selection. For basic programming mode selection, a low  
level must be applied.  
P0.7 -  
P0.0  
30-37  
I/O Data lines  
In programming mode, data bytes are transferred via the  
bidirectional D7 - D0 data lines which are located at  
Port 0.  
N.C.  
1-3, 6,  
–
Not Connected  
11-13, 28,  
38-44  
These pins should not be connected in programming  
mode.  
Data Sheet  
40  
2000-05  
C504  
Programming Mode Selection  
The selection for the OTP programming mode can be separated into two different parts:  
– Basic programming mode selection  
– Access mode selection  
With basic programming mode selection, the device is put into the mode in which it is  
possible to access the OTP memory through the programming interface logic. Further,  
after selection of the basic programming mode, OTP memory accesses are executed by  
using one of the access modes. These access modes are OTP memory byte program/  
read, version byte read, and program/read lock byte operations.  
The basic programming mode selection scheme is shown in Figure 22.  
5 V  
VDD  
Clock  
(XTAL1/  
XTAL2)  
Stable  
"1"  
RESET  
PSEN  
"0"  
PMSEL1,0  
PROG  
PRD  
0,1  
"0"  
"1"  
"0"  
PSEL  
PALE  
VPP  
VIH  
EA/VPP  
0 V  
Ready for access  
mode selection  
During this period signals  
are not actively driven  
MCT03362  
Figure 22  
Basic Programming Mode Selection  
Data Sheet  
41  
2000-05  
C504  
Table 12  
Access Modes Selection  
EA/ PROG PRD  
Access Mode  
PMSEL Address  
(Port 2)  
Data  
(Port 0)  
VPP  
1
0
Program OTP memory  
byte  
VPP  
H
H
H
H
A0 - A7  
A8 - A15  
D0 - D7  
Read OTP memory byte VIH  
H
Program OTP lock bits  
VPP  
VIH  
H
L
–
D1,D0  
see  
Table 13  
Read OTP lock bits  
H
H
Read OTP version byte VIH  
L
H
Byte addr.  
D0 - D7  
of version byte  
Lock Bits Programming / Read  
The C504-2E has two programmable lock bits which, when programmed according to  
Table 13, provide four levels of protection for the on-chip OTP code memory.  
Table 13  
Lock Bit Protection Types  
Lock Bits Protection Protection Type  
Level  
D1  
D0  
1
1
Level 0  
Level 1  
The OTP lock feature is disabled. During normal operation of  
the C504-2E, the state of the EA pin is not latched on reset.  
1
0
During normal operation of the C504-2E, MOVC instructions  
executed from external program memory are disabled from  
fetching code bytes from internal memory. EA is sampled  
and latched on reset. An OTP memory read operation is only  
possible according to ROM/OTP verification mode 2. Further  
programming of the OTP memory is disabled  
(reprogramming security).  
0
0
1
0
Level 2  
Level 3  
Same as level 1, but also OTP memory read operation using  
ROM verification mode 2 is disabled.  
Same as level 2; but additionally external code execution by  
setting EA = low during normal operation of the  
C504-2E is no more possible.  
External code execution, which is initiated by an internal  
program (e.g. by an internal jump instruction above the ROM  
boundary), is still possible.  
Note: A ‘1’ means that the lock bit is unprogrammed; a ‘0’ means that lock bit is  
programmed.  
Data Sheet  
42  
2000-05  
C504  
Version Bytes  
The C504-2E and C504-2R provide three version bytes at mapped address locations  
FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask  
of each microcontroller step. Therefore, the version bytes can be read but not written.  
The three version bytes hold information as manufacturer code, device type, and  
stepping code.  
The steppings of the C504 contain the following version byte information:  
Table 14  
Stepping  
Content of Version Bytes  
Version Byte 0,  
Version Byte 1,  
Version Byte 2,  
VR0 (mapped addr. VR1 (mapped addr. VR2 (mapped addr.  
FCH)  
FDH)  
FEH)  
C504-2R AC-Step C5H  
04H  
01H  
C504-2E  
ES-AA-Step  
C5H  
C5H  
84H  
01H  
C504-2E  
ES-BB-Step  
84H  
84H  
04H  
09H  
C504-2E CA-Step C5H  
Future steppings of the C504 will typically have a different value for version byte 2.  
Data Sheet  
43  
2000-05  
C504  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
max.  
Unit Notes  
min.  
– 65  
– 0.5  
Storage temperature  
TST  
150  
°C  
–
–
Voltage on VDD pins with  
respect to ground (VSS)  
VDD  
6.5  
V
Voltage on any pin with  
respect to ground (VSS)  
VIN  
–
– 0.5  
– 10  
–
V
DD + 0.5  
V
–
–
–
Input current on any pin  
during overload condition  
10  
mA  
mA  
Absolute sum of all input  
currents during overload  
condition  
–
|100 mA|  
Power dissipation  
PDISS  
–
1
W
–
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause  
permanent damage of the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in  
the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for longer periods may affect device reliability. During  
absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage  
on VDD pins with respect to ground (VSS) must not exceed the values defined by  
the absolute maximum ratings.  
Operating Conditions  
Parameter  
Symbol  
Limit Values  
Unit Notes  
min.  
max.  
5.5  
Supply voltage  
Ground voltage  
VDD  
VSS  
4.25  
V
–
–
–
0
V
Ambient temperature  
SAB-C504  
°C  
TA  
TA  
TA  
0
– 40  
– 40  
70  
85  
125  
SAF-C504  
SAK-C504  
Analog reference voltage  
Analog ground voltage  
Analog input voltage  
CPU clock  
VAREF  
VAGND  
VAIN  
4
V
DD + 0.1  
V
V
V
–
–
–
VSS – 0.1  
VAGND  
1.75  
VSS + 0.2  
VAREF  
20  
fCPU  
MHz –  
Data Sheet  
44  
2000-05  
C504  
Parameter Interpretation  
The parameters listed in the following partly represent the characteristics of the C504  
and partly its demands on the system. To aid in interpreting the parameters right, when  
evaluating them for a design, they are marked in column “Symbol”:  
CC (Controller Characteristics):  
The logic of the C504 will provide signals with the respective characteristics.  
SR (System Requirement):  
The external system must provide signals with the respective characteristics to the  
C504.  
DC Characteristics  
(Operating Conditions apply)  
Parameter  
Symbol  
Limit Values  
max.  
Unit Test Condition  
min.  
Input low voltage  
(except EA, RESET,  
CTRAP)  
VIL SR – 0.5  
VIL1 SR – 0.5  
0.2 VDD  
– 0.1  
V
V
–
–
Input low voltage (EA)  
0.2 VDD  
– 0.3  
Input low voltage  
(RESET, CTRAP)  
VIL2 SR – 0.5  
0.2 VDD + V  
–
0.1  
Input high voltage  
(except XTAL1, RESET and VIH SR 0.2 VDD + VDD + 0.5 V  
CTRAP) 0.9  
11)  
Input high voltage to XTAL1 VIH1 SR 0.7 VDD  
VDD + 0.5 V  
–
Input high voltage to  
RESET and CTRAP  
VIH2 SR 0.6 VDD  
VOL CC –  
V
DD + 0.5 V  
–
Output low voltage  
(Ports 1, 2, 3, COUT3)  
0.45  
0.45  
V
IOL = 1.6 mA1)  
IOL = 3.2 mA1)  
Output low voltage  
(Port 0, ALE, PSEN)  
VOL1 CC –  
V
V
Output high voltage  
(Ports 1, 2, 3)  
VOH CC 2.4  
0.9 VDD  
–
–
I
I
OH = – 80 µA  
OH = – 10 µA  
Output high voltage  
(Ports 1, 3 pins in push-pull VOH1 CC 0.9 VDD  
–
V
I
OH = – 800 µA  
mode and COUT3)  
Data Sheet  
45  
2000-05  
C504  
DC Characteristics (cont’d)  
(Operating Conditions apply)  
Parameter  
Symbol  
Limit Values  
max.  
Unit Test Condition  
min.  
Output high voltage  
(Port 0 in external bus  
mode, ALE, PSEN)  
VOH2 CC 2.4  
0.9 VDD  
–
–
V
I
I
OH = – 800 µA2)  
OH = – 80 µA2)  
Logic 0 input current  
(Ports 1, 2, 3)  
IIL  
ITL  
ILI  
SR – 10  
SR – 65  
CC –  
– 50  
– 650  
µA  
µA  
VIN = 0.45 V  
VIN = 2 V  
Logical 1-to-0 transition  
current (Ports 1, 2, 3)  
Input leakage current  
(Port 0, EA)  
± 1  
µA  
0.45 < VIN < VDD  
Pin capacitance  
CIO CC –  
10  
pF  
fc = 1 MHz,  
TA = 25 °C  
7) 8)  
Overload current  
IOV SR –  
± 5  
mA  
Programming voltage  
(C504-2E)  
VPP SR 10.9  
12.1  
11.5 V ± 5%10)  
V
Power Supply Current  
Parameter  
Sym-  
bol  
Limit Values Unit Test Condition  
typ.8) max.9)  
4)  
Active mode C504-2R 24 MHz IDD  
40 MHz IDD  
27.4  
43.1  
35.9  
57.2  
mA  
mA  
C504-2E 24 MHz IDD  
40 MHz IDD  
20.9  
31.0  
27.9  
41.5  
mA  
mA  
5)  
Idle mode  
C504-2R 24 MHz IDD  
40 MHz IDD  
14.6  
22.4  
19.3  
31.3  
mA  
mA  
C504-2E 24 MHz IDD  
40 MHz IDD  
12.3  
16.1  
16.1  
20.9  
mA  
mA  
Power-down C504-2R  
IPD  
1
30  
60  
30  
µA  
µA  
mA  
V
DD = 2 … 5.5 V 3)  
mode  
C504-2E  
IPD  
35  
–
At EA/VPP  
in prog. mode  
C504-2E  
IDDP  
–
Data Sheet  
46  
2000-05  
C504  
Notes:  
1) Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE  
and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these  
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise  
pulse on ALE line may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt-trigger,  
or use an address latch with a Schmitt-trigger strobe input.  
2) Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the  
0.9 VDD specification when the address lines are stabilizing.  
3) IPD (power-down mode) is measured under following conditions:  
EA = Port 0 = VDD; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS; VAGND = VSS; all other pins are disconnected.  
4) IDD (active mode) is measured with:  
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;  
EA = Port 0 = Port 1 = RESET = VDD; all other pins are disconnected. IDD would be slightly higher if a crystal  
oscillator is used (appr. 1 mA).  
5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;  
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.;  
RESET = EA = VSS; Port 0 = VDD; all other pins are disconnected;  
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin  
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VDD and VSS  
must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed  
50 mA.  
7) Not 100 % tested, guaranteed by design characterization.  
8) The typical IDD values are periodically measured at T = + 25 °C and VDD = 5 V but not 100% tested.  
A
9) The maximum IDD values are measured under worst case conditions (TA = 0 °C or – 40 °C and VDD = 5.5 V)  
10)This VPP specification is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2  
= 01H must be programmed with VPP = 12 V ± 5%.  
11)For the C504-2E ES-AA-step the VIH min. for EA is 0.8 VDD  
.
Data Sheet  
47  
2000-05  
C504  
MCD03367  
60  
mA  
50  
Active Mode  
C504-2R  
Ι
Ι
Ι
DD max  
DD typ  
DD  
Active Mode  
Idle Mode  
40  
30  
20  
10  
0
Idle Mode  
0
5
10  
15  
20  
25  
30  
35 MHz 40  
f
OSC  
MCD03368  
60  
mA  
50  
C504-2E  
Ι
Ι
Ι
DD max  
DD typ  
DD  
Active Mode  
Active Mode  
40  
30  
20  
10  
0
Idle Mode  
Idle Mode  
0
5
10  
15  
20  
25  
30  
35 MHz 40  
f
OSC  
Figure 23  
IDD Diagram  
Data Sheet  
48  
2000-05  
C504  
Power Supply Current Calculation Formulas  
Parameter  
Symbol  
Formula  
Active mode  
C504-2R  
C504-2E  
C504-2R  
C504-2E  
IDD typ  
IDD max  
0.98 × fOSC + 3.9  
1.33 × fOSC + 4.0  
IDD typ  
IDD max  
0.63 × fOSC + 5.75  
0.85 × fOSC + 7.5  
Idle mode  
IDD typ  
IDD max  
0.51 × fOSC + 2.35  
0.75 × fOSC + 1.3  
IDD typ  
IDD max  
0.24 × fOSC + 6.5  
0.30 × fOSC + 8.86  
Note: fosc is the oscillator frequency in MHz. IDD values are given in mA.  
A/D Converter Characteristics  
(Operating Conditions apply)  
Parameter  
Symbol  
Limit Values Unit Test Condition  
min. max.  
1)  
Analog input voltage  
Sample time  
VAIN SR VAGND VAREF  
V
tS  
CC  
–
64 × tIN ns  
32 × tIN  
Prescaler ÷ 32  
Prescaler ÷ 16  
Prescaler ÷ 8  
Prescaler ÷ 42)  
16 × tIN  
8 × tIN  
Conversion cycle time tADCC CC  
Total unadjusted error TUE CC  
–
384 × tIN ns  
192 × tIN  
96 × tIN  
Prescaler ÷ 32  
Prescaler ÷ 16  
Prescaler ÷ 8  
Prescaler ÷ 43)  
48 × tIN  
–
–
–
± 2  
± 4  
LSB VSS + 0.5 V ≤ VIN  
≤ VDD – 0.5 V4)  
LSB VSS < VIN < VSS + 0.5 V  
4)  
VDD – 0.5 V < VIN < VDD  
Internal resistance of  
reference voltage  
source  
R
R
AREF SR  
t
ADC/250 kΩ  
t
ADC in [ns] 5) 6)  
– 0.25  
Internal resistance of  
analog source  
ASRCSR  
–
–
tS/500  
kΩ  
tS in [ns] 2) 6)  
– 0.25  
6)  
ADC input capacitance CAIN CC  
50  
pF  
Notes see next page.  
Data Sheet  
49  
2000-05  
C504  
Clock Calculation Table  
Clock Prescaler  
Ratio  
ADCL1, 0  
tADC  
tS  
tADCC  
÷ 32  
÷ 16  
÷ 8  
1
1
0
0
1
0
1
0
32 × tIN  
16 × tIN  
8 × tIN  
64 × tIN  
32 × tIN  
16 × tIN  
8 × tIN  
384 × tIN  
192 × tIN  
96 × tIN  
48 × tIN  
÷ 4  
4 × tIN  
Further timing conditions:  
t
ADC min = 500 ns  
tIN = 2/fOSC = 2 tCLCL  
Notes:  
1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these  
cases will be X000H or X3FFH, respectively.  
2) During the sample time, the input capacitance CAIN can be charged/discharged by the external source. The  
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.  
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.  
3) This parameter includes the sample time tS, the time for determining the digital result and the time for the  
calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on  
the previous page.  
4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other  
voltages within the defined voltage range.  
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input  
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB  
is permissible.  
5) During the conversion, the ADC’s capacitance must be repeatedly charged or discharged. The internal  
resistance of the reference source must allow the capacitance to reach their final voltage level within the  
indicated time. The maximum internal resistance results from the programmed conversion timing.  
6) Not 100% tested, but guaranteed by design characterization.  
Data Sheet  
50  
2000-05  
C504  
AC Characteristics for C504-L / C504-2R / C504-2E  
(Operating Conditions apply)  
(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)  
Parameter  
Symbol  
Limit Values  
Unit  
12-MHz  
clock  
Variable Clock  
1/tCLCL = 3.5 MHz to  
12 MHz  
min. max. min.  
max.  
Program Memory Characteristics  
ALE pulse width  
tLHLL CC 127  
tAVLL CC 43  
–
2tCLCL – 40 –  
ns  
ns  
ns  
Address setup to ALE  
Address hold after ALE  
ALE low to valid instr in  
ALE to PSEN  
–
t
t
CLCL – 40  
CLCL – 23  
–
–
tLLAX CC 30  
tLLIV SR –  
tLLPL CC 58  
tPLPH CC 215  
tPLIV SR –  
–
233  
–
–
4tCLCL – 100 ns  
t
CLCL – 25  
–
ns  
ns  
PSEN pulse width  
–
3tCLCL – 35 –  
PSEN to valid instr in  
150  
–
–
0
3tCLCL – 100 ns  
Input instruction hold after tPXIX SR 0  
PSEN  
–
ns  
ns  
ns  
1)  
Input instruction float after tPXIZ SR –  
PSEN  
Address valid after PSEN tPXAV1) CC 75  
63  
–
t
CLCL – 20  
–
t
CLCL – 8  
–
Address to valid instr in  
Address float to PSEN  
tAVIV SR –  
tAZPL CC 0  
302  
–
–
0
5tCLCL – 115 ns  
ns  
–
Notes:  
1) Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not  
cause any damage to Port 0 drivers.  
Data Sheet  
51  
2000-05  
C504  
Unit  
AC Characteristics for C504-L / C504-2R / C504-2E (cont’d)  
Parameter Symbol Limit Values  
Variable Clock  
1/tCLCL = 3.5 MHz to 12 MHz  
12-MHz  
clock  
min. max. min.  
max.  
External Data Memory Characteristics  
RD pulse width  
tRLRH CC 400 –  
6tCLCL – 100  
6tCLCL – 100  
2tCLCL – 53  
–
–
–
ns  
ns  
ns  
WR pulse width  
tWLWH CC 400 –  
tLLAX2 CC 114 –  
Address hold after ALE  
RD to valid data in  
Data hold after RD  
Data float after RD  
ALE to valid data in  
Address to valid data in  
ALE to WR or RD  
tRLDV SR –  
tRHDX SR 0  
tRHDZ SR –  
tLLDV SR –  
tAVDV SR –  
252 –  
5tCLCL – 165 ns  
–
0
–
–
ns  
ns  
97  
2tCLCL – 70  
517 –  
585 –  
8tCLCL – 150 ns  
9tCLCL – 165 ns  
tLLWL CC 200 300 3tCLCL – 50  
4tCLCL – 130  
WR or RD high to ALE high tWHLH CC 43 123 tCLCL – 40  
Data valid to WR transition tQVWX CC 33 CLCL – 50  
7tCLCL – 150  
CLCL – 50  
3tCLCL + 50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address valid to WR or RD tAVWL CC 203 –  
–
t
CLCL + 40  
–
t
–
–
–
0
Data setup before WR  
Data hold after WR  
tQVWH CC 433 –  
tWHQX CC 33  
tRLAZ CC –  
–
0
t
Address float after RD  
–
External Clock Drive Characteristics  
Parameter  
Symbol  
Limit Values  
Variable Clock  
Unit  
Freq. = 3.5 MHz to 12 MHz  
min.  
max.  
Oscillator period  
High time  
tCLCL SR 83.3  
tCHCX SR 20  
tCLCX SR 20  
tCLCH SR –  
tCHCL SR –  
294  
ns  
ns  
ns  
ns  
ns  
t
t
CLCL – tCLCX  
CLCL – tCHCX  
Low time  
Rise time  
20  
20  
Fall time  
Data Sheet  
52  
2000-05  
C504  
AC Characteristics for C504-L24 / C504-2R24 / C504-2E24  
(Operating Conditions apply)  
(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)  
Parameter  
Symbol  
Limit Values  
Unit  
24-MHz  
clock  
Variable Clock  
1/tCLCL = 3.5 MHz to  
24 MHz  
min. max. min.  
max.  
Program Memory Characteristics  
ALE pulse width  
tLHLL CC 43  
tAVLL CC 17  
–
2tCLCL – 40 –  
ns  
ns  
ns  
Address setup to ALE  
Address hold after ALE  
ALE low to valid instr in  
ALE to PSEN  
–
t
t
CLCL – 25  
CLCL – 25  
–
–
tLLAX CC 17  
tLLIV SR –  
tLLPL CC 22  
tPLPH CC 95  
tPLIV SR –  
–
80  
–
–
4tCLCL – 87 ns  
t
CLCL – 20  
–
ns  
ns  
PSEN pulse width  
–
3tCLCL – 30 –  
PSEN to valid instr in  
60  
–
–
0
3tCLCL – 65 ns  
– ns  
Input instruction hold after tPXIX SR 0  
PSEN  
1)  
Input instruction float after tPXIZ SR –  
32  
–
tCLCL – 10 ns  
PSEN  
Address valid after PSEN  
Address to valid instr in  
Address float to PSEN  
tPXAV1)CC 37  
tAVIV SR –  
tAZPL CC 0  
–
t
CLCL – 5  
–
ns  
5tCLCL – 60 ns  
ns  
148  
–
–
0
–
Notes:  
1) Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not  
cause any damage to Port 0 drivers.  
Data Sheet  
53  
2000-05  
C504  
Unit  
AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (cont’d)  
Parameter Symbol Limit Values  
Variable Clock  
1/tCLCL = 3.5 MHz to 24 MHz  
24-MHz  
clock  
min. max. min.  
max.  
External Data Memory Characteristics  
RD pulse width  
tRLRH CC 180 –  
tWLWH CC 180 –  
6tCLCL – 70  
6tCLCL – 70  
2tCLCL – 27  
–
ns  
ns  
ns  
ns  
ns  
ns  
WR pulse width  
–
Address hold after ALE  
RD to valid data in  
Data hold after RD  
Data float after RD  
ALE to valid data in  
Address to valid data in  
ALE to WR or RD  
Address valid to WR  
tLLAX2 CC 56  
tRLDV SR –  
tRHDX SR 0  
tRHDZ SR –  
tLLDV SR –  
tAVDV SR –  
tLLWL CC 75  
tAVWL CC 67  
–
–
118 –  
5tCLCL – 90  
–
–
0
–
63  
2tCLCL – 20  
200 –  
8tCLCL – 133 ns  
9tCLCL – 155 ns  
220 –  
175 3tCLCL – 50  
3tCLCL + 50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
–
4tCLCL – 97  
–
WR or RD high to ALE high tWHLH CC 17  
Data valid to WR transition tQVWX CC 5  
67  
–
t
t
CLCL – 25  
CLCL – 37  
tCLCL + 25  
–
–
–
0
Data setup before WR  
Data hold after WR  
tQVWH CC 170 –  
7tCLCL – 122  
CLCL – 27  
tWHQX CC 15  
tRLAZ CC –  
–
0
t
Address float after RD  
–
External Clock Drive  
Parameter  
Symbol  
Limit Values  
Unit  
Variable Clock  
Freq. = 3.5 MHz to 24 MHz  
min.  
max.  
Oscillator period  
High time  
tCLCL SR 41.7  
tCHCX SR 12  
tCLCX SR 12  
tCLCH SR –  
tCHCL SR –  
294  
ns  
ns  
ns  
ns  
ns  
t
t
CLCL – tCLCX  
CLCL – tCHCX  
Low time  
Rise time  
12  
12  
Fall time  
Data Sheet  
54  
2000-05  
C504  
AC Characteristics for C504-L40 / C504-2R40 / C504-2E40  
(Operating Conditions apply)1)  
(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)  
Parameter  
Symbol  
Limit Values  
Unit  
40-MHz  
clock  
Variable Clock  
1/tCLCL = 3.5 MHz to  
40 MHz  
min. max. min.  
max.  
Program Memory Characteristics  
ALE pulse width  
tLHLL CC 35  
tAVLL CC 10  
–
2tCLCL – 15 –  
ns  
ns  
ns  
Address setup to ALE  
Address hold after ALE  
ALE low to valid instr in  
ALE to PSEN  
–
t
t
CLCL – 15 –  
CLCL – 15 –  
tLLAX CC 10  
tLLIV SR –  
tLLPL CC 10  
tPLPH CC 60  
tPLIV SR –  
tPXIX SR 0  
–
55  
–
–
4tCLCL – 45 ns  
t
CLCL – 15 –  
ns  
ns  
PSEN pulse width  
–
3tCLCL – 15 –  
PSEN to valid instr in  
25  
–
–
0
3tCLCL – 50 ns  
Input instruction hold after  
PSEN  
–
ns  
ns  
ns  
2)  
Input instruction float after  
PSEN  
tPXIZ SR –  
20  
–
t
CLCL – 5  
2)  
Address valid after PSEN  
Address to valid instr in  
Address float to PSEN  
tPXAV CC 20  
–
t
CLCL – 5  
–
tAVIV SR –  
65  
–
–
5tCLCL – 60 ns  
ns  
tAZPL CC – 5  
– 5  
–
Notes:  
1) SAK-C504 is not specified for 40 MHz operation.  
2) Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not  
cause any damage to Port 0 drivers.  
Data Sheet  
55  
2000-05  
C504  
Unit  
AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (cont’d)  
Parameter Symbol Limit Values  
Variable Clock  
1/tCLCL = 3.5 MHz to 40 MHz  
40-MHz  
clock  
min. max. min.  
max.  
External Data Memory Characteristics  
RD pulse width  
tRLRH CC 120 –  
tWLWH CC 120 –  
6tCLCL – 30  
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WR pulse width  
6tCLCL – 30  
–
Address hold after ALE  
RD to valid data in  
Data hold after RD  
Data float after RD  
ALE to valid data in  
Address to valid data in  
ALE to WR or RD  
Address valid to WR  
tLLAX2 CC 35  
tRLDV SR –  
tRHDX SR 0  
tRHDZ SR –  
tLLDV SR –  
tAVDV SR –  
–
2tCLCL – 15  
–
75  
–
5tCLCL – 50  
–
0
38  
–
2tCLCL – 12  
8tCLCL – 50  
9tCLCL – 75  
3tCLCL + 15  
–
150  
150  
–
–
tLLWL CC 60 90  
tAVWL CC 70  
3tCLCL – 15  
4tCLCL – 30  
–
WR or RD high to ALE high tWHLH CC 10 40  
Data valid to WR transition tQVWX CC 5  
t
t
CLCL – 15  
CLCL – 20  
tCLCL + 15  
–
–
–
–
0
Data setup before WR  
Data hold after WR  
tQVWH CC 125 –  
7tCLCL – 50  
tCLCL – 20  
tWHQX CC 5  
tRLAZ CC –  
–
0
Address float after RD  
–
External Clock Drive  
Parameter  
Symbol  
Limit Values  
Variable Clock  
Unit  
Freq. = 3.5 MHz to 40 MHz  
min.  
max.  
Oscillator period  
High time  
tCLCL SR 25  
tCHCX SR 10  
tCLCX SR 10  
tCLCH SR –  
tCHCL SR –  
294  
ns  
ns  
ns  
ns  
ns  
t
t
CLCL – tCLCX  
CLCL – tCHCX  
Low time  
Rise time  
10  
10  
Fall time  
Data Sheet  
56  
2000-05  
C504  
t LHLL  
ALE  
tAVLL  
t PLPH  
t LLPL  
t LLIV  
t PLIV  
PSEN  
t AZPL  
t LLAX  
t PXAV  
t PXIZ  
t PXIX  
Port 0  
A0 - A7  
Instr.IN  
A0 - A7  
t AVIV  
Port 2  
A8 - A15  
A8 - A15  
MCT00096  
Figure 24  
Program Memory Read Cycle  
tWHLH  
ALE  
PSEN  
RD  
t LLDV  
t LLWL  
t RLRH  
t RLDV  
t AVLL  
tRHDZ  
t LLAX2  
t RLAZ  
tRHDX  
A0 - A7 from  
Ri or DPL  
A0 - A7  
from PCL  
Instr.  
IN  
Port 0  
Data IN  
tAVWL  
t AVDV  
Port 2  
P2.0 - P2.7 or A8 - A15 from DPH  
A8 - A15 from PCH  
MCT00097  
Figure 25  
Data Memory Read Cycle  
Data Sheet  
57  
2000-05  
C504  
tWHLH  
ALE  
PSEN  
WR  
t LLWL  
t WLWH  
tQVWX  
t AVLL  
tWHQX  
t LLAX2  
tQVWH  
A0 - A7 from  
Ri or DPL  
A0 - A7  
from PCL  
Instr.IN  
Port 0  
Port 2  
Data OUT  
tAVWL  
P2.0 - P2.7 or A8 - A15 from DPH  
A8 - A15 from PCH  
MCT00098  
Figure 26  
Data Memory Write Cycle  
tCLCL  
VDD- 0.5V  
0.45V  
0.7 VDD  
0.2 VDD- 0.1  
tCLCX  
tCHCX  
MCT00033  
tCHCL  
tCLCH  
Figure 27  
External Clock Cycle  
Data Sheet  
58  
2000-05  
C504  
Unit  
AC Characteristics of Programming Mode  
(VDD = 5 V ± 10%; VPP = 11.5 V ± 5 %; TA = 25 °C ± 10 °C)  
Parameter  
Symbol Limit Values  
min.  
max.  
PALE pulse width  
tPAW  
tPMS  
35  
10  
10  
–
–
–
ns  
ns  
ns  
PMSEL setup to PALE rising edge  
Address setup to PALE, PROG, or PRD tPAS  
falling edge  
Address hold after PALE, PROG, or PRD tPAH  
10  
–
ns  
falling edge  
Address, data setup to PROG or PRD  
tPCS  
100  
0
–
ns  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
ns  
ns  
µs  
Address, data hold after PROG or PRD tPCH  
–
PMSEL setup to PROG or PRD  
PMSEL hold after PROG or PRD  
PROG pulse width  
tPMS  
tPMH  
tPWW  
tPRW  
tPAD  
tPRD  
tPDH  
tPDF  
10  
10  
100  
100  
–
–
–
–
PRD pulse width  
–
Address to valid data out  
PRD to valid data out  
Data hold after PRD  
75  
20  
–
–
0
Data float after PRD  
–
20  
–
PROG high between two consecutive  
PROG low pulses  
tPWH1  
1
PRD high between two consecutive PRD tPWH2  
low pulses  
100  
–
ns  
ns  
XTAL clock period  
tCLKP  
83.3  
285.7  
Note:  
VPP = 11.5 V ± 5% is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must  
be programmed with VPP = 12 V ± 5%.  
Data Sheet  
59  
2000-05  
C504  
t
PAW  
PMS  
PALE  
t
H, H  
PMSEL1,0  
t
t
PAH  
PAS  
A8-A13  
A0-A7  
D0-D7  
Port 2  
Port 0  
PROG  
t
PWH  
t
t
t
PCH  
PCS  
PWW  
MCT03369  
Note: PRD must be high during a programming read cycle  
Figure 28  
Programming Code Byte - Write Cycle Timing  
Data Sheet  
60  
2000-05  
C504  
t
PAW  
PMS  
PALE  
t
H, H  
PMSEL1,0  
t
t
PAH  
PAS  
A8-A13  
A0-A7  
Port 2  
Port 0  
PRD  
t
t
PDH  
PAD  
D0-D7  
t
t
t
PRD  
PDF  
PCH  
t
PWH  
t
t
PRW  
PCS  
MCT03370  
Note: PROG must be high during a programming read cycle  
Figure 29  
Verify Code Byte - Read Cycle Timing  
Data Sheet  
61  
2000-05  
C504  
H, L  
H, L  
PMSEL1,0  
Port 0  
D0, D1  
D0, D1  
t
t
PCH  
PCS  
t
t
PMS  
PMH  
PROG  
PRD  
t
PDH  
t
t
PRD  
t
t
PMS  
PWW  
PDF  
t
PMH  
t
PRW  
Note : PALE should be low during a lock bit read / write cycle  
MCT03371  
Figure 30  
Lock Bit Access Timing  
L, H  
PMSEL1,0  
Port 2  
e. g. FD  
H
t
PCH  
D0-7  
Port 0  
t
t
PCS  
PDH  
t
t
PRD  
PDF  
t
t
PMS  
PMH  
t
PRD  
PRW  
MCT03372  
Note : PROG must be high during a programming read cycle  
Figure 31  
Version Byte Read Timing  
Data Sheet  
62  
2000-05  
C504  
ROM/OTP Verification Characteristics for C504-2R / C504-2E  
ROM Verification Mode 1 (C504-2R only)  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
Address to valid data  
tAVQV  
10 tCLCL  
ns  
–
P1.0 - P1.7  
P2.0 - P2.5  
Address  
t
AVQV  
Port 0  
Data OUT  
Inputs: P2.6, P2.7, PSEN = V  
Address: P1.0 - P1.7 = A0 - A7  
P2.0 - P2.5 = A8 - A13  
SS  
ALE, EA = V  
IH  
Data:  
P0.0 - P0.7 = D0 - D7  
RESET = V  
IH2  
MCT03428  
Figure 32  
ROM Verification Mode 1  
Data Sheet  
63  
2000-05  
C504  
Unit  
ROM/OTP Verification Mode 2  
Parameter  
Symbol  
Limit Values  
min.  
typ  
max.  
ALE pulse width  
tAWD  
tACY  
tDVA  
tDSA  
tAS  
–
2 tCLCL  
–
ns  
ALE period  
–
12 tCLCL  
–
ns  
Data valid after ALE  
Data stable after ALE  
P3.5 setup to ALE low  
Oscillator frequency  
–
–
4 tCLCL  
ns  
8 tCLCL  
–
–
–
6
ns  
–
4
tCLCL  
ns  
1/tCLCL  
–
MHz  
t ACY  
t AWD  
ALE  
t DSA  
t DVA  
Port 0  
P3.5  
Data Valid  
t AS  
MCT02613  
Figure 33  
ROM Verification Mode 2  
Data Sheet  
64  
2000-05  
C504  
VDD -0.5 V  
0.2 VDD+0.9  
0.2 VDD -0.1  
Test Points  
0.45 V  
MCT00039  
AC Inputs during testing are driven at VDD – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’.  
Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.  
Figure 34  
AC Testing: Input, Output Waveforms  
-0.1 V  
VOH  
VLoad +0.1 V  
Timing Reference  
VLoad  
Points  
-0.1 V  
VLoad  
V
OL +0.1 V  
MCT00038  
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage  
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.  
IOL/IOH ≥ ± 20 mA  
Figure 35  
AC Testing: Float Waveforms  
Figure 36  
Recommended Oscillator Circuits for Crystal Oscillator  
Data Sheet  
65  
2000-05  
C504  
Package Information  
P-MQFP-44 (SMD)  
(Plastic Metric Quad Flat Package)  
Sorts of Packing  
Package outlines for tubes, trays etc. are contained in our  
Data Book “Package Information”.  
Dimensions in mm  
2000-05  
SMD = Surface Mounted Device  
Data Sheet  
66  
Infineon goes for Business Excellence  
“Business excellence means intelligent approaches and clearly  
defined processes, which are both constantly under review and  
ultimately lead to good operating results.  
Better operating results and business excellence mean less  
idleness and wastefulness for all of us, more professional  
success, more accurate information, a better overview and,  
thereby, less frustration and more satisfaction.”  
Dr. Ulrich Schumacher  
h t t p : / / w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  

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