SAK-C167CR-4R33MHA+ [INFINEON]
Microcontroller, 16-Bit, 33MHz, CMOS, PQFP144, PLASTIC, MQFP-144;
| 型号： | SAK-C167CR-4R33MHA+ |
| 厂家： | 
Infineon |
| 描述： | Microcontroller, 16-Bit, 33MHz, CMOS, PQFP144, PLASTIC, MQFP-144 微控制器 |
| 文件： | 总91页 (文件大小：1465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V3.3, Feb. 2005
C167CR
C167SR
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2005-02
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V3.3, Feb. 2005
C167CR
C167SR
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r s t o p t h i n k i n g .
C167CR, C167SR
Revision History:
2005-02
V3.3
Previous Version:
V3.2, 2001-07
V3.1, 2000-04
V3.0, 2000-02
1999-10 (Introduction of clock-related timing)
1999-06
1999-03 (Summarizes and replaces all older docs)
1998-03 (C167SR/CR, 25 MHz Addendum)
07.97 / 12.96 (C167CR-4RM)
12.96 (C167CR-16RM)
06.95 (C167CR, C167SR)
06.94 / 05.93 (C167)
Page
all
Subjects (major changes since last revision)
The layout of several graphics and text structures has been adapted to
company documentation rules, obvious typographical errors have been
corrected.
all
The contents of this document have been re-arranged into numbered
sections and a table of contents has been added.
6
8
9
BGA-type added to product list
Pin designation corrected (pin 78)
Input threshold control added to Port 6
17 … 25 Pin diagram and pin description for BGA package added
45
85
86
Port 6 added to input-threshold controlled ports
Mechanical package drawing corrected (P-MQFP-144-8)
Mechanical package drawing added (P-BGA-176-2)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
C167CR
C167SR
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration and Definition for P-MQFP-144-8 . . . . . . . . . . . . . . . . . . 8
Pin Configuration and Definition for P-BGA-176-2 . . . . . . . . . . . . . . . . . . 17
2.1
2.2
2.3
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Capture/Compare (CAPCOM) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PWM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General Purpose Timer (GPT) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CAN-Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Special Function Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Data Sheet
3
V3.3, 2005-02
16-Bit Single-Chip Microcontroller
C166 Family
C167CR/C167SR
1
Summary of Features
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
– 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 Kbytes On-Chip Internal RAM (IRAM)
– 2 Kbytes On-Chip Extension RAM (XRAM)
– 128/32 Kbytes On-Chip Mask ROM
• On-Chip Peripheral Modules
– 16-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and
High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects
(Full CAN / Basic CAN)
• Up to 16 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer and Oscillator Watchdog
Data Sheet
4
V3.3, 2005-02
C167CR
C167SR
Summary of Features
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 144-Pin MQFP Package
• 176-Pin BGA Package1)
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C167CR please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
This document describes several derivatives of the C167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term C167CR throughout this document.
1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,
although they are mechanically realized as solder balls.
Data Sheet
5
V3.3, 2005-02
C167CR
C167SR
Summary of Features
Table 1
Derivative1)
C167CR Derivative Synopsis
Program
XRAM Size Operating
Package
ROM Size
Frequency
SAK-C167SR-LM
SAB-C167SR-LM
SAK-C167SR-L33M
SAB-C167SR-L33M
SAK-C167CR-LM
SAF-C167CR-LM
SAB-C167CR-LM
–
–
–
2 Kbytes
2 Kbytes
2 Kbytes
25 MHz
P-MQFP-144-8
P-MQFP-144-8
P-MQFP-144-8
33 MHz
25 MHz
SAK-C167CR-L33M
SAB-C167CR-L33M
SAK-C167CR-4RM
SAB-C167CR-4RM
SAK-C167CR-4R33M 32 Kbytes
SAB-C167CR-4R33M
–
2 Kbytes
2 Kbytes
2 Kbytes
33 MHz
25 MHz
33 MHz
P-MQFP-144-8
P-MQFP-144-8
P-MQFP-144-8
32 Kbytes
SAK-C167CR-16RM
SAK-C167CR-16R33M 128 Kbytes 2 Kbytes
SAK-C167CR-LE 2 Kbytes
128 Kbytes 2 Kbytes
25 MHz
33 MHz
25 MHz
P-MQFP-144-8
P-MQFP-144-8
P-BGA-176-2
–
1) This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including
design step GA(-T)6.
Data Sheet
6
V3.3, 2005-02
C167CR
C167SR
General Device Information
2
General Device Information
2.1
Introduction
The C167CR derivatives are high performance derivatives of the Infineon C166 Family
of full featured single-chip CMOS microcontrollers. They combine high CPU
performance (up to 16.5 million instructions per second) with high peripheral functionality
and enhanced IO-capabilities. They also provide clock generation via PLL and various
on-chip memory modules such as program ROM, internal RAM, and extension RAM.
VAREF VAGND VDD
VSS
Port 0
16 Bit
XTAL1
XTAL2
Port 1
16 Bit
RSTIN
RSTOUT
Port 2
16 Bit
NMI
Port 3
15 Bit
EA
C167CR
Port 4
8 Bit
READY
ALE
Port 6
8 Bit
RD
WR/WRL
Port 7
8 Bit
Port 5
16 Bit
Port 8
8 Bit
MCL04411
Figure 1
Logic Symbol
Data Sheet
7
V3.3, 2005-02
C167CR
C167SR
General Device Information
2.2
Pin Configuration and Definition for P-MQFP-144-8
The pins of the C167CR are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package.
Note: The P-BGA-176-2 is described in Table 3 and Figure 3.
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO 10
P8.2/CC18IO 11
P8.3/CC19IO 12
P8.4/CC20IO 13
P8.5/CC21IO 14
P8.6/CC22IO 15
P8.7/CC23IO 16
VDD
VDD
VSS
P7.0/POUT0
17
18
19
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
P4.7/A23
P4.6/A22/CAN1_TxD
P4.5/A21/CAN1_RxD
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
OWE
C167CR
P7.1/POUT1 20
P7.2/POUT2 21
P7.3/POUT3 22
P7.4/CC28IO 23
P7.5/CC29IO 24
P7.6/CC30IO 25
P7.7/CC31IO 26
P5.0/AN0 27
P5.1/AN1 28
P5.2/AN2 29
P5.3/AN3 30
P5.4/AN4 31
P5.5/AN5 32
P5.6/AN6 33
P5.7/AN7 34
P5.8/AN8 35
P5.9/AN9 36
VSS
VDD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RxD0
P3.10/TxD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
76
75
74
73
MCP04410
Figure 2
Pin Configuration P-MQFP-144-8 (top view)
Data Sheet
8
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8
Symbol Pin
Input Function
No.
Outp.
P6
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 6
is selectable (TTL or special).
The Port 6 pins also serve for alternate functions:
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
1
2
3
4
5
6
7
O
O
O
O
O
I
CS0
Chip Select 0 Output
CS1
Chip Select 1 Output
CS2
Chip Select 2 Output
CS3
Chip Select 3 Output
CS4
Chip Select 4 Output
HOLD
HLDA
External Master Hold Request Input
Hold Acknowledge Output (master mode) or
Input (slave mode)
I/O
P6.7
8
O
BREQ
Bus Request Output
P8
IO
Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 8
is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CC16IO
CC17IO
CC18IO
CC19IO
CC20IO
CC21IO
CC22IO
CC23IO
CAPCOM2: CC16 Capture Inp./Compare Outp.
CAPCOM2: CC17 Capture Inp./Compare Outp.
CAPCOM2: CC18 Capture Inp./Compare Outp.
CAPCOM2: CC19 Capture Inp./Compare Outp.
CAPCOM2: CC20 Capture Inp./Compare Outp.
CAPCOM2: CC21 Capture Inp./Compare Outp.
CAPCOM2: CC22 Capture Inp./Compare Outp.
CAPCOM2: CC23 Capture Inp./Compare Outp.
10
11
12
13
14
15
16
Data Sheet
9
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
P7
IO
Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 7 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 7
is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
19
20
21
22
23
24
25
26
O
POUT0
POUT1
POUT2
POUT3
CC28IO
CC29IO
CC30IO
CC31IO
PWM Channel 0 Output
O
PWM Channel 1 Output
O
PWM Channel 2 Output
PWM Channel 3 Output
CAPCOM2: CC28 Capture Inp./Compare Outp.
CAPCOM2: CC29 Capture Inp./Compare Outp.
CAPCOM2: CC30 Capture Inp./Compare Outp.
CAPCOM2: CC31 Capture Inp./Compare Outp.
O
I/O
I/O
I/O
I/O
P5
I
Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristic.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
P5.0
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10,
AN11,
AN12,
AN13,
AN14,
AN15,
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
T6IN
T5IN
GPT2 Timer T6 Count Inp.
GPT2 Timer T5 Count Inp.
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.
Data Sheet
10
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
P2
IO
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 2 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 2
is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
47
48
49
50
51
52
53
54
57
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
EX0IN
CC9IO
EX1IN
CC10IO
EX2IN
CC11IO
EX3IN
CC12IO
EX4IN
CC13IO
EX5IN
CC14IO
EX6IN
CC15IO
EX7IN
T7IN
CAPCOM1: CC0 Capture Inp./Compare Output
CAPCOM1: CC1 Capture Inp./Compare Output
CAPCOM1: CC2 Capture Inp./Compare Output
CAPCOM1: CC3 Capture Inp./Compare Output
CAPCOM1: CC4 Capture Inp./Compare Output
CAPCOM1: CC5 Capture Inp./Compare Output
CAPCOM1: CC6 Capture Inp./Compare Output
CAPCOM1: CC7 Capture Inp./Compare Output
CAPCOM1: CC8 Capture Inp./Compare Output,
Fast External Interrupt 0 Input
P2.9
58
59
60
61
62
63
64
I/O
I
CAPCOM1: CC9 Capture Inp./Compare Output,
Fast External Interrupt 1 Input
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
I/O
I
CAPCOM1: CC10 Capture Inp./Compare Outp.,
Fast External Interrupt 2 Input
I/O
I
CAPCOM1: CC11 Capture Inp./Compare Outp.,
Fast External Interrupt 3 Input
I/O
I
CAPCOM1: CC12 Capture Inp./Compare Outp.,
Fast External Interrupt 4 Input
I/O
I
CAPCOM1: CC13 Capture Inp./Compare Outp.,
Fast External Interrupt 5 Input
I/O
I
CAPCOM1: CC14 Capture Inp./Compare Outp.,
Fast External Interrupt 6 Input
I/O
I
CAPCOM1: CC15 Capture Inp./Compare Outp.,
Fast External Interrupt 7 Input,
I
CAPCOM2: Timer T7 Count Input
Data Sheet
11
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
P3
IO
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 3
is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
65
66
67
68
69
70
73
74
75
76
77
78
79
I
T0IN
CAPCOM1 Timer T0 Count Input
O
I
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 External Up/Down Control Input
GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
SSC Master-Receive/Slave-Transmit Inp./Outp.
SSC Master-Transmit/Slave-Receive Outp./Inp.
ASC0 Clock/Data Output (Async./Sync.)
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
SSC Master Clock Output / Slave Clock Input.
O
I
I
I
T3IN
T2IN
I
I/O
I/O
O
I/O
O
O
I/O
O
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
P3.13
P3.15
80
81
CLKOUT System Clock Output (= CPU Clock)
OWE
(VPP)
84
I
Oscillator Watchdog Enable. This input enables the oscillator
watchdog when high or disables it when low e.g. for testing
purposes. An internal pull-up device holds this input high if
nothing is driving it.
For normal operation pin OWE should be high or not
connected.
In order to drive pin OWE low draw a current of at least
200 µA.
Data Sheet
12
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
Port 4 can be used to output the segment address lines and
for serial bus interfaces:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
85
86
87
88
89
90
O
O
O
O
O
O
I
O
O
O
A16
A17
A18
A19
A20
A21
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
P4.6
91
A22
Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
P4.7
RD
92
95
A23
Most Significant Segment Address Line
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
96
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
READY 97
I
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pull-up device will hold this pin high when nothing
is driving it.
ALE
EA
98
99
O
I
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin. A low level at this pin during and
after Reset forces the C167CR to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
Data Sheet
13
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
PORT0
P0L.0-7 100-
107
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
P0H.0-7 108,
111-
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
117
Demultiplexed bus modes:
8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0
Multiplexed bus modes:
8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0
PORT1
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
P1L.0-7 118-
125
P1H.0-7 128-
135
The following PORT1 pins also serve for alternate functions:
P1H.4
P1H.5
P1H.6
P1H.7
132
133
134
135
I
I
I
I
CC24IO
CC25IO
CC26IO
CC27IO
CAPCOM2: CC24 Capture Input
CAPCOM2: CC25 Capture Input
CAPCOM2: CC26 Capture Input
CAPCOM2: CC27 Capture Input
XTAL2 137
XTAL1 138
O
I
XTAL2:
XTAL1:
Output of the oscillator amplifier circuit.
Input to the oscillator amplifier and input to the
internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
Data Sheet
14
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
RSTIN 140
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C167CR.
An internal pull-up resistor permits power-on reset using only
a capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle and to let
the PLL lock a reset duration of ca. 1 ms is
recommended.
RST
OUT
141
142
O
I
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
VAGND
37
38
–
–
Reference voltage for the A/D converter.
Reference ground for the A/D converter.
Data Sheet
15
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 2
Pin Definitions and Functions P-MQFP-144-8 (cont’d)
Symbol Pin
Input Function
No.
Outp.
VDD
17, 46, –
Digital Supply Voltage:
56, 72,
82, 93,
109,
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.
126,
136,
144
VSS
18, 45, –
55, 71,
83, 94,
110,
Digital Ground.
127,
139,
143
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
16
V3.3, 2005-02
C167CR
C167SR
General Device Information
2.3
Pin Configuration and Definition for P-BGA-176-2
The pins1) of the C167CR are described in detail in Table 3, including all their alternate
functions. Figure 3 summarizes all pins in a condensed way, showing their location on
the bottom of the package.
Note: The P-MQFP-144-8 is described in Table 2 and Figure 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
A
B
C
D
E
F
V SS
P5.5
P5.2
P5.0
P7.7
P7.3
P8.5
P8.1
P6.7
P6.4
P6.0
V AREF
V DD
P5.8
P5.9
P5.4
P5.6
P7.6
P7.5
P7.4
P7.2
P7.1
P7.0
P8.4
P8.3
P8.2
P8.0
P6.6
P6.2
P6.5
P6.1
P5.11
V AGND
V DD
P5.3
P5.1
P8.7
P8.6
P6.3
XTAL1 NM I
R ST
OU T
P5.12 P5.13
V SS
V DD
P5.10 P5.7
XTAL2
R ST
IN
V SS
V SS
P5.15 P5.14
P1.15 P1.14
P2.1
P2.5
V SS
P2.0
P2.4
V DD
P2.2
P2.3
P2.8
V DD
P1.9 P1.10 P1.12 P1.13
G
H
J
G
H
J
P2.6
P2.7
V SS
P1.7
P1.4
P1.8 P1.11
V DD
P1.5
P1.6
P2.9 P2.10 P2.12 P2.11
P0.14 P0.15 P1.2
P0.9 P0.13 P1.0
P1.3
K
L
K
L
P2.13 P2.14 P3.1
V DD
P1.1
P0.10 P0.12 P0.11
V DD
P2.15 P3.2
P3.12
P4.2
P4.1
P4.6
P4.5
P4.3
P0.1
EA
V SS
V SS
P0.8
P0.3
P0.0
V SS
P0.5
P0.4
R D
V SS
P4.7
M
N
P
M
N
P
P3.0
P3.4
P3.3
P3.7
P3.6 P3.11
V DD
P3.8 P3.10 P3.15 OW E
W R
P0.7
P0.6
R EA
D Y
P3.5
2
P3.9 P3.13
P4.0
6
P4.4
7
ALE
10
P0.2
11
V DD
1
3
4
5
8
9
12
13
14
Not connected or therm al ground
m c_c167crle_pindiagram .vsd
Figure 3
Pin Configuration P-BGA-176-2 (top view)
1) The external connections of the C167CR in P-BGA-176-2 are referred to as pins throughout this document,
although they are mechanically realized as solder balls.
Data Sheet
17
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2
Input Function
Num. Outp.
P5
I
Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristic.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
P5.0
A5
D5
A4
C5
B4
A3
C4
D4
B3
C3
D3
C1
D1
D2
E3
E2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10,
AN11,
AN12,
AN13,
AN14,
AN15,
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
T6IN
T5IN
GPT2 Timer T6 Count Inp.
GPT2 Timer T5 Count Inp.
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.
P7
IO
Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 7 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 7
is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
D7
C7
B7
A7
D6
C6
B6
A6
O
POUT0
POUT1
POUT2
POUT3
CC28IO
CC29IO
CC30IO
CC31IO
PWM Channel 0 Output
O
PWM Channel 1 Output
O
PWM Channel 2 Output
PWM Channel 3 Output
CAPCOM2: CC28 Capture Inp./Compare Outp.
CAPCOM2: CC29 Capture Inp./Compare Outp.
CAPCOM2: CC30 Capture Inp./Compare Outp.
CAPCOM2: CC31 Capture Inp./Compare Outp.
O
I/O
I/O
I/O
I/O
Data Sheet
18
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
P8
IO
Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 8
is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
B10
A10
D9
C9
B9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CC16IO
CC17IO
CC18IO
CC19IO
CC20IO
CC21IO
CC22IO
CC23IO
CAPCOM2: CC16 Capture Inp./Compare Outp.
CAPCOM2: CC17 Capture Inp./Compare Outp.
CAPCOM2: CC18 Capture Inp./Compare Outp.
CAPCOM2: CC19 Capture Inp./Compare Outp.
CAPCOM2: CC20 Capture Inp./Compare Outp.
CAPCOM2: CC21 Capture Inp./Compare Outp.
CAPCOM2: CC22 Capture Inp./Compare Outp.
CAPCOM2: CC23 Capture Inp./Compare Outp.
A9
D8
C8
P6
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 6
is selectable (TTL or special).
The Port 6 pins also serve for alternate functions:
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
A13
B12
D10
C11
A12
B11
C10
O
O
O
O
O
I
CS0
Chip Select 0 Output
CS1
Chip Select 1 Output
CS2
Chip Select 2 Output
CS3
Chip Select 3 Output
CS4
Chip Select 4 Output
HOLD
HLDA
External Master Hold Request Input
Hold Acknowledge Output (master mode) or
Input (slave mode)
I/O
P6.7
NMI
A11
C14
O
I
BREQ
Bus Request Output
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Data Sheet
19
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
XTAL2 D13
XTAL1 C13
O
I
XTAL2:
XTAL1:
Output of the oscillator amplifier circuit.
Input to the oscillator amplifier and input to the
internal clock generator.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
RST
OUT
D12
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
RSTIN E11
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C167CR.
An internal pull-up resistor permits power-on reset using only
a capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle and to let
the PLL lock a reset duration of ca. 1 ms is
recommended.
Data Sheet
20
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
PORT1
P1L.0-7 K13,
K14,
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
J13,
J14,
H11,
H12,
H13,
G11
P1H.0-3 G13,
F11,
F12,
G14
The following PORT1 pins also serve for alternate functions:
P1H.4
P1H.5
P1H.6
P1H.7
F13
F14
E14
E13
I
I
I
I
CC24IO
CC25IO
CC26IO
CC27IO
CAPCOM2: CC24 Capture Input
CAPCOM2: CC25 Capture Input
CAPCOM2: CC26 Capture Input
CAPCOM2: CC27 Capture Input
PORT0
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
P0L.0-7 N10,
L9,
P11,
M10,
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
N11,
M11,
P12,
N12
Demultiplexed bus modes:
P0H.0-7 L10,
K11,
8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0
Multiplexed bus modes:
L12,
L14,
8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0
L13,
K12,
J11,
J12
RD
L8
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
Data Sheet
21
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
EA
M9
I
External Access Enable pin. A low level at this pin during and
after Reset forces the C167CR to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
WR/
N9
O
I
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pull-up device will hold this pin high when nothing
is driving it.
WRL
READY P9
ALE
P10
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
Port 4 can be used to output the segment address lines and
for serial bus interfaces:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P6
M6
L6
O
O
O
O
O
O
I
O
O
O
A16
A17
A18
A19
A20
A21
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
N7
P7
M7
Segment Address Line
Segment Address Line
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
P4.6
P4.7
L7
A22
CAN1_TxD CAN 1 Transmit Data Output
A23 Most Significant Segment Address Line
Segment Address Line,
N8
Data Sheet
22
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
OWE
(VPP)
N6
I
Oscillator Watchdog Enable. This input enables the oscillator
watchdog when high or disables it when low e.g. for testing
purposes. An internal pull-up device holds this input high if
nothing is driving it.
For normal operation pin OWE should be high or not
connected.
In order to drive pin OWE low draw a current of at least
200 µA.
P3
IO
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 3
is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
M1
K3
L2
I
T0IN
CAPCOM1 Timer T0 Count Input
O
I
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 External Up/Down Control Input
GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
SSC Master-Receive/Slave-Transmit Inp./Outp.
SSC Master-Transmit/Slave-Receive Outp./Inp.
ASC0 Clock/Data Output (Async./Sync.)
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
SSC Master Clock Output / Slave Clock Input.
M2
N1
P2
M3
N2
N3
P3
N4
M4
L4
O
I
I
I
T3IN
T2IN
I
I/O
I/O
O
I/O
O
O
I/O
O
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
P3.13
P3.15
P4
N5
CLKOUT System Clock Output (= CPU Clock)
Data Sheet
23
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
P2
IO
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 2 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 2
is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
F3
F2
F4
G4
G3
G2
G1
H1
H4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
EX0IN
CC9IO
EX1IN
CC10IO
EX2IN
CC11IO
EX3IN
CC12IO
EX4IN
CC13IO
EX5IN
CC14IO
EX6IN
CC15IO
EX7IN
T7IN
CAPCOM1: CC0 Capture Inp./Compare Output
CAPCOM1: CC1 Capture Inp./Compare Output
CAPCOM1: CC2 Capture Inp./Compare Output
CAPCOM1: CC3 Capture Inp./Compare Output
CAPCOM1: CC4 Capture Inp./Compare Output
CAPCOM1: CC5 Capture Inp./Compare Output
CAPCOM1: CC6 Capture Inp./Compare Output
CAPCOM1: CC7 Capture Inp./Compare Output
CAPCOM1: CC8 Capture Inp./Compare Output,
Fast External Interrupt 0 Input
P2.9
J1
J2
J4
J3
K1
K2
L1
I/O
I
CAPCOM1: CC9 Capture Inp./Compare Output,
Fast External Interrupt 1 Input
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
I/O
I
CAPCOM1: CC10 Capture Inp./Compare Outp.,
Fast External Interrupt 2 Input
I/O
I
CAPCOM1: CC11 Capture Inp./Compare Outp.,
Fast External Interrupt 3 Input
I/O
I
CAPCOM1: CC12 Capture Inp./Compare Outp.,
Fast External Interrupt 4 Input
I/O
I
CAPCOM1: CC13 Capture Inp./Compare Outp.,
Fast External Interrupt 5 Input
I/O
I
CAPCOM1: CC14 Capture Inp./Compare Outp.,
Fast External Interrupt 6 Input
I/O
I
CAPCOM1: CC15 Capture Inp./Compare Outp.,
Fast External Interrupt 7 Input,
I
CAPCOM2: Timer T7 Count Input
VAREF
VAGND
B2
C2
–
–
Reference voltage for the A/D converter.
Reference ground for the A/D converter.
Data Sheet
24
V3.3, 2005-02
C167CR
C167SR
General Device Information
Table 3
Symbol Pin
Pin Definitions and Functions P-BGA-176-2 (cont’d)
Input Function
Num. Outp.
VDD
B8,
–
Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.
C12,
D14,
F1,
H3,
H14,
K4,
M5,
M12,
P8
VSS
A8,
D11,
E1,
–
Digital Ground.
E12,
G12,
H2,
L3,
L5,
L11,
M8
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
25
V3.3, 2005-02
C167CR
C167SR
Functional Description
3
Functional Description
The architecture of the C167CR combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CR.
Note: All time specifications refer to a CPU clock of 33 MHz
(see definition in the AC Characteristics section).
C166-Core
ProgMem
IRAM
Internal
RAM
16
16
Data
Data
32
16
ROM
128/32
KByte
Instr. / Data
CPU
2 KByte
XTAL
Osc / PLL
WDT
XRAM
2 KByte
PEC
External Instr. / Data
16-Level
Priority
Interrupt Controller
16
Interrupt Bus
Peripheral Data Bus
16
CAN
Rev 2.0B active
ADC ASC0 SSC
GPT PWM CCOM2CCOM1
10-Bit
(USART)
(SPI)
T2
T3
T4
T7
T8
T0
T1
16
Channels
EBC
8
8
XBUS Control
External Bus
Control
16
T5
T6
BRGen
BRGen
Port 0
Port 1
Port 5
Port 3
Port 7
8
Port 8
8
16
16
16
15
Figure 4
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 4).
Data Sheet
26
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.1
Memory Organization
The memory space of the C167CR is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 Mbytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C167CR incorporates 128/32 Kbytes (depending on the derivative) of on-chip mask-
programmable ROM for code or constant data. The lower 32 Kbytes of the on-chip ROM
can be mapped either to segment 0 or segment 1.
2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
2 Kbytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks,
or code. The XRAM is accessed like external memory and therefore cannot be used for
the system stack or for register banks and is not bitaddressable. The XRAM permits
16-bit accesses with maximum speed.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
27
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
• 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
• 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
• 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
• 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. The C167CR offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
Access to very slow memories or memories with varying access times is supported via
a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external
resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)
are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA
pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA
is switched to input. This allows to directly connect the slave controller to another master
controller without glue logic.
For applications which require less than 16 Mbytes of external memory space, this
address space can be restricted to 1 Mbyte, 256 Kbyte, or to 64 Kbyte. In this case Port 4
outputs four, two, or no address lines at all. It outputs all 8 address lines, if an address
space of 16 Mbytes is used.
Data Sheet
28
V3.3, 2005-02
C167CR
C167SR
Functional Description
Note: When the on-chip CAN Module is to be used the segment address output on
Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate
function of the CAN interface pins. CS lines can be used to increase the total
amount of addressable external memory.
Data Sheet
29
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CR’s instructions can be
executed in just one machine cycle which requires 60 ns at 33 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a
16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another
pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5
CPU Block Diagram
Data Sheet
30
V3.3, 2005-02
C167CR
C167SR
Functional Description
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C167CR instruction set which
includes the following instruction classes:
• Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
31
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.4
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C167CR is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C167CR supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C167CR has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible C167CR interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
32
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 4
C167CR Interrupt Nodes
Source of Interrupt or Request
Enable
Interrupt Vector
Trap
PEC Service Request Flag
Flag
Vector
Location Number
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CC0IR
CC1IR
CC2IR
CC3IR
CC4IR
CC5IR
CC6IR
CC7IR
CC8IR
CC9IR
CC0IE
CC1IE
CC2IE
CC3IE
CC4IE
CC5IE
CC6IE
CC7IE
CC0INT
CC1INT
CC2INT
CC3INT
CC4INT
CC5INT
CC6INT
CC7INT
CC8INT
CC9INT
00’0040H 10H
00’0044H 11H
00’0048H 12H
00’004CH 13H
00’0050H 14H
00’0054H 15H
00’0058H 16H
00’005CH 17H
00’0060H 18H
00’0064H 19H
CC8IE
CC9IE
CAPCOM Register 10 CC10IR
CAPCOM Register 11 CC11IR
CAPCOM Register 12 CC12IR
CAPCOM Register 13 CC13IR
CAPCOM Register 14 CC14IR
CAPCOM Register 15 CC15IR
CAPCOM Register 16 CC16IR
CAPCOM Register 17 CC17IR
CAPCOM Register 18 CC18IR
CAPCOM Register 19 CC19IR
CAPCOM Register 20 CC20IR
CAPCOM Register 21 CC21IR
CAPCOM Register 22 CC22IR
CAPCOM Register 23 CC23IR
CAPCOM Register 24 CC24IR
CAPCOM Register 25 CC25IR
CAPCOM Register 26 CC26IR
CAPCOM Register 27 CC27IR
CAPCOM Register 28 CC28IR
CAPCOM Register 29 CC29IR
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
CC18IE
CC19IE
CC20IE
CC21IE
CC22IE
CC23IE
CC24IE
CC25IE
CC26IE
CC27IE
CC28IE
CC29IE
CC10INT 00’0068H 1AH
CC11INT 00’006CH 1BH
CC12INT 00’0070H 1CH
CC13INT 00’0074H 1DH
CC14INT 00’0078H 1EH
CC15INT 00’007CH 1FH
CC16INT 00’00C0H 30H
CC17INT 00’00C4H 31H
CC18INT 00’00C8H 32H
CC19INT 00’00CCH 33H
CC20INT 00’00D0H 34H
CC21INT 00’00D4H 35H
CC22INT 00’00D8H 36H
CC23INT 00’00DCH 37H
CC24INT 00’00E0H 38H
CC25INT 00’00E4H 39H
CC26INT 00’00E8H 3AH
CC27INT 00’00ECH 3BH
CC28INT 00’00E0H 3CH
CC29INT 00’0110H 44H
Data Sheet
33
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 4
C167CR Interrupt Nodes (cont’d)
Source of Interrupt or Request
Enable
Interrupt Vector
Trap
PEC Service Request Flag
Flag
Vector
Location Number
CAPCOM Register 30 CC30IR
CAPCOM Register 31 CC31IR
CC30IE
CC31IE
T0IE
T1IE
T7IE
T8IE
T2IE
T3IE
T4IE
T5IE
T6IE
CRIE
ADCIE
CC30INT 00’0114H 45H
CC31INT 00’0118H 46H
CAPCOM Timer 0
CAPCOM Timer 1
CAPCOM Timer 7
CAPCOM Timer 8
GPT1 Timer 2
T0IR
T1IR
T7IR
T8IR
T2IR
T3IR
T4IR
T5IR
T6IR
CRIR
ADCIR
T0INT
T1INT
T7INT
T8INT
T2INT
T3INT
T4INT
T5INT
T6INT
CRINT
ADCINT
00’0080H 20H
00’0084H 21H
00’00F4H 3DH
00’00F8H 3EH
00’0088H 22H
00’008CH 23H
00’0090H 24H
00’0094H 25H
00’0098H 26H
00’009CH 27H
00’00A0H 28H
GPT1 Timer 3
GPT1 Timer 4
GPT2 Timer 5
GPT2 Timer 6
GPT2 CAPREL Reg.
A/D Conversion
Complete
A/D Overrun Error
ASC0 Transmit
ASC0 Transmit Buffer S0TBIR
ASC0 Receive
ASC0 Error
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0 … 3
CAN Interface 1
Unassigned node
Unassigned node
PLL/OWD
ADEIR
S0TIR
ADEIE
S0TIE
S0TBIE
S0RIE
S0EIE
SCTIE
SCRIE
SCEIE
PWMIE
XP0IE
XP1IE
XP2IE
XP3IE
ADEINT
S0TINT
S0TBINT 00’011CH 47H
S0RINT
S0EINT
SCTINT
SCRINT
SCEINT
00’00A4H 29H
00’00A8H 2AH
S0RIR
S0EIR
SCTIR
SCRIR
SCEIR
PWMIR
XP0IR
XP1IR
XP2IR
XP3IR
00’00ACH 2BH
00’00B0H 2CH
00’00B4H 2DH
00’00B8H 2EH
00’00BCH 2FH
PWMINT 00’00FCH 3FH
XP0INT
XP1INT
XP2INT
XP3INT
00’0100H 40H
00’0104H 41H
00’0108H 42H
00’010CH 43H
Data Sheet
34
V3.3, 2005-02
C167CR
C167SR
Functional Description
The C167CR also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Trap
Vector
Trap
Trap
Flag
Vector
Location
Number
Priority
Reset Functions:
–
• Hardware Reset
• Software Reset
• W-dog Timer Overflow
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
• Non-Maskable Interrupt NMI
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
• Stack Overflow
• Stack Underflow
STKOF
STKUF
Class B Hardware Traps:
• Undefined Opcode
• Protected Instruction
Fault
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
• Illegal Word Operand
Access
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
00’0028H
00’0028H
00’0028H
0AH
0AH
0AH
I
I
I
• Illegal Instruction
Access
• Illegal External Bus
Access
Reserved
Software Traps
• TRAP Instruction
–
–
–
–
[2CH - 3CH] [0BH - 0FH] –
Any Any Current
[00’0000H - [00H - 7FH] CPU
00’01FCH]
in steps of
4H
Priority
Data Sheet
35
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.5
Capture/Compare (CAPCOM) Units
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically
used to handle high speed I/O tasks such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time
recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function. Each register has one port pin associated with it which serves as an
input pin for triggering the capture function, or as an output pin (except for
CC24 … CC27) to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
Data Sheet
36
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 6
Compare Modes (CAPCOM)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Mode 2
Mode 3
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Double
Register Mode
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible.
Data Sheet
37
V3.3, 2005-02
C167CR
C167SR
Functional Description
Reload Reg. TxREL
CAPCOM Timer Tx
fCPU
TxIN
2n : 1
Tx
Input
Control
Interrupt
Request
(TxIR)
GPT2 Timer T6
Over/Underflow
CCxIO
Mode
Control
(Capture
or
16-Bit
16 Capture Inputs
16 Compare Outputs
Capture/
Compare
Registers
16 Capture/Compare
Interrupt Request
Compare)
CCxIO
fCPU
2n : 1
Ty
Input
Control
Interrupt
Request
(TyIR)
CAPCOM Timer Ty
Reload Reg. TyREL
GPT2 Timer T6
Over/Underflow
MCB02143B
x = 0, 7
y = 1, 8
n = 3 … 10
Figure 6
CAPCOM Unit Block Diagram
3.6
PWM Module
The Pulse Width Modulation Module can generate up to four PWM output signals using
edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM
burst signals and single shot outputs. The frequency range of the PWM signals covers
4 Hz to 16.5 MHz (referred to a CPU clock of 33 MHz), depending on the resolution of
the PWM output signal. The level of the output signals is selectable and the PWM
module can generate interrupt requests.
Data Sheet
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V3.3, 2005-02
C167CR
C167SR
Functional Description
3.7
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
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V3.3, 2005-02
C167CR
C167SR
Functional Description
T2EUD
fCPU
T2IN
U/D
Interrupt
Request
2n : 1
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
Interrupt
Request
fCPU
2n : 1
Toggle FF
T3OTL
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OUT
U/D
T3EUD
Other
Timers
Capture
Reload
T4IN
T4
Mode
Control
Interrupt
Request
2n : 1
GPT1 Timer T4
U/D
fCPU
T4EUD
MCT02141
n = 3 … 10
Figure 7
Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock via a programmable prescaler or with external signals. The count direction
(up/down) for each timer is programmable by software or may additionally be altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The
CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the C167CR to measure absolute time
differences or to perform pulse multiplication without software overhead.
Data Sheet
40
V3.3, 2005-02
C167CR
C167SR
Functional Description
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
T5EUD
fCPU
T5IN
2n : 1
T5
Mode
Control
U/D
Interrupt
Request
GPT2 Timer T5
Clear
Capture
Interrupt
Request
T3
MUX
CT3
CAPIN
GPT2 CAPREL
Interrupt
Request
GPT2 Timer T6
U/D
T6OTL
T6OUT
T6IN
T6
Mode
Control
Other
Timers
fCPU
2n : 1
T6EUD
MCB03999
n = 2 … 9
Figure 8
Block Diagram of GPT2
Data Sheet
41
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.8
A/D Converter
For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less than 16 analog input channels, the remaining
channel inputs can be used as digital input port pins.
The A/D converter of the C167CR supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into
a running sequence without disturbing this sequence. This is called Channel Injection
Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
Data Sheet
42
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.9
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to
781 kbit/s/1.03 Mbit/s and half-duplex synchronous communication at up to
3.1/4.1 Mbit/s (@ 25/33 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25/8.25 Mbit/s
(@ 25/33 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
43
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.10
CAN-Module
The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.
The bit timing is derived from the XCLK and is programmable up to a data rate of
1 Mbit/s. The CAN-Module uses two pins of Port 4 to interface to an external bus
transceiver.
Note: When the CAN interface is to be used the segment address output on Port 4 must
be limited to 4 bits, i.e. A19 … A16. This is necessary to enable the alternate
function of the CAN interface pins.
3.11
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2
or by 128. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 15.5 µs and 254 ms can be
monitored (@ 33 MHz).
The default Watchdog Timer interval after reset is 3.97 ms (@ 33 MHz).
Data Sheet
44
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.12
Parallel Ports
The C167CR provides up to 111 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 6, Port 7, and Port 8 is selectable (TTL or
CMOS like), where the special CMOS like input threshold reduces noise sensitivity due
to the input hysteresis. The input threshold may be selected individually for each byte of
the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 Kbytes of memory.
Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or
compare outputs of the CAPCOM units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
The edge characteristics (transition time) of the C167CR’s port drivers can be selected
via the Port Driver Control Register (PDCR). Two bits select fast edges (‘0’) or reduced
edges (‘1’) for bus interface pins and non-bus pins separately.
PDCR.0 = BIPEC controls PORT0, PORT1, Port 4, RD, WR, ALE, CLKOUT, BHE/WRH.
PDCR.4 = NBPEC controls Port 3, Port 8, RSTOUT, RSTIN (bidir. reset mode).
Data Sheet
45
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.13
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (fCPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled via hardware by (externally) pulling low pin
OWE (internal pull-up provides high level if not connected). In this case (OWE = ‘0’) the
PLL remains idle and provides no clock signal, while the CPU clock signal is derived
directly from the oscillator clock or via prescaler. Also no interrupt request will be
generated in case of a missing oscillator clock.
Data Sheet
46
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.14
Instruction Set Summary
Table 7 lists the instructions of the C167CR in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 7
Mnemonic
ADD(B)
Instruction Set Summary
Description
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
2
Add word (byte) operands
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR
(16 × 16 bits)
DIV(U)
(Un)Signed divide register MDL by direct GPR
(16 / 16 bits)
(Un)Signed long divide reg. MD by direct GPR
(32 / 16 bits)
2
2
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
2
2
2 / 4
2 / 4
2 / 4
2
BSET
Set direct bit
2
BMOV(N)
BAND, BOR,
BXOR
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
4
4
BCMP
BFLDH/L
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
4
CMP(B)
Compare word (byte) operands
2 / 4
CMPD1/2
CMPI1/2
Compare word data to GPR and decrement GPR by 1/2 2 / 4
Compare word data to GPR and increment GPR by 1/2 2 / 4
Data Sheet
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V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 7
Instruction Set Summary (cont’d)
Mnemonic
PRIOR
Description
Bytes
2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
SHL / SHR
ROL / ROR
ASHR
MOV(B)
MOVBS
MOVBZ
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
Move byte operand to word operand with sign extension 2 / 4
Move byte operand to word operand. with zero extension 2 / 4
2
2
2
2 / 4
JMPA, JMPI,
JMPR
Jump absolute/indirect/relative if condition is met
4
JMPS
J(N)B
JBC
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
4
4
4
4
JNBS
CALLA, CALLI,
CALLR
Call absolute/indirect/relative subroutine if condition is met 4
CALLS
PCALL
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
4
4
TRAP
PUSH, POP
SCXT
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
2
2
4
RET
RETS
RETP
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
2
2
2
RETI
SRST
IDLE
PWRDN
SRVWDT
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
2
4
4
4
4
Data Sheet
48
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 7
Mnemonic
DISWDT
EINIT
ATOMIC
EXTR
Instruction Set Summary (cont’d)
Description
Bytes
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
4
4
2
2
Begin EXTended Register sequence
EXTP(R)
EXTS(R)
NOP
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
2 / 4
2 / 4
2
Data Sheet
49
V3.3, 2005-02
C167CR
C167SR
Functional Description
3.15
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C167CR in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Note: Registers within device specific interface modules (CAN) are only present in the
corresponding device, of course.
Table 8
Name
C167CR Registers, Ordered by Name
Physical 8-Bit Description
Reset
Value
Address Addr.
ADCIC
b FF98H
CCH A/D Converter End of Conversion
0000H
Interrupt Control Register
ADCON
ADDAT
ADDAT2
ADDRSEL1
ADDRSEL2
ADDRSEL3
ADDRSEL4
ADEIC
b FFA0H
D0H
50H
A/D Converter Control Register
A/D Converter Result Register
A/D Converter 2 Result Register
Address Select Register 1
Address Select Register 2
Address Select Register 3
Address Select Register 4
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
FEA0H
F0A0H E 50H
FE18H
FE1AH
FE1CH
0CH
0DH
0EH
0FH
FE1EH
b FF9AH
CDH A/D Converter Overrun Error Interrupt
Control Register
BUSCON0 b FF0CH
BUSCON1 b FF14H
BUSCON2 b FF16H
BUSCON3 b FF18H
BUSCON4 b FF1AH
86H
8AH
8BH
8CH
8DH
Bus Configuration Register 0
Bus Configuration Register 1
Bus Configuration Register 2
Bus Configuration Register 3
Bus Configuration Register 4
CAN1 Bit Timing Register
0XX0H
0000H
0000H
0000H
0000H
UUUUH
XX01H
UFUUH
C1BTR
C1CSR
C1GMS
EF04H X –
EF00H X –
EF06H X –
CAN1 Control / Status Register
CAN1 Global Mask Short
Data Sheet
50
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
C1IR
EF02H X –
EF0AH X –
EF0EH X –
EFn2H X –
CAN1 Interrupt Register
CAN1 Lower Global Mask Long
CAN1 Lower Mask of Last Message
CAN1 Upper Arbitration Register
(message n)
XXH
C1LGML
C1LMLM
C1UAR
UUUUH
UUUUH
UUUUH
C1UGML
C1UMLM
CAPREL
CC0
CC0IC
CC1
CC10
CC10IC
CC11
CC11IC
CC12
CC12IC
CC13
CC13IC
CC14
CC14IC
CC15
CC15IC
CC16
CC16IC
CC17
CC17IC
CC18
CC18IC
CC19
EF08H X –
EF0CH X –
CAN1 Upper Global Mask Long
CAN1 Upper Mask of Last Message
GPT2 Capture/Reload Register
CAPCOM Register 0
UUUUH
UUUUH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
FE4AH
FE80H
25H
40H
b FF78H
FE82H
FE94H
b FF8CH
FE96H
b FF8EH
FE98H
b FF90H
FE9AH
b FF92H
FE9CH
BCH CAPCOM Register 0 Interrupt Ctrl. Reg.
41H
4AH
C6H
4BH
C7H
4CH
C8H
4DH
C9H
4EH
CAPCOM Register 1
CAPCOM Register 10
CAPCOM Reg. 10 Interrupt Ctrl. Reg.
CAPCOM Register 11
CAPCOM Reg. 11 Interrupt Ctrl. Reg.
CAPCOM Register 12
CAPCOM Reg. 12 Interrupt Ctrl. Reg.
CAPCOM Register 13
CAPCOM Reg. 13 Interrupt Ctrl. Reg.
CAPCOM Register 14
b FF94H
FE9EH
b FF96H
FE60H
CAH CAPCOM Reg. 14 Interrupt Ctrl. Reg.
4FH CAPCOM Register 15
CBH CAPCOM Reg. 15 Interrupt Ctrl. Reg.
30H
CAPCOM Register 16
CAPCOM Reg. 16 Interrupt Ctrl. Reg.
CAPCOM Register 17
CAPCOM Reg. 17 Interrupt Ctrl. Reg.
CAPCOM Register 18
CAPCOM Reg. 18 Interrupt Ctrl. Reg.
CAPCOM Register 19
b F160H E B0H
FE62H 31H
b F162H E B1H
FE64H 32H
b F164H E B2H
FE66H 33H
Data Sheet
51
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
CC19IC
CC1IC
CC2
CC20
CC20IC
CC21
CC21IC
CC22
CC22IC
CC23
CC23IC
CC24
CC24IC
CC25
CC25IC
CC26
CC26IC
CC27
CC27IC
CC28
CC28IC
CC29
CC29IC
CC2IC
CC3
CC30
CC30IC
CC31
b F166H E B3H
CAPCOM Reg. 19 Interrupt Ctrl. Reg.
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
b FF7AH
FE84H
BDH CAPCOM Reg. 1 Interrupt Ctrl. Reg.
42H
34H
CAPCOM Register 2
CAPCOM Register 20
CAPCOM Reg. 20 Interrupt Ctrl. Reg.
CAPCOM Register 21
CAPCOM Reg. 21 Interrupt Ctrl. Reg.
CAPCOM Register 22
CAPCOM Reg. 22 Interrupt Ctrl. Reg.
CAPCOM Register 23
CAPCOM Reg. 23 Interrupt Ctrl. Reg.
CAPCOM Register 24
CAPCOM Reg. 24 Interrupt Ctrl. Reg.
CAPCOM Register 25
CAPCOM Reg. 25 Interrupt Ctrl. Reg.
CAPCOM Register 26
FE68H
b F168H E B4H
FE6AH 35H
b F16AH E B5H
FE6CH 36H
b F16CH E B6H
FE6EH 37H
b F16EH E B7H
FE70H 38H
b F170H E B8H
FE72H 39H
b F172H E B9H
FE74H 3AH
b F174H E BAH
FE76H 3BH
b F176H E BBH
FE78H 3CH
CAPCOM Reg. 26 Interrupt Ctrl. Reg.
CAPCOM Register 27
CAPCOM Reg. 27 Interrupt Ctrl. Reg.
CAPCOM Register 28
b F178H E BCH CAPCOM Reg. 28 Interrupt Ctrl. Reg.
FE7AH
3DH
CAPCOM Register 29
b F184H E C2H
CAPCOM Reg. 29 Interrupt Ctrl. Reg.
CAPCOM Reg. 2 Interrupt Ctrl. Reg.
CAPCOM Register 3
CAPCOM Register 30
CAPCOM Reg. 30 Interrupt Ctrl. Reg.
CAPCOM Register 31
b FF7CH
FE86H
BEH
43H
3EH
FE7CH
b F18CH E C6H
FE7EH 3FH
b F194H E CAH CAPCOM Reg. 31 Interrupt Ctrl. Reg.
CC31IC
CC3IC
b FF7EH
BFH
CAPCOM Reg. 3 Interrupt Ctrl. Reg.
Data Sheet
52
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
CC4
CC4IC
CC5
CC5IC
CC6
CC6IC
CC7
CC7IC
CC8
CC8IC
CC9
CC9IC
CCM0
CCM1
CCM2
CCM3
CCM4
CCM5
CCM6
CCM7
CP
FE88H
b FF80H
FE8AH
b FF82H
FE8CH
b FF84H
FE8EH
b FF86H
FE90H
44H
C0H
45H
C1H
46H
C2H
47H
C3H
48H
C4H
49H
C5H
A9H
AAH
ABH
CAPCOM Register 4
CAPCOM Reg. 4 Interrupt Ctrl. Reg.
CAPCOM Register 5
CAPCOM Register 5 Interrupt Ctrl. Reg.
CAPCOM Register 6
CAPCOM Reg. 6 Interrupt Ctrl. Reg.
CAPCOM Register 7
CAPCOM Reg. 7 Interrupt Ctrl. Reg.
CAPCOM Register 8
CAPCOM Reg. 8 Interrupt Ctrl. Reg.
CAPCOM Register 9
CAPCOM Reg. 9 Interrupt Ctrl. Reg.
CAPCOM Mode Control Register 0
CAPCOM Mode Control Register 1
CAPCOM Mode Control Register 2
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
FC00H
0000H
0000H
b FF88H
FE92H
b FF8AH
b FF52H
b FF54H
b FF56H
b FF58H
b FF22H
b FF24H
b FF26H
b FF28H
FE10H
ACH CAPCOM Mode Control Register 3
91H
92H
93H
94H
08H
B5H
04H
CAPCOM Mode Control Register 4
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
CAPCOM Mode Control Register 7
CPU Context Pointer Register
GPT2 CAPREL Interrupt Ctrl. Register
CPU Code Segment Pointer Register
(read only)
CRIC
CSP
b FF6AH
FE08H
DP0L
DP0H
DP1L
DP1H
DP2
b F100H E 80H
b F102H E 81H
b F104H E 82H
b F106H E 83H
P0L Direction Control Register
P0H Direction Control Register
P1L Direction Control Register
P1H Direction Control Register
Port 2 Direction Control Register
Port 3 Direction Control Register
00H
00H
00H
00H
b FFC2H
b FFC6H
E1H
E3H
0000H
0000H
DP3
Data Sheet
53
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
DP4
DP6
DP7
DP8
b FFCAH
b FFCEH
b FFD2H
b FFD6H
FE00H
E5H
E7H
E9H
EBH
00H
01H
02H
03H
Port 4 Direction Control Register
00H
00H
00H
Port 6 Direction Control Register
Port 7 Direction Control Register
Port 8 Direction Control Register
CPU Data Page Pointer 0 Reg. (10 bits)
CPU Data Page Pointer 1 Reg. (10 bits)
CPU Data Page Pointer 2 Reg. (10 bits)
CPU Data Page Pointer 3 Reg. (10 bits)
External Interrupt Control Register
CPU Multiply Divide Control Register
CPU Multiply Divide Reg. – High Word
CPU Multiply Divide Reg. – Low Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
Constant Value 1’s Register (read only)
Port 0 High Reg. (Upper half of PORT0)
Port 0 Low Reg. (Lower half of PORT0)
Port 1 High Reg. (Upper half of PORT1)
Port 1 Low Reg. (Lower half of PORT1)
Port 2 Register
00H
DPP0
DPP1
DPP2
DPP3
EXICON
MDC
MDH
MDL
ODP2
ODP3
ODP6
ODP7
ODP8
ONES
P0H
P0L
P1H
P1L
P2
P3
P4
P5
P5DIDIS
P6
0000H
0001H
0002H
0003H
0000H
0000H
0000H
0000H
0000H
0000H
00H
FE02H
FE04H
FE06H
b F1C0H E E0H
b FF0EH
FE0CH
87H
06H
07H
FE0EH
b F1C2H E E1H
b F1C6H E E3H
b F1CEH E E7H
b F1D2H E E9H
b F1D6H E EBH
00H
00H
FFFFH
00H
FF1EH
b FF02H
b FF00H
b FF06H
b FF04H
b FFC0H
b FFC4H
b FFC8H
b FFA2H
b FFA4H
b FFCCH
b FFD0H
b FFD4H
8FH
81H
80H
83H
82H
E0H
E2H
E4H
D1H
D2H
E6H
E8H
EAH
00H
00H
00H
0000H
0000H
00H
XXXXH
0000H
00H
Port 3 Register
Port 4 Register (8 bits)
Port 5 Register (read only)
Port 5 Digital Input Disable Register
Port 6 Register (8 bits)
P7
P8
Port 7 Register (8 bits)
Port 8 Register (8 bits)
00H
00H
Data Sheet
54
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICON
PDCR
PP0
PP1
PP2
PP3
PSW
PT0
PT1
PT2
PT3
FEC0H
FEC2H
FEC4H
FEC6H
FEC8H
FECAH
FECCH
FECEH
60H
61H
62H
63H
64H
65H
66H
67H
PEC Channel 0 Control Register
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
XXH
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Port Input Threshold Control Register
Pin Driver Control Register
PWM Module Period Register 0
PWM Module Period Register 1
PWM Module Period Register 2
PWM Module Period Register 3
CPU Program Status Word
PWM Module Up/Down Counter 0
PWM Module Up/Down Counter 1
PWM Module Up/Down Counter 2
PWM Module Up/Down Counter 3
PWM Module Pulse Width Register 0
PWM Module Pulse Width Register 1
PWM Module Pulse Width Register 2
PWM Module Pulse Width Register 3
PWM Module Control Register 0
PWM Module Control Register 1
PWM Module Interrupt Control Register
System Start-up Config. Reg. (Rd. only)
b F1C4H E E2H
F0AAH E 55H
F038H E 1CH
F03AH E 1DH
F03CH E 1EH
F03EH E 1FH
b FF10H
88H
F030H E 18H
F032H E 19H
F034H E 1AH
F036H E 1BH
FE30H
FE32H
FE34H
FE36H
PW0
PW1
PW2
PW3
18H
19H
1AH
1BH
98H
99H
PWMCON0 b FF30H
PWMCON1 b FF32H
PWMIC
RP0H
b F17EH E BFH
b F108H E 84H
S0BG
FEB4H
5AH
Serial Channel 0 Baudrate Generator
Reload Register
0000H
S0CON
b FFB0H
D8H
Serial Channel 0 Control Register
0000H
Data Sheet
55
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
S0EIC
S0RBUF
b FF70H
B8H
59H
Serial Chan. 0 Error Interrupt Ctrl. Reg.
Serial Channel 0 Receive Buffer Reg.
(read only)
0000H
XXH
FEB2H
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
0000H
00H
S0TBIC
S0TBUF
S0TIC
b F19CH E CEH Serial Channel 0 Transmit Buffer
Interrupt Control Register
Serial Channel 0 Transmit Buffer Reg.
(write only)
Serial Channel 0 Transmit Interrupt
Control Register
CPU System Stack Pointer Register
SSC Baudrate Register
SSC Control Register
SSC Error Interrupt Control Register
SSC Receive Buffer
SSC Receive Interrupt Control Register
SSC Transmit Buffer
SSC Transmit Interrupt Control Register
CPU Stack Overflow Pointer Register
CPU Stack Underflow Pointer Register
CPU System Configuration Register
CAPCOM Timer 0 Register
FEB0H
b FF6CH
FE12H
F0B4H E 5AH
b FFB2H
b FF76H
F0B2H E 59H
b FF74H
F0B0H E 58H
b FF72H
FE14H
FE16H
b FF12H
FE50H
b FF50H
b FF9CH
FE54H
FE52H
b FF9EH
FE56H
FE40H
b FF40H
58H
B6H
09H
0000H
SP
FC00H
0000H
0000H
0000H
XXXXH
0000H
0000H
0000H
FA00H
FC00H
1)0xx0H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
SSCBR
SSCCON
SSCEIC
SSCRB
SSCRIC
SSCTB
SSCTIC
STKOV
STKUN
SYSCON
T0
T01CON
T0IC
T0REL
T1
T1IC
T1REL
T2
D9H
BBH
BAH
B9H
0AH
0BH
89H
28H
A8H
CAPCOM Timer 0 and Timer 1 Ctrl. Reg.
CEH CAPCOM Timer 0 Interrupt Ctrl. Reg.
2AH
29H
CFH
2BH
20H
A0H
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Register
CAPCOM Timer 1 Interrupt Ctrl. Reg.
CAPCOM Timer 1 Reload Register
GPT1 Timer 2 Register
T2CON
GPT1 Timer 2 Control Register
Data Sheet
56
V3.3, 2005-02
C167CR
C167SR
Functional Description
Table 8
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address Addr.
T2IC
T3
T3CON
T3IC
T4
T4CON
T4IC
T5
T5CON
T5IC
T6
T6CON
T6IC
T7
T78CON
T7IC
T7REL
T8
T8IC
T8REL
TFR
WDT
WDTCON
XP0IC
XP1IC
XP2IC
XP3IC
ZEROS
b FF60H
FE42H
b FF42H
b FF62H
FE44H
b FF44H
b FF64H
FE46H
b FF46H
b FF66H
FE48H
B0H
21H
A1H
B1H
22H
A2H
B2H
23H
A3H
B3H
24H
A4H
B4H
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Register
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
2)00XXH
0000H
0000H
0000H
0000H
0000H
GPT1 Timer 3 Control Register
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Register
GPT1 Timer 4 Control Register
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Register
GPT2 Timer 5 Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Register
GPT2 Timer 6 Control Register
GPT2 Timer 6 Interrupt Control Register
CAPCOM Timer 7 Register
CAPCOM Timer 7 and 8 Ctrl. Reg.
CAPCOM Timer 7 Interrupt Ctrl. Reg.
CAPCOM Timer 7 Reload Register
CAPCOM Timer 8 Register
CAPCOM Timer 8 Interrupt Ctrl. Reg.
CAPCOM Timer 8 Reload Register
Trap Flag Register
Watchdog Timer Register (read only)
Watchdog Timer Control Register
CAN1 Module Interrupt Control Register
Unassigned Interrupt Control Register
b FF48H
b FF68H
F050H E 28H
b FF20H
90H
b F17AH E BEH
F054H E 2AH
F052H E 29H
b F17CH E BFH
F056H E 2BH
b FFACH
FEAEH
FFAEH
b F186H E C3H
b F18EH E C7H
D6H
57H
D7H
b F196H E CBH Unassigned Interrupt Control Register
b F19EH E CFH
8EH
PLL/OWD Interrupt Control Register
Constant Value 0’s Register (read only)
b FF1CH
1) The system configuration is selected during reset.
2) The reset value depends on the indicated reset source.
Data Sheet
57
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
Table 9
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
Min.
Max.
150
150
6.5
Storage temperature
Junction temperature
TST
TJ
-65
-40
-0.5
°C
°C
V
–
under bias
–
Voltage on VDD pins with VDD
respect to ground (VSS)
Voltage on any pin with
VIN
–
-0.5
-10
–
VDD + 0.5 V
–
–
–
respect to ground (VSS)
Input current on any pin
during overload condition
Absolute sum of all input
currents during overload
condition
10
mA
–
|100|
mA
Power dissipation
PDISS
–
1.5
W
–
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
58
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CR. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.
Table 10
Parameter
Operating Condition Parameters
Symbol Limit Values Unit Notes
Min.
Max.
Digital supply voltage
VDD
4.5
5.5
V
Active mode,
CPUmax = 33 MHz
Power Down mode
Reference voltage
f
2.51)
5.5
0
±5
50
V
V
Digital ground voltage
Overload current
VSS
IOV
–
–
mA Per pin2)3)
3)
Absolute sum of overload Σ|IOV|
mA
currents
External Load Capacitance CL
–
–
–
50
pF
pF
pF
Pin drivers in
fast edge mode
(PDCR.BIPEC = ‘0’)
30
Pin drivers in
reduced edge mode
(PDCR.BIPEC = ‘1’)3)
100
Pin drivers in
fast edge mode,
f
CPUmax = 25 MHz4)
Ambient temperature
TA
0
-40
-40
70
85
125
°C
°C
°C
SAB-C167CR …
SAF-C167CR …
SAK-C167CR …
1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL1, RD, WR, etc.
3) Not subject to production test - verified by design/characterization.
4) The increased capacitive load is valid for the 25 MHz-derivatives up to a CPU clock frequency of 25 MHz.
Under these circumstances the timing parameters as specified in the “C167CR Data Sheet 1999-06” are valid.
Data Sheet
59
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C167CR
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C167CR will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C167CR.
4.2
DC Parameters
Table 11
DC Characteristics (Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Max.
Input low voltage (TTL,
all except XTAL1)
VIL SR -0.5
0.2 VDD
V
–
- 0.1
Input low voltage XTAL1
Input low voltage
(Special Threshold)
VIL2 SR -0.5
VILS SR -0.5
0.3 VDD
2.0
V
V
–
–
Input high voltage (TTL,
VIH SR 0.2 VDD VDD +
+ 0.9 0.5
V
V
V
V
–
–
–
–
all except RSTIN and XTAL1)
Input high voltage RSTIN
(when operated as input)
Input high voltage XTAL1
VIH1 SR 0.6 VDD VDD +
0.5
VIH2 SR 0.7 VDD VDD +
0.5
Input high voltage
(Special Threshold)
Input Hysteresis
(Special Threshold)
VIHS SR 0.8 VDD VDD +
- 0.2
400
0.5
–
HYS
mV Series
resistance = 0 Ω
Output low voltage
VOL CC –
0.45
V
IOL = 2.4 mA
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT, RSTIN2))
Output low voltage
(all other outputs)
VOL1 CC –
0.45
V
IOL = 1.6 mA
Data Sheet
60
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Table 11
DC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
VOH CC 2.4
Max.
–
–
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)
Output high voltage3)
(all other outputs)
V
V
I
I
OH = -2.4 mA
OH = -0.5 mA
0.9 VDD
VOH1 CC 2.4
0.9 VDD
–
–
V
V
I
I
OH = -1.6 mA
OH = -0.5 mA
Input leakage current (Port 5)
IOZ1 CC –
IOZ2 CC –
±200
±500
nA 0 V < VIN < VDD
Input leakage current
nA 0.45 V < VIN <
(all other)4)
VDD
RSTIN inactive current5)
RSTIN active current5)
IRSTH
IRSTL
–
-100
–
-500
–
500
–
-500
–
-100
-10
–
-40
–
40
–
-40
–
-10
–
±20
10
µA VIN = VIH1
µA VIN = VIL
6)
7)
6)
READY/RD/WR inact. current8) IRWH
µA
µA
µA
µA
µA
µA
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
READY/RD/WR active current8) IRWL
7)
ALE inactive current8)
ALE active current8)
Port 6 inactive current8)
Port 6 active current8)
IALEL
IALEH
6)
7)
6)
IP6H
7)
IP6L
PORT0 configuration current9) IP0H
µA VIN = VIHmin
µA VIN = VILmax
µA 0 V < VIN < VDD
6)
7)
IP0L
IIL
XTAL1 input current
CC –
Pin capacitance10)
CIO CC –
pF f = 1 MHz;
(digital inputs/outputs)
TA = 25 °C
1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2) Valid in bidirectional reset mode only.
3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
4) This parameter is not valid for pins READY, ALE, RD, and WR while the respective pull device is on.
5) These parameters describe the RSTIN pull-up, which equals a resistance of ca. 50 to 250 kΩ.
6) The maximum current may be drawn while the respective signal line remains inactive.
7) The minimum current must be drawn in order to drive the respective signal line active.
8) This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins
are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The
READY-pull-up is always active, except for Power-down mode.
Data Sheet
61
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
9) This specification is valid during Reset and during Adapt-mode.
10) Not subject to production test - verified by design/characterization.
Table 12
Power Consumption C167CR (Operating Conditions apply)
Parameter
Symbol Limit Values
Unit Test Condition
Min.
Max.
Power supply current (active) IDD
–
15 + 2.5
× fCPU
mA RSTIN = VIL
with all peripherals active
f
CPU in [MHz]1)
Idle mode supply current
IID
–
–
10 + 1.0
mA RSTIN = VIH1
× fCPU
f
CPU in [MHz]1)
2)
Power-down mode supply
current
IPD
50
µA VDD = VDDmax
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Data Sheet
62
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
I [mA]
140
IDDmax
120
100
IDDtyp
80
60
40
20
IIDmax
IIDtyp
10
20
30
40
f
CPU [MHz]
Figure 9
Supply/Idle Current as a Function of Operating Frequency
Data Sheet
63
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4.3
Analog/Digital Converter Parameters
Table 13
A/D Converter Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Max.
Unit Test
Condition
Min.
AREF SR 4.0
AGNDSR VSS - 0.1 VSS + 0.2 V
1)
Analog reference supply
Analog reference ground
Analog input voltage range VAIN SR VAGND
Basic clock frequency
Conversion time
V
V
VDD + 0.1 V
–
2)
VAREF
6.25
V
MHz
–
3)
4)
fBC
tC
0.5
CC –
40 tBC + tS
+ 2 tCPU
t
CPU = 1/fCPU
5)
Calibration time after reset tCAL CC –
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of
analog source
ADC input capacitance
3328 tBC
±2
–
LSB
kΩ
1)
TUE CC –
RAREF SR –
tBC / 60
tBC in [ns]6)7)
- 0.25
RASRC SR –
tS / 450
kΩ
tS in [ns]7)8)
- 0.25
7)
CAIN CC –
33
pF
1) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within
the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e. VAREF = VDD + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.
2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
3) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock tBC depend on programming and can be taken from Table 14.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5) During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7) Not subject to production test - verified by design/characterization.
Data Sheet
64
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
8) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample time tS depend on programming and can be taken from Table 14.
Sample time and conversion time of the C167CR’s A/D Converter are programmable.
Table 14 should be used to calculate the above timings.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14
A/D Converter Computation Table
ADCON.15|14
A/D Converter
ADCON.13|12
Sample time
(ADCTC)
Basic clock fBC
(ADSTC)
tS
00
01
10
11
fCPU / 4
fCPU / 2
fCPU / 16
fCPU / 8
00
01
10
11
t
t
t
t
BC × 8
BC × 16
BC × 32
BC × 64
Converter Timing Example:
Assumptions:
Basic clock
Sample time
fCPU = 25 MHz (i.e. tCPU = 40 ns), ADCTC = ‘00’, ADSTC = ‘00’
fBC
tS
= fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns
= tBC × 8 = 1280 ns
Conversion
time
tC
= tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 µs
Data Sheet
65
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4.4
AC Parameters
4.4.1
Definition of Internal Timing
The internal operation of the C167CR is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
MCT04338
TCL
Figure 10
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C167CR.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
Data Sheet
66
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
P0.15-13 (P0H.7-5).
Table 15 associates the combinations of these three bits with the respective clock
generation mode.
Table 15
C167CR Clock Generation Modes
CPU Frequency External Clock
CLKCFG
Notes
(P0H.7-5)
f
CPU = fOSC × F
Input Range1)
2.5 to 8.25 MHz
3.33 to 11 MHz
5 to 16.5 MHz
2 to 6.6 MHz
1 to 33 MHz
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
f
f
f
f
f
f
f
f
OSC × 4
OSC × 3
OSC × 2
OSC × 5
OSC × 1
OSC × 1.5
OSC / 2
Default configuration
–
–
–
Direct drive2)
6.66 to 22 MHz
2 to 66 MHz
4 to 13.2 MHz
–
CPU clock via prescaler
–
OSC × 2.5
1) The external clock input range refers to a CPU clock range of 10 … 33 MHz (PLL operation).
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU
= fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU clock
to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
Data Sheet
67
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N × TCL the minimum value is computed using the corresponding
deviation DN:
(N × TCL)min = N × TCLNOM - DN, DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz],
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
(1)
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 × 6.3) / 25 = 1.288 ns,
and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).
Max. jitter DN
±30
10 MHz
±26.5
This approximated formula is valid for
ns
1
N
40 and 10 MHz fCPU 33 MHz.
±20
16 MHz
20 MHz
25 MHz
33 MHz
±10
±1
N
1
5
10
20
40
MCD04413
Figure 11
Approximated Maximum Accumulated PLL Jitter
Data Sheet
68
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Direct Drive
When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
f
CPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC
.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin (DC = duty cycle)
(2)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to be
used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC
.
Data Sheet
69
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4.4.2
External Clock Drive XTAL1
Table 16
External Clock Drive Characteristics (Operating Conditions apply)
Parameter
Symbol
Direct Drive
Prescaler
PLL
Unit
1:1
2:1
1:N
Min.
30
153)
153)
–
Max. Min.
Max. Min.
Max.
5001) ns
Oscillator period tOSC SR
–
–
–
8
8
15
5
5
–
–
–
–
–
5
5
451)
10
10
–
High time2)
Low time2)
Rise time2)
Fall time2)
t1
t2
t3
t4
SR
SR
SR
SR
–
ns
ns
ns
ns
–
10
10
–
–
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock
generation mode. Please see respective table above.
2) The clock input signal must reach the defined levels VIL2 and VIH2
.
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in
direct drive mode depends on the duty cycle of the clock input signal.
t 1
t 3
t 4
VIH2
VIL
0.5 VDD
t 2
t OSC
MCT02534
Figure 12
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
70
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4.4.3
Testing Waveforms
2.4 V
1.8 V
1.8 V
0.8 V
Test Points
0.8 V
0.45 V
AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at IH min for a logic ’1’ and IL max for a logic ’0’.
V
V
MCA04414
Figure 13
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH
/
VOL level occurs (IOH
/
I
OL = 20 mA).
MCA00763
Figure 14
Float Waveforms
Data Sheet
71
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
4.4.4
External Bus Timing
Table 17
CLKOUT Reference Signal
Parameter
Symbol
Limits
Unit
Min.
Max.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
tc5 CC
tc6 CC
tc7 CC
tc8 CC
tc9 CC
301)
–
ns
ns
ns
ns
ns
8
6
–
–
–
4
4
CLKOUT fall time
1) The CLKOUT cycle time is influenced by the PLL jitter.
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for fCPU > 25 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tc9
tc7
tc8
tc5
tc6
CLKOUT
MCT04415
Figure 15
CLKOUT Signal Timing
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 18
Bus Cycle Type
Demultiplexed bus cycle 4 + 2 × (15 - <MCTC>) TCL 80 ns/60.6 ns
with normal ALE + 2 × (1 - <MTTC>)
Demultiplexed bus cycle 6 + 2 × (15 - <MCTC>) TCL 120 ns/90.9 ns
with extended ALE + 2 × (1 - <MTTC>)
Multiplexed bus cycle with 6 + 2 × (15 - <MCTC>) TCL 120 ns/90.9 ns
normal ALE + 2 × (1 - <MTTC>)
Variable Memory Cycles
Bus Cycle Duration
Unit 25/33 MHz, 0 Waitstates
Multiplexed bus cycle with 8 + 2 × (15 - <MCTC>) TCL 160 ns/121.2 ns
extended ALE
Data Sheet
+ 2 × (1 - <MTTC>)
72
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Table 19
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
Min. Max.
Output delay from CLKOUT falling edge
tc10 CC -2
tc11 CC -2
tc12 CC -2
11
ns
ns
ns
Valid for: address, BHE, early CS, write data out, ALE
Output delay from CLKOUT rising edge
Valid for: latched CS, ALE low
Output delay from CLKOUT rising edge
Valid for: WR low (no RW delay), RD low (no RW
delay)
6
8
Output delay from CLKOUT falling edge
Valid for: RD/WR low (with RW delay), RD high (with
RW delay)
tc13 CC -2
6
ns
Input setup time to CLKOUT falling edge
Valid for: read data in
tc14 SR 14
tc15 SR 0
tc17 CC -2
tc18 CC -2
tc19 CC -2
tc20 CC –
tc21 CC -5
–
–
6
–
4
7
–
ns
ns
ns
ns
ns
ns
ns
Input hold time after CLKOUT falling edge
Valid for: read data in1)
Output hold time after CLKOUT falling edge
Valid for: address, BHE, early CS2)
Output hold time after CLKOUT edge3)
Valid for: write data out
Output delay from CLKOUT falling edge
Valid for: WR high
Turn off delay after CLKOUT edge3)
Valid for: write data out
Turn on delay after CLKOUT falling edge3)
Valid for: write data out
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore the read data may be removed immediately after the rising edge of RD. Address changes
before the end of RD have also no impact on (demultiplexed) read cycles.
2) Due to comparable propagation delays (at comparable capacitive loads) the address does not change before
WR goes high. The minimum output delay (tc17min) is therefore the actual value of tc19.
3) Not subject to production test - verified by design/characterization.
Data Sheet
73
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
General Notes for the Following Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1. The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the
Read/Write delay feature (bit BUSCON.RWDCx).
2. A bus cycle is extended here, if MCTC waitstates are selected or if the READY input
is sampled inactive.
3. A bus cycle is extended here, if an MTTC waitstate is selected.
Data Sheet
74
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
Normal ALE Cycle
tc11
tc10
Normal ALE
Extended ALE Cycle
tc10
tc10
Extended ALE
CSxL
tc11
tc11
tc11
tc10
tc10
tc17
A23-A0
BHE, CSxE
Valid
tc13
tc12
tc19
WRL, WRH,
WR, WrCS
1)
tc10
tc20
tc18
tc21
D15-D0
Data OUT
2)
MCTC
3)
MTTC
MCT04416
Figure 16
Demultiplexed Bus, Write Access
Data Sheet
75
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
Normal ALE Cycle
tc11
tc10
Normal ALE
Extended ALE Cycle
tc10
tc10
Extended ALE
CSxL
tc11
tc11
tc11
tc10
tc10
tc17
A23-A0,
BHE, CSxE
Valid
tc13
tc12
tc13
RD,
RdCS
1)
tc15
tc14
D15-D0
Data IN
2)
MCTC
3)
MTTC
MCT04417
Figure 17
Demultiplexed Bus, Read Access
Data Sheet
76
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
Normal ALE Cycle
tc11
tc10
Normal ALE
Extended ALE Cycle
tc10
tc10
Extended ALE
CSxL
tc11
tc11
tc10
tc10
tc17
A23-A16
BHE, CSxE
Valid
tc13
tc12
tc19
WRL, WRH,
WR, WrCS
1)
tc10
tc10
tc17
tc20
tc18
tc21
AD15-AD0
(Normal ALE)
Low Address
Data OUT
Data OUT
tc10
tc10
tc20
tc21
tc17
tc18
AD15-AD0
(Extended ALE)
Low Address
2)
MCTC
3)
MTTC
MCT04418
Figure 18
Multiplexed Bus, Write Access
Data Sheet
77
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
Normal ALE Cycle
tc11
tc10
Normal ALE
Extended ALE Cycle
tc10
tc10
Extended ALE
CSxL
tc11
tc11
tc10
tc10
tc17
A23-A16
BHE, CSxE
Valid
tc13
tc12
tc13
RD,
RdCS
1)
tc10
tc20
tc17
tc15
tc21
tc14
AD15-AD0
(Normal ALE)
Low Address
Data IN
tc10
tc20
tc15
tc21
tc17
tc14
AD15-AD0
(Extended ALE)
Low Address
Data IN
2)
MCTC
3)
MTTC
MCT04419
Figure 19
Multiplexed Bus, Read Access
Data Sheet
78
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage.
Table 20
READY Timing (Operating Conditions apply)
Parameter
Symbol
Min.
tc25 CC 12
Limits
Max.
Unit
Input setup time to CLKOUT rising edge
Valid for: READY input
Input hold time after CLKOUT rising edge
Valid for: READY input
Asynchronous READY input low time6)
–
–
–
ns
ns
ns
tc26 CC
0
tc27 CC tc5 + tc25
Notes (Valid also for Figure 20)
4. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
5. READY sampled HIGH at this sampling point generates a READY controlled
waitstate, READY sampled LOW at this sampling point terminates the currently
running bus cycle.
6. These timings are given for test purposes only, in order to assure recognition at a
specific clock edge. If the Asynchronous READY signal does not fulfill the indicated
setup and hold times with respect to CLKOUT, it must fulfill tc27 in order to be safely
synchronized. Proper deactivation of READY is guaranteed if READY is deactivated
in response to the trailing (rising) edge of the corresponding command (RD or WR).
7. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an
additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC
waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC
waitstate this delay is zero.
8. If the next following bus cycle is READY controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates
and the ALE mode of the next following cycle. If the current cycle uses a multiplexed
bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY
deactivation time.
Data Sheet
79
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
Running Cycle4)
READY WS
MUX/MTTC
7)
CLKOUT
D15-D0
tc15
tc14
Data IN
tc10
tc20
tc18
tc21
D15-D0
Data OUT
tc13
tc12
tc13
/
tc19
Command
(RD, WR)
1)
6)
tc26
tc26
tc25
tc25
Synchronous
READY
5)
5)
tc27
tc26
tc25
tc26
tc25
Asynchronous
READY
5)
5)
8)
MCT04420
Figure 20
READY Timings
Data Sheet
80
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
External Bus Arbitration
Table 21
Parameter
Bus Arbitration Timing (Operating Conditions apply)
Symbol Limits
Max.
Unit
Min.
HOLD input setup time to CLKOUT falling edge tc28 SR 18
–
6
6
10
6
ns
ns
ns
ns
ns
ns
ns
CLKOUT to BREQ delay
CLKOUT to HLDA delay
CSx release1)
tc29 CC -4
tc30 CC -4
tc31 CC 0
tc32 CC -2
tc33 CC 0
tc34 CC 0
CSx drive
Other signals release1)
10
6
Other signals drive1)
1) Not subject to production test - verified by design/characterization.
Data Sheet
81
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
HOLD
HLDA
BREQ
CS
tc28
tc30
1)
tc29
2)
tc31
3)
tc33
Other
Signals
MCT04421
Figure 21
Notes
External Bus Arbitration, Releasing the Bus
1. The C167CR will complete the currently running bus cycle before granting bus
access.
2. This is the first possibility for BREQ to get active.
3. The CS outputs will be resistive high (pull-up) after t33. Latched CS outputs are driven
high for 1 TCL before the output drivers are switched off.
Data Sheet
82
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
CLKOUT
HOLD
HLDA
BREQ
CS
5)
tc28
tc30
tc29
tc29
tc29
4)
tc32
tc34
Other
Signals
MCT04422
Figure 22
Notes
External Bus Arbitration, Regaining the Bus
4. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if
BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C167CR requesting the
bus.
5. The next C167CR driven bus cycle may start here.
Data Sheet
83
V3.3, 2005-02
C167CR
C167SR
Electrical Parameters
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Table 22
XRAM Access Timing (Operating Conditions apply)1)
Parameter
Symbol
Limits
Min. Max.
Unit
Address setup time before RD/WR falling edge
Address hold time after RD/WR rising edge
Data turn on delay after RD falling edge
Data output valid delay after address latched
Data turn off delay after RD rising edge
Write data setup time before WR rising edge
Write data hold time after WR rising edge
WR pulse width
t40
t41
t42
t43
t44
t45
t46
t47
t48
SR
SR
CC
CC
CC
SR 10
SR
SR 20
4
0
1
–
1
–
–
–
40
14
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
WR signal recovery time
1) The minimum access cycle time is 60 ns.
SR t40
–
t40
t41
Address
t47
t48
Command
(RD, WR)
t46
t45
Write Data
t43
t42
t44
Read Data
MCT04423
Figure 23
External Access to the XRAM
Data Sheet
84
V3.3, 2005-02
C167CR
C167SR
Package Outlines
5
Package Outlines
H
0.65
±0.15
0.88
144x
0.12 A-B D C
±0.08
0.3
C
0.1
M
35 x 0.65 = 22.75
31.2
281)
0.2 A-B D 4x
0.2 A-B D H 4x
D
A
B
144
1
1 x 45˚
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
GPM05248
Figure 24
P-MQFP-144-8 (Plastic Metric Quad Flat Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
V3.3, 2005-02
Data Sheet
85
C167CR
C167SR
Package Outlines
13 x 1 = 13
A14
A1
1
P1
+0.14
176x
ø0.5
-0.16
C
M
ø0.3
0.2
A B C
C
M
ø0.1
A
±0.5
1.5
Index Marking
4x
±1
13
Index Marking
(sharp edge)
±0.2
15
B
GPA09430
Figure 25
P-BGA-176-2 (Plastic Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
V3.3, 2005-02
Data Sheet
86
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
Home > Products > Product Categories > Microcontrollers > 16-Bit > C166 Family > C167CR⁄SR > Product Type List
Product Type List
Product Type
Description
Datasheet
Parameter
Packages
Order Info
16-Bit
XC166 Family
C166 Family
C161CS, C161JC, C161JI
SAB-C167CR-LM HA+
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, 0 degC/70 degC, 5V, HA+ step
PG-MQFP-144
in production
SAF-C167CR-LM HA+
SAK-C167CR-LM HA+
SAB-C167CR-LM HA+
25 MHz, 4 kByte RAM, CAN, ASC, SSC,
-40 degC/85 degC, 5V, HA+ step
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
on request
on request
on request
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/125 degC, 5V, HA+ step
C161K, C161O
C161PI
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, 0 degC/70 degC, 5V, automotive
quality, HA+ step
C161S
C164CI, C164CL, C164SI
C164CM, C164SM, C164SV
C165
SAF C167CR-LM HA+
SAK-C167CR-LM HA+
SAB-C167CR-L33M HA+
SAF-C167CR-L33M HA+
SAK-C167CR-L33M HA+
SAB-C167CR-4RM HA+
SAF-C167CR-4RM HA+
SAK-C167CR-4RM HA+
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/85 degC, 5V, automotive
quality, HA+ step
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
on request
in production
on request
on request
on request
on request
on request
on request
on request
on request
on request
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/125 degC, 5V,
automotive quality, HA+ step
C167CR⁄SR
Product Type List
Documents
33 MHz, 4 kByte RAM, CAN, ASC,
SSC, 0 degC/70 degC, 5V, automotive
quality, HA+ step
C167CS
SAF C165 UTAH-LF
SAFC165H-LF
SAF-C161U-LF
33 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/85 degC, 5V, automotive
quality, HA+ step
33 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/125 degC, 5V,
automotive quality, HA+ step
Archive of Discontinued
Products (Technical
Documentation only)
25 MHz, 4 kByte RAM, CAN, ASC, SSC,
0 degC/70 degC, 5V, automotive quality,
HA+ step
Parameter Table
Documents
C166 Architecture & Core
Parameter Table
Documents
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/85 degC, 5V, automotive
quality, HA+ step
25 MHz, 4 kByte RAM, CAN, ASC, SSC,
-40 degC/125 degC, 5V, automotive
quality, HA+ step
Product Overviews
Application Notes - 16-bit
Microcontrollers
SAB-C167CR-4R33M HA+ 33 MHz, 4 kByte RAM, CAN, ASC,
SSC, 0 degC/70 degC, 5V, automotive
quality, HA+ step
SAF-C167CR-4R33M HA+ 33 MHz, 4 kByte RAM, CAN, ASC, SSC,
-40 degC/85 degC, 5V, automotive
quality, HA+ step
SAK-C167CR-4R33M HA+ 33 MHz, 4 kByte RAM, CAN, ASC,
SSC, -40 degC/125 degC, 5V,
automotive quality, HA+ step
SAB-C167CR-16RM HA+
SAF-C167CR-16RM HA+
SAK-C167CR-16RM HA+
25 MHz, 4 kByte RAM, CAN, ASC, SSC,
-40 degC/85 degC, 5V, automotive
quality, HA+ step
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
on request
on request
on request
25 MHz, 4 kByte RAM, CAN, ASC, SSC,
-40 degC/125 degC, 5V, automotive
quality, HA+ step
25 MHz, 4 kByte RAM, CAN, ASC,
SSC, 0 degC/70 degC, 5V, automotive
quality, HA+ step
SAB-C167SR-LM HA+
SAF-C167SR-LM HA+
SAK-C167SR-LM HA+
SAB-C167SR-LM HA+
25 MHz, 4 kByte RAM, ASC,
SSC, 0 degC/70 degC, 5V, HA+ step
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
PG-MQFP-144
in production
on request
on request
on request
25 MHz, 4 kByte RAM, ASC, SSC, -40
degC/85 degC, 5V, HA+ step
25 MHz, 4 kByte RAM, ASC, SSC,
-40 degC/125 degC, 5V, HA+ step
25 MHz, 4 kByte RAM, ASC,
SSC, 0 degC/70 degC, 5V, automotive
quality, HA+ step
SAF-C167SR-LM HA+
SAK-C167SR-LM HA+
25 MHz, 4 kByte RAM, ASC,
SSC, -40 degC/85 degC
, 5V, automotive quality, HA+ step
PG-MQFP-144
PG-MQFP-144
on request
25 MHz, 4 kByte RAM, ASC, SSC,
-40 degC/125 degC, 5V, automotive
quality, HA+ step
in production
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相关型号：
SAK-C167CR-LMHA+
Microcontroller, 16-Bit, C166 CPU, 25MHz, CMOS, PQFP144, PLASTIC, MQFP-144
INFINEON
SAK-C167CS-4R33M-BA
Microcontroller, 16-Bit, MROM, 33MHz, CMOS, PQFP144, METRIC, PLASTIC, QFP-144
INFINEON
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