SAK-TC1791F-512F240EP AB [INFINEON]

TC1791 是 AUDO MAX 系列三种优质衍生产品之一。;


型号：	SAK-TC1791F-512F240EP AB
厂家：	Infineon
描述：	TC1791 是 AUDO MAX 系列三种优质衍生产品之一。
文件：	总153页 (文件大小：4075K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

32-Bit

Microcontroller

TC1791

32-Bit Single-Chip Microcontroller

Data Sheet

V 1.1 2014-05

Microcontrollers

Edition 2014-05

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

32-Bit

Microcontroller

TC1791

32-Bit Single-Chip Microcontroller

Data Sheet

V 1.1 2014-05

Microcontrollers

TC1791

Table of Contents

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

System Overview of the TC1791 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.1

TC1791 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67

5.1

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70

Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-71

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72

Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75

Extended Range Operating Conditions . . . . . . . . . . . . . . . . . . . . . 5-81

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83

Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83

Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . 5-104

Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110

Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . 5-113

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116

Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-118

Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120

ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-123

JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-124

DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-126

Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127

Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 5-130

SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132

ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.6.1

5.3

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.4

5.5

5.5.1

5.5.2

Data Sheet

I-1

V 1.1, 2014-05

TC1791

5.5.3

Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140

History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Data Sheet

I-2

V 1.1, 2014-05

TC1791

Data Sheet

V 1.1, 2014-05

TC1791

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

The SAK-TC1791F-512F240EL / SAK-TC1791F-512F240EP has the following

features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 240 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

48 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, and ADC2)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

The SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP has the following

features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 200 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

•

– 32 Kbyte Code Memory (CMEM)

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

44 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, and ADC2)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

The SAK-TC1791F-384F200EL / SAK-TC1791F-384F200EP has the following

features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 200 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

•

– 200 MHz operation at full temperature range

Multiple on-chip memories

– 3 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

•

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

44 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, and ADC2)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

•

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

The SAK-TC1791S-512F240EP has the following features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 240 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 4 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

48 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, and ADC2)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

Secure Hardware Extension (SHE)

•

– For further information please contact your Infineon representative

The SAK-TC1791S-384F200EP has the following features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 200 MHz operation at full temperature range

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

•

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

– 3 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

– 16 Kbyte BootROM (BROM)

•

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– One FlexRay^TMmodule with 2 channels (E-Ray).

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

44 analog input lines for ADC

•

– 4 independent kernels (ADC0, ADC1, and ADC2)

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– Analog supply voltage range from 3.3 V to 5 V (single supply)

•

4 different FADC input channels

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

Power Management System

•

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

Secure Hardware Extension (SHE)

•

– For further information please contact your Infineon representative

The SAK-TC1791N-384F200EP has the following features:

•

High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– 200 MHz operation at full temperature range

32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

– 200 MHz operation at full temperature range

Multiple on-chip memories

•

– 3 Mbyte Program Flash Memory (PFLASH) with ECC

– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 2 x 8 Kbyte Key Flash

– 128 Kbyte Data Scratch-Pad RAM (DSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Data Cache (DACHE)

– 128 Kbyte Memory (SRAM)

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

– 16 Kbyte BootROM (BROM)

16-Channel DMA Controller

8-Channel Safe DMA (SDMA) Controller

Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels

serviced by CPU or PCP2

•

High performing on-chip bus structure

– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

•

Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,

parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data

length and shift direction

– Four SSC Guardian (SSCG) modules, one for each SSC

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external

power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor

communication

– One MultiCAN Module with 4 CAN nodes and 128 free assignable message

objects for high efficiency data handling via FIFO buffering and gateway data

transfer (one CAN node supports TTCAN functionality)

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer

Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer

functionality to realize autonomous and complex Input/Output management

– Two Capture / Compare 6 modules

– Two General Purpose 12 Timer Units (GPT120 and GPT121)

44 analog input lines for ADC

– 4 independent kernels (ADC0, ADC1, and ADC2)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

4 different FADC input channels

•

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of f_FADCclock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of

consecutive conversions in digital data reduction filter)

8 digital input lines for SENT

•

– communication according to the SENT specification J2716 FEB2008

128 digital general purpose I/O lines (GPIO)

Digital I/O ports with 3.3 V capability

On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)

Dedicated Emulation Device chip available (TC1791ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

•

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

•

Power Management System

Clock Generation Unit with PLL and PLL_ERAY

Flexible CRC Engine (FCE)

– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)

– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)

Data Sheet

V 1.1, 2014-05

TC1791

Summary of Features

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

•

The derivative itself, i.e. its function set, the temperature range, and the supply

voltage

•

The package and the type of delivery.

For the available ordering codes for the TC1791 please refer to the “Product Catalog

Microcontrollers”, which summarizes all available microcontroller variants.

This document describes the derivatives of the device.The Table 1 enumerates these

derivatives and summarizes the differences.

Table 1

TC1791 Derivative Synopsis

Derivative

Ambient Temperature Range

T_A= -40^oC to +125^oC

SAK-TC1791F-512F240EL

SAK-TC1791F-512F240EP

SAK-TC1791F-512F200EL

SAK-TC1791F-512F200EP

SAK-TC1791F-384F200EL

SAK-TC1791F-384F200EP

SAK-TC1791S-512F240EP

SAK-TC1791S-384F200EP

SAK-TC1791N-384F200EP

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791

The TC1791 combines three powerful technologies within one silicon die, achieving new

levels of power, speed, and economy for embedded applications:

•

Reduced Instruction Set Computing (RISC) processor architecture

Digital Signal Processing (DSP) operations and addressing modes

On-chip memories and peripherals

DSP operations and addressing modes provide the computational power necessary to

efficiently analyze complex real-world signals. The RISC load/store architecture

provides high computational bandwidth with low system cost. On-chip memory and

peripherals are designed to support even the most demanding high-bandwidth real-time

embedded control-systems tasks.

Additional high-level features of the TC1791 include:

•

Efficient memory organization: instruction and data scratch memories, caches

Serial communication interfaces – flexible synchronous and asynchronous modes

Peripheral Control Processor – standalone data operations and interrupt servicing

DMA Controller – DMA operations and interrupt servicing

General-purpose timers

High-performance on-chip buses

On-chip debugging and emulation facilities

Flexible interconnections to external components

Flexible power-management

The TC1791 is a high-performance microcontroller with TriCore CPU, program and data

memories, buses, bus arbitration, an interrupt controller, a peripheral control processor

and a DMA controller and several on-chip peripherals. The TC1791 is designed to meet

the needs of the most demanding embedded control systems applications where the

competing issues of price/performance, real-time responsiveness, computational power,

data bandwidth, and power consumption are key design elements.

The TC1791 offers several versatile on-chip peripheral units such as serial controllers,

timer units, and Analog-to-Digital converters. Within the TC1791, all these peripheral

units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect

(FPI) Bus and the Cross Bar Interconnect (SRI). Several I/O lines on the TC1791 ports

are reserved for these peripheral units to communicate with the external world.

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791Block Diagram

2.1

Block Diagram

Figure 1 shows the block diagram of the SAK-TC1791F-512F240EL / SAK-TC1791F-

512F240EP / SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP.

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar(XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

2 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1791

Figure 1

Block Diagram

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791Block Diagram

Figure 2 shows the block diagram of the SAK-TC1791F-384F200EL / SAK-TC1791F-

384F200EP.

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar(XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

1 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1791

Figure 2

Block Diagram

Figure 3 shows the block diagram of the SAK-TC1791S-512F240EP.

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791Block Diagram

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

SRI Cross Bar (XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

2 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

SHE

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1791

Figure 3

Block Diagram

Figure 4 shows the block diagram of the SAK-TC1791S-384F200EP.

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791Block Diagram

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar(XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

1 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

SHE

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

E-Ray

(2 Channels)

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1791

Figure 4

Block Diagram

Figure 5 shows the block diagram of the SAK-TC1791N-384F200EP.

Data Sheet

V 1.1, 2014-05

TC1791

System Overview of the TC1791Block Diagram

Abbreviations:

FPU

ICACHE:

DCACHE

PSPR:

Instruction Cache

Data Cache

Program Scratch-Pad RAM

Data Scratch-Padl Data RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

SRI Cross Bar (XBar_SRI)

On Chip Bus Slave Interface

On Chip Bus Master Interface

PMI

DMI

LMU

DSPR:

TriCore

CPU

128 KB DSPR

32 KB PSPR

16 KB ICACHE

LDRAM

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

XBAR:

16 KB DCACHE

128 KB

SRAM

DCACHE

M/S

EBU

Cross Bar Interconnect (SRI)

XBAR

M/S

OCDSL1 Debug

Interface/JTAG

PMU0

PMU1

DMA

16 channels

(MemCheck)

Bridge

(SFI)

2 MB PFlash

192 KB DFlash

16 KB BROM

KeyFlash

1 MB PFlash

MLI

M/S

16 KB PRAM

Interrupt

System

SDMA

8 channels

ASC

PCP2

STM

SBCU

Ports

SSC

Core

SSCG

BMU

SSC Guardian

32 KB CMEM

5V (3.3V su

pported as well)

Ext. ADC Su

pply

External

Request Unit

MultiCAN

(4 Nodes, 128 MO)

ADC0

ADC1

ADC2

CCU6

(2xCCU6)

(5V max)

SENT

(8 channels )

FCE

GPT120

SCU

GPTA0

GPTA1

LTCA2

MSC

FM-PLL

(LVDS)

(3.3V max)

PLL E-RAY

FADC

System Peripheral Bus (SPB)

3.3V

Ext. FADC Supply

TC1791

Figure 5

Block Diagram

Data Sheet

V 1.1, 2014-05

TC1791

Pinning

Figure 6 is showing the TC1791 Logic Symbol.

Alternate Functions :

PORST

GPTA/ HWCFG / E-RAY /

GPT12

GPTA/ ERU / SSC1 / SSC3 /

CCU6 / GPT12

TESTMODE

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

General Control

ESR0

ESR1

GPTA/ SSC0 / SSC1

TRST

GPTA / CCU6 / GPT12

GPTA/ SSC2 / CCU6 / GPT12

TCK / DAP0

TDI / BRKIN/

OCDS /

BRKOUT

JTAG Control

ASC0 / ASC1 / MSC0 / LVDS /

MLI0 / MLI1 / CCU6 / GPT12

TDO /BRKOUT/

DAP2 / BRKIN

ASC0 / ASC1 / SSC1 / CAN /

E-RAY / CCU6 / GPT12

TMS / DAP1

ERU / ADC-Mux / SSC3

XTAL1

XTAL2

V_DDOSC

MLI1 / GPTA / SENT /

CCU6 / GPT12

MSC0 / MSC1 / GPTA/

SENT / CCU6 / GPT12

V_DDOSC3

Oscillator

SSC0

Port 10

Port 13

V_SSOSC

TC1791

GPTA

V_DDPF

Port 14

Port 17

GPTA / CCU6 / GPT12

V_DDPF3

SENT

V_DDP

V_DD

(Overlay with Analog Inputs )

Digital Circuitry

Power Supply

V_DDFL3

1) Only available for SAK-TC1791S-512F240EP,

SAK-TC1791F-512F240EP, SAK-TC1791F-

512F240EL, SAK-TC1791S-384F200EP, SAK-

TC1791F-384F200EL, SAK-TC1791F-384F200EP,

and SAK-TC1791F-384F200EL.

V_SS

V_SSP

V_DDSB

(ED only, N.C. in PD)

ADC / FADC

Analog Inputs

AN[47:0]

V_SSAF

V_SSMF

V_AREFx

V_AGND

V_DDM

V_SSM

V_FAGND

V_FAREF

V_DDMF

V_DDAF

FADC Analog

Power Supply

ADC0 /ADC1 / ADC2

Analog Power Supply

N.C.

TC1791_LogSym_292

Figure 6

TC1791 Logic Symbol

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

3.1

TC1791 Pin Configuration

This chapter shows the pin configuration of the TC1791 package PG-LFBGA- 292-6.

VSS

VA AN39 AN37

VSS P14.6 P14.8 VSSP P10.5 P10.0 P10.3 P4.7 P4.3 VSSP

AN30 AN26

AN34 AN1 NC

AN33 AN2 AN3

AN4 AN44

GND0 REF0 P17.11 P17.9

VFA

GND

VA VA AN38 AN36

REF2 REF1 P17.10 P17.8

W VDD VSS P14.4 VDDP P10.4 P10.1 P4.10 P4.6 P4.2 VDDP

V P14.2 VDD

AN29 AN25

VDD VFA

MF REF

AN43 AN41

AN47 AN32

P17.15 P17. 13

U P14.0 P13.15

T P13.14 P13.13

R P13.12 P13.11

P P13.9 P13.8

N P13.5 P13.4

M VDDP VDDP

L VSSP VSSP

K XTAL1 XTAL2

VSS P10.2 P4.14 P4.9 P4.5 P4.1

VDD VSS P4.12 P4.8 P4.4 P4.0

P13.10 VDD

AN28 AN24

AN5 AN45

VDD

AN42 AN40

AN7 AN0

P17.14 P17. 12

AN31 AN27 AN35

AN6 AN46

AN8 AN9

P17.0 P17.1

VDDM VSSM

AN10 AN11

P17.2 P17.3

AN12 AN13

P17.4 P17.5

P13.7 P13.6

P13.3 P13.2

P13.1 P13.0

VDD VSS VSS VSS VSS VDD

VSS VSS VSS VSS

AN14 AN15

P17.6 P17.7

VDD

VSS VSS

VDD

AN16 AN17

AN18 AN19

VSS VSS

AN20 AN21

AN22 AN23

VDDP VSSP

P7.2 P7.1

P1.12 P1.0

P1.6 P1.7

P8.4 P8.0

P8.3 P6.15

P6.11 P6.14

P6.10 P6.13

VDD VDD

PF3 FL3

VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD

PF OSC3

VDD

FL3

P7.5

VSS VDD

TDI TMS

TDO P9.14

VSS VSS

VDD

VSS VSS

VDD

P7.4 P7.3

P7.0 P1.1

P1.9 P8.6

P8.5 P8.7

OSC OSC

TCK TRST

VSS VSS VSS VSS

Test

P9.13

mode

G ESR1 ESR0

F P9.10 PORST

VDD VSS VSS VSS VSS VDD

P9.5 P9.6

P9.7 P9.8

P9.2 P9.1

P9.3 P9.4

P9.0 VSSP P5.5 P3.0 P3.4 P3.12 P0.1 P0.3 P0.5 P0.7 P2.6 P8.1 VSSP P8.2

VSSP P5.7 P5.2 P5.12 P3.10 P0.0 P0.2 P0.4 P0.6 P2.10 P2.5 P2.4 P6.7 VSSP

P5.6 VSSP VDDP P5.9 P5.8 P5.3 P5.13 P5.14 P0.10 P0.13 VDDP P0.9 P2.12 P2.7 P2.3 P6.8 P6.4 VDDP VSSP P6.12

A VSSP VDDP P5.4 P5.11 P5.10 P5.0 P5.1 P5.15 P0.11 P0.12 VSSP P0.14 P2.14 P2.8 P2.2 P6.9 P6.6 P6.5 VDDP NC

Figure 7

TC1791 Pinning for PG-LFBGA-292 Package

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions

Symbol Ctrl. Type Function

Port 0

D12

P0.0

I/O

A1+/ Port 0 General Purpose I/O Line 0

HWCFG0

OUT56

OUT80

P0.1

Hardware Configuration Input 0

I/O

OUT56 Line of GPTA0

OUT56 Line of GPTA1

OUT80 Line of LTCA2

E11

D11

E10

A1/

Port 0 General Purpose I/O Line 1

Hardware Configuration Input 1

OUT57 Line of GPTA0

HWCFG1

OUT57

OUT81

P0.2

I/O

OUT57 Line of GPTA1

OUT81 Line of LTCA2

A2/

Port 0 General Purpose I/O Line 2

Hardware Configuration Input 2

OUT58 Line of GPTA0

HWCFG2

OUT58

OUT82

P0.3

I/O

OUT58 Line of GPTA1

OUT82 Line of LTCA2

A1/

Port 0 General Purpose I/O Line 3

Hardware Configuration Input 3

OUT59 Line of GPTA0

HWCFG3

OUT59

OUT83

OUT59 Line of GPTA1

OUT83 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P0.4

Ctrl. Type Function

D10

I/O

A1/

Port 0 General Purpose I/O Line 4

Hardware Configuration Input 4

OUT60 Line of GPTA0

HWCFG4

OUT60

EVTO0

P0.5

I/O

OUT60 Line of GPTA1

MCDS Output Event 0¹⁾

Port 0 General Purpose I/O Line 5

Hardware Configuration Input 5

OUT61 Line of GPTA0

A1/

HWCFG5

OUT61

EVTO1

P0.6

I/O

OUT61 Line of GPTA1

MCDS Output Event 1¹⁾

Port 0 General Purpose I/O Line 6

Hardware Configuration Input 6

OUT62 Line of GPTA0

A2/

HWCFG6

OUT62

EVTO2

P0.7

I/O

OUT62 Line of GPTA1

MCDS Output Event 2¹⁾

Port 0 General Purpose I/O Line 7

Hardware Configuration Input 7

OUT63 Line of GPTA0

A1/

HWCFG7

OUT63

EVTO3

P0.9

I/O

OUT63 Line of GPTA1

MCDS Output Event 3¹⁾

Port 0 General Purpose I/O Line 9

E-Ray Channel A Receive Data Input 0 ²⁾

A1/

RXDA0

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P0.10

Ctrl. Type Function

B12

I/O

A2/

Port 0 General Purpose I/O Line 10

TXENA

E-Ray Channel A transmit Data Output

enable ²⁾

Reserved

P0.11

I/O

A12

A2/

Port 0 General Purpose I/O Line 11

T5INB

GPT120

GPT121

T5INA

TXENB

E-Ray Channel B transmit Data Output

enable ²⁾

Reserved

P0.12

I/O

A11

A2/

Port 0 General Purpose I/O Line 12

T5EUDA

T5EUDB

TXDB

GPT120

GPT121

I/O

E-Ray Channel B transmit Data Output ²⁾

Reserved

P0.13

B11

A1/

Port 0 General Purpose I/O Line 13

RXDB0

E-Ray Channel B Receive Data Input 0 ²⁾

T5EUDB

T5EUDA

Reserved

GPT120

GPT121

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P0.14

Ctrl. Type Function

I/O

A2/

Port 0 General Purpose I/O Line 14

T6INA

GPT120

T6INB

GPT121

TXDA

E-Ray Channel A transmit Data Output ²⁾

Reserved

Port 1

P1.0

I/O

A2/

Port 1 General Purpose I/O Line 0

REQ0

External trigger Input 0

EXTCLK1

Reserved

P1.1

I/O

External Clock Output 1

A1/

Port 1 General Purpose I/O Line 1

REQ1

External trigger Input 1

CC60INA

CC60INB

CC60

CCU60

CCU61

I/O

CCU60

Reserved

P1.6

A2/

Port 1 General Purpose I/O Line 6

MLI0 transmit Channel valid Output A

SSC1 Slave Select Output Line 10

CCU60

TVALID0A

SLSO10

COUT60

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P1.7

Ctrl. Type Function

I/O

A2/

Port 1 General Purpose I/O Line 7

CCU60

CC61INB

CC61INA

TData0

CC61

CCU61

I/O

MLI0 transmit Channel Data Output

CCU61

T3OUT

P1.9

GPT120

A2/

Port 1 General Purpose I/O Line 9

MLI0 Receive Channel ready Output A

SSC1 Slave Select Output Line 11

OUT65 Line of GPTA0

Port 1 General Purpose I/O Line 12

External Clock Output 0

OUT68 Line of GPTA0

OUT68 Line of GPTA1

RREADY0A O1

SLSO11

OUT65

P1.12

I/O

A2/

EXTCLK0

OUT68

Port 2

P2.2

I/O

A1+/ Port 2 General Purpose I/O Line 2

SLSO02

SLSO12

SSC0 Slave Select Output Line 2

SSC1 Slave Select Output Line 12

SLSO02

AND

SSC0 & SSC1 Slave Select Output Line 2

AND Slave Select Output Line 12

SLSO12

P2.3

I/O

A1+/ Port 2 General Purpose I/O Line 3

SLSO03

SLSO13

SSC0 Slave Select Output Line 3

SSC1 Slave Select Output Line 13

SLSO03

AND

SSC0 & SSC1 Slave Select Output Line 3

AND Slave Select Output Line 13

SLSO13

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P2.4

Ctrl. Type Function

I/O

A1+/ Port 2 General Purpose I/O Line 4

SLSO04

SLSO14

SSC0 Slave Select Output Line 4

SSC1 Slave Select Output Line 14

SLSO04

AND

SSC0 & SSC1 Slave Select Output Line 4

AND Slave Select Output Line 14

SLSO14

P2.5

I/O

A1+/ Port 2 General Purpose I/O Line 5

SLSO05

SLSO15

SSC0 Slave Select Output Line 5

SSC1 Slave Select Output Line 15

SLSO05

AND

SLSO15

SSC0 & SSC1 Slave Select Output Line 5

AND Slave Select Output Line 15

P2.6

I/O

A1+/ Port 2 General Purpose I/O Line 6

SLSO06

SLSO16

SSC0 Slave Select Output Line 6

SSC1 Slave Select Output Line 16

SLSO06

AND

SLSO16

SSC0 & SSC1 Slave Select Output Line 6

AND Slave Select Output Line 16

P2.7

I/O

A1+/ Port 2 General Purpose I/O Line 7

SLSO07

SLSO17

SSC0 Slave Select Output Line 7

SSC1 Slave Select Output Line 17

SLSO07

AND

SSC0 & SSC1 Slave Select Output Line

7AND Slave Select Output Line 17

SLSO17

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P2.8

Ctrl. Type Function

I/O

A1/

Port 2 General Purpose I/O Line 8

IN0 Line of GPTA0

IN0 Line of GPTA1

IN0 Line of LTCA2

CCU62

IN0

CCPOS0A

T12HRB

T3INB

T3INA

OUT0

P2.10

IN2

CCU63

GPT120

GPT121

OUT0 Line of GPTA0

OUT0 Line of GPTA1

OUT0 Line of LTCA2

Port 2 General Purpose I/O Line 10

IN2 Line of GPTA0

IN2 Line of GPTA1

IN2 Line of LTCA2

CCU60

I/O

A1/

IN2

T12HRE

CC61INC

CTRAPA

CTRAPB

CC60INC

OUT2

CCU60

CCU61

CCU63

CCU61

OUT2 Line of GPTA0

OUT2 Line of GPTA1

OUT2 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P2.12

IN4

Ctrl. Type Function

I/O

A1/

Port 2 General Purpose I/O Line 12

IN4 Line of GPTA0

IN4 Line of GPTA1

IN4 Line of LTCA2

CCU62

IN4

T12HRB

CCPOS0A

T2INB

T2INA

OUT4

P2.14

IN6

CCU63

GPT120

GPT121

OUT4 Line of GPTA0

OUT4 Line of GPTA1

OUT4 Line of LTCA2

Port 2 General Purpose I/O Line 14

IN6 Line of GPTA0

IN6 Line of GPTA1

IN6 Line of LTCA2

CCU60

I/O

A1/

IN6

CCPOS0A

T12HRB

T3INA

T3INB

OUT6

CCU61

GPT120

GPT121

OUT6 Line of GPTA0

OUT6 Line of GPTA1

OUT6 Line of LTCA2

Port 3

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P3.0

Ctrl. Type Function

E14

I/O

A1/

Port 3 General Purpose I/O Line 0

IN8 Line of GPTA0

IN8 Line of GPTA1

IN8 Line of LTCA2

CCU62

IN8

CTRAPA

CTRAPB

CC60INC

T12HRE

CC61INC

T5INA

T5INB

OUT8

CCU61

CCU62

CCU63

GPT120

GPT121

OUT8 Line of GPTA0

OUT8 Line of GPTA1

OUT8 Line of LTCA2

Port 3 General Purpose I/O Line 4

IN12 Line of GPTA0

IN12 Line of GPTA1

IN12 Line of LTCA2

CCU62

OUT8

E13

P3.4

I/O

A1/

IN12

T12HRE

CC61INC

CTRAPA

CTRAPB

CC60INC

OUT12

CCU62

CCU63

CCU60

CCU63

OUT12 Line of GPTA0

OUT12 Line of GPTA1

OUT12 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P3.10

Ctrl. Type Function

D13

I/O

A1+/ Port 3 General Purpose I/O Line 10

IN18

IN18 Line of GPTA0

IN18 Line of GPTA1

IN18 Line of LTCA2

CCU62

IN18

CCPOS1A

T13HRB

T3EUDB

T3EUDA

OUT18

P3.12

CCU63

GPT120

GPT121

OUT18 Line of GPTA0

OUT18 Line of GPTA1

OUT18 Line of LTCA2

Port 3 General Purpose I/O Line 12

IN20 Line of GPTA0

IN20 Line of GPTA1

IN20 Line of LTCA2

CCU62

E12

I/O

A1/

IN20

CCPOS2A

T12HRC

T13HRC

T4INB

CCU63

GPT120

T4INA

GPT121

OUT20

OUT20 Line of GPTA0

OUT20 Line of GPTA1

OUT20 Line of LTCA2

Port 4

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.0

Ctrl. Type Function

T12

I/O

A1+/ Port 4 General Purpose I/O Line 0

IN24

IN24 Line of GPTA0

IN24

IN24 Line of GPTA1

IN24

IN24 Line of LTCA2

MRST2A

OUT24

MRST2

P4.1

SSC2 Master Receive Input A (Master Mode)

OUT24 Line of GPTA0

OUT24 Line of GPTA1

SSC2 Slave Transmit Output (Slave Mode)

U12

I/O

A1+/ Port 4 General Purpose I/O Line 1

IN25

IN25 Line of GPTA0

IN25

IN25 Line of GPTA1

IN25

IN25 Line of LTCA2

MTSR2A

MRSTG2A

SSC2 Slave Receive Input A (Slave Mode)

SSC Guardian 2 Master Receive Input A

(Master Mode)³⁾

OUT25

MTSR2

OUT25 Line of GPTA0

OUT25 Line of GPTA1

SSC2 Master Transmit Output (Master

Mode)

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.2

Ctrl. Type Function

W12

I/O

A1+/ Port 4 General Purpose I/O Line 2

IN26

IN26 Line of GPTA0

IN26 Line of GPTA1

IN26 Line of LTCA2

SSC2 Input

IN26

SCLK2

OUT26

SCLK2

P4.3

I/O

OUT26 Line of GPTA0

OUT26 Line of GPTA1

SSC2 Output

Y12

A1+/ Port 4 General Purpose I/O Line 3

IN27

IN27 Line of GPTA0

IN27

IN27 Line of GPTA1

IN27 Line of LTCA2

IN27

OUT27

SLSO20

P4.4

I/O

OUT27 Line of GPTA0

OUT27 Line of GPTA1

SSC2 Output

T13

A1+/ Port 4 General Purpose I/O Line 4

IN28

IN28 Line of GPTA0

IN28

IN28 Line of GPTA1

IN28 Line of LTCA2

OUT28 Line of GPTA0

OUT28 Line of GPTA1

SSC2 Output

IN28

OUT28

SLSO21

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.5

Ctrl. Type Function

U13

I/O

A1+/ Port 4 General Purpose I/O Line 5

IN29

IN29 Line of GPTA0

IN29 Line of GPTA1

IN29 Line of LTCA2

OUT29 Line of GPTA0

OUT29 Line of GPTA1

SSC2 Output

IN29

OUT29

SLSO22

P4.6

I/O

W13

A1+/ Port 4 General Purpose I/O Line 6

IN30

IN30 Line of GPTA0

IN30

IN30 Line of GPTA1

IN30 Line of LTCA2

IN30

OUT30

SLSO23

P4.7

I/O

OUT30 Line of GPTA0

OUT30 Line of GPTA1

SSC2 Output

Y13

A1+/ Port 4 General Purpose I/O Line 7

IN31

IN31 Line of GPTA0

IN31

IN31 Line of GPTA1

IN31Line of LTCA2

GPT120

IN31

T6INB

T6INA

OUT31

SLSO24

GPT121

OUT31 Line of GPTA0

OUT31 Line of GPTA1

SSC2 Output

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.8

Ctrl. Type Function

T14

I/O

A1/

Port 4 General Purpose I/O Line 8

IN32 Line of GPTA0

IN32 Line of GPTA1

CCU60

IN32

CCPOS1A

T13HRB

T3EUDA

T3EUDB

OUT32

OUT0

CCU61

GPT120

GPT121

OUT32 Line of GPTA0

OUT32 Line of GPTA1

OUT0 Line of LTCA2

Port 4 General Purpose I/O Line 9

IN33 Line of GPTA0

IN33 Line of GPTA1

CCU60

AB19 P4.9

IN33

I/O

A1/

IN33

CCPOS2A

T12HRC

T13HRC

T4INA

CCU61

GPT120

T4INB

GPT121

SLSI2

SSC2

OUT33

OUT1

OUT33 Line of GPTA0

OUT33 Line of GPTA1

OUT1 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.10

Ctrl. Type Function

W14

I/O

A1/

Port 4 General Purpose I/O Line 10

IN34 Line of GPTA0

IN34 Line of GPTA1

CCU60

IN34

T12HRB

CCPOS0A

T2INA

CCU61

GPT120

T2INB

GPT121

OUT34

OUT2

I/O

OUT34 Line of GPTA0

OUT34 Line of GPTA1

OUT2 Line of LTCA2

Port 4 General Purpose I/O Line 12

IN36 Line of GPTA0

IN36 Line of GPTA1

CCU60

T15

P4.12

A1/

IN36

T13HRB

CCPOS1A

T2EUDA

T2EUDB

OUT36

OUT4

CCU61

GPT120

GPT121

OUT36 Line of GPTA0

OUT36 Line of GPTA1

OUT4 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P4.14

Ctrl. Type Function

U15

I/O

A1/

Port 4 General Purpose I/O Line 14

IN38 Line of GPTA0

IN38 Line of GPTA1

CCU60

IN38

T12HRC

T13HRC

CCPOS2A

T4EUDA

T4EUDB

OUT38

OUT6

CCU60

CCU61

GPT120

GPT121

OUT38 Line of GPTA0

OUT38 Line of GPTA1

OUT6 Line of LTCA2

Port 5

A15

P5.0

I/O

A1+/ Port 5 General Purpose I/O Line 0

RXD0A

T6EUDA

T6EUDB

RXD0A

OUT72

P5.1

ASC0 Receiver Input/Output A

GPT120

GPT121

I/O

ASC0 Receiver Input/Output A

OUT72 Line of GPTA0

OUT72 Line of GPTA1

A1+/ Port 5 General Purpose I/O Line 1

A14

TXD0

ASC0 Transmitter Output A

OUT73

OUT73 Line of GPTA0

OUT73 Line of GPTA1

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P5.2

Ctrl. Type Function

D15

I/O

A2/

Port 5 General Purpose I/O Line 2

ASC1 Receiver Input/Output A

OUT74 Line of GPTA0

RXD1A

OUT74

P5.3

I/O

OUT74 Line of GPTA1

B15

A18

A1+/ Port 5 General Purpose I/O Line 3

TXD1

ASC1 Transmitter Output A

OUT75

P5.4

OUT75 Line of GPTA0

OUT75 Line of GPTA1

A2/

Port 5 General Purpose I/O Line 4

T13HRB

CCPOS1A

T2EUDB

T2EUDA

EN00

CCU62

CCU63

GPT120

GPT121

MSC0 Device Select Output 0

MLI0 Receive Channel ready Output B

OUT76 Line of GPTA0

RREADY0B O2

OUT76 O3

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P5.5

Ctrl. Type Function

E15

I/O

A1+/ Port 5 General Purpose I/O Line 5

SDI0

MSC0 Serial Data Input

T12HRC

T13HRC

CCPOS2A

T4EUDB

T4EUDA

OUT77

OUT101

P5.6

CCU62

CCU63

GPT120

GPT121

I/O

OUT77 Line of GPTA0

OUT77 Line of GPTA1

OUT101 Line of LTCA2

Port 5 General Purpose I/O Line 6

CCU62

B20

A2/

CC60INA

CC60INB

EN10

CCU63

I/O

MSC1 Device Select Output 0

MLI0 transmit Channel valid Output B

CCU62

TVALID0B

CC60

D16

P5.7

A1+/ Port 5 General Purpose I/O Line 7

SDI1

MSC1 Serial Data Input

CC61INA

CC61INB

OUT79

CC61

CCU62

CCU63

OUT79 Line of GPTA0

OUT79 Line of GPTA1

CCU62

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P5.8

Ctrl. Type Function

B16

I/O

Port 5 General Purpose I/O Line 8

CC62INA

CC62INB

SON0

CCU62

CCU63

MSC0 Differential Driver Serial Data Output

Negative

OUT80

CC62

P5.9

I/O

OUT80 Line of GPTA0

CCU62

B17

A16

A17

D14

Port 5 General Purpose I/O Line 9

SOP0A

MSC0 Differential Driver Serial Data Output

Positive A

OUT81

COUT60

P5.10

I/O

OUT81 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 10

FCLN0

MSC0 Differential Driver Clock Output

Negative

OUT82

COUT61

P5.11

I/O

OUT82 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 11

FCLP0A

MSC0 Differential Driver Clock Output

Positive A

OUT83

COUT62

P5.12

I/O

OUT83 Line of GPTA0

CCU62

Port 5 General Purpose I/O Line 12

SON1

MSC1 Differential Driver Serial Data Output

Negative

OUT84

OUT84 Line of GPTA0

OUT84 Line of GPTA1

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P5.13

Ctrl. Type Function

B14

I/O

Port 5 General Purpose I/O Line 13

SOP1A

MSC1 Differential Driver Serial Data Output

Positive A

OUT85

P5.14

I/O

OUT85 Line of GPTA0

OUT85 Line of GPTA1

B13

A13

Port 5 General Purpose I/O Line 14

FCLN1

MSC1 Differential Driver Clock Output

Negative

OUT86

P5.15

I/O

OUT86 Line of GPTA0

OUT86 Line of GPTA1

Port 5 General Purpose I/O Line 15

FCLNP1A

MSC1 Differential Driver Clock Output

Positive A

OUT87

OUT87 Line of GPTA0

OUT87 Line of GPTA1

Port 6

P6.4

I/O

A1+/ Port 6 General Purpose I/O Line 4

MTSR1

MRSTG1

SSC1 Slave Receive Input (Slave Mode)

SSC Guardian 1 Master Receive Input

(Master Mode)

MTSR1

SSC1 Master Transmit Output (Master

Mode)³⁾

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P6.5

Ctrl. Type Function

I/O

A1+/ Port 6 General Purpose I/O Line 5

MRST1

Reserved

P6.6

SSC1 Master Receive Input (Master Mode)

I/O

SSC1 Slave Transmit Output (Slave Mode)

A1+/ Port 6 General Purpose I/O Line 6

SCLK1

Reserved

P6.7

SSC1 Clock Input/Output

I/O

SSC1 Clock Input/Output

A1+/ Port 6 General Purpose I/O Line 7

SLSI1

SSC1 slave Select Input

T6OFL

Reserved

P6.8

I/O

GPT120

A2/

Port 6 General Purpose I/O Line 8

RXDCAN0

CAN Node 0 Receiver Input 0

CAN Node 3 Receiver Input 1

RXD0B

ASC0 Receiver Input/Output B

CAPINB

CAPINA

Reserved

RXD0B

GPT120

GPT121

ASC0 Receiver Input/Output B

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P6.9

Ctrl. Type Function

I/O

A2/

Port 6 General Purpose I/O Line 9

CAN Node 0 Transmitter Output

ASC0 Transmitter Output B

GPT120

TXDCAN0

TXD0

T60FL

P6.10

A2/

Port 6 General Purpose I/O Line 10

RXDCAN1

CAN Node 1 Receiver Input 0

CAN Node 0 Receiver Input 1

RXD1B

Reserved

RXD1B

TXENA

ASC1 Receiver Input/Output B

E-Ray Channel A transmit Data Output

enable ²⁾

P6.11

I/O

A2/

Port 6 General Purpose I/O Line 11

CAN Node 1 Transmitter Output

ASC1 Transmitter Output B

TXDCAN1

TXD1

TXENB

E-Ray Channel B transmit Data Output

enable ²⁾

P6.12

I/O

A1/

Port 6 General Purpose I/O Line 12

RXDCAN2

CAN Node 2 Receiver Input 0

CAN Node 1 Receiver Input 1

RXDA1

E-Ray Channel A Receive Data Input 1 ²⁾

Reserved

COUT61

CCU60

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P6.13

Ctrl. Type Function

I/O

A2/

Port 6 General Purpose I/O Line 13

CAN Node 2 Transmitter Output

E-Ray Channel A transmit Data Output ²⁾

CCU60

TXDCAN2

TXDA

COUT62

P6.14

A1/

Port 6 General Purpose I/O Line 14

RXDCAN3

CAN Node 3 Receiver Input 0

CAN Node 2 Receiver Input 1

RXDB1

E-Ray Channel B Receive Data Input 1 ²⁾

Reserved

COUT63

P6.15

I/O

CCU60

A2/

Port 6 General Purpose I/O Line 15

CC60INB

CC60INA

TXDCAN3

TXDB

CCU60

CCU61

CAN Node 3 Transmitter Output

E-Ray Channel B transmit Data Output ²⁾

CCU61

CC60

Port 7

P7.0

I/O

A1+/ Port 7 General Purpose I/O Line 0

MRST3

REQ4

SSC3 Master Receive Input (Slave Mode)

External trigger Input 4

AD2EMUX2 O1

ADC2 external multiplexer Control Output 2

SSC3 Slave Transmit Output (Master Mode)

MRST3

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P7.1

Ctrl. Type Function

I/O

A1+/ Port 7 General Purpose I/O Line 1

REQ5

External trigger Input 5

MTSR3

MRSTG3B

SSC3 Slave Receive Input (Slave Mode)

SSC Guardian 3 Master Receive Input B

(Master Mode)

AD0EMUX2 O1

ADC0 external multiplexer Control Output 2

MTSR3

SSC3 Master Transmit Output (Master

Mode)³⁾

Reserved

P7.2

I/O

A1+/ Port 7 General Purpose I/O Line 2

SCLK3

SSC3 Input

AD0EMUX0 O1

ADC0 external multiplexer Control Output 0

SCLK3

Reserved

P7.3

I/O

SSC3 Output

A1+/ Port 7 General Purpose I/O Line 3

AD0EMUX1 O1

ADC0 external multiplexer Control Output 1

SLSO30

Reserved

P7.4

I/O

SSC3 Output

A1+/ Port 7 General Purpose I/O Line 4

REQ6

External trigger Input 6

AD2EMUX0 O1

ADC2 external multiplexer Control Output 0

SLSO31

SSC3 Output

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P7.5

Ctrl. Type Function

I/O

A1+/ Port 7 General Purpose I/O Line 5

REQ7

External trigger Input 7

AD2EMUX1 O1

ADC2 external multiplexer Control Output 1

SLSO32

SSC3 Output

Reserved

Port 8

P8.0

I/O

A2/

Port 8 General Purpose I/O Line 0

IN40 Line of GPTA0

IN40 Line of GPTA1

SENT Digital Input

IN40

SENT0

OUT40

COUT62

TCLK1

P8.1

I/O

OUT40 Line of GPTA0

CCU61

MLI1 transmit Channel Clock Output

Port 8 General Purpose I/O Line 1

IN41 Line of GPTA0

IN41 Line of GPTA1

MLI1 transmit Channel ready Input A

SENT Digital Input

A1/

IN41

TREADY1A

SENT1

CC61INA

CC61INB

OUT41

CC61

CCU60

CCU61

OUT41 Line of GPTA0

CCU60

SENT1

SENT Digital Output

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P8.2

Ctrl. Type Function

I/O

A2/

Port 8 General Purpose I/O Line 2

IN42 Line of GPTA0

IN42 Line of GPTA1

SENT Digital Input

GPT120

IN42

SENT2

CAPINA

CAPINB

COUT63

OUT42

TVALID1A

P8.3

GPT121

I/O

CCU61

OUT42 Line of GPTA1

MLI1 transmit Channel valid Output A

Port 8 General Purpose I/O Line 3

IN43 Line of GPTA0

IN43 Line of GPTA1

SENT Digital Input

CCU60

A2/

IN43

SENT3

CC62INA

CC62INB

OUT43

CC62

CCU61

OUT43 Line of GPTA0

CCU60

TDATA1

MLI1 transmit Channel Data Output A

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P8.4

Ctrl. Type Function

I/O

A1/

Port 8 General Purpose I/O Line 4

IN44 Line of GPTA0

IN44 Line of GPTA1

MLI1 Receive Channel Clock Input A

SENT Digital Input

CCU60

IN44

RCLK1A

SENT4

CC62INB

CC62INA

OUT44

CC62

CCU61

OUT44 Line of GPTA0

CCU61

T3OUT

P8.5

GPT121

I/O

A2/

Port 8 General Purpose I/O Line 5

IN45 Line of GPTA0

IN45 Line of GPTA1

SENT Digital Input

CCU60

IN45

SENT5

CTRAPA

CTRAPB

CC60INC

T12HRE

CC61INC

OUT45

CCU62

CCU60

CCU61

OUT45 Line of GPTA0

OUT45 Line of GPTA1

MLI1 Receive Channel ready Output A

RREADY1A O3

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P8.6

Ctrl. Type Function

I/O

A1/

Port 8 General Purpose I/O Line 6

IN46 Line of GPTA0

IN46 Line of GPTA1

MLI1 Receive Channel valid Input A

SENT Digital Input

IN46

RVALID1A

SENT6

OUT46

COUT60

T6OUT

P8.7

I/O

OUT46 Line of GPTA0

CCU61

GPT120

A1/

Port 8 General Purpose I/O Line 7

IN47 Line of GPTA0

IN47 Line of GPTA1

MLI1 Receive Channel Data Input A

SENT Digital Input

IN47

RDATA1A

SENT7

OUT47

COUT61

T6OUT

OUT47 Line of GPTA0

CCU61

GPT121

Port 9

E17

P9.0

I/O

A2/

Port 9 General Purpose I/O Line 0

IN48 Line of GPTA0

IN48

IN48 Line of GPTA1

COUT63

OUT48

EN12

CCU62

OUT48 Line of GPTA1

MSC1 Device Select Output 2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P9.1

Ctrl. Type Function

D19

I/O

A2/

Port 9 General Purpose I/O Line 1

IN49 Line of GPTA0

IN49 Line of GPTA1

CCU62

IN49

CC60INB

CC60INA

CC60

CCU63

I/O

CCU63

OUT49

EN11

OUT49 Line of GPTA1

MSC1 Device Select Output 1

Port 9 General Purpose I/O Line 2

IN50 Line of GPTA0

IN50 Line of GPTA1

CCU62

D20

P9.2

A2/

IN50

CC61INB

CC61INA

CC61

CCU63

I/O

CCU63

OUT50

SOP1B

P9.3

OUT50 Line of GPTA1

MSC1 serial Data Output

Port 9 General Purpose I/O Line 3

IN51 Line of GPTA0

IN51 Line of GPTA1

CCU62

C20

A2/

IN51

CC62INB

CC62INA

CC62

CCU63

OUT51

FCLP1B

OUT51 Line of GPTA1

MSC1 Clock Output

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P9.4

Ctrl. Type Function

C19

I/O

A2/

Port 9 General Purpose I/O Line 4

IN52 Line of GPTA0

IN52

IN52 Line of GPTA1

COUT60

OUT52

EN03

P9.5

I/O

CCU63

OUT52 Line of GPTA1

MSC0 Device Select Output 3

Port 9 General Purpose I/O Line 5

IN53 Line of GPTA0

F17

A2/

IN53

IN53 Line of GPTA1

SENT1

COUT61

OUT53

EN02

P9.6

SENT Digital Input

I/O

CCU63

OUT53 Line of GPTA1

MSC0 Device Select Output 2

Port 9 General Purpose I/O Line 6

IN54 Line of GPTA0

F16

A2/

IN54

IN54 Line of GPTA1

SENT3

OUT54

SENT3

EN01

SENT Digital Input

OUT54 Line of GPTA0

SENT Digital Output

MSC0 Device Select Output 1

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P9.7

Ctrl. Type Function

E20

I/O

A2/

Port 9 General Purpose I/O Line 7

IN55 Line of GPTA0

IN55 Line of GPTA1

SENT Digital Input

OUT55 Line of GPTA0

SENT Digital Output

MSC0 serial Data Output

Port 9 General Purpose I/O Line 8

SENT Digital Input

CCU63

IN55

SENT4

OUT55

SENT4

SOP0B

P9.8

I/O

E19

F20

A2/

SENT6

COUT62

SENT6

FCLP0B

P9.10

I/O

SENT Digital Output

MSC0 Clock Output

Port 9 General Purpose I/O Line 10

Emergency Stop

SENT Digital Input

CCU63

A1/

EMGSTOP

SENT7

COUT63

SENT7

Reserved

P9.13

I/O

SENT Digital Output

G16

A2/

Port 9 General Purpose I/O Line 13

OCDS Break Input

TTCAN Input

BRKIN

ECTT1

Reserved

BRKOUT

OCDS Break Output

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P9.14

Ctrl. Type Function

H16

I/O

A2/

Port 9 General Purpose I/O Line 14

BRKIN

OCDS Break Input

ECTT2

TTCAN Input

REQ15

External trigger Input 15

Reserved

BRKOUT

OCDS Break Output

Port 10

Y15

P10.0

I/O

A2/

Port 10 General Purpose I/O Line 0

SSC0 Master Receive Input (Master Mode)

SSC0 Slave Transmit Output (Slave Mode)

MRST0

Reserved

P10.1

I/O

W15

A2/

Port 10 General Purpose I/O Line 1

SSC0 Slave Receive Input (Slave Mode)

MTSR0

MRSTG0

SSC Guardian 0 Master Receive Input

(Master Mode)

MTSR0

SSC0 Master Transmit Output (Master

Mode)

Reserved

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P10.2

Ctrl. Type Function

U16

I/O

A1/

Port 10 General Purpose I/O Line 2

SLSI0

SSC0 Slave Select Input

Reserved

P10.3

I/O

Y14

A2/

Port 10 General Purpose I/O Line 3

SCLK0

SSC0 Clock Input/Output

SCLK0

I/O

SSC0 Clock Input/Output

Reserved

P10.4

W16

Y16

A1+/ Port 10 General Purpose I/O Line 4

SLSO0

SSC0 Slave Select Output Line 0

Reserved

P10.5

A1+/ Port 10 General Purpose I/O Line 5

SLSO1

SSC0 Slave Select Output Line 1

Reserved

Port 13

M16

P13.0

I/O

A2/

Port 13 General Purpose I/O Line 0

OUT88 Line of GPTA0

OUT88

OUT80

OUT88 Line of GPTA1

OUT80 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P13.1

Ctrl. Type Function

M17

I/O

A2/

Port 13 General Purpose I/O Line 1

OUT89 Line of GPTA0

OUT89

OUT81

P13.2

OUT89 Line of GPTA1

OUT81 Line of LTCA2

N16

N17

N19

N20

P16

A2/

Port 13 General Purpose I/O Line 2

OUT90 Line of GPTA0

OUT90

OUT82

P13.3

OUT90 Line of GPTA1

OUT82 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 3

OUT91 Line of GPTA0

OUT91

OUT83

P13.4

OUT91 Line of GPTA1

OUT83 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 4

OUT92 Line of GPTA0

OUT92

OUT84

P13.5

OUT92 Line of GPTA1

OUT84 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 5

OUT93 Line of GPTA0

OUT93

OUT85

P13.6

OUT93 Line of GPTA1

OUT85 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 6

OUT94 Line of GPTA0

OUT94

OUT86

OUT94 Line of GPTA1

OUT86 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P13.7

Ctrl. Type Function

P17

I/O

A2/

Port 13 General Purpose I/O Line 7

OUT95 Line of GPTA0

OUT95

OUT87

P13.8

OUT95 Line of GPTA1

OUT87 Line of LTCA2

P19

P20

R17

R19

R20

A2/

Port 13 General Purpose I/O Line 8

OUT96 Line of GPTA0

OUT96

OUT88

P13.9

OUT96 Line of GPTA1

OUT88 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 9

OUT97 Line of GPTA0

OUT97

OUT89

P13.10

OUT98

OUT90

P13.11

OUT99

OUT91

P13.12

OUT100

OUT92

OUT97 Line of GPTA1

OUT89 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 10

OUT98 Line of GPTA0

OUT98 Line of GPTA1

OUT90 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 11

OUT99 Line of GPTA0

OUT99 Line of GPTA1

OUT91 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 12

OUT100 Line of GPTA0

OUT100 Line of GPTA1

OUT92 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P13.13

Ctrl. Type Function

T19

I/O

A2/

Port 13 General Purpose I/O Line 13

OUT101 Line of GPTA0

OUT101

OUT93

P13.14

OUT101 Line of GPTA1

OUT93 Line of LTCA2

T20

U19

A2/

Port 13 General Purpose I/O Line 14

OUT102 Line of GPTA0

OUT102

OUT94

P13.15

OUT102 Line of GPTA1

OUT94 Line of LTCA2

A2/

Port 13 General Purpose I/O Line 15

OUT103 Line of GPTA0

OUT103

OUT95

OUT103 Line of GPTA1

OUT95 Line of LTCA2

Port 14

U20

P14.0

I/O

A2/

Port 14 General Purpose I/O Line 0

CCU60

CC60

OUT96

P14.2

OUT96 Line of GPTA1

OUT96 Line of LTCA2

Port 14 General Purpose I/O Line 2

CCU60

V20

A2/

CC62

OUT98

P14.4

OUT98 Line of GPTA1

OUT98 Line of LTCA2

Port 14 General Purpose I/O Line 4

CCU60

W18

A2/

COUT61

OUT100

OUT100 Line of GPTA1

OUT100 Line of LTCA2

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P14.6

Ctrl. Type Function

Y19

I/O

A2/

Port 14 General Purpose I/O Line 6

CCU60

COUT63

OUT102

P14.8

OUT102 Line of GPTA1

OUT102 Line of LTCA2

Port 14 General Purpose I/O Line 8

CCU61

Y18

A2/

CC61

T3OUT

OUT104

GPT120

OUT104 Line of LTCA2

Port 17

P17.0

SENT0

AN8

D / S Port 17 General Purpose I Line 0⁴⁾

SENT Digital Input 0

Analog Input : ADC0.CH8 ⁵⁾

D / S Port 17 General Purpose I Line 1⁴⁾

SENT Digital Input 1

P17.1

SENT1

AN9

Analog Input : ADC0.CH9 ⁵⁾

D / S Port 17 General Purpose I Line 2⁴⁾

SENT Digital Input 2

P17.2

SENT2

AN10

P17.3

SENT3

AN11

P17.4

SENT4

AN12

Analog Input : ADC0.CH10 ⁵⁾

D / S Port 17 General Purpose I Line 3⁴⁾

SENT Digital Input 3

Analog Input : ADC0.CH11 ⁵⁾

D / S Port 17 General Purpose I Line 4⁴⁾

SENT Digital Input 4

Analog Input : ADC0.CH12 ⁵⁾

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P17.5

Ctrl. Type Function

D / S Port 17 General Purpose I Line 5⁴⁾

SENT5

AN13

SENT Digital Input 5

Analog Input : ADC0.CH13 ⁵⁾

D / S Port 17 General Purpose I Line 6⁴⁾

SENT Digital Input 6

P17.6

SENT6

AN14

Analog Input : ADC0.CH14 ⁵⁾

D / S Port 17 General Purpose I Line 7⁴⁾

SENT Digital Input 7

P17.7

SENT7

AN15

Analog Input : ADC0.CH15 ⁵⁾

D / S Port 17 General Purpose I Line 8⁴⁾

SENT Digital Input 0

P17.8

SENT0

AN36

Analog Input : ADC2.CH4 ⁵⁾

D / S Port 17 General Purpose I Line 9⁴⁾

SENT Digital Input 1

P17.9

SENT1

AN37

Analog Input : ADC2.CH5 ⁵⁾

D / S Port 17 General Purpose I Line 10⁴⁾

SENT Digital Input 2

P17.10

SENT2

AN38

Analog Input : ADC2.CH6 ⁵⁾

D / S Port 17 General Purpose I Line 11⁴⁾

SENT Digital Input 3

P17.11

SENT3

AN39

Analog Input : ADC2.CH7 ⁵⁾

D / S Port 17 General Purpose I Line 12⁴⁾

SENT Digital Input 4

P17.12

SENT4

AN40

Analog Input : ADC2.CH8 ⁵⁾

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

P17.13

SENT5

AN41

Ctrl. Type Function

D / S Port 17 General Purpose I Line 13⁴⁾

SENT Digital Input 5

Analog Input : ADC2.CH9 ⁵⁾

D / S Port 17 General Purpose I Line 14⁴⁾

SENT Digital Input 6

P17.14

SENT6

AN42

Analog Input : ADC2.CH10 ⁵⁾

D / S Port 17 General Purpose I Line 15⁴⁾

SENT Digital Input 7

P17.15

SENT7

AN43

Analog Input : ADC2.CH11 ⁵⁾

Analog Input Port

AN0

Analog Input 0: ADC0.CH0 ⁵⁾

Analog Input 1: ADC0.CH1 ⁵⁾

Analog Input 2: ADC0.CH2 ⁵⁾

Analog Input 3: ADC0.CH3 ⁵⁾

Analog Input 4: ADC0.CH4 ⁵⁾

Analog Input 5: ADC0.CH5 ⁵⁾

Analog Input 6: ADC0.CH6 ⁵⁾

Analog Input 7: ADC0.CH7 ⁵⁾

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

D / S Analog Input 8: ADC0.CH8, SENT0 ⁵⁾

D / S Analog Input 9: ADC0.CH9, SENT1 ⁵⁾

D / S Analog Input 10: ADC0.CH10, SENT2 ⁵⁾

D / S Analog Input 11: ADC0.CH11, SENT3 ⁵⁾

D / S Analog Input 12: ADC0.CH12, SENT4 ⁵⁾

D / S Analog Input 13: ADC0.CH13, SENT5 ⁵⁾

D / S Analog Input 14: ADC0.CH14, SENT6 ⁵⁾

D / S Analog Input 15: ADC0.CH15, SENT7 ⁵⁾

AN9

AN10

AN11

AN12

AN13

AN14

AN15

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Ctrl. Type Function

Symbol

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

Analog Input 16: ADC1.CH0 ⁵⁾

Analog Input 17: ADC1.CH1 ⁵⁾

Analog Input 18: ADC1.CH2 ⁵⁾

Analog Input 19: ADC1.CH3 ⁵⁾

Analog Input 20: ADC1.CH4 ⁵⁾

Analog Input 21: ADC1.CH5 ⁵⁾

Analog Input 22: ADC1.CH6 ⁵⁾

Analog Input 23: ADC1.CH7 ⁵⁾

Analog Input 24: ADC1.CH8,

FADC_FADIN0P ⁶⁾

AN25

AN26

AN27

AN28

AN29

AN30

AN31

Analog Input 25: ADC1.CH9,

FADC_FADIN0N ⁶⁾

Analog Input 26: ADC1.CH10,

FADC_FADIN1P ⁶⁾

Analog Input 27: ADC1.CH11,

FADC_FADIN1N ⁶⁾

Analog Input 28: ADC1.CH12,

FADC_FADIN2P ⁶⁾

Analog Input 29: ADC1.CH13,

FADC_FADIN2N ⁶⁾

Analog Input 30: ADC1.CH14,

FADC_FADIN3P ⁶⁾

T10

Analog Input 31: ADC1.CH15,

FADC_FADIN3N ⁶⁾

AN32

AN33

AN34

AN35

Analog Input 32: ADC2.CH0 ⁵⁾

Analog Input 33: ADC2.CH1 ⁵⁾

Analog Input 34: ADC2.CH2 ⁵⁾

Analog Input 35: ADC2.CH3 ⁵⁾

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Ctrl. Type Function

Symbol

AN36

AN37

AN38

AN39

AN40

AN41

AN42

AN43

AN44

AN45

AN46

AN47

Analog Input 36: ADC2.CH4, SENT0 ⁵⁾

Analog Input 37: ADC2.CH5, SENT1 ⁵⁾

Analog Input 38: ADC2.CH6, SENT2 ⁵⁾

Analog Input 39: ADC2.CH7, SENT3 ⁵⁾

Analog Input 40: ADC2.CH8, SENT4 ⁵⁾

Analog Input 41: ADC2.CH9, SENT5 ⁵⁾

Analog Input 42: ADC2.CH10, SENT6 ⁵⁾

Analog Input 43: ADC2.CH11, SENT7 ⁵⁾

Analog Input 44: ADC2.CH12 ⁵⁾

Analog Input 45: ADC2.CH13 ⁵⁾

Analog Input 46: ADC2.CH14 ⁵⁾

Analog Input 47: ADC2.CH15 ⁵⁾

System I/O

F19

G19

PORST

Power-on Reset Input

ESR0

I/O

External System Request Reset Input 0

Default configuration during and after reset is

open-drain driver. The driver drives low during

power-on reset.

G20

H20

ESR1

I/O

A2/

External System Request Reset Input 1

TCK

JTAG Module Clock Input

DAP0

Device Access Port Line 0

J17

TDI

A2/

JTAG Module Serial Data Input

OCDS Break Input (Alternate Output)

OCDS Break Output (Alternate Input)

Test Mode Select Input

BRKIN

BRKOUT

TESTMODE

G17

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

TMS

Ctrl. Type Function

J16

A2/

JTAG Module State Machine Control Input

Device Access Port Line 1

DAP1

I/O

H19

K20

K19

H17

TRST

XTAL1

XTAL2

TDO

JTAG Module Reset/Enable Input

Main Oscillator/PLL/Clock Generator Input

Main Oscillator/PLL/Clock Generator Output

JTAG Module Serial Data Output

OCDS Break Input (Alternate Input)

OCDS Break Output (Alternate Output)

Device Access Port Line 2

A2/

BRKIN

BRKOUT

DAP2

Power Supply

V_DDM

ADC Analog Part Power Supply (3.3V - 5V)

ADC Analog Part Ground

ADC0 Reference Voltage

V_SSM

V_AREF0

V_AREF1

V_AREF2

V_AGND0

V_AGND1

V_AGND2

V_FAREF

V_FAGND

V_DDMF

V_DDAF

ADC1 Reference Voltage

ADC2 Reference Voltage

ADC0 Reference Ground

ADC1 Reference Ground

ADC2 Reference Ground

U10

W10

U11

T11

FADC Reference Voltage

FADC Reference Ground

FADC Analog Part Power Supply (3.3V)

FADC Analog Part Logic Power Supply

(1.3V)

Y10

V_SSMF

V_SSAF

FADC Analog Part Ground

FADC Analog Part Logic Ground

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Ctrl. Type Function

K5,

V_DDFL3

Flash Power Supply (3.3V)

L16

J20

V_SSOSC

V_SSOSC3

V_DDOSC

V_DDOSC3

V_DDPF

Oscillator Ground (Main & E-Ray)

Main Oscillator Power Supply (1.3V)

Main Oscillator Power Supply (3.3V)

E-Ray PLL Power Supply (1.3V)

E-Ray PLL Power Supply (3.3V)

Digital Core Power Supply (1.3V)

J19

K16

K17

L17

V_DDPF3

V_DD

G8,

G13,

H7,

H14,

N7,

N14,

P8,

P13,

R16,

T17,

V19,

W20

A2,

V_DDP

Port Power Supply (3.3V)

A19,

B3,

B10,

B18,

K2,

M19,

M20,

W11,

W17

L4, L5 V_DDSB

Emulation Stand-by SRAM Power Supply

(1.3V) (Emulation device only)

Note: This pin is N.C. in a productive device.

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Ctrl. Type Function

P9,

V_SS

Digital Ground (center balls)

P10,

P11,

P12,

N9,

N10,

N11,

N12

M7,

V_SS

Digital Ground (center balls cont’d)

M8,

M10,

M11,

M13,

M14,

J7, J8,

J10,

J11,

J13,

J14

L7,L8, V_SS

L9,

L10,

L11,

L12,

Digital Ground (center balls cont’d)

L13,

L14

K7,

V_SS

K8,

K9,

K10,

K11,

K12,

K13,

K14

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Ctrl. Type Function

G9,

V_SS

Digital Ground (center balls cont’d)

G10,

G11,

G12,

H9,

H10,

H11,

H12

T16,

U17,

W19

V_SS

Digital Ground (outer balls)

L19,

L20,

Y17,

Y20

V_SS

A10,

A20,

B2,

V_SS

Digital Ground (outer balls)

B19,

D4,

D17,

E5,

E16,

K1,

Y11

A1, Y1 N.C.

Not connected. These pins are reserved for

future extension and shall not be connected

externally.

1) Only applicable in TC1791ED. Reserved in TC1791PD.

2) Only available for SAK-TC1791S-512F240EP, SAK-TC1791F-512F240EP, SAK-TC1791F-512F240EL, SAK-

TC1791S-384F200EP, SAK-TC1791F-384F200EP, and SAK-TC1791F-384F200EL.

3) The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx

4) Analog Input overlayed with a SENT Digitial Input. The related port logic is used configure the input as either

analog input (default after reset) or digital input. The related port logic supports only the port input features as

the connected pads are input pads only.

5) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.

6) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.

Data Sheet

V 1.1, 2014-05

TC1791

PinningTC1791 Pin Configuration

Legend for Table 2

Column “Ctrl.”:

I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXX_B)

O = Output

O0 = Output with IOCR bit field selection PCx = 1X00_B

O1 = Output with IOCR bit field selection PCx = 1X01_B(ALT1)

O2 = Output with IOCR bit field selection PCx = 1X10_B(ALT2)

O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)

Column “Type”:

A1 = Pad class A1 (LVTTL)

A1+ = Pad class A1+ (LVTTL)

A2 = Pad class A2 (LVTTL)

F = Pad class F (LVDS/CMOS)

D = Pad class D (ADC)

S = Pad class S(SENT)

PU = with pull-up device connected during reset (PORST = 0)

PD = with pull-down device connected during reset (PORST = 0)

TR = tri-state during reset (PORST = 0)

Data Sheet

V 1.1, 2014-05

TC1791

Identification Registers

The Identification Registers uniquely identify the whole device.

Table 3

SAK-TC1791F-512F240EL Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

0700 9502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 4

SAK-TC1791F-512F240EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

8700 9502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 5

SAK-TC1791F-512F200EL Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

1700 9502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 6

SAK-TC1791F-512F200EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

Value

Address

Stepping

0000 6350_H

1018 E083_H

9700 9502_H

F000 0408_H

F000 0464_H

F000 0640_H

Data Sheet

V 1.1, 2014-05

TC1791

Identification Registers

Table 6

SAK-TC1791F-512F200EP Identification Registers (cont’d)

Short Name

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 1820_H

0000 0000_H

F000 0644_H

F000 0648_H

Table 7

SAK-TC1791F-384F200EL Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

1600 9502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 8

SAK-TC1791F-384F200EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

9600 9502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 9

SAK-TC1791S-512F240EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

8700 AA02_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Data Sheet

V 1.1, 2014-05

TC1791

Identification Registers

Table 10

SAK-TC1791S-384F200EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

9600 AA02_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Table 11

SAK-TC1791N-384F200EP Identification Registers

Short Name

CBS_JDPID

CBS_JTAGID

SCU_CHIPID

SCU_MANID

SCU_RTID

Value

Address

Stepping

0000 6350_H

1018 E083_H

9600 B502_H

0000 1820_H

0000 0000_H

F000 0408_H

F000 0464_H

F000 0640_H

F000 0644_H

F000 0648_H

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Electrical Parameters

This specification provides all electrical parameters of the TC1791.

5.1

General Parameters

5.1.1

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1791

and partly its requirements on the system. To aid interpreting the parameters easily

when evaluating them for a design, they are marked with an two-letter abbreviation in

column “Symbol”:

•

Such parameters indicate Controller Characteristics which are a distinctive feature of

the TC1791 and must be regarded for a system design.

•

Such parameters indicate System Requirements which must provided by the

microcontroller system in which the TC1791 designed in.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

5.1.2

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic

characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.

Table 12

Pad Driver and Pad Classes Overview

Class Power Type

Supply

Sub Class Speed Load Leakage Termination

Grade

150^oC ¹⁾

3.3 V

LVTTL A1

6 MHz 100 pF 500 nA

I/O,

(e.g. GPIO)

LVTTL

outputs

A1+

(e.g. serial

I/Os)

MHz

50 pF 1 μA

50 pF 3 μA

Series

termination

recommended

Series

(e.g. serial

I/Os)

MHz

termination

recommended

3.3 V

LVDS

–

Parallel

MHz

termination,

100 Ω ± 10% ²⁾

CMOS

ADC

–

6 MHz 50 pF

–

D_E

5 V

–

3.3 V

LVTTL

(input

only)

1) These values show typical application configurations for the pad. Complete and detailed pad parameters are

available in the individual pad parameter table on the following pages.

2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or

properly terminated with the differential parallel termination of 100 Ω ± 10%.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

5.1.3

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 13

Absolute Maximum Rating Parameters

Symbol Values

Min. Typ. Max.

Parameter

Unit Note /

Test Con

dition

Storage temperature

T_ST

SR -65

–

150

2.0

°C

–

Voltage at 1.3 V power supply V_DDSR –

pins with respect to V_SS

Voltage at 3.3 V power supply V_DDP

pins with respect to V_SSSR

–

4.33

7.0

–

Voltage at 5 V power supply V_DDMSR –

pins with respect to V_SS

Voltage on any Class A input V_IN

pin and dedicated input pins

with respect to V_SS

SR -0.7

V_DDP+ 0.5

Whatever

is lower

or max. 4.33

Voltage on any Class D

analog input pin with respect V_AREFx

to V_AGND

V_AIN

-0.6

–

7.0

–

Voltage on any shared Class V_AINF

D analog input pin with

V_FAREF

respect to V_SSAF, if the FADC

is switched through to the pin.

Input current on any pin

during overload condition

I_IN

-10

-25

–

+10

+25

Absolute maximum sum of all I_IN

input circuit currents for one

port group during overload

condition¹⁾

Absolute maximum sum of all ΣI_IN

input circuit currents during

overload condition

-200 –

200

1) The port groups are defined in Table 18.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

5.1.4

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience

overload currents and voltages that go beyond their own IO power supplies specification.

Table 14 defines overload conditions that will not cause any negative reliability impact if

all the following conditions are met:

•

full operation life-time (24000 h) is not exceeded

Operating Conditions are met for

– pad supply levels (V_DDPor V_DDM

)

– temperature

If a pin current is out of the Operating Conditions but within the overload parameters,

then the parameters functionality of this pin as stated in the Operating Conditions can no

longer be guaranteed. Operation is still possible in most cases but with relaxed

parameters.

Note: An overload condition on one or more pins does not require a reset.

Table 14

Overload Parameters

Symbol

Parameter

Values

Unit Note /

Test Con

dition

Min. Typ. Max.

Input current on any digital pin I_IN

during overload condition

except LVDS pins

-5

–

Input current on LVDS pins

I_INLVDS

I_ING

-3

–

Absolute sum of all input

circuit currents for one port

group during overload

condition¹⁾

-20

+20

Input current on analog pins I_INANA

-3

–

Absolute sum of all analog

input currents for analog

inputs during overload

condition

I_INSA

-45

+45

Absolute sum of all input

circuit currents during

overload condition

ΣI_INS

-100 –

100

1) The port groups are defined in Table 18.

Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 15

PN-Junction Characterisitics for positive Overload

I_IN= 3 mA I_IN= 5 mA

Pad Type

A1 / A1+ / F

U_IN= V_DDP+ 0.6 V

U_IN= V_DDP+ 0.5 V

U_IN= V_DDP+ 0.7 V

U_IN= V_DDM+ 0.6 V

_IN= V_DDP+ 0.7 V

LVDS

_IN= V_DDP+ 0.6 V

Table 16

PN-Junction Characterisitics for negative Overload

I_IN= -3 mA I_IN= -5 mA

Pad Type

A1 / A1+ / F

U_IN= V_SS- 0.6 V

U_IN= V_SS- 0.5 V

U_IN= V_SS- 0.7 V

U_IN= V_SSM- 0.6 V

_IN= V_SS- 0.7 V

LVDS

_IN= V_SS- 0.6 V

Note: A series resistor at the pin to limit the current to the maximum permitted overload

current is sufficient to handle failure situations like short to battery without having

any negative reliability impact on the operational life-time.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

5.1.5

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation and reliability of the TC1791. All parameters specified in the following tables

refer to these operating conditions, unless otherwise noticed.

Digital supply voltages applied to the TC1791 must be static regulated voltages which

allow a typical voltage swing of ± 5 %.

All parameters specified in the following tables (Table 19 and following) refer to these

operating conditions (Table 17), unless otherwise noticed in the Note / Test Condition

column.

The Extended Range Operating Conditions did not increase area of validity of the

parameters defined in table 11 and later.

Table 17

Operating Conditions Parameters

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Overload coupling factor K_OVAN

for analog inputs, negative CC

−

0.0001

I_OV≤ 0 mA;

I_OV≥ -2 mA;

analog

pad= 5.0 V

Overload coupling factor K_OVAP

for analog inputs, positive CC

−

0.0000

I_OV≤ 3 mA;

I_OV≥ 0 mA;

analog

pad= 5.0 V

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 17

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ. Max.

CPU Frequency

_CPUSR

−

240

200

MHz SAK-TC1791F-

512F 240EL;

SAK-TC1791F-

512F 240EP;

SAK-TC1791S-

512F 240EP

−

MHz SAK-TC1791F-

512F 200EL

SAK-TC1791F-

512F 200EP;

SAK-TC1791F-

384F 200EL;

SAK-TC1791F-

384F 200EP;

SAK-TC1791S-

384F 200EP;

SAK-TC1791F-

384N 200EL;

SAK-TC1791F-

384N 200EP

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 17

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Modulated f_CPU

f_{CPU_mod}

_ulatedSR

−

240

MHz SAK-TC1791F-

512F 240EL;

SAK-TC1791F-

512F 240EP;

SAK-TC1791S-

512F 240EP

−

200

MHz SAK-TC1791F-

512F 200EL

SAK-TC1791F-

512F 200EP;

SAK-TC1791F-

384F 200EL;

SAK-TC1791F-

384F 200EP;

SAK-TC1791S-

384F 200EP;

SAK-TC1791F-

384N 200EL;

SAK-TC1791F-

384N 200EP

FPI bus frequency

_FPISR

−

100

MHz

Modulated f_FPI

f_{FPI_modul}

_atedSR

100-

MHz MA = modulatio

n amplitude

2*MA¹⁾

FSI frequency

_FSISR

−

150

MHz

Modulated f_FSI

f_{FSI_modul}

_atedSR

150-

MHz MA = modulatio

n amplitude

2*MA¹⁾

PCP Frequency

_PCPSR

−

200

MHz

Modulated f_PCP

f_{PCP_mod}

_ulatedSR

200-

MHz MA = modulatio

n amplitude

2*MA¹⁾

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 17

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

SRI Frequency

_SRISR

−

240

MHz SAK-TC1791F-

512F 240EL;

SAK-TC1791F-

512F 240EP;

SAK-TC1791S-

512F 240EP

−

200

MHz SAK-TC1791F-

512F 200EL

SAK-TC1791F-

512F 200EP;

SAK-TC1791F-

384F 200EL;

SAK-TC1791F-

384F 200EP;

SAK-TC1791S-

384F 200EP;

SAK-TC1791F-

384N 200EL;

SAK-TC1791F-

384N 200EP

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 17

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Modulated f_SRI

f_{SRI_modul}

_atedSR

−

240

MHz SAK-TC1791F-

512F 240EL;

SAK-TC1791F-

512F 240EP;

SAK-TC1791S-

512F 240EP

−

200

MHz SAK-TC1791F-

512F 200EL

SAK-TC1791F-

512F 200EP;

SAK-TC1791F-

384F 200EL;

SAK-TC1791F-

384F 200EP;

SAK-TC1791S-

384F 200EP;

SAK-TC1791F-

384N 200EL;

SAK-TC1791F-

384N 200EP

Inactive device pin current I_IDSR

-1

−

mA All power

supply voltages

V_DDx= 0

Short circuit current of

digital outputs²⁾

_SCSR -5

−

Absolute sum of short

circuit currents of the

device

ΣI_{SC_D}

−

100

Absolute sum of short

circuit currents per pin

group

ΣI_{SC_PG}

−

Ambient Temperature

Junction temperature

Core Supply Voltage

T_ASR

T_JSR

-40

−

125

°C

−

150

1.43³⁾

_DDSR 1.17

1.3

for duration

limitation see

Section 5.1.5.1

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 17

Operating Conditions Parameters (cont’d)

Parameter

Symbol

Values

Typ.

3.3

Unit Note /

Test Condition

Min.

Max.

3.63⁵⁾

Flash supply voltage 3.3V V_DDFL3

2.97

for duration

limitation see

Section 5.1.5.1

ADC analog supply

voltage

V_DDM

3.135

5.5⁴⁾

Oscillator core supply

voltage

V_DDOSC1.17

1.3

1.43³⁾

for duration

limitation see

Section 5.1.5.1

Oscillator 3.3V supply

voltage

V_DDOSC32.97

3.3

1.3

3.3

−

3.63⁵⁾

3.63 ⁵⁾

1.43³⁾

3.63⁵⁾

−

for duration

limitation see

Section 5.1.5.1

Digital supply voltage for

IO pads

_DDPSR 2.97

for duration

limitation see

Section 5.1.5.1

E-Ray PLL core voltage

supply

V_DDPF

1.17

for duration

limitation see

Section 5.1.5.1

E-Ray PLL 3.3V supply

V_DDPF32.97

for duration

limitation see

Section 5.1.5.1

VDDP voltage to ensure

defined pad states⁶⁾

V_DDPPA0.65

Digital ground voltage

_SSSR

−

Analog ground voltage for

_SSMSR -0.1

0.1

V_DDM

Analog core supply

V_DDAF

1.17

2.97

-0.1

1.3

3.3

1.43³⁾

3.63⁵⁾

0.1

FADC / ADC analog

supply voltage

V_DDMF

Analog ground voltage for V_SSAF

V_DDMFSR

1) MA equals the modulation amplitude in percentage times the configured PLL clock out frequency.

2) Applicable for digital outputs.

3) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

4) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

5) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less

than 100 μs and the cumulated sum of the pulses does not exceed 1 h.

6) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-

up/power-down of V_DDP

5.1.5.1 Extended Range Operating Conditions

The following extended operating conditions are defined:

•

1.3V + 5% < V_DD/ V_DDOSC/ V_DDPF/ V_DDAF< 1.3V + 7.5% (overvoltage condition):

– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction

of the chip caused by the overvoltage stress.

1.3V + 7.5% < V_DD/ V_DDOSC/ V_DDPF/ V_DDAF< 1.3V + 10% (overvoltage condition):

– limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction

of the chip caused by the overvoltage stress.

3.3V + 5% < V_DDP/ V_DDOSC3/ V_DDPF3/ V_DDFL3/ V_DDMF< 3.3V + 10%

(overvoltage condition):

limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction of

the chip caused by the overvoltage stress.

Table 18

Pin Groups for Overload / Short-Circuit Current Sum Parameter

Pins

Group

P2.[4:2], P6.[6:9]

P6.[5:4], P6.[11:10]

P6.[15:12]

P8.[5:0]

P8.[7:6]

P1.7, P1.9

P1.6, P1.12

P1.[1:0], P7.[2:0]

P7.[5:3]

P4.[6:0]

P4.[10:7]

P4.12, P4.14

P10.[5:0]

P14.8

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersGeneral Parameters

Table 18

Group

Pin Groups for Overload / Short-Circuit Current Sum Parameter

Pins

P14.4, P14.6

P13.15, P14.0, P14.2

P13.[14:11]

P13.[10:8]

P13.[7:4]

P13.[3:0]

P9.10, P9.14

P9.7, P9.13

P9.[4:2], P9.6

P9.1, P9.5, P9.8

P9.0

P5.[11:8]

P5.6, P5.[15:12]

P5.0, P5.[5:2], P5.7

P3.0, P3.4, P5.1

P3.10, P3.12

P0.[3:0]

P0.[11:4]

P0.[14:12]

P2:12, P2.14

P2.[10:5]

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

5.2

DC Parameters

5.2.1

Input/Output Pins

Table 19

Standard_Pads Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Pin capacitance (digital

inputs/outputs)

C_IOCC

−

T_A= 25 °C;

f= 1 MHz

Pull-down current

|I_PDL

−

150

μA

V_i≥ 0.6 x V_DDPV

V_i≥ 0.36 x

−

_DDPV

Pull-Up current

|I_PUH

−

μA

V_i≤ 0.6 x V_DDPV

V_i≤ 0.36 x

−

100

_DDPV

Spike filter always blocked t_SF1CC

pulse duration

−

only PORST pin

Spike filter pass-through

pulse duration

_SF2CC 100

−

only PORST pin

Table 20

Standard_Pads Class_A1

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A1

pads ¹⁾

HYSA1 0.1 x

−

V_DDP

Input Leakage Current

Class A1

I_OZA1

-500

−

500

V_i≥ 0 V;

V_i≤ V_DDPV

Ratio Vil/Vih, A1 pads

V_ILA1

V_IHA1

0.6

−

On-Resistance of the

class A1 pad, weak driver CC

R_DSONW

−

450

210

600

340

Ohm I_OH> -0.5 mA;

P_MOS

Ohm I_OL< 0.5 mA;

N_MOS

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 20

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

On-Resistance of the

class A1 pad, medium

driver

R_DSONM

−

155

Ohm I_OH> -2 mA;

P_MOS

−

110

150

Ohm I_OL< 2 mA;

N_MOS

Fall time, pad type A1

_FA1CC

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 20

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Rise time, pad type A1

_RA1CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage class

A1 pads

V_IHA1

0.6 x

V_DDP

min(V

DDP+

0.3,3.6

)

Input low voltage class A1 V_ILA1SR -0.3

−

0.36 x

pads

V_DDP

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 20

Standard_Pads Class_A1 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage high class V_OHA1

A1 pads CC

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= medium

2.4

−

I_OH≥ -2 mA; pin

out

driver= medium

V_DDP

0.4

−

I_OH≥ -400 μA;

pin out

driver= weak

2.4

−

I_OH≥ -500 μA;

pin out

driver= weak

Output voltage low class V_OLA1

A1 pads CC

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 21

Standard_Pads Class_A1+

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A1+

pads ¹⁾

HYSA1 0.1 x

−

+ CC

V_DDP

Input Leakage Current

Class A1+

I_OZA1+

-1000

−

1000

600

On-Resistance of the

class A1+ pad, weak

driver

R_DSONW

−

450

210

Ohm I_OH> -0.5 mA;

P_MOS

340

Ohm I_OL< 0.5 mA;

N_MOS

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 21

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

On-Resistance of the

class A1+ pad, medium

driver

R_DSONM

−

155

Ohm I_OH> -2 mA;

P_MOS

−

110

100

Ohm I_OL< 2 mA;

N_MOS

On-Resistance of the

class A1+ pad, strong

driver

R_DSON1+

Ohm I_OH> -2 mA;

P_MOS

Ohm I_OL< 2 mA;

N_MOS

Fall time, pad type A1+

_FA1+CC −

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= slow ;

pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 21

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

_RA1+CC −

Max.

Rise time, pad type A1+

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= slow ;

pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

140

550

C_L= 150 pF; pin

out

driver= medium

C_L= 150 pF; pin

out

driver= weak

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage, Class V_IHA1+

0.6 x

V_DDP

min(V

DDP+

0.3,3.6

)

A1+ pads

Input low voltage Class

A1+ pads

V_ILA1+

-0.3

0.6

−

0.36 x

V_DDP

Ratio Vil/Vih, A1+ pads

V_ILA1+

V_IHA1+

−

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 21

Standard_Pads Class_A1+ (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage high class V_OHA1+V_DDP

A1+ pads

−

I_OH≥ -1.4 mA;

pin out

driver= medium

0.4

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= strong

2.4

−

I_OH≥ -2 mA; pin

out

driver= medium

−

I_OH≥ -2 mA; pin

out

driver= strong

V_DDP

0.4

−

I_OH≥ -400 μA;

pin out

driver= weak

2.4

−

I_OH≥ -500 μA;

pin out

driver= weak

Output voltage low class V_OLA1+

A1+ pads CC

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

I_OL≤ 2 mA; pin

out

driver= strong

−

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Input Hysteresis for A2

pads ¹⁾

HYSA2 0.1 x

−

V_DDP

Input Leakage current

Class A2

I_OZA2

-6000

−

6000

V_i< V_DDP/ 2 -

1 V; V_i> V_DDP/2

+ 1 V; V_i≥ 0 V;

V_i≤ V_DDPV

-3000

0.6

−

3000

V_i> V_DDP/ 2 -

1 V; V_i< V_DDP/2

+ 1 V

Ratio Vil/Vih, A2 pads

On-Resistance of the

V_ILA2

V_IHA2

−

R_DSONW

−

450

210

−

600

340

155

110

Ohm I_OH> -0.5 mA;

class A2 pad, weak driver CC

P_MOS

Ohm I_OL< 0.5 mA;

N_MOS

On-Resistance of the

class A2 pad, medium

driver

R_DSONM

Ohm I_OH> -2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

On-Resistance of the

class A2 pad, strong driver CC

R_DSON2

−

Ohm I_OH> -2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Fall time, pad type A2

_FA2CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

C_L= 50 pF;

edge= medium

; pin out

driver= strong

3.7

C_L= 50 pF;

edge= medium-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= sharp ;

pin out

driver= strong

C_L= 50 pF;

edge= sharp-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

7.5

C_L= 100 pF;

edge= sharp ;

pin out

driver= strong

−

140

C_L= 150 pF; pin

out

driver= medium

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

−

550

C_L= 150 pF; pin

out

driver= weak

−

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Rise time, pad type A2

_RA2CC

−

150

C_L= 20 pF; pin

out

driver= weak

−

7.0

3.7

C_L= 50 pF;

edge= medium

; pin out

driver= strong

C_L= 50 pF;

edge= medium-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= sharp ;

pin out

driver= strong

C_L= 50 pF;

edge= sharp-

minus ; pin out

driver= strong

C_L= 50 pF;

edge= soft ; pin

out

driver= strong

−

C_L= 50 pF; pin

out

driver= medium

7.5

C_L= 100 pF;

edge= sharp ;

pin out

driver= strong

−

140

C_L= 150 pF; pin

out

driver= medium

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

−

550

C_L= 150 pF; pin

out

driver= weak

−

18000 ns

65000 ns

C_L= 20000 pF;

pin out

driver= medium

C_L= 20000 pF;

pin out

driver= weak

Input high voltage, class

A2 pads

V_IHA2

0.6 x

V_DDP

min(V

DDP+

0.3,

3.6)

Input low voltage Class A2 V_ILA2SR -0.3

pads

−

0.36 x

V_DDP

Output voltage high class V_OHA2

V_DDP

−

I_OH≥ -1.4 mA;

pin out

driver= medium

A2 pads

0.4

V_DDP

0.4

−

I_OH≥ -1.4 mA;

pin out

driver= strong

2.4

I_OH≥ -2 mA; pin

out

driver= medium

I_OH≥ -2 mA; pin

out

driver= strong

V_DDP

0.4

I_OH≥ -400 μA;

pin out

driver= weak

2.4

I_OH≥ -500 μA;

pin out

driver= weak

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 22

Standard_Pads Class_A2 (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Output voltage low class V_OLA2

A2 pads CC

−

0.4

I_OL≤ 2 mA; pin

out

driver= medium

−

0.4

I_OL≤ 2 mA; pin

out

driver= strong

I_OL≤ 500 μA;

pin out

driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 23

Standard_Pads Class_F

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis F¹⁾

HYSF

0.05 x

V_DDP

−

Input Leakage Current

Class F

_OZFCC -6000

−

6000

3000

V_i< V_DDP/ 2 -

1 V; V_i> V_DDP/2

+ 1 V; V_i≥ 0 V;

V_i≤ V_DDPV

-3000

−

V_i> V_DDP/ 2 -

1 V; V_i< V_DDP/2

+ 1 V

Ratio Vil/ Vih, F pads

V_ILF

0.6

−

_IHFCC

On-Resistance of the

class F pad, medium

driver

R_DSONM

170

145

Ohm I_OH> -2 mA;

P_MOS

−

Ohm I_OL< 2 mA;

N_MOS

Fall time, pad type F,

CMOS mode

_FFCC

_RFCC

−

C_L= 50 pF

Rise time, pad type F,

CMOS mode

−

C_L= 50 pF

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 23

Standard_Pads Class_F (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Input high voltage, pad

class F, CMOS mode

_IHFSR 0.6 x

−

min(V

DDP+

0.3,

V_DDP

3.6)

Input low voltage, Class F

pads, CMOS mode

_ILFSR -0.3

−

0.36 x

V_DDP

Output high voltage, class V_OHF

F pads, CMOS mode

V_DDP-

0.4

−

I_OH≥ -1.4 mA

2.4

−

I_OH≥ -2 mA

I_OL≤ 2 mA

Output low voltage, class

F pads, CMOS mode

_OLFCC −

0.4

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Table 24

Standard_Pads Class_I

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis Class I¹⁾HYSI

0.1 x

−

V_DDP

Input Leakage Current

_OZICC -1000

_ILI/ V_IHI0.6

−

1000

Ratio between low and

high input threshold

−

Input high voltage, class I

pins

_IHISR 0.6 x

−

min(V

DDP+

0.3,

V_DDP

3.6)

Input low voltage, Class I

pads

_ILISR -0.3

−

0.36 x

V_DDP

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Class S pad parameters are only valid for V_DDM= 4.75 V to 5.25 V.

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 25

Standard_Pads Class_S

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input Hysteresis for class HYSS

0.3

−

S pads¹⁾

Input leakage current

Input voltage high

Input voltage low

_OZSCC -300

−

300

3.6

−

_IHSCC

−

_ILSCC 1.9

_ILSDelta ²⁾

V_ILSD

-50

mV Maximum input

low state

threshold

variation over

1ms

(V_DDP= consta

nt)

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

2) V_ILSDis implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to

external noise.

Table 26

LVDS_Pads Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

R_OCC 40

Max.

Output impedance, pad

class F, LVDS mode

140

Ohm

Fall time, pad type LVDS

_FLCC

−

termination

100 Ω ± 1 %;

differential

capacitance = 1

0 pF; input

capacitance = 2

0 pF

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 26

LVDS_Pads Parameters (cont’d)

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Rise time, pad type LVDS t_RLCC

−

termination

100 Ω ± 1 %;

differential

capacitance = 1

0 pF; input

capacitance = 2

0 pF

Pad set-up time

t_{SET_LVD}

_SCC

−

μs

termination

100 Ω ± 1 %

Output Differential Voltage V_ODCC 150

400

1525

−

mV termination

100 Ω ± 1 %

Output voltage high, pad

class F, LVDS mode

_OHCC

−

mV termination

100 Ω ± 1 %

Output voltage low, pad

class F, LVDS mode

_OLCC 875

mV termination

100 Ω ± 1 %

Output Offset Voltage

_OSCC 1075

1325

mV termination

100 Ω ± 1 %

Data Sheet

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

5.2.2

Analog to Digital Converters (ADCx)

ADC parameter are valid for V_{DD / DDAF}= 1.235 V to 1.365 V; V_DDM= 4.5 V to 5.5 V.

Table 27

ADC Parameters

Symbol

Parameter

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Switched capacitance at C_AINSW

−

the analog voltage inputs¹⁾CC

Total capacitance of an

analog input

C_AINTOT

−

Switched capacitance at C_AREFSW

the positive reference

voltage input²⁾³⁾

Total capacitance of the

C_AREFTO

−

voltage reference inputs²⁾_TCC

Differential Non-Linearity EA_DNL

-3

−

LSB ADC

Error^4)5)6)7)

resolution= 12-

bit ^{8) 9)}

LSB ADC

Gain Error^4)5)6)7)

EA_GAIN-3.5

−

3.5

resolution= 12-

bit ^{8) 9)}

Integral Non-

Linearity^4)5)6)7)

EA_INL

-3

-4

LSB ADC

resolution= 12-

bit ^{8) 9)}

Offset Error^4)5)6)7)

EA_OFF

LSB ADC

resolution= 12-

bit ^{8) 9)}

Converter clock

_ADCSR

−

100

MHz f_ADC= f_FPI

Internal ADC clock

_ADCICC 1

−

MHz ADC0

MHz ADC1

MHz ADC2

−

20¹⁰⁾

−

Charge consumption per Q_CONV

85¹¹⁾

100

chargeneedsto

conversion

Data Sheet

be provided via

V_AREF0

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 27

ADC Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

_OZ1CC -100

Max.

Input leakage at analog

inputs¹²⁾

500

V_i≤ V_DDMV;

V_i≥ 0.97 x

_DDMV;

overlayed= No

-100

-500

-600

-100

−

600

100

200

V_i≥ 0.97 x

_DDMV;

V_i≤ V_DDMV;

overlayed= Yes

V_i≤ 0.03 x

_DDMV;

V_i≥ 0 V;

overlayed= No

V_i≤ 0.03 x

_DDMV;

V_i≥ 0 V;

overlayed= Yes

V_i> 0.03 x

_DDMV;

V_i< 0.97 x

_DDMV;

overlayed= No

-100

−

300

V_i< 0.97 x

_DDMV;

V_i> 0.03 x

_DDMV;

overlayed= Yes

Input leakage current at

_OZ2CC -1

−

μA

V_AREFx≥ 0 V;

V_AREFx≤ V_DDMV

_AREF0/ V_AREF2

Input leakage current at

V_AREF1

-2

−

μA

V_AREFx≥ 0 V;

V_AREFx≤ V_DDMV

Input leakage current at

_OZ3CC -4

−

μA

V_AGND0≥ 0 V;

V_AGND0

V_AGND0≤ V_DDMV

ON resistance of the

transmission gates in the

analog voltage path

_AINCC

−

900

1500

Ohm

Data Sheet

100

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Table 27

ADC Parameters (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

ON resistance for the ADC R_AIN7T

180

550

900

Ohm

test (pull down for AIN7)

Resistance of the

reference voltage input

path

R_AREF

−

500

1000

Sample time

t_SCC

−

257

T_ADCI

Calibration time after bit

ADC_GLOBCFG.SUCAL

is set

_CALCC

−

4352

cycle

Total Unadjusted

Error^6)5)13)

TUE CC -4

−

4¹⁴⁾

LSB ADC

resolution= 12-

bit

Analog reference ground²⁾V_AGNDxV_SSM

SR 0.05

_AINSR V_AGNDx

Analog reference voltage²⁾V_AREFxV_AGNDx

V_AREFx

- 1

Analog input voltage

−

V_AREFx

_DDM+ V

+ 1

0.05¹⁵⁾

16)

Analog reference voltage V_AREFx

_DDM/2 −

0.05

_DDM+ V

range⁶⁾⁵⁾²⁾

V_AGNDx

1) The sampling capacity of the conversion C-network is pre-charged to V_AREF/2 before the sampling moment.

Because of the parasitic elements the voltage measured at AINx can deviate from V_AREF/2.

2) Applies to AINx, when used as auxiliary reference input.

3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage

at once. Instead smaller capacitances are successively switched to the reference voltage.

4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

5) If a reduced analog reference voltage between 1V and V_DDM/ 2 is used, then there are additional decrease in

the ADC speed and accuracy.

6) If the analog reference voltage range is below V_DDMbut still in the defined range of V_DDM/ 2 and V_DDMis used,

then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),

TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.

7) If the analog reference voltage is > V_DDM, then the ADC converter errors increase.

8) For 10-bit conversions the error value must be multiplied with a factor 0.25.

9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.

10) For f_ADCIbetween 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits. For

STC < 2 INL, DNL , and Offset errors can also increase.

Data Sheet

101

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

11) For a conversion time of 1 µs a rms value of 85µA result for I_AREF0.

12) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The

numerical values defined determine the characteristic points of the given continuous linear approximation -

they do not define step function.

13) Measured without noise.

14) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB

15) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).

16) If the reference voltage V_AREFincrease or the V_DDMdecrease, so that V_AREF= (V_DDM+ 0.05V to V_DDM+ 0.07V),

then the accuracy of the ADC decrease by 4LSB12.

Table 28

Conversion Time (Operating Conditions apply)

Symbol Values

Parameter

Unit Note

Conversion

time with

t_CCC 2 × T_ADC+ (4 + STC + n) × T_ADCIμs

n = 8, 10, 12 for

n - bit conversion

post-calibration

_ADC= 1 / f_FPI

_ADCI= 1 / f_ADCI

Conversion

2 × T_ADC+ (2 + STC + n) × T_ADCI

time without

post-calibration

The power-up calibration of the ADC requires a maximum number of 4352 f_ADCIcycles.

Analog Input Circuitry

R_{AIN, On}

R_EXT

ANx

V_AIN

C_EXT

C_AINSW

_AINTOT- C_AINSW

V_AGNDx

R_AIN7T

Reference Voltage Input Circuitry

R_{AREF, On}

V_AREFx

V_AREF

_AREFTOT- C_AREFSW

C_AREFSW

V_AGNDx

Analog_InpRefDiag

Figure 8

ADCx Input Circuits

Data Sheet

102

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

Ioz1

Single ADC Input

500nA

200nA

100nA

VIN[VDDM%]

-100nA

97%100%

-500nA

Ioz1

Overlayed ADC/FADC Input

600nA

300nA

100nA

VIN[VDDM%]

-100nA

97%100%

-600nA

Figure 9

ADCx Analog Inputs Leakage

Data Sheet

103

V 1.1, 2014-05

TC1791

Electrical ParametersDC Parameters

5.2.3

Fast Analog to Digital Converter (FADC)

FADC parameter are vaild for V_{DD / DDAF}= 1.235 V to 1.365 V; V_DDMF= 2.97 V to 3.6 V.

Table 29

FADC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Input current at VFAREF I_FAREF

−

120

μA

Input leakage current at

VFAREF¹⁾

I_FOZ2

-500

-1

−

500

V_FAREF≤ V_DDMF

V; V_FAREF≥ 0 V

Input leakage current at

VFAGND

I_FOZ3

DNL error

EF_DNL

LSB

V_INmode=

differential;

Gain = 1 or 2

-2

-1

-2

−

LSB

V_INmode=

differential;

Gain = 4 or 8²⁾

_INmode=

single ended;

Gain = 1 or 2

_INmode=

single ended;

Gain = 4 or 8²⁾

GRADient error

EF_GRAD-5

V_INmode=

differential ;

Gain≤ 4

-5

-6

V_INmode=

single ended ;

Gain≤ 4

V_INmode=

differential ;

Gain= 8

V_INmode=

single ended ;

Gain= 8

Data Sheet

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Electrical ParametersDC Parameters

Table 29

FADC Parameters (cont’d)

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

INL error

EF_INL

-4

LSB

_INmode=

differential

_INmode=

single ended

_INmode=

-4

−

Offset error

EF_OFF

-90

differential ;

Calibration= No

-90

-20

−

V_INmode=

single ended ;

Calibration= No

_INmode=

differential ;

Calibration= Ye

s ³⁾⁴⁾

-20

−

V_INmode=

single ended ;

Calibration= Ye

s ³⁾⁴⁾

Error of commen mode

voltage V_FAREF/2

EF_REF

-60

−

Channel amplifier cutoff

frequency

f_COFF

MHz

1 /

Converter clock

f_FADC

100

200

_FADC= f_FPI

Conversion time

t_CCC

−

For 10-bit

f_FADCconversion

Input resistance of the

analog voltage path (Rn, CC

R_FAIN

100

kOh

Rp)

Settling time of a channel

amplifier after changing

ENN or ENP

_SETCC

−

μs

Analog input voltage

range

V_AINF

V_FAGND

V_DDMF

Data Sheet

105

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Electrical ParametersDC Parameters

Table 29

FADC Parameters (cont’d)

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Analog reference ground V_FAGNDV_SSAF

SR 0.05

V_SSAF

+ 0.05

Analog reference voltage V_FAREF2.97

−

3.63⁵⁾

1) This value applies in power-down mode.

2) No missing codes.

3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed

minimium once per week.

4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.

5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum

of the pulses does not exceed 1 h.

6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage

overshoots).

The calibration procedure should run after each power-up, when all power supply

voltages and the reference voltage have stabilized.

Data Sheet

106

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Electrical ParametersDC Parameters

FADC Analog Input Stage

R_N

FAINxN

V_FAREF/2

V_FAGND

R_P

FAINxP

FADC Reference Voltage

Input Circuitry

V_FAREF

I_FAREF

V_FAREF

V_FAGND

FADC_InpRefDiag

Figure 10

FADC Input Circuits

Data Sheet

107

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Electrical ParametersDC Parameters

5.2.4

Oscillator Pins

Table 30

OSC_XTAL Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

_IX1CC -25

Max.

Input current at XTAL1

Input frequency

μA

V_IN<V_DDOSC3

V_IN>0 V

;

_OSCSR

−

MHz Direct Input

Mode selected

MHz ExternalCrystal

Mode selected

Oscillator start-up time¹⁾

t_OSCS

Input high voltage at

XTAL1²⁾

_IHXSR 0.7 x

V_DDOS

0.5

Input low voltage at

XTAL1

_ILXSR -0.5

−

0.3 x

V_DDOS

Input Hysteresis for

XTAL1 pad ³⁾

HYSAX

−

200

t_OSCSis defined from the moment when V_DDOSC3= 3.13V until the oscillations reach an amplitude at XTAL1 of

0.3 * V_DDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative

resistance as recommended and specified by crystral suppliers.

2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * V_DDOSC3is

necessary.

3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be

guaranteed that it suppresses switching due to external system noise.

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters

for the oscillator operation. Please refer to the limits specified by the crystal or

ceramic resonator supplier.

Data Sheet

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Electrical ParametersDC Parameters

5.2.5

Temperature Sensor

Table 31

DTS Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

100

Measurement time

t_MCC

−

μs

Temperature sensor

range

_SRSR -40

150

°C

Sensor Accuracy

(calibrated)

_TSACC -6

−

°C

Start-up time after resets

inactive

_TSSTSR −

μs

The following formula calculates the temperature measured by the DTS in [^oC] from the

RESULT bit field of the DTSSTAT register.

(1)

DTSSTATRESULT – 596

Tj = ------------------------------------------------------------------

2, 03

Data Sheet

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Electrical ParametersDC Parameters

5.2.6

Power Supply Current

The total power supply current defined below consists of leakage and switching

component.

Application relevant values are typically lower than those given in the following

two tables and depend on the customer's system operating conditions (e.g.

thermal connection or used application configurations).

The operating conditions for the parameters in the following table are:

_DD/ V_DDOSC/ V_DDAF/ V_DDPF= 1.365 V, V_DDP/ V_DDOSC/ V_DDMF/ V_DDFL3/ V_DDPF= 3.47 V,

_DDM= 5.25 V _{SRI / CPU}=240 / 200 MHz, _PCP=120 / 200 MHz, _SRI=80 / 100 MHz,

T_J=150 ^oC

The realisic power pattern defines the following conditions:

•

T_J=150 ^oC

_SRI= f_CPU= 240 / 200 MHz

_PCP= 120 / 200 MHz

_FPI= 80 / 100MHz

_DD= V_DDOSC= V_DDAF= V_DDPF= 1.326 V

_DDP= V_DDOSC3= V_DDFL3V_DDPF3= V_DDMF= 3.366 V

_DDM= 5.1 V

The max power pattern defines the following conditions:

•

T_J=150 ^oC

_SRI= f_CPU= 240 / 200 MHz

_PCP= 120 / 200 MHz

_FPI= 80 / 100MHz

_DD= V_DDOSC= V_DDAF= V_DDPF= 1.43 V

_DDP= V_DDOSC3= V_DDFL3

_DDM= 5.5 V

_DDPF3= V_DDMF= 3.63 V

Data Sheet

110

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Electrical ParametersDC Parameters

Table 32

Power Supply Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

789³⁾

Core active mode supply

current¹⁾²⁾

_DDCC

−

mA power

pattern= max;

_CPU=240 MHz

mA power

pattern= realisti

−

591

_CPU=240 MHz

−

735⁴⁾

555

mA power

pattern= max;

_CPU=200 MHz

mA power

pattern= realisti

_CPU=200 MHz

I_DDcurrent at PORST Low I_{DD_PORS}

−

298

249

mA T_J=150 ^oC

mA T_J=140 ^oC

_TCC

E-Ray PLL core supply

current

I_DDPF

Oscillator core supply

current

I_DDOSC

−

Analog core supply

current

I_DDAF

624

Sum of all 1.3 V supply

currents

I_DDSUM

mA power

pattern= realisti

_CPU=240 MHz

−

588

mA power

pattern= realisti

_CPU=200 MHz

E-Ray PLL 3.3V supply

I_DDPF3

−

Oscillator power supply

current, 3.3V

I_DDOSC3

Data Sheet

111

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Electrical ParametersDC Parameters

Table 32

Power Supply Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

FADC analog supply

current, 3.3V

I_DDMF

−

_DDPcurrent at PORST

I_{DDP_POR}

_STCC

−

Low

_DDPcurrent no pad

_DDPCC

I_{DDP_}

mA including flash

read current

activity, LVDS off ⁵⁾

PORST

+ 25

−

I_{DDP_}

mA including flash

programming

current ⁶⁾

PORST

+ 55

I_{DDP_}

mA including flash

erase verify

PORST

+ 40 ⁷⁾

current ⁶⁾

Flash memory current ⁵⁾

I_DDFL3

−

mA flash read

current

mA flash

programming

current ⁶⁾

−

mA flash erase

current ⁶⁾

Current Consumption of

LVDS Pad Pairs

I_LVDS

mA in total for all

LVDS pairs

Sum of all 3.3 V supply

currents, no pad activity, CC

I_DD3SUM

160 ⁸⁾mA including flash

read current

LVDS off

ADC 5V power supply

current

_DDMCC −

−

Data Sheet

112

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Electrical ParametersDC Parameters

Table 32

Power Supply Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

Maximum power

dissipation

PD CC

−

1706

mW power

pattern= max;

_CPU=240 MHz

mW power

pattern= realisti

−

1449

_CPU=240 MHz

−

1523

1403

mW power

pattern= max;

_CPU=200 MHz

mW power

pattern= realisti

_CPU=200 MHz

1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer

application will most probably be lower than this value, but must be evaluated seperately.

2) This current includes the E-Ray module power consumption, including the PCP operation component.

3) The I_DDdecreases typically by 102 mA if the f_CPUdecreases by 50MHz, at constant T_J

4) The I_DDdecreases typically by 105 mA if the f_CPUdecreases by 50MHz, at constant T_J

5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash

operation.

6) Relevant for the power supply dimensioning, not for thermal considerations.

7) In case of erase of Program Flash PFx, internal flash array loading effects may generate transient current

spikes of up to 15 mA for maximum 5 ms per flash module.

8) For power supply dimensioning of V_DDP30 mA have to added for flash programming case.

Note: In general current consumption for operations with data flash are always lower

than the defined values for program flash read operation.

5.2.6.1 Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:

•

Static current consumption

Dynamic current consumption

The static current consumption is related to the device temperature T_Jand the dynamic

current consumption depends of the configured clocking frequencies and the software

Data Sheet

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Electrical ParametersDC Parameters

application executed. These two parts needs to be added in order to get the rail current

consumption.

(2)

0, 02041 × T

--------

= 3, 75

× e

[C]

(3)

--------

0, 01825 × T

= 18, 77

× e

[C]

Function 2 defines the typical static current consumption and Function 3 defines the

maximum static current consumption. Both functions are valid for V_DD= 1.326 V.

For the dynamic current consumption using the real pattern and f_SRI= 2 * f_PCP= 3 * f_FPI

the function 4 applies:

(4)

MHz

------------

= 1, 22

× f

[MHz]

D m

CPU

For the dynamic current consumption using the real pattern and f_SRI= f_PCP= 2 * f_FPIthe

function 5 applies:

(5)

------------

MHz

= 1, 305

× f

[MHz]

D m

CPU

and this finally results in

(6)

= I + I

DYM

Data Sheet

114

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Electrical ParametersAC Parameters

5.3

AC Parameters

All AC parameters are defined with maximum driver strength unless otherwise noted.

5.3.1

Testing Waveforms

V_DDP

90%

10%

V_SS

t_R

t_F

rise_fall

Figure 11

Rise/Fall Time Parameters

V_DDP

V_DDE/ 2

Test Points

V_DDE/ 2

V_SS

mct04881_a.vsd

Figure 12

Testing Waveform, Output Delay

V_Load+ 0.1 V

V_Load- 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_OL- 0.1 V

MCT04880_new

Figure 13

Testing Waveform, Output High Impedance

Data Sheet

115

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Electrical ParametersAC Parameters

5.3.2

Power Sequencing

5.25V

4.75V

3.47V

V_AREF

3.3V

1.3V

3.0V

-12%

1.365V

1.235V

0.5V

-12%

0.5V

V_DDP

PORST

power

down

power

fail

Power-Up 10.vsd

Figure 14

5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

The following list of rules applies to the power-up/down sequence:

•

All ground pins V_SSmust be externally connected to one single star point in the

system. Regarding the DC current component, all ground pins are internally directly

connected.

At any moment in time to avoid increased latch-up risk,

each power supply must be higher then any lower_power_supply - 0.5 V, or:

V_DD5> V_DD3.3- 0.5 V; V_DD5> V_DD1.3- 0.5 V;V_DD3.3> V_DD1.3- 0.5 V, see Figure 14.

– The latch-up risk is minimized if the I/O currents are limited to:

– 20 mA for one pin group

– AND 100 mA for the completed device I/Os

– AND additionally before power-up / after power-down:

1 mA for one pin in inactive mode (0 V on all power supplies)

During power-up and power-down, the voltage difference between the power supply

pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example

•

V_DDP, V_DDFL3...), that are internally connected via diodes, must be lower than 100 mV.

On the other hand, all power supply pins with the same name (for example all V_DDP),

Data Sheet

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Electrical ParametersAC Parameters

are internally directly connected. It is recommended that the power pins of the same

voltage are driven by a single power supply.

1. The PORST signal may be deactivated after all V_DD5, V_DD3.3, V_DD1.3, and V_AREFpower-

supplies and the oscillator have reached stable operation, within the normal

operating conditions.

2. At normal power down the PORST signal should be activated within the normal

operating range, and then the power supplies may be switched off. Care must be

taken that all Flash write or delete sequences have been completed.

3. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V

power supply voltage falls 12% below the nominal level. If, under these conditions,

the PORST is activated during a Flash write, only the memory row that was the target

of the write at the moment of the power loss will contain unreliable content. In order

to ensure clean power-down behavior, the PORST signal should be activated as

close as possible to the normal operating voltage range.

4. In case of a power-loss at any power-supply, all power supplies must be powered-

down, conforming at the same time to the rules number 2 and 4.

5. Although not necessary, it is additionally recommended that all power supplies are

powered-up/down together in a controlled way, as tight to each other as possible.

6. Additionally, regarding the ADC reference voltage V_AREF

– V_AREFmust power-up at the same time or later then V_DDM, and

– V_AREFmust power-down either earlier or at latest to satisfy the condition

V_AREF< V_DDM+ 0.5 V. This is required in order to prevent discharge of V_AREFfilter

capacitance through the ESD diodes through the V_DDMpower supply. In case of

discharging the reference capacitance through the ESD diodes, the current must

be lower than 5 mA.

Data Sheet

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Electrical ParametersAC Parameters

5.3.3

Power, Pad and Reset Timing

Reset Timings Parameters

Table 33

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

1015

1140

2.5

Application Reset Boot

Time¹⁾²⁾

t_BCC

−

μs

_CPU= 240 MHz

_CPU= 200 MHz

Power on Reset Boot

Time³⁾⁴⁾

_BPCC

HWCFG pins hold time

from ESR0 rising edge

_HDHSR 16 /

−

f_FPI

HWCFG pins setup time to t_HDSSR

ESR0 rising edge

−

Ports inactive after ESR0

reset active

_PICC

8/f_FPI

150

−

Ports inactive after

_PIPCC

PORST reset active⁵⁾

Minimum PORST active

time after power supplies

are stable at operating

levels

_POASR 10

TESTMODE / TRST hold

time from PORST rising

edge

_POHSR 100

−

PORST rise time

_PORSR

_POSSR

−

TESTMODE / TRST

setup time to PORST

rising edge

−

Application Reset inactive t_{POR_APP}

−

40 ⁶⁾

μs

after PORST deassertion SR

1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock

cycle when the first user instruction has entered the CPU pipeline and its processing starts.

2) The given time includes the time of the internal reset extension for

SCU_RSTCNTCON.RELSA = 0x05BE.

a configured value of

3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the

first user instruction has entered the CPU pipeline and its processing starts.

4) The given time includes the internal reset extension time for the System and Application Reset which is visible

through ESR0.

Data Sheet

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Electrical ParametersAC Parameters

5) This parameter includes the delay of the analog spike filter in the PORST pad.

6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the

Application Reset is extended.

V_DDP-12%

V_DDPPA

VDDP

VDD

V_DD-12%

t_POA

PORST

t_POH

TRST

TESTMODE

t_hd

ESR0

t_HDH

HWCFG

t_PIP

t _PIP

t_PI

Pads

t_PI

t _PIP

Pad-state undefined

Tri-state or pull device active

As programmed

reset_beh2

Figure 15

Power, Pad and Reset Timing

Data Sheet

119

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Electrical ParametersAC Parameters

5.3.4

Phase Locked Loop (PLL)

Table 34

PLL_SysClk Parameters

Parameter

Symbol

Min.

Values

Typ.

−

Unit Note /

Test Condition

Max.

Accumulated Jitter

Modulation frequency

PLL base frequency

D_PCC -7

_MODSR 50

−

200

320

kHz

MHz

f_PLLBASE50

200

VCO input frequency

VCO frequency range

_REFCC

−

MHz

_VCOCC 400

720

MHz with inactive

modulation

400

−

600

MHz with active

modulation

Modulation jitter

_MODCC −

−

2.5

9.5

Total long term jitter

J_TOTCC

−

Sum of D_Pand

J_MOD

Modulation Amplitude

PLL lock-in time

MA SR

t_LCC

−

2.5

% of f_VCO

N > 32

−

200

400

0.01

μs

N ≤ 32

System frequency

deviation

f_SYSD

with active

modulation

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock f_VCO(and with it the SRI-

Bus clock f_SRI) is constantly adjusted to the selected frequency. The PLL is constantly

adjusting its output frequency to correspond to the input frequency (from crystal or clock

source), resulting in an accumulated jitter that is limited. This means that the relative

deviation for periods of more than one clock cycle is lower than for a single clock cycle.

This is especially important for bus cycles using wait states and for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is negligible.

Data Sheet

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Electrical ParametersAC Parameters

Two formulas are defined for the (absolute) approximate maximum value of jitter D_min

[ns] dependent on the K2 - factor, the SRI clock frequency f_SRIin [MHz], and the number

m of consecutive f_SRIclock periods.

for

(K2 ≤ 100)

and

(m ≤ (f_SRI[MHz]) ⁄ 2)

(7)

(8)

740

(1 – 0, 01 × K2) × (m – 1)

0, 5 × f_SRI[MHz] – 1

⎛

⎞

+ 5 ×

⎠

⎛

⎝

⎞

-----------------------------------------

----------------------------------------------------------------

Dm[ns] =

+ 0, 01 × K2

⎝

⎠

K2 × f_SRI[MHz]

740

-----------------------------------------

+ 5

else

Dm[ns] =

K2 × f_SRI[MHz]

With rising number m of clock cycles the maximum jitter increases linearly up to a value

of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum

accumulated jitter remains at a constant value. Further, a lower SRI-Bus clock frequency

_SRIresults in a higher absolute maximum jitter value.

Note: The specified PLL jitter values are valid if the capacitive load per pin does not

exceed C_L= 20 pF with the maximum driver and sharp edge.

Note: The maximum peak-to-peak noise on the pad supply voltage, measured between

_DDOSC3and V_SSOSC, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

The maximum peak-to peak noise on the pad supply voltage, measured between

_DDOSCand V_SSOSC, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

These conditions can be achieved by appropriate blocking of the supply voltage

as near as possible to the supply pins and using PCB supply and ground planes.

Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The

OSC_WDT checks for too low frequencies and for too high frequencies.

The frequency that is monitored is f_OSCREFwhich is derived for f_OSC

(9)

OSC

----------------------------------

OSCREF

OSCVAL + 1

The divider value SCU_OSCCON.OSCVAL has to be selected in a way that f_OSCREFis

2.5 MHz.

Data Sheet

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Electrical ParametersAC Parameters

Note: f_OSCREFhas to be within the range of 2 MHz to 3 MHz and should be as close as

possible to 2.5 MHz.

The monitored frequency is too low if it is below 1.25 MHz and too high if it is above

7.5 MHz. This leads to the following two conditions:

•

Too low: f_OSC< 1.25 MHz × (SCU_OSCCON.OSCVAL+1)

Too high: f_OSC> 7.5 MHz × (SCU_OSCCON.OSCVAL+1)

Note: The accuracy is 30% for these boundaries.

Frequency Modulation

Frequency modulation defines a slow and predictable variation of the clock speed. The

modulation configuration itself is controlled via register SCU_PLLCON2 where the two

bit fields define the modulation properties.

(10)

OSC MODFREQ × 31, 32

-------------- ----------------------------------------------------

MOD

MODAMP

(11)

MODAMP

N × 161

----------------------------

MA =

Data Sheet

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Electrical ParametersAC Parameters

5.3.5

ERAY Phase Locked Loop (ERAY_PLL)

Table 35

PLL_ERAY Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

_PPCC -0.8

Max.

Accumulated jitter at

SYSCLK pin

0.8

Accumulated_Jitter

D_PCC -0.5

−

0.5

PLL Base Frequency of

the ERAY PLL

f_{PLLBASE_}50

_ERAYCC

250

360

MHz

VCO input frequency of

the ERAY PLL

_REFCC 20

−

MHz

μs

VCO frequency range of f_{VCO_ERA}450

the ERAY PLL

500

200

_YCC

PLL lock-in time

t_LCC

5.6

Note: The specified PLL jitter values are valid if the capacitive load per pin does not

exceed C_L= 20 pF with the maximum driver and sharp edge.

Note: The maximum peak-to-peak noise on the pad supply voltage, measured between

_DDPF3and V_SSPF, is limited to a peak-to-peak voltage of V_PP= 100 mV for noise

frequencies below 300 KHz and V_PP= 40 mV for noise frequencies above

300 KHz.

These conditions can be achieved by appropriate blocking of the supply voltage

as near as possible to the supply pins and using PCB supply and ground planes.

Data Sheet

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Electrical ParametersAC Parameters

5.3.6

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug

interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note: These parameters are not subject to production test but verified by design and/or

characterization.

Table 36

JTAG Interface Timing Parameters

(Operating Conditions apply)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

–

Typ.

Max.

TCK clock period

TCK high time

t₁SR

t₂SR

t₃SR

t₄SR

t₅SR

t₆SR

–

TCK low time

TCK clock rise time

TCK clock fall time

–

TDI/TMS setup

to TCK rising edge

TDI/TMS hold

t₇SR

–

after TCK rising edge

TDO valid after TCK falling t₈CC

–

C_L= 50 pF

C_L= 20 pF

edge¹⁾(propagation delay)

t₈CC

TDO hold after TCK falling t₁₈CC

–

edge¹⁾

TDO high imped. to valid t₉CC

–

C_L= 50 pF

from TCK falling edge¹⁾²⁾

TDO valid to high imped.

from TCK falling edge¹⁾

₁₀CC

13.5

1) The falling edge on TCK is used to generate the TDO timing.

2) The setup time for TDO is given implicitly by the TCK cycle time.

Data Sheet

124

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TC1791

Electrical ParametersAC Parameters

t₁

0.9 V_DDP

0.1 V_DDP

0.5 V_DDP

t₅

t₄

t₂

t₃

MC_JTAG_TCK

Figure 16

Test Clock Timing (TCK)

TCK

t₆

t₇

TMS

t₆

t₇

TDI

t₉

t₈

t₁₀

TDO

t₁₈

MC_JTAG

Figure 17

JTAG Timing

Data Sheet

125

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TC1791

Electrical ParametersAC Parameters

5.3.7

DAP Interface Timing

The following parameters are applicable for communication through the DAP debug

interface.

Note: These parameters are not subject to production test but verified by design and/or

characterization.

Table 37

DAP Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min.

_TCKSR 12.5

Typ.

Max.

DAP0 clock period¹⁾

DAP0 high time

DAP0 low time¹⁾

−

₁₂SR

₁₃SR

₁₄SR

₁₅SR

₁₆SR

DAP0 clock rise time

DAP0 clock fall time

−

DAP1 setup to DAP0

rising edge

6.0

DAP1 hold after DAP0

rising edge

₁₇SR

₁₉CC

6.0

−

DAP1 valid per DAP0

clock period²⁾

C_L= 20 pF;

f= 80 MHz

C_L= 50 pF;

f= 40 MHz

1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.

2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

t₁₁

0.9 V_DDP

0.1 V_DDP

0.5 V_DDP

t₁₅

t₁₄

t₁₂

t₁₃

MC_DAP0

Figure 18

Test Clock Timing (DAP0)

Data Sheet

126

V 1.1, 2014-05

TC1791

Electrical ParametersAC Parameters

DAP0

DAP1

t₁₆

t₁₇

MC_DAP1_RX

Figure 19

DAP Timing Host to Device

t₁₁

DAP1

t₁₉

MC_DAP1_TX

Figure 20

5.3.8

DAP Timing Device to Host

Micro Link Interface (MLI) Timing

Data Sheet

127

V 1.1, 2014-05

TC1791

Electrical ParametersAC Parameters

MLI Transmitter Timing

t₁₃

t₁₄

t₁₀

t₁₂

TCLKx

t₁₁

t₁₅

TDATAx

TVALIDx

t₁₆

t₁₇

TREADYx

MLI Receiver Timing

t₂₃

t₂₄

t₂₀

t₂₂

RCLKx

t₂₁

t₂₅

t₂₆

RDATAx

RVALIDx

t₂₇

RREADYx

MLI_Tmg_2.vsd

Figure 21

MLI Interface Timing

Note: The generation of RREADYx is in the input clock domain of the receiver. The

reception of TREADYx is asynchronous to TCLKx.

The MLI parameters are vaild for C_L= 50 pF and strong driver medium edge.

Data Sheet

128

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TC1791

Electrical ParametersAC Parameters

Table 38

MLI Receiver

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

1 / f_FPI

−

Max.

RCLK clock period

RCLK high time¹⁾²⁾

₂₀SR

₂₁SR

−

0.5 x

t₂₀

RCLK low time¹⁾²⁾

₂₂SR

−

0.5 x

−

t₂₀

RCLK rise time³⁾

RCLK fall time³⁾

₂₃SR

₂₄SR

₂₅SR

−

RDATA/RVALID setup

time before RCLK falling

edge

4.2

RDATA/RVALID hold time t₂₆SR

after RCLK falling edge

2.2

−

RREADY output delay

time

₂₇SR

1) The following formula is valid: t21 + t22 = t20.

2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver

timing parameters.

3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower

input signal rise/fall times can be used for longer RCLK clock periods.

Table 39

MLI Transmitter

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

TCLK clock period

TCLK high time¹⁾²⁾

TCLK low time¹⁾²⁾

TCLK rise time

₁₀CC

₁₁CC

₁₂CC

₁₃CC

₁₄CC

2 x 1 /

f_FPI

−

0.45 x 0.5 x

t₁₀t₁₀

0.45 x 0.5 x

0.55 x ns

t₁₀

0.55 x ns

t₁₀

−

0.3 x

t₁₀

TCLK fall time

−

0.3 x

t₁₀

Data Sheet

129

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TC1791

Electrical ParametersAC Parameters

Table 39

MLI Transmitter (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

-3

Max.

TDATA/TVALID output

delay time

₁₅CC

₁₆SR

₁₇SR

4.4

TREADY setup time

before TCLK rising edge

-2

−

TREADY hold time after

TCLK rising edge

1) The following formula is valid: t11 + t12 = t10.

2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be

regarded additionally to t11 / t12.

3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended

for TCLK.

5.3.9

Micro Second Channel (MSC) Interface Timing

The MSC parameters are vaild for C_L= 50 pF.

Table 40

MSC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

FCLP clock period¹⁾²⁾

₄₀CC

₄₅CC

2 x

T_MSC

−

SOP⁴⁾/ENx outputs delay

from FCLP⁴⁾rising edge

-2

−

ENx with strong

driver and

sharp (minus )

edge

−

ENx with strong

driver and

medium

(minus) edge

−

ENx with strong

driver and soft

edge

SDI bit time

Data Sheet

₄₆CC

8 x

T_MSC

−

130

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TC1791

Electrical ParametersAC Parameters

Table 40

MSC Parameters (cont’d)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

200

SDI rise time

SDI fall time

₄₈SR

₄₉SR

−

200

1) FCLP signal rise/fall times are only defined by the pad rise/fall times.

2) FCLP signal high and low can be minimum 1xT_MSC

3) TMSC = TSYS = 1 / fSYS.

4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.

t₄₀

0.9 V_DDP

0.1 V_DDP

FCLP

t₄₅

SOP

t₄₈

t₄₉

0.9 V_DDP

0.1 V_DDP

SDI

t₄₆

MSC Interface Timing

t₄₆

MSC_Tmg_1.vsd

Figure 22

Note: The data at SOP should be sampled with the falling edge of FCLP in the target

device.

Data Sheet

131

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TC1791

Electrical ParametersAC Parameters

5.3.10

SSC Master/Slave Mode Timing

The SSC parameters are vaild for C_L= 50 pF and strong driver medium edge.

Table 41

SSC Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

SCLK clock period¹⁾²⁾³⁾

₅₀CC

₅₁CC

₅₂SR

₅₃SR

₅₄SR

2 x 1 /

f_FPI

−

MTSR/SLSOx delay form

SCLK rising edge

−

MRST setup to SCLK

latching edge³⁾

16.5

−

MRST hold from SCLK

latching edge³⁾

−

SCLK input clock

period¹⁾³⁾

4 x 1 /

f_FPI

−

SCLK input clock duty

cycle

t₅₅_t₅₄

−

MTSR setup to SCLK

latching edge³⁾⁴⁾

₅₆SR

₅₇SR

₅₈SR

₅₉SR

₆₀CC

₆₁CC

1 / f_FPI

MTSR hold from SCLK

latching edge

1 / f_FPI

+ 5

−

SLSI setup to first SCLK

latching edge

1 / f_FPI

+ 5

−

SLSI hold from last SCLK

latching edge⁵⁾

−

MRST delay from SCLK

shift edge

16.5

SLSI to valid data on

MRST

1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.

2) SCLK signal high and low times can be minimum 1xTSSC.

3) TSSCmin = TSYS = 1/fSYS.

4) Fractional divider switched off, SSC internal baud rate generation used.

Data Sheet

132

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TC1791

Electrical ParametersAC Parameters

5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever

is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair

of shifting / latching edges.

t₅₀

SCLK¹⁾²⁾

t₅₁

MTSR¹⁾

t₅₂

t₅₃

Data

valid

MRST¹⁾

t₅₁

SLSOn²⁾

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.

SSC_TmgMM

Figure 23

SSC Master Mode Timing

Data Sheet

133

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TC1791

Electrical ParametersAC Parameters

t₅₄

First latching

SCLK edge

Last latching

SCLK edge

First shift

SCLK edge

SCLK¹⁾

t₅₅

t₅₆

t₅₇

Data

valid

Data

valid

MTSR¹⁾

MRST¹⁾

SLSI

t₆₀

t₆₁

t₅₉

t₅₈

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM

Figure 24

SSC Slave Mode Timing

Data Sheet

134

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TC1791

Electrical ParametersAC Parameters

5.3.11

ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium

edge settings of the output drivers with C_L= 25 pF.

The ERAY interface is only available for the SAK-TC1791F-512F240EP / SAK-

TC1791F-512F240EL / SAK-TC1791S-512F240EP / SAK-TC1791F-

384F200EL / SAK-TC1791F-384F200EP / SAK-TC1791S-384F200EP.

Table 42

ERAY Parameters

Symbol

Parameter

Values

Typ.

Unit Note /

Test Condition

Min.

Max.

Time span from last BSS

to FES without the

₆₀CC

997.75 −

1002.2 ns

influence of quartz

tolerancies (d10Bit_TX)¹⁾

TxD data valid from

fsample flip flop txd_reg

TxDA, TxDB

t₆₁-t₆₂

−

1.5

Asymmetrical

delay of rising

and falling edge

(TxDA, TxDB)

(dTxAsym)²⁾³⁾

Time span between last

BSS and FES without

influence of quartz

tolerancies

₆₃SR

966

1046.1 ns

(d10Bit_RX)¹⁾⁴⁾⁵⁾

RxD capture by fsample

(RxDA/RxDB sampling

flip-flop) (dRxAsym)⁶⁾

t₆₄-t₆₅

−

3.0

Asymmetrical

delay of rising

and falling edge

(RxDA, RxDB)

TxD data delay from

sampling flip-flop

dTxdly

−

10.0

15.0

10.0

Px_PDR.PDy =

000_B

Px_PDR.PDy =

001_B

RxD capture delay by

sampling flip-flop

dRxdly

1) This includes the PLL_ERAY accumulated jitter.

2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.

Quarz tolerance and PLL_ERAY accumulated jitter are not included.

3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |t_FA2- t_RA2| ≤ 1 ns.

4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * V_DDPFlexRay standard input thresholds. For input

thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.

Data Sheet

135

V 1.1, 2014-05

TC1791

Electrical ParametersFlash Memory Parameters

5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * V_DDPto 80% * V_DDP, according to the

FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming

signal have to satisfy the following inequality: -1.6ns ≤ t_FA2- t_RA2≤ 1.3ns.

6) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * V_DDPto 80% * V_DDP, according to the

FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming

signal have to satisfy the following inequality: -1.6ns ≤ t_FA2- t_RA2≤ 1.3ns.

Last CRC Byte

BSS

FES

(Byte Start Sequence)

(Frame End Sequence)

0.7 V_DD

0.3 V_DD

TXD

t₆₀

t_sample

0.9 V_DD

0.1 V_DD

TXD

t₆₁

t₆₂

Last CRC Byte

BSS

FES

(Byte Start Sequence)

(Frame End Sequence)

0.7 V_DD

0.3 V_DD

RXD

t₆₃

t_sample

0.7 V_DD

0.3 V_DD

RXD

t₆₄

t₆₅

ERAY_TIMING

Figure 25

5.4

ERAY Timing

Flash Memory Parameters

The data retention time of the TC1791’s Flash memory depends on the number of times

the Flash memory has been erased and programmed.

Data Sheet

136

V 1.1, 2014-05

TC1791

Electrical ParametersFlash Memory Parameters

Table 43

FLASH32 Parameters

Symbol

Parameter

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

4.2¹⁾

Data Flash Erase Time

per Sector

_ERDCC

_ERPCC

−

Program Flash Erase

Time per 256 KByte

Sector

−

Program time data flash

per page²⁾

_PRDCC

−

5.3

without

reprogramming

15.9

with two

reprogramming

cycles

Program time program

flash per page³⁾

_PRPCC

−

5.3

without

reprogramming

10.6

with one

reprogramming

cycle

Data Flash Endurance

Erase suspend delay

N_ECC 60000

−

cycle Min. data

retention time 5

years

t_{FL_ErSusp}

−

μs

Wait time after margin

change

t_{FL_Margin}10

_DelCC

Program Flash Retention

Time, Physical Sector⁵⁾⁶⁾

_RETCC 20

_RETLCC 20

_RTUCC 20

−

year Max. 1000

erase/program

cycles

year Max. 100

erase/program

cycles

year Max. 4

Program Flash Retention

Time, Logical Sector⁵⁾⁶⁾

−

UCB Retention Time⁵⁾⁶⁾

−

erase/program

cycles per UCB

Wake-Up time

_WUCC

−

270

μs

Data Sheet

137

V 1.1, 2014-05

TC1791

Electrical ParametersFlash Memory Parameters

Table 43

FLASH32 Parameters (cont’d)

Parameter

Symbol

Values

Typ.

−

Unit Note /

Test Condition

Min.

Max.

DFlash wait state

configuration

WS_DF

50 ns x

f_FSI

−

PFlash wait state

configuration

WS_PF

26 ns x

f_FSI

−

1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can

increase by up to 100%.

2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each

reprogramming takes additional 5 ms.

3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The

reprogramming takes additional 5 ms.

4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.

5) Storage and inactive time included.

6) At average weighted junction temperature T_j= 100°C, or the retention time at average weighted temperature

of T_j= 110°C is minimum 10 years, or the retention time at average weighted temperature of T_j= 150°C is

minimum 0.7 years.

Data Sheet

138

V 1.1, 2014-05

TC1791

Electrical ParametersPackage and Reliability

5.5

Package and Reliability

5.5.1

Package Parameters

Table 44

Device

Thermal Characteristics of the Package

Package

R_ΘJCT

R_ΘJCB

R_ΘJA

Unit

Note

TC1791

PG-LFBGA- 292-6

3,73

4,98

15,0

K/W

1) The top and bottom thermal resistances between the case and the ambient (R_TCAT, R_TCAB) are to be combined

with the thermal resistances between the junction and the case given above (R_TJCT, R_TJCB), in order to calculate

the total thermal resistance between the junction and the ambient (R_TJA). The thermal resistances between

the case and the ambient (R_TCAT, R_TCAB) depend on the external system (PCB, case) characteristics, and are

under user responsibility.

The junction temperature can be calculated using the following equation: T_J= T_A+ R_TJA× P_D, where the R_TJA

is the total thermal resistance between the junction and the ambient. This total junction ambient resistance

R_TJAcan be obtained from the upper four partial thermal resistances.

Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).

Data Sheet

139

V 1.1, 2014-05

TC1791

Electrical ParametersPackage and Reliability

5.5.2

Package Outline

292x

0.5 ±0 .0 5

0.15

0.08

A B

1.7 MAX

0.1 C

17 ±0.1

CODE

292 x

0.15

COPLANARITY

Y W V U T R P N ML

K J HG F E D C B A

INDEX

INDEX MARKING

(LASERED )

0.8

MARKING

19 x 0.8 = 15.2

0.33 MIN

STANDOFF

Figure 26

Package Outlines PG-LFBGA- 292-6

You can find all of our packages, sorts of packing and others in our Infineon Internet

Page “Products”: http://www.infineon.com/products.

5.5.3

Quality Declarations

Table 45

Quality Parameters

Symbol

Parameter

Values

Unit Note / Test Condition

Min. Typ. Max.

Operation

Lifetime¹⁾

t_OP

–

24000 hours –²⁾

ESD susceptibility V_HBM

according to

Human Body

–

2000

500

Conforming to

JESD22-A114-B

Model (HBM)

ESD susceptibility V_HBM1

–

of the LVDS pins

Data Sheet

140

V 1.1, 2014-05

TC1791

Electrical ParametersPackage and Reliability

Table 45

Quality Parameters

Symbol

Parameter

Values

Unit Note / Test Condition

Min. Typ. Max.

ESD susceptibility V_CDM

according to

–

500

Conforming to

JESD22-C101-C

Charged Device

Model (CDM)

Moisture

Sensitivity Level

MSL

–

Conforming to Jedec

J-STD-020C for 240°C

1) This lifetime refers only to the time when the device is powered on.

2)For worst-case temperature profile equivalent to:

1200 hours at T_j= 125...150^oC

3600 hours at T_j= 110...125^oC

7200 hours at T_j= 100...110^oC

11000 hours at T_j= 25...100^oC

1000 hours at T_j= -40...25^oC

Data Sheet

141

V 1.1, 2014-05

TC1791

History

The following changes where done between Version 0.6 and 0.62 of this document:

•

add footnote to port 4.1 alternate output 3 MTSR2

change function description for port 4.1 alternate output 3 MTSR2 from Slave to

Master Transmit

•

add footnote to port 6.4 alternate output 1 MTSR1

add footnote to port 7.1 alternate output 2 MTSR3

change for port 8.3 the symbol from OUT43 (GPTA1) to CC62 (CCU60)

change for port 17 the type from S to D / S

add clarification that table 11 defines the conditions for all other parameters

add conditions for MLI, MSC, SSC, parameters

add parameters dTxdly and dRxdly to ERAY parameters

correct footnotes for ERAY parameters

split flash parameters tPRD and tPRP in two conditions

add conditions to LVDS pad parameters

remove Pin Reliability in Overload section

add parameters IIN and Sum IIN to absolute ratings

add parameter HYSX to PSC_XTAL

added RDSON values for all driver settings (weak, medium, and strong)

removed footnote 2 of table 10

change load for timing of SSC, MSC, and MLI from C_L= 25 pF to C_L= 50 pF (typical)

add to parameters t_RFand t_FFcondition C_L= 50 pF

add new footnote 7) to ADC parameter table

add min and max value for Q_CONVand adapt typ value

add load conditions for t_FF1and t_RF1

add conditions to PLL parameter t_L

change DAP parameter t₁₉from SR to CC classification

remove footnote 2 for the FADC

adapt IDs for AB step

removed footnote 2 in table 11

change max value for ADC parameter t_Sfrom 255 to 257

switch input function ECTT1 and ECTT2

add input function REQ15 to P9.14

add alternate output O1 for OUT97 of GPTA0

changed the name for O3 from EVTO2 to EVTO1 for P0.5

changed the name for O3 from EVTO3 to EVTO2 for P0.6

changed the name for O3 from EVTO4 to EVTO3 for P0.7

add input function SLSI2 for SSC2 to P4.9

The following changes where done between Version 0.62 and 0.63 of this document:

Data Sheet

V 1.1, 2014-05

TC1791

History

•

switch input function ECTT1 and ECTT2

add input function REQ15 to P9.14

add alternate output O1 for OUT97 of GPTA0

changed the name for O3 from EVTO2 to EVTO1 for P0.5

changed the name for O3 from EVTO3 to EVTO2 for P0.6

changed the name for O3 from EVTO4 to EVTO3 for P0.7

add input function SLSI2 for SSC2 to P4.9

change for port 6.15 the symbol from CC61(CCU60) to CC60(CCU61)

change for port 8.2 the symbol from CC61(CCU60) to COUT63(CCU61)

add to all SSC signal the assosiated SSC module where is was missing in the pinning

add section Pin Reliability in Overload

incease values for absolute maximium parameters I_INand SumI_IN

correct P14.8 O2 as this was incorrected label as O1

add to P4.9 output function OUT1 for LTCA2

The following changes where done between Version 0.63 and 0.7 of this document:

•

update value of RTID registers in section Identification Registers for AB step

remove sentence ‘Exposure to conditions within the maximum ratings will not affect

device reliability. To replace this sentence section Pin Reliability in Overload was

added.

•

add footnote 1 to table 12 (Operating Conditions)

increase values for absolute maximum parameters I_INand SumI_IN

remove capacitance conditions for LVDS pad parameters as loads are defined by

interface (MSC) timings

•

add parameter V_ILSDfor class S pads

add V_DDMsupply limitation for class S parameters

add footnote 10 to table 23 (ADC parameters)

remove old footnote 2 from table 24 (FADC parameters)

remove term typical from load of Peripheral Timings

add definition of driver strength settings for ERAY Interface Timing

update formulas for frequency modulation

change SSC parameter from t₅₉CC to SR

change footnote 4 wording for ERAY timing back to TC1797 wording

increase flash parameters t_PRDand t_PRPvalues

increase flash parameter t_ERD

add section 5.2.6.1.

change in legende of table 2 definition of class S pad

correct section Extended Range Operating Conditions for the 3.3 V area

increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours

specify wording for limitation of pad performance in section Extended Range

Operating Conditions

•

remove incorrect test conditions for RDSONx parameters

adjust typo in temperature profile

Data Sheet

V 1.1, 2014-05

TC1791

History

•

removed RDSON parameters for class F pads weak driver as only medium is

available

•

add parameter f_SYSDfor the SYSPLL

update all current values of table 28 (Power Supply Parameters)

rework the 3.3 V current part of the Power Supply Parameters for better description

and usage

– Parameters I_{DDP_FP}, I_DDFL3Eand I_DDFL3Rare removed and replaced in the following

way

– I_{DDP_FP}is replaced by I_DDPwith the condition including flash programming current

– I_DDFL3Eis replaced by I_DDPwith the condition including flash erase verify current

– I_DDFL3Ris replaced by I_DDPwith the condition including flash read current

– parameter I_DDFL3Rwas renamed to I_DDFL3

The rework of the 3.3 V current part of the Power Supply Parameters was done for

simplification and clarification. Former given values could still be used if liked, the new

definition results in the same resulting values or slightly better values. The flash module

is supplied via I_DDFL3and I_DDP. For the different flash operating modes in worst case

different allocations for the two domains resulting.

The application typical case ‘flash read’ has max I_DDPof 25 mA and max I_DDFL3of 98 mA

resulting is a sum of 123 mA.

The case ‘flash programming’ has max I_DDPof 55 mA and max I_DDFL3of 29 mA resulting

is a sum of 84 mA.

The case ‘flash erase verify’ has max I_DDPof 40 mA and max I_DDFL3of 98 mA resulting

is a sum of 138 mA.

So for the old parameter I_DDPwith 35 mA, the new version reads as

_DDP= 25+I_{DDP_PORST}= 32 mA for the same application relevant case.

The following changes where done between Version 0.7 and 1.0 of this document:

•

add product options SAK-TC1791S-512F240EP, SAK-TC1791S-384F200EP, and

SAK-TC1791N-384F200EP

•

update block diagrams to cover new options

add note to TC1791 Logic Symbol figure and pin list for E-RAY pins availability

add identification registers for new options

adapt Absolute Maximum Rating

clarify pad supply levels in Pin Reliability in Overload section

correct errors for analog inputs in tables 12 and 13

add note at the end of Pin Reliability in Overload section

clarify wording for valid operating conditions

add negative limit for class S pad leakage

change description of parameter t_CALfor the ADC

update footnote 10 for the ADC

split FADC DNL parameter into two conditions and change value for gain 4 and 8

add footnote 5 to I_DDP

Data Sheet

V 1.1, 2014-05

TC1791

History

•

improve parameters I_DDFL3

add footnote for D-Flash currents in power section

rework first sentence for chapter 5.3

increase max values for parameter t_B

reduce min value for t_Lfor both PLLs

split f_VCOfor the system PLL into two conditions

change formula 10

add for MLI and SSC timing parameter: valid strong driver medium edge only

change MLI parameter t₁₇min value

update parameter description for SSC parameters t₅₂, t₅₃, t₅₆, t₅₇, t₅₈, and t₅₉

change SSC parameters from CC to SR Symbol for t₅₆, t₅₇, t₅₈and t₅₉

add note to ERAY parameters for availability

add footnote to Flash parameter t_ERD

change for parameter N_Enote from Max. data retention to Min.

The following changes where done between Version 1.0 and 1.1 of this document:

•

remove the following product options:

– SAK-TC1791N-384F200EL

•

change V_ILSfrom 2.1V to 1.9V in table 25

change t₄₈from 100ns to 200ns in table 40

change t₄₉from 100ns to 200ns in table 40

extend K_OVANconditon from I_OV≤ 0 mA; I_OV≥ -1 mA to I_OV≤ 0 mA; I_OV≥ -2 mA

change package version from PG-LFBGA-292-3 to PG-LFBGA-292-6

Data Sheet

V 1.1, 2014-05

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

SAK-TC1791F-512F240EP AB [INFINEON]

相关型号：

SAK-TC1793F-512F200EB

SAK-TC1793F-512F200EF

SAK-TC1793F-512F270EF

SAK-TC1793N-512F270EF

SAK-TC1793S-512F270EF

SAK-TC1796-256F150E

SAK-TC1796-256F150E BE

SAK-TC1796-256F150EBC

SAK-TC1796-256F150EBD

SAK-TC1796-256F150EBE

SAK-TC1796-256F150EBE

SAK-TC1796-256F150EBEPB