SAK-TC1791F-512F240EP AB [INFINEON]

TC1791 是 AUDO MAX 系列三种优质衍生产品之一。;
SAK-TC1791F-512F240EP AB
型号: SAK-TC1791F-512F240EP AB
厂家: Infineon    Infineon
描述:

TC1791 是 AUDO MAX 系列三种优质衍生产品之一。

文件: 总153页 (文件大小:4075K)
中文:  中文翻译
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32-Bit  
Microcontroller  
TC1791  
32-Bit Single-Chip Microcontroller  
Data Sheet  
V 1.1 2014-05  
Microcontrollers  
Edition 2014-05  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© 2014 Infineon Technologies AG  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions or  
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any  
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties  
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights  
of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact the nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances. For information on the types in  
question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
32-Bit  
Microcontroller  
TC1791  
32-Bit Single-Chip Microcontroller  
Data Sheet  
V 1.1 2014-05  
Microcontrollers  
TC1791  
Table of Contents  
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
2
System Overview of the TC1791 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13  
2.1  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14  
3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19  
3.1  
TC1791 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20  
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67  
5
5.1  
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70  
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70  
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70  
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-71  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72  
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75  
Extended Range Operating Conditions . . . . . . . . . . . . . . . . . . . . . 5-81  
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83  
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83  
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-99  
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . 5-104  
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108  
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109  
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110  
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . 5-113  
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115  
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115  
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116  
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-118  
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120  
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . 5-123  
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-124  
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-126  
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127  
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 5-130  
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132  
ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135  
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136  
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139  
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139  
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.1.5  
5.1.5.1  
5.2  
5.2.1  
5.2.2  
5.2.3  
5.2.4  
5.2.5  
5.2.6  
5.2.6.1  
5.3  
5.3.1  
5.3.2  
5.3.3  
5.3.4  
5.3.5  
5.3.6  
5.3.7  
5.3.8  
5.3.9  
5.3.10  
5.3.11  
5.4  
5.5  
5.5.1  
5.5.2  
Data Sheet  
I-1  
V 1.1, 2014-05  
TC1791  
5.5.3  
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140  
6
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1  
Data Sheet  
I-2  
V 1.1, 2014-05  
TC1791  
Data Sheet  
3
V 1.1, 2014-05  
TC1791  
Data Sheet  
4
V 1.1, 2014-05  
TC1791  
Summary of Features  
1
Summary of Features  
The SAK-TC1791F-512F240EL / SAK-TC1791F-512F240EP has the following  
features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 240 MHz operation at full temperature range  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 4 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
Data Sheet  
1
V 1.1, 2014-05  
TC1791  
Summary of Features  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– One FlexRayTM module with 2 channels (E-Ray).  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
48 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
The SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP has the following  
features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 200 MHz operation at full temperature range  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
Data Sheet  
2
V 1.1, 2014-05  
TC1791  
Summary of Features  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 4 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– One FlexRayTM module with 2 channels (E-Ray).  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
44 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
Data Sheet  
3
V 1.1, 2014-05  
TC1791  
Summary of Features  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
The SAK-TC1791F-384F200EL / SAK-TC1791F-384F200EP has the following  
features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 200 MHz operation at full temperature range  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 3 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Data Sheet  
4
V 1.1, 2014-05  
TC1791  
Summary of Features  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– One FlexRayTM module with 2 channels (E-Ray).  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
44 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Data Sheet  
5
V 1.1, 2014-05  
TC1791  
Summary of Features  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
The SAK-TC1791S-512F240EP has the following features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 240 MHz operation at full temperature range  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 4 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
Data Sheet  
6
V 1.1, 2014-05  
TC1791  
Summary of Features  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– One FlexRayTM module with 2 channels (E-Ray).  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
48 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
Secure Hardware Extension (SHE)  
– For further information please contact your Infineon representative  
The SAK-TC1791S-384F200EP has the following features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 200 MHz operation at full temperature range  
Data Sheet  
7
V 1.1, 2014-05  
TC1791  
Summary of Features  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 3 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– One FlexRayTM module with 2 channels (E-Ray).  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
44 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
Data Sheet  
8
V 1.1, 2014-05  
TC1791  
Summary of Features  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
Secure Hardware Extension (SHE)  
– For further information please contact your Infineon representative  
The SAK-TC1791N-384F200EP has the following features:  
High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline  
– Superior real-time performance  
– Strong bit handling  
– Fully integrated DSP capabilities  
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
– Fully pipelined Floating point unit (FPU)  
– 200 MHz operation at full temperature range  
32-bit Peripheral Control Processor with single cycle instruction (PCP2)  
– 16 Kbyte Parameter Memory (PRAM)  
– 32 Kbyte Code Memory (CMEM)  
– 200 MHz operation at full temperature range  
Multiple on-chip memories  
– 3 Mbyte Program Flash Memory (PFLASH) with ECC  
– 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation  
– 2 x 8 Kbyte Key Flash  
– 128 Kbyte Data Scratch-Pad RAM (DSPR)  
– 16 Kbyte Instruction Cache (ICACHE)  
– 32 Kbyte Instruction Scratch-Pad RAM (PSPR)  
– 16 Kbyte Data Cache (DACHE)  
– 128 Kbyte Memory (SRAM)  
Data Sheet  
9
V 1.1, 2014-05  
TC1791  
Summary of Features  
– 16 Kbyte BootROM (BROM)  
16-Channel DMA Controller  
8-Channel Safe DMA (SDMA) Controller  
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels  
serviced by CPU or PCP2  
High performing on-chip bus structure  
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory  
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
– One bus bridge (SFI Bridge)  
Versatile On-chip Peripheral Units  
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,  
parity, framing and overrun error detection  
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data  
length and shift direction  
– Four SSC Guardian (SSCG) modules, one for each SSC  
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external  
power devices  
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor  
communication  
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message  
objects for high efficiency data handling via FIFO buffering and gateway data  
transfer (one CAN node supports TTCAN functionality)  
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer  
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer  
functionality to realize autonomous and complex Input/Output management  
– Two Capture / Compare 6 modules  
– Two General Purpose 12 Timer Units (GPT120 and GPT121)  
44 analog input lines for ADC  
– 4 independent kernels (ADC0, ADC1, and ADC2)  
– Analog supply voltage range from 3.3 V to 5 V (single supply)  
4 different FADC input channels  
– channels with impedance control and overlaid with ADC1 inputs  
– Extreme fast conversion, 21 cycles of fFADC clock  
– 10-bit A/D conversion (higher resolution can be achieved by averaging of  
consecutive conversions in digital data reduction filter)  
8 digital input lines for SENT  
– communication according to the SENT specification J2716 FEB2008  
128 digital general purpose I/O lines (GPIO)  
Digital I/O ports with 3.3 V capability  
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)  
Dedicated Emulation Device chip available (TC1791ED)  
– multi-core debugging, real time tracing, and calibration  
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface  
Data Sheet  
10  
V 1.1, 2014-05  
TC1791  
Summary of Features  
Power Management System  
Clock Generation Unit with PLL and PLL_ERAY  
Flexible CRC Engine (FCE)  
– IEEE 802.3 CRC32 ethernet polynomial: 0x82608EDB (CRC kernel 0)  
– CRC32C Castagnoli: 0xD419CC15 (CRC kernel 1)  
Data Sheet  
11  
V 1.1, 2014-05  
TC1791  
Summary of Features  
Ordering Information  
The ordering code for Infineon microcontrollers provides an exact reference to the  
required product. This ordering code identifies:  
The derivative itself, i.e. its function set, the temperature range, and the supply  
voltage  
The package and the type of delivery.  
For the available ordering codes for the TC1791 please refer to the “Product Catalog  
Microcontrollers”, which summarizes all available microcontroller variants.  
This document describes the derivatives of the device.The Table 1 enumerates these  
derivatives and summarizes the differences.  
Table 1  
TC1791 Derivative Synopsis  
Derivative  
Ambient Temperature Range  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
TA = -40oC to +125oC  
SAK-TC1791F-512F240EL  
SAK-TC1791F-512F240EP  
SAK-TC1791F-512F200EL  
SAK-TC1791F-512F200EP  
SAK-TC1791F-384F200EL  
SAK-TC1791F-384F200EP  
SAK-TC1791S-512F240EP  
SAK-TC1791S-384F200EP  
SAK-TC1791N-384F200EP  
Data Sheet  
12  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791  
2
System Overview of the TC1791  
The TC1791 combines three powerful technologies within one silicon die, achieving new  
levels of power, speed, and economy for embedded applications:  
Reduced Instruction Set Computing (RISC) processor architecture  
Digital Signal Processing (DSP) operations and addressing modes  
On-chip memories and peripherals  
DSP operations and addressing modes provide the computational power necessary to  
efficiently analyze complex real-world signals. The RISC load/store architecture  
provides high computational bandwidth with low system cost. On-chip memory and  
peripherals are designed to support even the most demanding high-bandwidth real-time  
embedded control-systems tasks.  
Additional high-level features of the TC1791 include:  
Efficient memory organization: instruction and data scratch memories, caches  
Serial communication interfaces – flexible synchronous and asynchronous modes  
Peripheral Control Processor – standalone data operations and interrupt servicing  
DMA Controller – DMA operations and interrupt servicing  
General-purpose timers  
High-performance on-chip buses  
On-chip debugging and emulation facilities  
Flexible interconnections to external components  
Flexible power-management  
The TC1791 is a high-performance microcontroller with TriCore CPU, program and data  
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor  
and a DMA controller and several on-chip peripherals. The TC1791 is designed to meet  
the needs of the most demanding embedded control systems applications where the  
competing issues of price/performance, real-time responsiveness, computational power,  
data bandwidth, and power consumption are key design elements.  
The TC1791 offers several versatile on-chip peripheral units such as serial controllers,  
timer units, and Analog-to-Digital converters. Within the TC1791, all these peripheral  
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect  
(FPI) Bus and the Cross Bar Interconnect (SRI). Several I/O lines on the TC1791 ports  
are reserved for these peripheral units to communicate with the external world.  
Data Sheet  
13  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791Block Diagram  
2.1  
Block Diagram  
Figure 1 shows the block diagram of the SAK-TC1791F-512F240EL / SAK-TC1791F-  
512F240EP / SAK-TC1791F-512F200EL / SAK-TC1791F-512F200EP.  
Abbreviations:  
FPU  
ICACHE:  
DCACHE  
PSPR:  
Instruction Cache  
Data Cache  
Program Scratch-Pad RAM  
Data Scratch-Padl Data RAM  
Boot ROM  
Program Flash  
Data Flash  
Parameter RAM in PCP  
Code RAM in PCP  
SRI Cross Bar(XBar_SRI)  
On Chip Bus Slave Interface  
On Chip Bus Master Interface  
PMI  
DMI  
LMU  
DSPR:  
TriCore  
CPU  
128 KB DSPR  
32 KB PSPR  
16 KB ICACHE  
BROM:  
PFlash:  
DFlash:  
PRAM:  
CMEM:  
XBAR:  
16 KB DCACHE  
128 KB  
SRAM  
M/S  
M/S  
S
EBU  
S
:
:
Cross Bar Interconnect (SRI)  
M
XBAR  
S
S
M
M/S  
OCDSL1 Debug  
Interface/JTAG  
PMU0  
PMU1  
DMA  
16 channels  
(MemCheck)  
Bridge  
(SFI)  
2
2 MB PFlash  
192 KB DFlash  
16 KB BROM  
KeyFlash  
2 MB PFlash  
MLI  
M/S  
M/S  
16 KB PRAM  
Interrupt  
System  
SDMA  
2
4
4
8 channels  
ASC  
PCP2  
STM  
SBCU  
Ports  
SSC  
Core  
SSCG  
BMU  
SSC Guardian  
32 KB CMEM  
E-Ray  
(2 Channels)  
5V (3.3V su  
pported as well)  
Ext. ADC Su  
pply  
External  
Request Unit  
MultiCAN  
(4 Nodes, 128 MO)  
2
2
2
ADC0  
ADC1  
ADC2  
CCU6  
(2xCCU6)  
(5V max)  
SENT  
(8 channels )  
44  
FCE  
GPT120  
SCU  
GPTA0  
GPTA1  
LTCA2  
MSC  
FM-PLL  
(LVDS)  
(3.3V max)  
PLL E-RAY  
FADC  
8
System Peripheral Bus (SPB)  
3.3V  
Ext. FADC Supply  
TC1791  
Figure 1  
Block Diagram  
Data Sheet  
14  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791Block Diagram  
Figure 2 shows the block diagram of the SAK-TC1791F-384F200EL / SAK-TC1791F-  
384F200EP.  
Abbreviations:  
FPU  
ICACHE:  
DCACHE  
PSPR:  
Instruction Cache  
Data Cache  
Program Scratch-Pad RAM  
Data Scratch-Padl Data RAM  
Boot ROM  
Program Flash  
Data Flash  
Parameter RAM in PCP  
Code RAM in PCP  
SRI Cross Bar(XBar_SRI)  
On Chip Bus Slave Interface  
On Chip Bus Master Interface  
PMI  
DMI  
LMU  
DSPR:  
TriCore  
CPU  
128 KB DSPR  
32 KB PSPR  
16 KB ICACHE  
BROM:  
PFlash:  
DFlash:  
PRAM:  
CMEM:  
XBAR:  
16 KB DCACHE  
128 KB  
SRAM  
M/S  
M/S  
S
EBU  
S
:
:
Cross Bar Interconnect (SRI)  
M
XBAR  
S
S
M
M/S  
OCDSL1 Debug  
Interface/JTAG  
PMU0  
PMU1  
DMA  
16 channels  
(MemCheck)  
Bridge  
(SFI)  
2
2 MB PFlash  
192 KB DFlash  
16 KB BROM  
KeyFlash  
1 MB PFlash  
MLI  
M/S  
M/S  
16 KB PRAM  
Interrupt  
System  
SDMA  
2
4
4
8 channels  
ASC  
PCP2  
STM  
SBCU  
Ports  
SSC  
Core  
SSCG  
BMU  
SSC Guardian  
32 KB CMEM  
E-Ray  
(2 Channels)  
5V (3.3V su  
pported as well)  
Ext. ADC Su  
pply  
External  
Request Unit  
MultiCAN  
(4 Nodes, 128 MO)  
2
2
2
ADC0  
ADC1  
ADC2  
CCU6  
(2xCCU6)  
(5V max)  
SENT  
(8 channels )  
44  
FCE  
GPT120  
SCU  
GPTA0  
GPTA1  
LTCA2  
MSC  
FM-PLL  
(LVDS)  
(3.3V max)  
PLL E-RAY  
FADC  
8
System Peripheral Bus (SPB)  
3.3V  
Ext. FADC Supply  
TC1791  
Figure 2  
Block Diagram  
Figure 3 shows the block diagram of the SAK-TC1791S-512F240EP.  
Data Sheet  
15  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791Block Diagram  
Abbreviations:  
FPU  
ICACHE:  
DCACHE  
PSPR:  
Instruction Cache  
Data Cache  
Program Scratch-Pad RAM  
Data Scratch-Padl Data RAM  
Boot ROM  
Program Flash  
Data Flash  
Parameter RAM in PCP  
Code RAM in PCP  
PMI  
DMI  
LMU  
DSPR:  
TriCore  
CPU  
128 KB DSPR  
32 KB PSPR  
16 KB ICACHE  
BROM:  
PFlash:  
DFlash:  
PRAM:  
CMEM:  
XBAR:  
16 KB DCACHE  
128 KB  
SRAM  
M/S  
M/S  
S
EBU  
SRI Cross Bar (XBar_SRI)  
On Chip Bus Slave Interface  
On Chip Bus Master Interface  
S
:
:
Cross Bar Interconnect (SRI)  
M
XBAR  
S
S
M
M/S  
OCDSL1 Debug  
Interface/JTAG  
PMU0  
PMU1  
DMA  
16 channels  
(MemCheck)  
Bridge  
(SFI)  
2
2 MB PFlash  
192 KB DFlash  
16 KB BROM  
KeyFlash  
2 MB PFlash  
MLI  
M/S  
M/S  
16 KB PRAM  
Interrupt  
System  
SDMA  
2
4
4
8 channels  
ASC  
PCP2  
SHE  
STM  
SBCU  
Ports  
SSC  
Core  
SSCG  
BMU  
SSC Guardian  
32 KB CMEM  
E-Ray  
(2 Channels)  
5V (3.3V su  
pported as well)  
Ext. ADC Su  
pply  
External  
Request Unit  
MultiCAN  
(4 Nodes, 128 MO)  
2
2
2
ADC0  
ADC1  
ADC2  
CCU6  
(2xCCU6)  
(5V max)  
SENT  
(8 channels )  
44  
FCE  
GPT120  
SCU  
GPTA0  
GPTA1  
LTCA2  
MSC  
FM-PLL  
(LVDS)  
(3.3V max)  
PLL E-RAY  
FADC  
8
System Peripheral Bus (SPB)  
3.3V  
Ext. FADC Supply  
TC1791  
Figure 3  
Block Diagram  
Figure 4 shows the block diagram of the SAK-TC1791S-384F200EP.  
Data Sheet  
16  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791Block Diagram  
Abbreviations:  
FPU  
ICACHE:  
DCACHE  
PSPR:  
Instruction Cache  
Data Cache  
Program Scratch-Pad RAM  
Data Scratch-Padl Data RAM  
Boot ROM  
Program Flash  
Data Flash  
Parameter RAM in PCP  
Code RAM in PCP  
SRI Cross Bar(XBar_SRI)  
On Chip Bus Slave Interface  
On Chip Bus Master Interface  
PMI  
DMI  
LMU  
DSPR:  
TriCore  
CPU  
128 KB DSPR  
32 KB PSPR  
16 KB ICACHE  
BROM:  
PFlash:  
DFlash:  
PRAM:  
CMEM:  
XBAR:  
16 KB DCACHE  
128 KB  
SRAM  
M/S  
M/S  
S
EBU  
S
:
:
Cross Bar Interconnect (SRI)  
M
XBAR  
S
S
M
M/S  
OCDSL1 Debug  
Interface/JTAG  
PMU0  
PMU1  
DMA  
16 channels  
(MemCheck)  
Bridge  
(SFI)  
2
2 MB PFlash  
192 KB DFlash  
16 KB BROM  
KeyFlash  
1 MB PFlash  
MLI  
M/S  
M/S  
16 KB PRAM  
Interrupt  
System  
SDMA  
2
4
4
8 channels  
ASC  
PCP2  
SHE  
STM  
SBCU  
Ports  
SSC  
Core  
SSCG  
BMU  
SSC Guardian  
32 KB CMEM  
E-Ray  
(2 Channels)  
5V (3.3V su  
pported as well)  
Ext. ADC Su  
pply  
External  
Request Unit  
MultiCAN  
(4 Nodes, 128 MO)  
2
2
2
ADC0  
ADC1  
ADC2  
CCU6  
(2xCCU6)  
(5V max)  
SENT  
(8 channels )  
44  
FCE  
GPT120  
SCU  
GPTA0  
GPTA1  
LTCA2  
MSC  
FM-PLL  
(LVDS)  
(3.3V max)  
PLL E-RAY  
FADC  
8
System Peripheral Bus (SPB)  
3.3V  
Ext. FADC Supply  
TC1791  
Figure 4  
Block Diagram  
Figure 5 shows the block diagram of the SAK-TC1791N-384F200EP.  
Data Sheet  
17  
V 1.1, 2014-05  
TC1791  
System Overview of the TC1791Block Diagram  
Abbreviations:  
FPU  
ICACHE:  
DCACHE  
PSPR:  
Instruction Cache  
Data Cache  
Program Scratch-Pad RAM  
Data Scratch-Padl Data RAM  
Boot ROM  
Program Flash  
Data Flash  
Parameter RAM in PCP  
Code RAM in PCP  
SRI Cross Bar (XBar_SRI)  
On Chip Bus Slave Interface  
On Chip Bus Master Interface  
PMI  
DMI  
LMU  
DSPR:  
TriCore  
CPU  
128 KB DSPR  
32 KB PSPR  
16 KB ICACHE  
BROM:  
PFlash:  
DFlash:  
PRAM:  
CMEM:  
XBAR:  
16 KB DCACHE  
128 KB  
SRAM  
M/S  
M/S  
S
EBU  
S
:
:
Cross Bar Interconnect (SRI)  
M
XBAR  
S
S
M
M/S  
OCDSL1 Debug  
Interface/JTAG  
PMU0  
PMU1  
DMA  
16 channels  
(MemCheck)  
Bridge  
(SFI)  
2
2 MB PFlash  
192 KB DFlash  
16 KB BROM  
KeyFlash  
1 MB PFlash  
MLI  
M/S  
M/S  
16 KB PRAM  
Interrupt  
System  
SDMA  
2
4
4
8 channels  
ASC  
PCP2  
STM  
SBCU  
Ports  
SSC  
Core  
SSCG  
BMU  
SSC Guardian  
32 KB CMEM  
5V (3.3V su  
pported as well)  
Ext. ADC Su  
pply  
External  
Request Unit  
MultiCAN  
(4 Nodes, 128 MO)  
2
2
2
ADC0  
ADC1  
ADC2  
CCU6  
(2xCCU6)  
(5V max)  
SENT  
(8 channels )  
44  
FCE  
GPT120  
SCU  
GPTA0  
GPTA1  
LTCA2  
MSC  
FM-PLL  
(LVDS)  
(3.3V max)  
PLL E-RAY  
FADC  
8
System Peripheral Bus (SPB)  
3.3V  
Ext. FADC Supply  
TC1791  
Figure 5  
Block Diagram  
Data Sheet  
18  
V 1.1, 2014-05  
TC1791  
Pinning  
3
Pinning  
Figure 6 is showing the TC1791 Logic Symbol.  
Alternate Functions :  
PORST  
1)  
14  
6
GPTA/ HWCFG / E-RAY /  
GPT12  
GPTA/ ERU / SSC1 / SSC3 /  
CCU6 / GPT12  
TESTMODE  
Port 0  
Port 1  
Port 2  
Port 3  
Port 4  
Port 5  
Port 6  
Port 7  
Port 8  
Port 9  
General Control  
ESR0  
ESR1  
10  
4
GPTA/ SSC0 / SSC1  
TRST  
GPTA / CCU6 / GPT12  
GPTA/ SSC2 / CCU6 / GPT12  
TCK / DAP0  
13  
16  
12  
6
TDI / BRKIN/  
OCDS /  
BRKOUT  
JTAG Control  
ASC0 / ASC1 / MSC0 / LVDS /  
MLI0 / MLI1 / CCU6 / GPT12  
TDO /BRKOUT/  
DAP2 / BRKIN  
ASC0 / ASC1 / SSC1 / CAN /  
E-RAY / CCU6 / GPT12  
TMS / DAP1  
ERU / ADC-Mux / SSC3  
XTAL1  
XTAL2  
VDDOSC  
8
MLI1 / GPTA / SENT /  
CCU6 / GPT12  
MSC0 / MSC1 / GPTA/  
SENT / CCU6 / GPT12  
12  
VDDOSC3  
6
Oscillator  
SSC0  
Port 10  
Port 13  
VSSOSC  
TC1791  
16  
GPTA  
VDDPF  
5
Port 14  
Port 17  
GPTA / CCU6 / GPT12  
VDDPF3  
16  
10  
12  
2
SENT  
VDDP  
VDD  
(Overlay with Analog Inputs )  
Digital Circuitry  
Power Supply  
VDDFL3  
1) Only available for SAK-TC1791S-512F240EP,  
SAK-TC1791F-512F240EP, SAK-TC1791F-  
512F240EL, SAK-TC1791S-384F200EP, SAK-  
TC1791F-384F200EL, SAK-TC1791F-384F200EP,  
and SAK-TC1791F-384F200EL.  
48  
13  
3
VSS  
VSSP  
VDDSB  
(ED only, N.C. in PD)  
ADC / FADC  
Analog Inputs  
AN[47:0]  
VSSAF  
VSSMF  
V
3
VAREFx  
VAGND  
VDDM  
VSSM  
VFAGND  
VFAREF  
VDDMF  
VDDAF  
FADC Analog  
Power Supply  
ADC0 /ADC1 / ADC2  
Analog Power Supply  
2
N.C.  
TC1791_LogSym_292  
Figure 6  
TC1791 Logic Symbol  
Data Sheet  
19  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
3.1  
TC1791 Pin Configuration  
This chapter shows the pin configuration of the TC1791 package PG-LFBGA- 292-6.  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
VSS  
MF  
9
8
7
6
5
4
3
2
1
VA  
VA AN39 AN37  
Y
VSS P14.6 P14.8 VSSP P10.5 P10.0 P10.3 P4.7 P4.3 VSSP  
AN30 AN26  
AN34 AN1 NC  
AN33 AN2 AN3  
AN4 AN44  
GND0 REF0 P17.11 P17.9  
VFA  
GND  
VA VA AN38 AN36  
REF2 REF1 P17.10 P17.8  
W VDD VSS P14.4 VDDP P10.4 P10.1 P4.10 P4.6 P4.2 VDDP  
V P14.2 VDD  
AN29 AN25  
VDD VFA  
MF REF  
AN43 AN41  
AN47 AN32  
P17.15 P17. 13  
U P14.0 P13.15  
T P13.14 P13.13  
R P13.12 P13.11  
P P13.9 P13.8  
N P13.5 P13.4  
M VDDP VDDP  
L VSSP VSSP  
K XTAL1 XTAL2  
VSS P10.2 P4.14 P4.9 P4.5 P4.1  
VDD VSS P4.12 P4.8 P4.4 P4.0  
P13.10 VDD  
AN28 AN24  
AN5 AN45  
VDD  
AF  
AN42 AN40  
AN7 AN0  
P17.14 P17. 12  
AN31 AN27 AN35  
AN6 AN46  
AN8 AN9  
P17.0 P17.1  
VDDM VSSM  
AN10 AN11  
P17.2 P17.3  
AN12 AN13  
P17.4 P17.5  
P13.7 P13.6  
P13.3 P13.2  
P13.1 P13.0  
VDD VSS VSS VSS VSS VDD  
VSS VSS VSS VSS  
AN14 AN15  
P17.6 P17.7  
VDD  
VSS VSS  
VDD  
AN16 AN17  
AN18 AN19  
VSS VSS  
VSS VSS  
AN20 AN21  
AN22 AN23  
VDDP VSSP  
P7.2 P7.1  
P1.12 P1.0  
P1.6 P1.7  
P8.4 P8.0  
P8.3 P6.15  
P6.11 P6.14  
P6.10 P6.13  
VDD VDD  
PF3 FL3  
VSS VSS VSS VSS VSS VSS VSS VSS  
VSS VSS VSS VSS VSS VSS VSS VSS  
NC  
NC  
VDD VDD  
PF OSC3  
VDD  
FL3  
P7.5  
VSS VDD  
J
TDI TMS  
TDO P9.14  
VSS VSS  
VDD  
VSS VSS  
VSS VSS  
VDD  
P7.4 P7.3  
P7.0 P1.1  
P1.9 P8.6  
P8.5 P8.7  
OSC OSC  
H
TCK TRST  
VSS VSS VSS VSS  
Test  
P9.13  
mode  
G ESR1 ESR0  
F P9.10 PORST  
VDD VSS VSS VSS VSS VDD  
P9.5 P9.6  
E
D
C
B
P9.7 P9.8  
P9.2 P9.1  
P9.3 P9.4  
P9.0 VSSP P5.5 P3.0 P3.4 P3.12 P0.1 P0.3 P0.5 P0.7 P2.6 P8.1 VSSP P8.2  
VSSP P5.7 P5.2 P5.12 P3.10 P0.0 P0.2 P0.4 P0.6 P2.10 P2.5 P2.4 P6.7 VSSP  
P5.6 VSSP VDDP P5.9 P5.8 P5.3 P5.13 P5.14 P0.10 P0.13 VDDP P0.9 P2.12 P2.7 P2.3 P6.8 P6.4 VDDP VSSP P6.12  
A VSSP VDDP P5.4 P5.11 P5.10 P5.0 P5.1 P5.15 P0.11 P0.12 VSSP P0.14 P2.14 P2.8 P2.2 P6.9 P6.6 P6.5 VDDP NC  
Figure 7  
TC1791 Pinning for PG-LFBGA-292 Package  
Data Sheet  
20  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions  
Symbol Ctrl. Type Function  
Port 0  
D12  
P0.0  
I/O  
I
A1+/ Port 0 General Purpose I/O Line 0  
PU  
HWCFG0  
OUT56  
OUT56  
OUT80  
P0.1  
Hardware Configuration Input 0  
O1  
O2  
O3  
I/O  
I
OUT56 Line of GPTA0  
OUT56 Line of GPTA1  
OUT80 Line of LTCA2  
E11  
D11  
E10  
A1/  
PU  
Port 0 General Purpose I/O Line 1  
Hardware Configuration Input 1  
OUT57 Line of GPTA0  
HWCFG1  
OUT57  
OUT57  
OUT81  
P0.2  
O1  
O2  
O3  
I/O  
I
OUT57 Line of GPTA1  
OUT81 Line of LTCA2  
A2/  
PU  
Port 0 General Purpose I/O Line 2  
Hardware Configuration Input 2  
OUT58 Line of GPTA0  
HWCFG2  
OUT58  
OUT58  
OUT82  
P0.3  
O1  
O2  
O3  
I/O  
I
OUT58 Line of GPTA1  
OUT82 Line of LTCA2  
A1/  
PU  
Port 0 General Purpose I/O Line 3  
Hardware Configuration Input 3  
OUT59 Line of GPTA0  
HWCFG3  
OUT59  
OUT59  
OUT83  
O1  
O2  
O3  
OUT59 Line of GPTA1  
OUT83 Line of LTCA2  
Data Sheet  
21  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P0.4  
Ctrl. Type Function  
D10  
I/O  
I
A1/  
PU  
Port 0 General Purpose I/O Line 4  
Hardware Configuration Input 4  
OUT60 Line of GPTA0  
HWCFG4  
OUT60  
OUT60  
EVTO0  
P0.5  
O1  
O2  
O3  
I/O  
I
OUT60 Line of GPTA1  
MCDS Output Event 01)  
Port 0 General Purpose I/O Line 5  
Hardware Configuration Input 5  
OUT61 Line of GPTA0  
E9  
D9  
E8  
B9  
A1/  
PU  
HWCFG5  
OUT61  
OUT61  
EVTO1  
P0.6  
O1  
O2  
O3  
I/O  
I
OUT61 Line of GPTA1  
MCDS Output Event 11)  
Port 0 General Purpose I/O Line 6  
Hardware Configuration Input 6  
OUT62 Line of GPTA0  
A2/  
PU  
HWCFG6  
OUT62  
OUT62  
EVTO2  
P0.7  
O1  
O2  
O3  
I/O  
I
OUT62 Line of GPTA1  
MCDS Output Event 21)  
Port 0 General Purpose I/O Line 7  
Hardware Configuration Input 7  
OUT63 Line of GPTA0  
A1/  
PU  
HWCFG7  
OUT63  
OUT63  
EVTO3  
P0.9  
O1  
O2  
O3  
I/O  
I
OUT63 Line of GPTA1  
MCDS Output Event 31)  
Port 0 General Purpose I/O Line 9  
E-Ray Channel A Receive Data Input 0 2)  
-
A1/  
PU  
RXDA0  
Reserved  
Reserved  
Reserved  
O1  
O2  
O3  
-
-
Data Sheet  
22  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P0.10  
Ctrl. Type Function  
B12  
I/O  
O1  
A2/  
PU  
Port 0 General Purpose I/O Line 10  
TXENA  
E-Ray Channel A transmit Data Output  
enable 2)  
Reserved  
Reserved  
P0.11  
O2  
O3  
I/O  
I
-
-
A12  
A2/  
PU  
Port 0 General Purpose I/O Line 11  
T5INB  
GPT120  
GPT121  
T5INA  
I
TXENB  
O1  
E-Ray Channel B transmit Data Output  
enable 2)  
Reserved  
Reserved  
P0.12  
O2  
O3  
I/O  
I
-
-
A11  
A2/  
PU  
Port 0 General Purpose I/O Line 12  
T5EUDA  
T5EUDB  
TXDB  
GPT120  
I
GPT121  
O1  
O2  
O3  
I/O  
I
E-Ray Channel B transmit Data Output 2)  
Reserved  
Reserved  
P0.13  
-
-
B11  
A1/  
PU  
Port 0 General Purpose I/O Line 13  
RXDB0  
E-Ray Channel B Receive Data Input 0 2)  
T5EUDB  
T5EUDA  
Reserved  
Reserved  
Reserved  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
-
-
-
Data Sheet  
23  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P0.14  
Ctrl. Type Function  
A9  
I/O  
I
A2/  
PU  
Port 0 General Purpose I/O Line 14  
T6INA  
GPT120  
T6INB  
I
GPT121  
TXDA  
O1  
O2  
O3  
E-Ray Channel A transmit Data Output 2)  
Reserved  
Reserved  
-
-
Port 1  
H1  
P1.0  
I/O  
I
A2/  
PU  
Port 1 General Purpose I/O Line 0  
REQ0  
External trigger Input 0  
EXTCLK1  
Reserved  
Reserved  
P1.1  
O1  
O2  
O3  
I/O  
I
External Clock Output 1  
-
-
H4  
A1/  
PU  
Port 1 General Purpose I/O Line 1  
REQ1  
External trigger Input 1  
CC60INA  
CC60INB  
CC60  
I
CCU60  
I
CCU61  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
CCU60  
Reserved  
Reserved  
P1.6  
-
-
G2  
A2/  
PU  
Port 1 General Purpose I/O Line 6  
MLI0 transmit Channel valid Output A  
SSC1 Slave Select Output Line 10  
CCU60  
TVALID0A  
SLSO10  
COUT60  
Data Sheet  
24  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P1.7  
Ctrl. Type Function  
G1  
I/O  
I
A2/  
PU  
Port 1 General Purpose I/O Line 7  
CCU60  
CC61INB  
CC61INA  
TData0  
CC61  
I
CCU61  
O1  
O2  
O3  
I/O  
MLI0 transmit Channel Data Output  
CCU61  
T3OUT  
P1.9  
GPT120  
G5  
H2  
A2/  
PU  
Port 1 General Purpose I/O Line 9  
MLI0 Receive Channel ready Output A  
SSC1 Slave Select Output Line 11  
OUT65 Line of GPTA0  
Port 1 General Purpose I/O Line 12  
External Clock Output 0  
OUT68 Line of GPTA0  
OUT68 Line of GPTA1  
RREADY0A O1  
SLSO11  
OUT65  
P1.12  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
EXTCLK0  
OUT68  
OUT68  
Port 2  
A6  
P2.2  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 2  
PU  
SLSO02  
SLSO12  
SSC0 Slave Select Output Line 2  
SSC1 Slave Select Output Line 12  
SLSO02  
AND  
SSC0 & SSC1 Slave Select Output Line 2  
AND Slave Select Output Line 12  
SLSO12  
B6  
P2.3  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 3  
PU  
SLSO03  
SLSO13  
SSC0 Slave Select Output Line 3  
SSC1 Slave Select Output Line 13  
SLSO03  
AND  
SSC0 & SSC1 Slave Select Output Line 3  
AND Slave Select Output Line 13  
SLSO13  
Data Sheet  
25  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P2.4  
Ctrl. Type Function  
D6  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 4  
PU  
SLSO04  
SLSO14  
SSC0 Slave Select Output Line 4  
SSC1 Slave Select Output Line 14  
SLSO04  
AND  
SSC0 & SSC1 Slave Select Output Line 4  
AND Slave Select Output Line 14  
SLSO14  
D7  
E7  
B7  
P2.5  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 5  
PU  
SLSO05  
SLSO15  
SSC0 Slave Select Output Line 5  
SSC1 Slave Select Output Line 15  
SLSO05  
AND  
SLSO15  
SSC0 & SSC1 Slave Select Output Line 5  
AND Slave Select Output Line 15  
P2.6  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 6  
PU  
SLSO06  
SLSO16  
SSC0 Slave Select Output Line 6  
SSC1 Slave Select Output Line 16  
SLSO06  
AND  
SLSO16  
SSC0 & SSC1 Slave Select Output Line 6  
AND Slave Select Output Line 16  
P2.7  
I/O  
O1  
O2  
O3  
A1+/ Port 2 General Purpose I/O Line 7  
PU  
SLSO07  
SLSO17  
SSC0 Slave Select Output Line 7  
SSC1 Slave Select Output Line 17  
SLSO07  
AND  
SSC0 & SSC1 Slave Select Output Line  
7AND Slave Select Output Line 17  
SLSO17  
Data Sheet  
26  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P2.8  
Ctrl. Type Function  
A7  
I/O  
A1/  
PU  
Port 2 General Purpose I/O Line 8  
IN0 Line of GPTA0  
IN0 Line of GPTA1  
IN0 Line of LTCA2  
CCU62  
IN0  
I
IN0  
I
IN0  
I
CCPOS0A  
T12HRB  
T3INB  
T3INA  
OUT0  
OUT0  
OUT0  
P2.10  
IN2  
I
I
CCU63  
I
GPT120  
I
GPT121  
O1  
OUT0 Line of GPTA0  
OUT0 Line of GPTA1  
OUT0 Line of LTCA2  
Port 2 General Purpose I/O Line 10  
IN2 Line of GPTA0  
IN2 Line of GPTA1  
IN2 Line of LTCA2  
CCU60  
O2  
O3  
D8  
I/O  
A1/  
PU  
I
IN2  
I
IN2  
I
T12HRE  
CC61INC  
CTRAPA  
CTRAPB  
CC60INC  
OUT2  
OUT2  
OUT2  
I
I
CCU60  
I
CCU61  
I
CCU63  
I
CCU61  
O1  
O2  
O3  
OUT2 Line of GPTA0  
OUT2 Line of GPTA1  
OUT2 Line of LTCA2  
Data Sheet  
27  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P2.12  
IN4  
Ctrl. Type Function  
B8  
I/O  
A1/  
PU  
Port 2 General Purpose I/O Line 12  
IN4 Line of GPTA0  
IN4 Line of GPTA1  
IN4 Line of LTCA2  
CCU62  
I
IN4  
I
IN4  
I
T12HRB  
CCPOS0A  
T2INB  
T2INA  
OUT4  
OUT4  
OUT4  
P2.14  
IN6  
I
I
CCU63  
I
GPT120  
I
GPT121  
O1  
OUT4 Line of GPTA0  
OUT4 Line of GPTA1  
OUT4 Line of LTCA2  
Port 2 General Purpose I/O Line 14  
IN6 Line of GPTA0  
IN6 Line of GPTA1  
IN6 Line of LTCA2  
CCU60  
O2  
O3  
A8  
I/O  
A1/  
PU  
I
IN6  
I
IN6  
I
CCPOS0A  
T12HRB  
T3INA  
T3INB  
OUT6  
OUT6  
OUT6  
I
I
CCU61  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
OUT6 Line of GPTA0  
OUT6 Line of GPTA1  
OUT6 Line of LTCA2  
Port 3  
Data Sheet  
28  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P3.0  
Ctrl. Type Function  
E14  
I/O  
A1/  
PU  
Port 3 General Purpose I/O Line 0  
IN8 Line of GPTA0  
IN8 Line of GPTA1  
IN8 Line of LTCA2  
CCU62  
IN8  
I
IN8  
I
IN8  
I
CTRAPA  
CTRAPB  
CC60INC  
T12HRE  
CC61INC  
T5INA  
T5INB  
OUT8  
I
I
CCU61  
I
CCU62  
I
CCU63  
I
CCU63  
I
GPT120  
I
GPT121  
O1  
OUT8 Line of GPTA0  
OUT8 Line of GPTA1  
OUT8 Line of LTCA2  
Port 3 General Purpose I/O Line 4  
IN12 Line of GPTA0  
IN12 Line of GPTA1  
IN12 Line of LTCA2  
CCU62  
OUT8  
O2  
OUT8  
O3  
E13  
P3.4  
I/O  
A1/  
PU  
IN12  
I
IN12  
I
IN12  
I
T12HRE  
CC61INC  
CTRAPA  
CTRAPB  
CC60INC  
OUT12  
OUT12  
OUT12  
I
I
CCU62  
I
CCU63  
I
CCU60  
I
CCU63  
O1  
O2  
O3  
OUT12 Line of GPTA0  
OUT12 Line of GPTA1  
OUT12 Line of LTCA2  
Data Sheet  
29  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P3.10  
Ctrl. Type Function  
D13  
I/O  
A1+/ Port 3 General Purpose I/O Line 10  
PU  
IN18  
I
IN18 Line of GPTA0  
IN18 Line of GPTA1  
IN18 Line of LTCA2  
CCU62  
IN18  
I
IN18  
I
CCPOS1A  
T13HRB  
T3EUDB  
T3EUDA  
OUT18  
OUT18  
OUT18  
P3.12  
I
I
CCU63  
I
GPT120  
I
GPT121  
O1  
OUT18 Line of GPTA0  
OUT18 Line of GPTA1  
OUT18 Line of LTCA2  
Port 3 General Purpose I/O Line 12  
IN20 Line of GPTA0  
IN20 Line of GPTA1  
IN20 Line of LTCA2  
CCU62  
O2  
O3  
E12  
I/O  
A1/  
PU  
IN20  
I
IN20  
I
IN20  
I
CCPOS2A  
T12HRC  
T13HRC  
T4INB  
I
I
CCU63  
I
CCU63  
I
GPT120  
T4INA  
I
GPT121  
OUT20  
OUT20  
OUT20  
O1  
O2  
O3  
OUT20 Line of GPTA0  
OUT20 Line of GPTA1  
OUT20 Line of LTCA2  
Port 4  
Data Sheet  
30  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.0  
Ctrl. Type Function  
T12  
I/O  
A1+/ Port 4 General Purpose I/O Line 0  
PU  
IN24  
I
IN24 Line of GPTA0  
IN24  
I
IN24 Line of GPTA1  
IN24  
I
IN24 Line of LTCA2  
MRST2A  
OUT24  
OUT24  
MRST2  
P4.1  
I
SSC2 Master Receive Input A (Master Mode)  
OUT24 Line of GPTA0  
O1  
O2  
OUT24 Line of GPTA1  
O3  
SSC2 Slave Transmit Output (Slave Mode)  
U12  
I/O  
A1+/ Port 4 General Purpose I/O Line 1  
PU  
IN25  
I
I
I
I
I
IN25 Line of GPTA0  
IN25  
IN25 Line of GPTA1  
IN25  
IN25 Line of LTCA2  
MTSR2A  
MRSTG2A  
SSC2 Slave Receive Input A (Slave Mode)  
SSC Guardian 2 Master Receive Input A  
(Master Mode)3)  
OUT25  
OUT25  
MTSR2  
O1  
O2  
O3  
OUT25 Line of GPTA0  
OUT25 Line of GPTA1  
SSC2 Master Transmit Output (Master  
Mode)  
Data Sheet  
31  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.2  
Ctrl. Type Function  
W12  
I/O  
I
A1+/ Port 4 General Purpose I/O Line 2  
PU  
IN26  
IN26 Line of GPTA0  
IN26 Line of GPTA1  
IN26 Line of LTCA2  
SSC2 Input  
IN26  
I
IN26  
I
SCLK2  
OUT26  
OUT26  
SCLK2  
P4.3  
I
O1  
O2  
O3  
I/O  
I
OUT26 Line of GPTA0  
OUT26 Line of GPTA1  
SSC2 Output  
Y12  
A1+/ Port 4 General Purpose I/O Line 3  
PU  
IN27  
IN27 Line of GPTA0  
IN27  
I
IN27 Line of GPTA1  
IN27 Line of LTCA2  
IN27  
I
OUT27  
OUT27  
SLSO20  
P4.4  
O1  
O2  
O3  
I/O  
I
OUT27 Line of GPTA0  
OUT27 Line of GPTA1  
SSC2 Output  
T13  
A1+/ Port 4 General Purpose I/O Line 4  
PU  
IN28  
IN28 Line of GPTA0  
IN28  
I
IN28 Line of GPTA1  
IN28 Line of LTCA2  
OUT28 Line of GPTA0  
OUT28 Line of GPTA1  
SSC2 Output  
IN28  
I
OUT28  
OUT28  
SLSO21  
O1  
O2  
O3  
Data Sheet  
32  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.5  
Ctrl. Type Function  
U13  
I/O  
I
A1+/ Port 4 General Purpose I/O Line 5  
PU  
IN29  
IN29 Line of GPTA0  
IN29 Line of GPTA1  
IN29 Line of LTCA2  
OUT29 Line of GPTA0  
OUT29 Line of GPTA1  
SSC2 Output  
IN29  
I
IN29  
I
OUT29  
OUT29  
SLSO22  
P4.6  
O1  
O2  
O3  
I/O  
I
W13  
A1+/ Port 4 General Purpose I/O Line 6  
PU  
IN30  
IN30 Line of GPTA0  
IN30  
I
IN30 Line of GPTA1  
IN30 Line of LTCA2  
IN30  
I
OUT30  
OUT30  
SLSO23  
P4.7  
O1  
O2  
O3  
I/O  
I
OUT30 Line of GPTA0  
OUT30 Line of GPTA1  
SSC2 Output  
Y13  
A1+/ Port 4 General Purpose I/O Line 7  
PU  
IN31  
IN31 Line of GPTA0  
IN31  
I
IN31 Line of GPTA1  
IN31Line of LTCA2  
GPT120  
IN31  
I
T6INB  
T6INA  
OUT31  
OUT31  
SLSO24  
I
I
GPT121  
O1  
O2  
O3  
OUT31 Line of GPTA0  
OUT31 Line of GPTA1  
SSC2 Output  
Data Sheet  
33  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.8  
Ctrl. Type Function  
T14  
I/O  
A1/  
PU  
Port 4 General Purpose I/O Line 8  
IN32 Line of GPTA0  
IN32 Line of GPTA1  
CCU60  
IN32  
I
IN32  
I
CCPOS1A  
T13HRB  
T3EUDA  
T3EUDB  
OUT32  
OUT32  
OUT0  
I
I
CCU61  
I
GPT120  
I
GPT121  
O1  
OUT32 Line of GPTA0  
OUT32 Line of GPTA1  
OUT0 Line of LTCA2  
Port 4 General Purpose I/O Line 9  
IN33 Line of GPTA0  
IN33 Line of GPTA1  
CCU60  
O2  
O3  
AB19 P4.9  
IN33  
I/O  
A1/  
PU  
I
IN33  
I
CCPOS2A  
I
T12HRC  
T13HRC  
T4INA  
I
CCU61  
I
CCU61  
I
GPT120  
T4INB  
I
GPT121  
SLSI2  
I
SSC2  
OUT33  
OUT33  
OUT1  
O1  
O2  
O3  
OUT33 Line of GPTA0  
OUT33 Line of GPTA1  
OUT1 Line of LTCA2  
Data Sheet  
34  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.10  
Ctrl. Type Function  
W14  
I/O  
A1/  
PU  
Port 4 General Purpose I/O Line 10  
IN34 Line of GPTA0  
IN34 Line of GPTA1  
CCU60  
IN34  
I
IN34  
I
T12HRB  
CCPOS0A  
T2INA  
I
I
CCU61  
I
GPT120  
T2INB  
I
GPT121  
OUT34  
OUT34  
OUT2  
O1  
O2  
O3  
I/O  
I
OUT34 Line of GPTA0  
OUT34 Line of GPTA1  
OUT2 Line of LTCA2  
Port 4 General Purpose I/O Line 12  
IN36 Line of GPTA0  
IN36 Line of GPTA1  
CCU60  
T15  
P4.12  
A1/  
PU  
IN36  
IN36  
I
T13HRB  
CCPOS1A  
T2EUDA  
T2EUDB  
OUT36  
OUT36  
OUT4  
I
I
CCU61  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
OUT36 Line of GPTA0  
OUT36 Line of GPTA1  
OUT4 Line of LTCA2  
Data Sheet  
35  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P4.14  
Ctrl. Type Function  
U15  
I/O  
A1/  
PU  
Port 4 General Purpose I/O Line 14  
IN38 Line of GPTA0  
IN38 Line of GPTA1  
CCU60  
IN38  
I
IN38  
I
T12HRC  
T13HRC  
CCPOS2A  
T4EUDA  
T4EUDB  
OUT38  
OUT38  
OUT6  
I
I
CCU60  
I
CCU61  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
OUT38 Line of GPTA0  
OUT38 Line of GPTA1  
OUT6 Line of LTCA2  
Port 5  
A15  
P5.0  
I/O  
I
A1+/ Port 5 General Purpose I/O Line 0  
PU  
RXD0A  
T6EUDA  
T6EUDB  
RXD0A  
OUT72  
OUT72  
P5.1  
ASC0 Receiver Input/Output A  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
ASC0 Receiver Input/Output A  
OUT72 Line of GPTA0  
OUT72 Line of GPTA1  
A1+/ Port 5 General Purpose I/O Line 1  
A14  
PU  
TXD0  
ASC0 Transmitter Output A  
OUT73  
OUT73  
OUT73 Line of GPTA0  
OUT73 Line of GPTA1  
Data Sheet  
36  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P5.2  
Ctrl. Type Function  
D15  
I/O  
I
A2/  
PU  
Port 5 General Purpose I/O Line 2  
ASC1 Receiver Input/Output A  
ASC1 Receiver Input/Output A  
OUT74 Line of GPTA0  
RXD1A  
RXD1A  
OUT74  
OUT74  
P5.3  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
I
OUT74 Line of GPTA1  
B15  
A18  
A1+/ Port 5 General Purpose I/O Line 3  
PU  
TXD1  
ASC1 Transmitter Output A  
OUT75  
OUT75  
P5.4  
OUT75 Line of GPTA0  
OUT75 Line of GPTA1  
A2/  
PU  
Port 5 General Purpose I/O Line 4  
T13HRB  
CCPOS1A  
T2EUDB  
T2EUDA  
EN00  
CCU62  
I
CCU63  
I
GPT120  
I
GPT121  
O1  
MSC0 Device Select Output 0  
MLI0 Receive Channel ready Output B  
OUT76 Line of GPTA0  
RREADY0B O2  
OUT76 O3  
Data Sheet  
37  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P5.5  
Ctrl. Type Function  
E15  
I/O  
I
A1+/ Port 5 General Purpose I/O Line 5  
PU  
SDI0  
MSC0 Serial Data Input  
T12HRC  
T13HRC  
CCPOS2A  
T4EUDB  
T4EUDA  
OUT77  
OUT77  
OUT101  
P5.6  
I
CCU62  
I
CCU62  
I
CCU63  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
I/O  
I
OUT77 Line of GPTA0  
OUT77 Line of GPTA1  
OUT101 Line of LTCA2  
Port 5 General Purpose I/O Line 6  
CCU62  
B20  
A2/  
PU  
CC60INA  
CC60INB  
EN10  
I
CCU63  
O1  
O2  
O3  
I/O  
I
MSC1 Device Select Output 0  
MLI0 transmit Channel valid Output B  
CCU62  
TVALID0B  
CC60  
D16  
P5.7  
A1+/ Port 5 General Purpose I/O Line 7  
PU  
SDI1  
MSC1 Serial Data Input  
CC61INA  
CC61INB  
OUT79  
OUT79  
CC61  
I
CCU62  
I
CCU63  
O1  
O2  
O3  
OUT79 Line of GPTA0  
OUT79 Line of GPTA1  
CCU62  
Data Sheet  
38  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P5.8  
Ctrl. Type Function  
B16  
I/O  
F/  
Port 5 General Purpose I/O Line 8  
PU  
CC62INA  
CC62INB  
SON0  
I
CCU62  
CCU63  
I
O1  
MSC0 Differential Driver Serial Data Output  
Negative  
OUT80  
CC62  
P5.9  
O2  
O3  
I/O  
O1  
OUT80 Line of GPTA0  
CCU62  
B17  
A16  
A17  
D14  
F/  
PU  
Port 5 General Purpose I/O Line 9  
SOP0A  
MSC0 Differential Driver Serial Data Output  
Positive A  
OUT81  
COUT60  
P5.10  
O2  
O3  
I/O  
O1  
OUT81 Line of GPTA0  
CCU62  
F/  
PU  
Port 5 General Purpose I/O Line 10  
FCLN0  
MSC0 Differential Driver Clock Output  
Negative  
OUT82  
COUT61  
P5.11  
O2  
O3  
I/O  
O1  
OUT82 Line of GPTA0  
CCU62  
F/  
PU  
Port 5 General Purpose I/O Line 11  
FCLP0A  
MSC0 Differential Driver Clock Output  
Positive A  
OUT83  
COUT62  
P5.12  
O2  
O3  
I/O  
O1  
OUT83 Line of GPTA0  
CCU62  
F/  
PU  
Port 5 General Purpose I/O Line 12  
SON1  
MSC1 Differential Driver Serial Data Output  
Negative  
OUT84  
OUT84  
O2  
O3  
OUT84 Line of GPTA0  
OUT84 Line of GPTA1  
Data Sheet  
39  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P5.13  
Ctrl. Type Function  
B14  
I/O  
O1  
F/  
Port 5 General Purpose I/O Line 13  
PU  
SOP1A  
MSC1 Differential Driver Serial Data Output  
Positive A  
OUT85  
OUT85  
P5.14  
O2  
O3  
I/O  
O1  
OUT85 Line of GPTA0  
OUT85 Line of GPTA1  
B13  
A13  
F/  
PU  
Port 5 General Purpose I/O Line 14  
FCLN1  
MSC1 Differential Driver Clock Output  
Negative  
OUT86  
OUT86  
P5.15  
O2  
O3  
I/O  
O1  
OUT86 Line of GPTA0  
OUT86 Line of GPTA1  
F/  
PU  
Port 5 General Purpose I/O Line 15  
FCLNP1A  
MSC1 Differential Driver Clock Output  
Positive A  
OUT87  
OUT87  
O2  
O3  
OUT87 Line of GPTA0  
OUT87 Line of GPTA1  
Port 6  
B4  
P6.4  
I/O  
A1+/ Port 6 General Purpose I/O Line 4  
PU  
MTSR1  
MRSTG1  
I
I
SSC1 Slave Receive Input (Slave Mode)  
SSC Guardian 1 Master Receive Input  
(Master Mode)  
MTSR1  
O1  
SSC1 Master Transmit Output (Master  
Mode)3)  
Reserved  
Reserved  
O2  
O3  
-
-
Data Sheet  
40  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P6.5  
Ctrl. Type Function  
A3  
I/O  
I
A1+/ Port 6 General Purpose I/O Line 5  
PU  
MRST1  
MRST1  
Reserved  
Reserved  
P6.6  
SSC1 Master Receive Input (Master Mode)  
O1  
O2  
O3  
I/O  
I
SSC1 Slave Transmit Output (Slave Mode)  
-
-
A4  
D5  
B5  
A1+/ Port 6 General Purpose I/O Line 6  
PU  
SCLK1  
SCLK1  
Reserved  
Reserved  
P6.7  
SSC1 Clock Input/Output  
O1  
O2  
O3  
I/O  
I
SSC1 Clock Input/Output  
-
-
A1+/ Port 6 General Purpose I/O Line 7  
PU  
SLSI1  
SSC1 slave Select Input  
T6OFL  
Reserved  
Reserved  
P6.8  
O1  
O2  
O3  
I/O  
I
GPT120  
-
-
A2/  
PU  
Port 6 General Purpose I/O Line 8  
RXDCAN0  
CAN Node 0 Receiver Input 0  
CAN Node 3 Receiver Input 1  
RXD0B  
I
ASC0 Receiver Input/Output B  
CAPINB  
CAPINA  
Reserved  
RXD0B  
I
GPT120  
I
GPT121  
O1  
O2  
O3  
-
ASC0 Receiver Input/Output B  
-
Reserved  
Data Sheet  
41  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P6.9  
Ctrl. Type Function  
A5  
I/O  
O1  
O2  
O3  
I/O  
I
A2/  
PU  
Port 6 General Purpose I/O Line 9  
CAN Node 0 Transmitter Output  
ASC0 Transmitter Output B  
GPT120  
TXDCAN0  
TXD0  
T60FL  
C2  
P6.10  
A2/  
PU  
Port 6 General Purpose I/O Line 10  
RXDCAN1  
CAN Node 1 Receiver Input 0  
CAN Node 0 Receiver Input 1  
RXD1B  
Reserved  
RXD1B  
TXENA  
I
ASC1 Receiver Input/Output B  
O1  
O2  
O3  
-
ASC1 Receiver Input/Output B  
E-Ray Channel A transmit Data Output  
enable 2)  
D2  
B1  
P6.11  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 6 General Purpose I/O Line 11  
CAN Node 1 Transmitter Output  
ASC1 Transmitter Output B  
TXDCAN1  
TXD1  
TXENB  
E-Ray Channel B transmit Data Output  
enable 2)  
P6.12  
I/O  
I
A1/  
PU  
Port 6 General Purpose I/O Line 12  
RXDCAN2  
CAN Node 2 Receiver Input 0  
CAN Node 1 Receiver Input 1  
RXDA1  
I
E-Ray Channel A Receive Data Input 1 2)  
Reserved  
Reserved  
COUT61  
O1  
O2  
O3  
-
-
CCU60  
Data Sheet  
42  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P6.13  
Ctrl. Type Function  
C1  
I/O  
O1  
O2  
O3  
I/O  
I
A2/  
PU  
Port 6 General Purpose I/O Line 13  
CAN Node 2 Transmitter Output  
E-Ray Channel A transmit Data Output 2)  
CCU60  
TXDCAN2  
TXDA  
COUT62  
P6.14  
D1  
A1/  
PU  
Port 6 General Purpose I/O Line 14  
RXDCAN3  
CAN Node 3 Receiver Input 0  
CAN Node 2 Receiver Input 1  
RXDB1  
I
E-Ray Channel B Receive Data Input 1 2)  
Reserved  
Reserved  
COUT63  
P6.15  
O1  
O2  
O3  
I/O  
I
-
-
CCU60  
E1  
A2/  
PU  
Port 6 General Purpose I/O Line 15  
CC60INB  
CC60INA  
TXDCAN3  
TXDB  
CCU60  
I
CCU61  
O1  
O2  
O3  
CAN Node 3 Transmitter Output  
E-Ray Channel B transmit Data Output 2)  
CCU61  
CC60  
Port 7  
H5  
P7.0  
I/O  
A1+/ Port 7 General Purpose I/O Line 0  
PU  
MRST3  
REQ4  
I
I
SSC3 Master Receive Input (Slave Mode)  
External trigger Input 4  
AD2EMUX2 O1  
ADC2 external multiplexer Control Output 2  
SSC3 Slave Transmit Output (Master Mode)  
-
MRST3  
O2  
O3  
Reserved  
Data Sheet  
43  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P7.1  
Ctrl. Type Function  
J1  
I/O  
A1+/ Port 7 General Purpose I/O Line 1  
PU  
REQ5  
I
I
I
External trigger Input 5  
MTSR3  
MRSTG3B  
SSC3 Slave Receive Input (Slave Mode)  
SSC Guardian 3 Master Receive Input B  
(Master Mode)  
AD0EMUX2 O1  
ADC0 external multiplexer Control Output 2  
MTSR3  
O2  
SSC3 Master Transmit Output (Master  
Mode)3)  
Reserved  
P7.2  
O3  
I/O  
I
-
J2  
A1+/ Port 7 General Purpose I/O Line 2  
PU  
SCLK3  
SSC3 Input  
AD0EMUX0 O1  
ADC0 external multiplexer Control Output 0  
SCLK3  
Reserved  
P7.3  
O2  
O3  
I/O  
SSC3 Output  
-
J4  
J5  
A1+/ Port 7 General Purpose I/O Line 3  
PU  
AD0EMUX1 O1  
ADC0 external multiplexer Control Output 1  
SLSO30  
Reserved  
P7.4  
O2  
O3  
I/O  
I
SSC3 Output  
-
A1+/ Port 7 General Purpose I/O Line 4  
PU  
REQ6  
External trigger Input 6  
AD2EMUX0 O1  
ADC2 external multiplexer Control Output 0  
SLSO31  
O2  
O3  
SSC3 Output  
-
Reserved  
Data Sheet  
44  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P7.5  
Ctrl. Type Function  
K4  
I/O  
I
A1+/ Port 7 General Purpose I/O Line 5  
PU  
REQ7  
External trigger Input 7  
AD2EMUX1 O1  
ADC2 external multiplexer Control Output 1  
SLSO32  
O2  
O3  
SSC3 Output  
-
Reserved  
Port 8  
F1  
P8.0  
I/O  
A2/  
PU  
Port 8 General Purpose I/O Line 0  
IN40 Line of GPTA0  
IN40 Line of GPTA1  
SENT Digital Input  
IN40  
I
IN40  
I
SENT0  
OUT40  
COUT62  
TCLK1  
P8.1  
I
O1  
O2  
O3  
I/O  
I
OUT40 Line of GPTA0  
CCU61  
MLI1 transmit Channel Clock Output  
Port 8 General Purpose I/O Line 1  
IN41 Line of GPTA0  
IN41 Line of GPTA1  
MLI1 transmit Channel ready Input A  
SENT Digital Input  
E6  
A1/  
PU  
IN41  
IN41  
I
TREADY1A  
SENT1  
CC61INA  
CC61INB  
OUT41  
CC61  
I
I
I
CCU60  
I
CCU61  
O1  
O2  
O3  
OUT41 Line of GPTA0  
CCU60  
SENT1  
SENT Digital Output  
Data Sheet  
45  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P8.2  
Ctrl. Type Function  
E4  
I/O  
A2/  
PU  
Port 8 General Purpose I/O Line 2  
IN42 Line of GPTA0  
IN42 Line of GPTA1  
SENT Digital Input  
GPT120  
IN42  
I
IN42  
I
SENT2  
CAPINA  
CAPINB  
COUT63  
OUT42  
TVALID1A  
P8.3  
I
I
I
GPT121  
O1  
O2  
O3  
I/O  
I
CCU61  
OUT42 Line of GPTA1  
MLI1 transmit Channel valid Output A  
Port 8 General Purpose I/O Line 3  
IN43 Line of GPTA0  
IN43 Line of GPTA1  
SENT Digital Input  
CCU60  
E2  
A2/  
PU  
IN43  
IN43  
I
SENT3  
CC62INA  
CC62INB  
OUT43  
CC62  
I
I
I
CCU61  
O1  
O2  
O3  
OUT43 Line of GPTA0  
CCU60  
TDATA1  
MLI1 transmit Channel Data Output A  
Data Sheet  
46  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P8.4  
Ctrl. Type Function  
F2  
I/O  
A1/  
PU  
Port 8 General Purpose I/O Line 4  
IN44 Line of GPTA0  
IN44 Line of GPTA1  
MLI1 Receive Channel Clock Input A  
SENT Digital Input  
CCU60  
IN44  
I
IN44  
I
RCLK1A  
SENT4  
CC62INB  
CC62INA  
OUT44  
CC62  
I
I
I
I
CCU61  
O1  
OUT44 Line of GPTA0  
CCU61  
O2  
T3OUT  
P8.5  
O3  
GPT121  
F5  
I/O  
A2/  
PU  
Port 8 General Purpose I/O Line 5  
IN45 Line of GPTA0  
IN45 Line of GPTA1  
SENT Digital Input  
CCU60  
IN45  
I
IN45  
I
SENT5  
CTRAPA  
CTRAPB  
CC60INC  
T12HRE  
CC61INC  
OUT45  
OUT45  
I
I
I
CCU62  
I
CCU60  
I
CCU61  
I
CCU61  
O1  
O2  
OUT45 Line of GPTA0  
OUT45 Line of GPTA1  
MLI1 Receive Channel ready Output A  
RREADY1A O3  
Data Sheet  
47  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P8.6  
Ctrl. Type Function  
G4  
I/O  
A1/  
PU  
Port 8 General Purpose I/O Line 6  
IN46 Line of GPTA0  
IN46 Line of GPTA1  
MLI1 Receive Channel valid Input A  
SENT Digital Input  
IN46  
I
IN46  
I
RVALID1A  
SENT6  
OUT46  
COUT60  
T6OUT  
P8.7  
I
I
O1  
O2  
O3  
I/O  
I
OUT46 Line of GPTA0  
CCU61  
GPT120  
F4  
A1/  
PU  
Port 8 General Purpose I/O Line 7  
IN47 Line of GPTA0  
IN47 Line of GPTA1  
MLI1 Receive Channel Data Input A  
SENT Digital Input  
IN47  
IN47  
I
RDATA1A  
SENT7  
OUT47  
COUT61  
T6OUT  
I
I
O1  
O2  
O3  
OUT47 Line of GPTA0  
CCU61  
GPT121  
Port 9  
E17  
P9.0  
I/O  
I
A2/  
PU  
Port 9 General Purpose I/O Line 0  
IN48 Line of GPTA0  
IN48  
IN48  
I
IN48 Line of GPTA1  
COUT63  
OUT48  
EN12  
O1  
O2  
O3  
CCU62  
OUT48 Line of GPTA1  
MSC1 Device Select Output 2  
Data Sheet  
48  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P9.1  
Ctrl. Type Function  
D19  
I/O  
A2/  
PU  
Port 9 General Purpose I/O Line 1  
IN49 Line of GPTA0  
IN49 Line of GPTA1  
CCU62  
IN49  
I
IN49  
I
CC60INB  
CC60INA  
CC60  
I
I
CCU63  
O1  
O2  
O3  
I/O  
I
CCU63  
OUT49  
EN11  
OUT49 Line of GPTA1  
MSC1 Device Select Output 1  
Port 9 General Purpose I/O Line 2  
IN50 Line of GPTA0  
IN50 Line of GPTA1  
CCU62  
D20  
P9.2  
A2/  
PU  
IN50  
IN50  
I
CC61INB  
CC61INA  
CC61  
I
I
CCU63  
O1  
O2  
O3  
I/O  
I
CCU63  
OUT50  
SOP1B  
P9.3  
OUT50 Line of GPTA1  
MSC1 serial Data Output  
Port 9 General Purpose I/O Line 3  
IN51 Line of GPTA0  
IN51 Line of GPTA1  
CCU62  
C20  
A2/  
PU  
IN51  
IN51  
I
CC62INB  
CC62INA  
CC62  
I
I
CCU63  
O1  
O2  
O3  
CCU63  
OUT51  
FCLP1B  
OUT51 Line of GPTA1  
MSC1 Clock Output  
Data Sheet  
49  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P9.4  
Ctrl. Type Function  
C19  
I/O  
I
A2/  
PU  
Port 9 General Purpose I/O Line 4  
IN52 Line of GPTA0  
IN52  
IN52  
I
IN52 Line of GPTA1  
COUT60  
OUT52  
EN03  
P9.5  
O1  
O2  
O3  
I/O  
I
CCU63  
OUT52 Line of GPTA1  
MSC0 Device Select Output 3  
Port 9 General Purpose I/O Line 5  
IN53 Line of GPTA0  
F17  
A2/  
PU  
IN53  
IN53  
I
IN53 Line of GPTA1  
SENT1  
COUT61  
OUT53  
EN02  
P9.6  
I
SENT Digital Input  
O1  
O2  
O3  
I/O  
I
CCU63  
OUT53 Line of GPTA1  
MSC0 Device Select Output 2  
Port 9 General Purpose I/O Line 6  
IN54 Line of GPTA0  
F16  
A2/  
PU  
IN54  
IN54  
I
IN54 Line of GPTA1  
SENT3  
OUT54  
SENT3  
EN01  
I
SENT Digital Input  
O1  
O2  
O3  
OUT54 Line of GPTA0  
SENT Digital Output  
MSC0 Device Select Output 1  
Data Sheet  
50  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P9.7  
Ctrl. Type Function  
E20  
I/O  
I
A2/  
PU  
Port 9 General Purpose I/O Line 7  
IN55 Line of GPTA0  
IN55 Line of GPTA1  
SENT Digital Input  
OUT55 Line of GPTA0  
SENT Digital Output  
MSC0 serial Data Output  
Port 9 General Purpose I/O Line 8  
SENT Digital Input  
CCU63  
IN55  
IN55  
I
SENT4  
OUT55  
SENT4  
SOP0B  
P9.8  
I
O1  
O2  
O3  
I/O  
I
E19  
F20  
A2/  
PU  
SENT6  
COUT62  
SENT6  
FCLP0B  
P9.10  
O1  
O2  
O3  
I/O  
I
SENT Digital Output  
MSC0 Clock Output  
Port 9 General Purpose I/O Line 10  
Emergency Stop  
SENT Digital Input  
CCU63  
A1/  
PU  
EMGSTOP  
SENT7  
COUT63  
SENT7  
Reserved  
P9.13  
I
O1  
O2  
O3  
I/O  
I
SENT Digital Output  
-
G16  
A2/  
PU  
Port 9 General Purpose I/O Line 13  
OCDS Break Input  
TTCAN Input  
BRKIN  
ECTT1  
Reserved  
Reserved  
Reserved  
BRKOUT  
I
O1  
O2  
O3  
O
-
-
-
OCDS Break Output  
Data Sheet  
51  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P9.14  
Ctrl. Type Function  
H16  
I/O  
I
A2/  
PU  
Port 9 General Purpose I/O Line 14  
BRKIN  
OCDS Break Input  
ECTT2  
I
TTCAN Input  
REQ15  
I
External trigger Input 15  
Reserved  
Reserved  
Reserved  
BRKOUT  
O1  
O2  
O3  
O
-
-
-
OCDS Break Output  
Port 10  
Y15  
P10.0  
I/O  
I
A2/  
PU  
Port 10 General Purpose I/O Line 0  
SSC0 Master Receive Input (Master Mode)  
SSC0 Slave Transmit Output (Slave Mode)  
-
MRST0  
MRST0  
Reserved  
Reserved  
P10.1  
O1  
O2  
O3  
I/O  
I
-
W15  
A2/  
PU  
Port 10 General Purpose I/O Line 1  
SSC0 Slave Receive Input (Slave Mode)  
MTSR0  
MRSTG0  
I
SSC Guardian 0 Master Receive Input  
(Master Mode)  
MTSR0  
O1  
SSC0 Master Transmit Output (Master  
Mode)  
Reserved  
Reserved  
O2  
O3  
-
-
Data Sheet  
52  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P10.2  
Ctrl. Type Function  
U16  
I/O  
I
A1/  
PU  
Port 10 General Purpose I/O Line 2  
SLSI0  
SSC0 Slave Select Input  
Reserved  
Reserved  
Reserved  
P10.3  
O1  
O2  
O3  
I/O  
I
-
-
-
Y14  
A2/  
PU  
Port 10 General Purpose I/O Line 3  
SCLK0  
SSC0 Clock Input/Output  
SCLK0  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
SSC0 Clock Input/Output  
Reserved  
Reserved  
P10.4  
-
-
W16  
Y16  
A1+/ Port 10 General Purpose I/O Line 4  
PU  
SLSO0  
SSC0 Slave Select Output Line 0  
Reserved  
Reserved  
P10.5  
-
-
A1+/ Port 10 General Purpose I/O Line 5  
PU  
SLSO1  
SSC0 Slave Select Output Line 1  
Reserved  
Reserved  
-
-
Port 13  
M16  
P13.0  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 13 General Purpose I/O Line 0  
OUT88 Line of GPTA0  
OUT88  
OUT88  
OUT80  
OUT88 Line of GPTA1  
OUT80 Line of LTCA2  
Data Sheet  
53  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P13.1  
Ctrl. Type Function  
M17  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 13 General Purpose I/O Line 1  
OUT89 Line of GPTA0  
OUT89  
OUT89  
OUT81  
P13.2  
OUT89 Line of GPTA1  
OUT81 Line of LTCA2  
N16  
N17  
N19  
N20  
P16  
A2/  
PU  
Port 13 General Purpose I/O Line 2  
OUT90 Line of GPTA0  
OUT90  
OUT90  
OUT82  
P13.3  
OUT90 Line of GPTA1  
OUT82 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 3  
OUT91 Line of GPTA0  
OUT91  
OUT91  
OUT83  
P13.4  
OUT91 Line of GPTA1  
OUT83 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 4  
OUT92 Line of GPTA0  
OUT92  
OUT92  
OUT84  
P13.5  
OUT92 Line of GPTA1  
OUT84 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 5  
OUT93 Line of GPTA0  
OUT93  
OUT93  
OUT85  
P13.6  
OUT93 Line of GPTA1  
OUT85 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 6  
OUT94 Line of GPTA0  
OUT94  
OUT94  
OUT86  
OUT94 Line of GPTA1  
OUT86 Line of LTCA2  
Data Sheet  
54  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P13.7  
Ctrl. Type Function  
P17  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 13 General Purpose I/O Line 7  
OUT95 Line of GPTA0  
OUT95  
OUT95  
OUT87  
P13.8  
OUT95 Line of GPTA1  
OUT87 Line of LTCA2  
P19  
P20  
R17  
R19  
R20  
A2/  
PU  
Port 13 General Purpose I/O Line 8  
OUT96 Line of GPTA0  
OUT96  
OUT96  
OUT88  
P13.9  
OUT96 Line of GPTA1  
OUT88 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 9  
OUT97 Line of GPTA0  
OUT97  
OUT97  
OUT89  
P13.10  
OUT98  
OUT98  
OUT90  
P13.11  
OUT99  
OUT99  
OUT91  
P13.12  
OUT100  
OUT100  
OUT92  
OUT97 Line of GPTA1  
OUT89 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 10  
OUT98 Line of GPTA0  
OUT98 Line of GPTA1  
OUT90 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 11  
OUT99 Line of GPTA0  
OUT99 Line of GPTA1  
OUT91 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 12  
OUT100 Line of GPTA0  
OUT100 Line of GPTA1  
OUT92 Line of LTCA2  
Data Sheet  
55  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P13.13  
Ctrl. Type Function  
T19  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 13 General Purpose I/O Line 13  
OUT101 Line of GPTA0  
OUT101  
OUT101  
OUT93  
P13.14  
OUT101 Line of GPTA1  
OUT93 Line of LTCA2  
T20  
U19  
A2/  
PU  
Port 13 General Purpose I/O Line 14  
OUT102 Line of GPTA0  
OUT102  
OUT102  
OUT94  
P13.15  
OUT102 Line of GPTA1  
OUT94 Line of LTCA2  
A2/  
PU  
Port 13 General Purpose I/O Line 15  
OUT103 Line of GPTA0  
OUT103  
OUT103  
OUT95  
OUT103 Line of GPTA1  
OUT95 Line of LTCA2  
Port 14  
U20  
P14.0  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 14 General Purpose I/O Line 0  
CCU60  
CC60  
OUT96  
OUT96  
P14.2  
OUT96 Line of GPTA1  
OUT96 Line of LTCA2  
Port 14 General Purpose I/O Line 2  
CCU60  
V20  
A2/  
PU  
CC62  
OUT98  
OUT98  
P14.4  
OUT98 Line of GPTA1  
OUT98 Line of LTCA2  
Port 14 General Purpose I/O Line 4  
CCU60  
W18  
A2/  
PU  
COUT61  
OUT100  
OUT100  
OUT100 Line of GPTA1  
OUT100 Line of LTCA2  
Data Sheet  
56  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P14.6  
Ctrl. Type Function  
Y19  
I/O  
O1  
O2  
O3  
I/O  
O1  
O2  
O3  
A2/  
PU  
Port 14 General Purpose I/O Line 6  
CCU60  
COUT63  
OUT102  
OUT102  
P14.8  
OUT102 Line of GPTA1  
OUT102 Line of LTCA2  
Port 14 General Purpose I/O Line 8  
CCU61  
Y18  
A2/  
PU  
CC61  
T3OUT  
OUT104  
GPT120  
OUT104 Line of LTCA2  
Port 17  
R5  
P17.0  
SENT0  
AN8  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D / S Port 17 General Purpose I Line 04)  
SENT Digital Input 0  
Analog Input : ADC0.CH8 5)  
D / S Port 17 General Purpose I Line 14)  
SENT Digital Input 1  
R4  
P5  
P4  
P2  
P17.1  
SENT1  
AN9  
Analog Input : ADC0.CH9 5)  
D / S Port 17 General Purpose I Line 24)  
SENT Digital Input 2  
P17.2  
SENT2  
AN10  
P17.3  
SENT3  
AN11  
P17.4  
SENT4  
AN12  
Analog Input : ADC0.CH10 5)  
D / S Port 17 General Purpose I Line 34)  
SENT Digital Input 3  
Analog Input : ADC0.CH11 5)  
D / S Port 17 General Purpose I Line 44)  
SENT Digital Input 4  
Analog Input : ADC0.CH12 5)  
Data Sheet  
57  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P17.5  
Ctrl. Type Function  
D / S Port 17 General Purpose I Line 54)  
P1  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SENT5  
AN13  
SENT Digital Input 5  
Analog Input : ADC0.CH13 5)  
D / S Port 17 General Purpose I Line 64)  
SENT Digital Input 6  
N2  
N1  
W4  
Y4  
W5  
Y5  
T6  
P17.6  
SENT6  
AN14  
Analog Input : ADC0.CH14 5)  
D / S Port 17 General Purpose I Line 74)  
SENT Digital Input 7  
P17.7  
SENT7  
AN15  
Analog Input : ADC0.CH15 5)  
D / S Port 17 General Purpose I Line 84)  
SENT Digital Input 0  
P17.8  
SENT0  
AN36  
Analog Input : ADC2.CH4 5)  
D / S Port 17 General Purpose I Line 94)  
SENT Digital Input 1  
P17.9  
SENT1  
AN37  
Analog Input : ADC2.CH5 5)  
D / S Port 17 General Purpose I Line 104)  
SENT Digital Input 2  
P17.10  
SENT2  
AN38  
Analog Input : ADC2.CH6 5)  
D / S Port 17 General Purpose I Line 114)  
SENT Digital Input 3  
P17.11  
SENT3  
AN39  
Analog Input : ADC2.CH7 5)  
D / S Port 17 General Purpose I Line 124)  
SENT Digital Input 4  
P17.12  
SENT4  
AN40  
Analog Input : ADC2.CH8 5)  
Data Sheet  
58  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
P17.13  
SENT5  
AN41  
Ctrl. Type Function  
U6  
I
I
I
I
I
I
I
I
I
D / S Port 17 General Purpose I Line 134)  
SENT Digital Input 5  
Analog Input : ADC2.CH9 5)  
D / S Port 17 General Purpose I Line 144)  
SENT Digital Input 6  
T7  
U7  
P17.14  
SENT6  
AN42  
Analog Input : ADC2.CH10 5)  
D / S Port 17 General Purpose I Line 154)  
SENT Digital Input 7  
P17.15  
SENT7  
AN43  
Analog Input : ADC2.CH11 5)  
Analog Input Port  
T4  
Y2  
W2  
W1  
V2  
U2  
T2  
T5  
R5  
R4  
P5  
P4  
P2  
P1  
N2  
N1  
AN0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
Analog Input 0: ADC0.CH0 5)  
Analog Input 1: ADC0.CH1 5)  
Analog Input 2: ADC0.CH2 5)  
Analog Input 3: ADC0.CH3 5)  
Analog Input 4: ADC0.CH4 5)  
Analog Input 5: ADC0.CH5 5)  
Analog Input 6: ADC0.CH6 5)  
Analog Input 7: ADC0.CH7 5)  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
D / S Analog Input 8: ADC0.CH8, SENT0 5)  
D / S Analog Input 9: ADC0.CH9, SENT1 5)  
D / S Analog Input 10: ADC0.CH10, SENT2 5)  
D / S Analog Input 11: ADC0.CH11, SENT3 5)  
D / S Analog Input 12: ADC0.CH12, SENT4 5)  
D / S Analog Input 13: ADC0.CH13, SENT5 5)  
D / S Analog Input 14: ADC0.CH14, SENT6 5)  
D / S Analog Input 15: ADC0.CH15, SENT7 5)  
AN9  
AN10  
AN11  
AN12  
AN13  
AN14  
AN15  
Data Sheet  
59  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
N5  
Pin Definitions and Functions (cont’d)  
Ctrl. Type Function  
Symbol  
AN16  
AN17  
AN18  
AN19  
AN20  
AN21  
AN22  
AN23  
AN24  
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
D
Analog Input 16: ADC1.CH0 5)  
Analog Input 17: ADC1.CH1 5)  
Analog Input 18: ADC1.CH2 5)  
Analog Input 19: ADC1.CH3 5)  
Analog Input 20: ADC1.CH4 5)  
Analog Input 21: ADC1.CH5 5)  
Analog Input 22: ADC1.CH6 5)  
Analog Input 23: ADC1.CH7 5)  
N4  
M5  
M4  
M2  
M1  
L2  
L1  
U8  
Analog Input 24: ADC1.CH8,  
FADC_FADIN0P 6)  
W8  
Y8  
AN25  
AN26  
AN27  
AN28  
AN29  
AN30  
AN31  
I
I
I
I
I
I
I
D
D
D
D
D
D
D
Analog Input 25: ADC1.CH9,  
FADC_FADIN0N 6)  
Analog Input 26: ADC1.CH10,  
FADC_FADIN1P 6)  
T9  
Analog Input 27: ADC1.CH11,  
FADC_FADIN1N 6)  
U9  
W9  
Y9  
Analog Input 28: ADC1.CH12,  
FADC_FADIN2P 6)  
Analog Input 29: ADC1.CH13,  
FADC_FADIN2N 6)  
Analog Input 30: ADC1.CH14,  
FADC_FADIN3P 6)  
T10  
Analog Input 31: ADC1.CH15,  
FADC_FADIN3N 6)  
U4  
W3  
Y3  
T8  
AN32  
AN33  
AN34  
AN35  
I
I
I
I
D
D
D
D
Analog Input 32: ADC2.CH0 5)  
Analog Input 33: ADC2.CH1 5)  
Analog Input 34: ADC2.CH2 5)  
Analog Input 35: ADC2.CH3 5)  
Data Sheet  
60  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
W4  
Y4  
Pin Definitions and Functions (cont’d)  
Ctrl. Type Function  
Symbol  
AN36  
AN37  
AN38  
AN39  
AN40  
AN41  
AN42  
AN43  
AN44  
AN45  
AN46  
AN47  
I
I
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
D
D
D
D
Analog Input 36: ADC2.CH4, SENT0 5)  
Analog Input 37: ADC2.CH5, SENT1 5)  
Analog Input 38: ADC2.CH6, SENT2 5)  
Analog Input 39: ADC2.CH7, SENT3 5)  
Analog Input 40: ADC2.CH8, SENT4 5)  
Analog Input 41: ADC2.CH9, SENT5 5)  
Analog Input 42: ADC2.CH10, SENT6 5)  
Analog Input 43: ADC2.CH11, SENT7 5)  
Analog Input 44: ADC2.CH12 5)  
W5  
Y5  
T6  
U6  
T7  
U7  
V1  
U1  
Analog Input 45: ADC2.CH13 5)  
T1  
Analog Input 46: ADC2.CH14 5)  
U5  
Analog Input 47: ADC2.CH15 5)  
System I/O  
F19  
G19  
PORST  
I
PD  
A2  
Power-on Reset Input  
ESR0  
I/O  
External System Request Reset Input 0  
Default configuration during and after reset is  
open-drain driver. The driver drives low during  
power-on reset.  
G20  
H20  
ESR1  
I/O  
A2/  
PD  
External System Request Reset Input 1  
TCK  
I
PD  
JTAG Module Clock Input  
DAP0  
I
Device Access Port Line 0  
J17  
TDI  
I
A2/  
PU  
JTAG Module Serial Data Input  
OCDS Break Input (Alternate Output)  
OCDS Break Output (Alternate Input)  
Test Mode Select Input  
BRKIN  
BRKOUT  
TESTMODE  
I
O
I
G17  
PU  
Data Sheet  
61  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
TMS  
Ctrl. Type Function  
J16  
I
A2/  
PD  
JTAG Module State Machine Control Input  
Device Access Port Line 1  
DAP1  
I/O  
I
H19  
K20  
K19  
H17  
TRST  
XTAL1  
XTAL2  
TDO  
PD  
JTAG Module Reset/Enable Input  
Main Oscillator/PLL/Clock Generator Input  
Main Oscillator/PLL/Clock Generator Output  
JTAG Module Serial Data Output  
OCDS Break Input (Alternate Input)  
OCDS Break Output (Alternate Output)  
Device Access Port Line 2  
I
O
O
I
A2/  
PU  
BRKIN  
BRKOUT  
DAP2  
O
O
Power Supply  
R2  
R1  
Y6  
W6  
W7  
Y7  
VDDM  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC Analog Part Power Supply (3.3V - 5V)  
ADC Analog Part Ground  
ADC0 Reference Voltage  
VSSM  
VAREF0  
VAREF1  
VAREF2  
VAGND0  
VAGND1  
VAGND2  
VFAREF  
VFAGND  
VDDMF  
VDDAF  
ADC1 Reference Voltage  
ADC2 Reference Voltage  
ADC0 Reference Ground  
ADC1 Reference Ground  
ADC2 Reference Ground  
U10  
W10  
U11  
T11  
FADC Reference Voltage  
FADC Reference Ground  
FADC Analog Part Power Supply (3.3V)  
FADC Analog Part Logic Power Supply  
(1.3V)  
Y10  
VSSMF  
VSSAF  
-
-
-
-
FADC Analog Part Ground  
FADC Analog Part Logic Ground  
Data Sheet  
62  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
Ctrl. Type Function  
K5,  
VDDFL3  
-
-
Flash Power Supply (3.3V)  
L16  
J20  
VSSOSC  
VSSOSC3  
VDDOSC  
VDDOSC3  
VDDPF  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Oscillator Ground (Main & E-Ray)  
Oscillator Ground (Main & E-Ray)  
Main Oscillator Power Supply (1.3V)  
Main Oscillator Power Supply (3.3V)  
E-Ray PLL Power Supply (1.3V)  
E-Ray PLL Power Supply (3.3V)  
Digital Core Power Supply (1.3V)  
J19  
K16  
K17  
L17  
VDDPF3  
VDD  
G8,  
G13,  
H7,  
H14,  
N7,  
N14,  
P8,  
P13,  
R16,  
T17,  
V19,  
W20  
A2,  
VDDP  
-
-
Port Power Supply (3.3V)  
A19,  
B3,  
B10,  
B18,  
K2,  
M19,  
M20,  
W11,  
W17  
L4, L5 VDDSB  
-
-
Emulation Stand-by SRAM Power Supply  
(1.3V) (Emulation device only)  
Note: This pin is N.C. in a productive device.  
Data Sheet  
63  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
Ctrl. Type Function  
P9,  
VSS  
-
-
Digital Ground (center balls)  
P10,  
P11,  
P12,  
N9,  
N10,  
N11,  
N12  
M7,  
VSS  
-
-
Digital Ground (center balls cont’d)  
M8,  
M10,  
M11,  
M13,  
M14,  
J7, J8,  
J10,  
J11,  
J13,  
J14  
L7,L8, VSS  
L9,  
L10,  
L11,  
L12,  
-
-
-
-
Digital Ground (center balls cont’d)  
Digital Ground (center balls cont’d)  
L13,  
L14  
K7,  
VSS  
K8,  
K9,  
K10,  
K11,  
K12,  
K13,  
K14  
Data Sheet  
64  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Table 2  
Pin  
Pin Definitions and Functions (cont’d)  
Symbol  
Ctrl. Type Function  
G9,  
VSS  
-
-
Digital Ground (center balls cont’d)  
G10,  
G11,  
G12,  
H9,  
H10,  
H11,  
H12  
T16,  
U17,  
W19  
VSS  
-
-
-
-
Digital Ground (outer balls)  
Digital Ground (outer balls)  
L19,  
L20,  
Y17,  
Y20  
VSS  
A10,  
A20,  
B2,  
VSS  
-
-
Digital Ground (outer balls)  
B19,  
D4,  
D17,  
E5,  
E16,  
K1,  
Y11  
A1, Y1 N.C.  
-
-
Not connected. These pins are reserved for  
future extension and shall not be connected  
externally.  
1) Only applicable in TC1791ED. Reserved in TC1791PD.  
2) Only available for SAK-TC1791S-512F240EP, SAK-TC1791F-512F240EP, SAK-TC1791F-512F240EL, SAK-  
TC1791S-384F200EP, SAK-TC1791F-384F200EP, and SAK-TC1791F-384F200EL.  
3) The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx  
4) Analog Input overlayed with a SENT Digitial Input. The related port logic is used configure the input as either  
analog input (default after reset) or digital input. The related port logic supports only the port input features as  
the connected pads are input pads only.  
5) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.  
6) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.  
Data Sheet  
65  
V 1.1, 2014-05  
TC1791  
PinningTC1791 Pin Configuration  
Legend for Table 2  
Column “Ctrl.”:  
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)  
O = Output  
O0 = Output with IOCR bit field selection PCx = 1X00B  
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)  
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)  
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)  
Column “Type”:  
A1 = Pad class A1 (LVTTL)  
A1+ = Pad class A1+ (LVTTL)  
A2 = Pad class A2 (LVTTL)  
F = Pad class F (LVDS/CMOS)  
D = Pad class D (ADC)  
S = Pad class S(SENT)  
PU = with pull-up device connected during reset (PORST = 0)  
PD = with pull-down device connected during reset (PORST = 0)  
TR = tri-state during reset (PORST = 0)  
Data Sheet  
66  
V 1.1, 2014-05  
TC1791  
Identification Registers  
4
Identification Registers  
The Identification Registers uniquely identify the whole device.  
Table 3  
SAK-TC1791F-512F240EL Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
0700 9502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 4  
SAK-TC1791F-512F240EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
8700 9502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 5  
SAK-TC1791F-512F200EL Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
1700 9502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 6  
SAK-TC1791F-512F200EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
9700 9502H  
F000 0408H  
F000 0464H  
F000 0640H  
AB  
AB  
Data Sheet  
67  
V 1.1, 2014-05  
TC1791  
Identification Registers  
Table 6  
SAK-TC1791F-512F200EP Identification Registers (cont’d)  
Short Name  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 1820H  
0000 0000H  
F000 0644H  
F000 0648H  
AB  
Table 7  
SAK-TC1791F-384F200EL Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
1600 9502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 8  
SAK-TC1791F-384F200EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
9600 9502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 9  
SAK-TC1791S-512F240EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
8700 AA02H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Data Sheet  
68  
V 1.1, 2014-05  
TC1791  
Identification Registers  
Table 10  
SAK-TC1791S-384F200EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
9600 AA02H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Table 11  
SAK-TC1791N-384F200EP Identification Registers  
Short Name  
CBS_JDPID  
CBS_JTAGID  
SCU_CHIPID  
SCU_MANID  
SCU_RTID  
Value  
Address  
Stepping  
AB  
0000 6350H  
1018 E083H  
9600 B502H  
0000 1820H  
0000 0000H  
F000 0408H  
F000 0464H  
F000 0640H  
F000 0644H  
F000 0648H  
AB  
AB  
AB  
AB  
Data Sheet  
69  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
5
Electrical Parameters  
This specification provides all electrical parameters of the TC1791.  
5.1  
General Parameters  
5.1.1  
Parameter Interpretation  
The parameters listed in this section partly represent the characteristics of the TC1791  
and partly its requirements on the system. To aid interpreting the parameters easily  
when evaluating them for a design, they are marked with an two-letter abbreviation in  
column “Symbol”:  
CC  
Such parameters indicate Controller Characteristics which are a distinctive feature of  
the TC1791 and must be regarded for a system design.  
SR  
Such parameters indicate System Requirements which must provided by the  
microcontroller system in which the TC1791 designed in.  
Data Sheet  
70  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
5.1.2  
Pad Driver and Pad Classes Summary  
This section gives an overview on the different pad driver classes and its basic  
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.  
Table 12  
Pad Driver and Pad Classes Overview  
Class Power Type  
Supply  
Sub Class Speed Load Leakage Termination  
1)  
Grade  
150oC 1)  
1)  
A
3.3 V  
LVTTL A1  
6 MHz 100 pF 500 nA  
No  
I/O,  
(e.g. GPIO)  
LVTTL  
outputs  
A1+  
(e.g. serial  
I/Os)  
25  
MHz  
50 pF 1 μA  
50 pF 3 μA  
Series  
termination  
recommended  
A2  
40  
Series  
(e.g. serial  
I/Os)  
MHz  
termination  
recommended  
F
3.3 V  
LVDS  
50  
Parallel  
MHz  
termination,  
100 Ω ± 10% 2)  
CMOS  
ADC  
6 MHz 50 pF  
DE  
I
5 V  
3.3 V  
LVTTL  
(input  
only)  
1) These values show typical application configurations for the pad. Complete and detailed pad parameters are  
available in the individual pad parameter table on the following pages.  
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or  
properly terminated with the differential parallel termination of 100 Ω ± 10%.  
Data Sheet  
71  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
5.1.3  
Absolute Maximum Ratings  
Stresses above the values listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions may affect device reliability.  
Table 13  
Absolute Maximum Rating Parameters  
Symbol Values  
Min. Typ. Max.  
Parameter  
Unit Note /  
Test Con  
dition  
Storage temperature  
TST  
SR -65  
150  
2.0  
°C  
Voltage at 1.3 V power supply VDD SR –  
pins with respect to VSS  
V
Voltage at 3.3 V power supply VDDP  
pins with respect to VSS SR  
4.33  
7.0  
V
V
V
Voltage at 5 V power supply VDDM SR –  
pins with respect to VSS  
Voltage on any Class A input VIN  
pin and dedicated input pins  
with respect to VSS  
SR -0.7  
VDDP + 0.5  
Whatever  
is lower  
or max. 4.33  
Voltage on any Class D  
analog input pin with respect VAREFx  
to VAGND  
VAIN  
-0.6  
-0.6  
7.0  
7.0  
V
V
SR  
SR  
Voltage on any shared Class VAINF  
D analog input pin with  
VFAREF  
respect to VSSAF, if the FADC  
is switched through to the pin.  
Input current on any pin  
during overload condition  
IIN  
-10  
-25  
+10  
+25  
mA  
mA  
Absolute maximum sum of all IIN  
input circuit currents for one  
port group during overload  
condition1)  
Absolute maximum sum of all ΣIIN  
input circuit currents during  
overload condition  
-200 –  
200  
mA  
1) The port groups are defined in Table 18.  
Data Sheet  
72  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
5.1.4  
Pin Reliability in Overload  
When receiving signals from higher voltage devices, low-voltage devices experience  
overload currents and voltages that go beyond their own IO power supplies specification.  
Table 14 defines overload conditions that will not cause any negative reliability impact if  
all the following conditions are met:  
full operation life-time (24000 h) is not exceeded  
Operating Conditions are met for  
– pad supply levels (VDDP or VDDM  
)
– temperature  
If a pin current is out of the Operating Conditions but within the overload parameters,  
then the parameters functionality of this pin as stated in the Operating Conditions can no  
longer be guaranteed. Operation is still possible in most cases but with relaxed  
parameters.  
Note: An overload condition on one or more pins does not require a reset.  
Table 14  
Overload Parameters  
Symbol  
Parameter  
Values  
Unit Note /  
Test Con  
dition  
Min. Typ. Max.  
Input current on any digital pin IIN  
during overload condition  
except LVDS pins  
-5  
+5  
mA  
Input current on LVDS pins  
IINLVDS  
IING  
-3  
+3  
mA  
mA  
Absolute sum of all input  
circuit currents for one port  
group during overload  
condition1)  
-20  
+20  
Input current on analog pins IINANA  
-3  
+3  
mA  
mA  
Absolute sum of all analog  
input currents for analog  
inputs during overload  
condition  
IINSA  
-45  
+45  
Absolute sum of all input  
circuit currents during  
overload condition  
ΣIINS  
-100 –  
100  
mA  
1) The port groups are defined in Table 18.  
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.  
Data Sheet  
73  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 15  
PN-Junction Characterisitics for positive Overload  
IIN = 3 mA IIN = 5 mA  
Pad Type  
A1 / A1+ / F  
UIN = VDDP + 0.6 V  
UIN = VDDP + 0.5 V  
UIN = VDDP + 0.7 V  
UIN = VDDM + 0.6 V  
UIN = VDDM + 0.6 V  
U
U
-
IN = VDDP + 0.7 V  
A2  
LVDS  
D
IN = VDDP + 0.6 V  
-
S
-
Table 16  
PN-Junction Characterisitics for negative Overload  
IIN = -3 mA IIN = -5 mA  
Pad Type  
A1 / A1+ / F  
UIN = VSS - 0.6 V  
UIN = VSS - 0.5 V  
UIN = VSS - 0.7 V  
UIN = VSSM - 0.6 V  
UIN = VSSM - 0.6 V  
U
U
-
IN = VSS - 0.7 V  
A2  
LVDS  
D
IN = VSS - 0.6 V  
-
S
-
Note: A series resistor at the pin to limit the current to the maximum permitted overload  
current is sufficient to handle failure situations like short to battery without having  
any negative reliability impact on the operational life-time.  
Data Sheet  
74  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
5.1.5  
Operating Conditions  
The following operating conditions must not be exceeded in order to ensure correct  
operation and reliability of the TC1791. All parameters specified in the following tables  
refer to these operating conditions, unless otherwise noticed.  
Digital supply voltages applied to the TC1791 must be static regulated voltages which  
allow a typical voltage swing of ± 5 %.  
All parameters specified in the following tables (Table 19 and following) refer to these  
operating conditions (Table 17), unless otherwise noticed in the Note / Test Condition  
column.  
The Extended Range Operating Conditions did not increase area of validity of the  
parameters defined in table 11 and later.  
Table 17  
Operating Conditions Parameters  
Symbol Values  
Parameter  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
Overload coupling factor KOVAN  
for analog inputs, negative CC  
0.0001  
IOV0 mA;  
IOV-2 mA;  
analog  
pad= 5.0 V  
Overload coupling factor KOVAP  
for analog inputs, positive CC  
0.0000  
1
IOV3 mA;  
IOV0 mA;  
analog  
pad= 5.0 V  
Data Sheet  
75  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 17  
Operating Conditions Parameters (cont’d)  
Parameter  
Symbol  
Values  
Unit Note /  
Test Condition  
Min.  
Typ. Max.  
CPU Frequency  
f
CPU SR  
240  
200  
MHz SAK-TC1791F-  
512F 240EL;  
SAK-TC1791F-  
512F 240EP;  
SAK-TC1791S-  
512F 240EP  
MHz SAK-TC1791F-  
512F 200EL  
SAK-TC1791F-  
512F 200EP;  
SAK-TC1791F-  
384F 200EL;  
SAK-TC1791F-  
384F 200EP;  
SAK-TC1791S-  
384F 200EP;  
SAK-TC1791F-  
384N 200EL;  
SAK-TC1791F-  
384N 200EP  
Data Sheet  
76  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 17  
Operating Conditions Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Modulated fCPU  
fCPU_mod  
ulated SR  
240  
MHz SAK-TC1791F-  
512F 240EL;  
SAK-TC1791F-  
512F 240EP;  
SAK-TC1791S-  
512F 240EP  
200  
MHz SAK-TC1791F-  
512F 200EL  
SAK-TC1791F-  
512F 200EP;  
SAK-TC1791F-  
384F 200EL;  
SAK-TC1791F-  
384F 200EP;  
SAK-TC1791S-  
384F 200EP;  
SAK-TC1791F-  
384N 200EL;  
SAK-TC1791F-  
384N 200EP  
FPI bus frequency  
f
FPI SR  
100  
MHz  
Modulated fFPI  
fFPI_modul  
ated SR  
100-  
MHz MA = modulatio  
n amplitude  
2*MA1)  
FSI frequency  
f
FSI SR  
150  
MHz  
Modulated fFSI  
fFSI_modul  
ated SR  
150-  
MHz MA = modulatio  
n amplitude  
2*MA1)  
PCP Frequency  
f
PCP SR  
200  
MHz  
Modulated fPCP  
fPCP_mod  
ulated SR  
200-  
MHz MA = modulatio  
n amplitude  
2*MA1)  
Data Sheet  
77  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 17  
Operating Conditions Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
SRI Frequency  
f
SRI SR  
240  
MHz SAK-TC1791F-  
512F 240EL;  
SAK-TC1791F-  
512F 240EP;  
SAK-TC1791S-  
512F 240EP  
200  
MHz SAK-TC1791F-  
512F 200EL  
SAK-TC1791F-  
512F 200EP;  
SAK-TC1791F-  
384F 200EL;  
SAK-TC1791F-  
384F 200EP;  
SAK-TC1791S-  
384F 200EP;  
SAK-TC1791F-  
384N 200EL;  
SAK-TC1791F-  
384N 200EP  
Data Sheet  
78  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 17  
Operating Conditions Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Modulated fSRI  
fSRI_modul  
ated SR  
240  
MHz SAK-TC1791F-  
512F 240EL;  
SAK-TC1791F-  
512F 240EP;  
SAK-TC1791S-  
512F 240EP  
200  
MHz SAK-TC1791F-  
512F 200EL  
SAK-TC1791F-  
512F 200EP;  
SAK-TC1791F-  
384F 200EL;  
SAK-TC1791F-  
384F 200EP;  
SAK-TC1791S-  
384F 200EP;  
SAK-TC1791F-  
384N 200EL;  
SAK-TC1791F-  
384N 200EP  
Inactive device pin current IID SR  
-1  
1
mA All power  
supply voltages  
VDDx = 0  
Short circuit current of  
digital outputs2)  
I
SC SR -5  
5
mA  
Absolute sum of short  
circuit currents of the  
device  
ΣISC_D  
CC  
100  
mA  
Absolute sum of short  
circuit currents per pin  
group  
ΣISC_PG  
CC  
20  
mA  
Ambient Temperature  
Junction temperature  
Core Supply Voltage  
TA SR  
TJ SR  
-40  
-40  
125  
°C  
°C  
150  
1.433)  
V
DD SR 1.17  
1.3  
V
for duration  
limitation see  
Section 5.1.5.1  
Data Sheet  
79  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 17  
Operating Conditions Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
3.3  
Unit Note /  
Test Condition  
Min.  
Max.  
3.635)  
Flash supply voltage 3.3V VDDFL3  
2.97  
V
for duration  
SR  
limitation see  
Section 5.1.5.1  
ADC analog supply  
voltage  
VDDM  
SR  
3.135  
5
5.54)  
V
V
Oscillator core supply  
voltage  
VDDOSC 1.17  
SR  
1.3  
1.433)  
for duration  
limitation see  
Section 5.1.5.1  
Oscillator 3.3V supply  
voltage  
VDDOSC3 2.97  
SR  
3.3  
3.3  
1.3  
3.3  
3.635)  
3.63 5)  
1.433)  
3.635)  
V
V
V
V
V
for duration  
limitation see  
Section 5.1.5.1  
Digital supply voltage for  
IO pads  
V
DDP SR 2.97  
for duration  
limitation see  
Section 5.1.5.1  
E-Ray PLL core voltage  
supply  
VDDPF  
1.17  
for duration  
limitation see  
Section 5.1.5.1  
SR  
E-Ray PLL 3.3V supply  
VDDPF3 2.97  
SR  
for duration  
limitation see  
Section 5.1.5.1  
VDDP voltage to ensure  
defined pad states6)  
VDDPPA 0.65  
CC  
Digital ground voltage  
V
V
SS SR  
0
V
V
Analog ground voltage for  
SSM SR -0.1  
0
0.1  
VDDM  
Analog core supply  
VDDAF  
SR  
1.17  
2.97  
-0.1  
1.3  
3.3  
0
1.433)  
3.635)  
0.1  
V
V
V
FADC / ADC analog  
supply voltage  
VDDMF  
SR  
Analog ground voltage for VSSAF  
VDDMF SR  
1) MA equals the modulation amplitude in percentage times the configured PLL clock out frequency.  
2) Applicable for digital outputs.  
3) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less  
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.  
Data Sheet  
80  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
4) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less  
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.  
5) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less  
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.  
6) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-  
up/power-down of VDDP  
.
5.1.5.1 Extended Range Operating Conditions  
The following extended operating conditions are defined:  
1.3V + 5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 7.5% (overvoltage condition):  
– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction  
of the chip caused by the overvoltage stress.  
1.3V + 7.5% < VDD / VDDOSC / VDDPF / VDDAF < 1.3V + 10% (overvoltage condition):  
– limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction  
of the chip caused by the overvoltage stress.  
3.3V + 5% < VDDP / VDDOSC3 / VDDPF3 / VDDFL3 / VDDMF < 3.3V + 10%  
(overvoltage condition):  
limited to 1000 hours duration cumulative in lifetime, due to the reliability reduction of  
the chip caused by the overvoltage stress.  
Table 18  
Pin Groups for Overload / Short-Circuit Current Sum Parameter  
Pins  
Group  
1
P2.[4:2], P6.[6:9]  
P6.[5:4], P6.[11:10]  
P6.[15:12]  
P8.[5:0]  
2
3
4
5
P8.[7:6]  
6
P1.7, P1.9  
P1.6, P1.12  
P1.[1:0], P7.[2:0]  
P7.[5:3]  
7
8
9
10  
11  
12  
13  
14  
P4.[6:0]  
P4.[10:7]  
P4.12, P4.14  
P10.[5:0]  
P14.8  
Data Sheet  
81  
V 1.1, 2014-05  
TC1791  
Electrical ParametersGeneral Parameters  
Table 18  
Group  
15  
Pin Groups for Overload / Short-Circuit Current Sum Parameter  
Pins  
P14.4, P14.6  
P13.15, P14.0, P14.2  
P13.[14:11]  
P13.[10:8]  
16  
17  
18  
19  
P13.[7:4]  
20  
P13.[3:0]  
21  
P9.10, P9.14  
P9.7, P9.13  
P9.[4:2], P9.6  
P9.1, P9.5, P9.8  
P9.0  
22  
23  
24  
25  
26  
P5.[11:8]  
27  
P5.6, P5.[15:12]  
P5.0, P5.[5:2], P5.7  
P3.0, P3.4, P5.1  
P3.10, P3.12  
P0.[3:0]  
28  
29  
30  
31  
32  
P0.[11:4]  
33  
P0.[14:12]  
34  
P2:12, P2.14  
P2.[10:5]  
35  
Data Sheet  
82  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2  
DC Parameters  
5.2.1  
Input/Output Pins  
Table 19  
Standard_Pads Parameters  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
Pin capacitance (digital  
inputs/outputs)  
CIO CC  
10  
pF  
TA= 25 °C;  
f= 1 MHz  
Pull-down current  
|IPDL  
CC  
|
150  
μA  
μA  
Vi0.6 x VDDP V  
Vi0.36 x  
10  
V
DDP V  
Pull-Up current  
|IPUH  
CC  
|
10  
μA  
μA  
Vi0.6 x VDDP V  
Vi0.36 x  
100  
V
DDP V  
Spike filter always blocked tSF1 CC  
pulse duration  
10  
ns  
ns  
only PORST pin  
Spike filter pass-through  
pulse duration  
t
SF2 CC 100  
only PORST pin  
Table 20  
Standard_Pads Class_A1  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
Input Hysteresis for A1  
pads 1)  
HYSA1 0.1 x  
V
CC  
VDDP  
Input Leakage Current  
Class A1  
IOZA1  
CC  
-500  
500  
nA  
Vi0 V;  
ViVDDP V  
Ratio Vil/Vih, A1 pads  
VILA1  
VIHA1  
CC  
/
0.6  
On-Resistance of the  
class A1 pad, weak driver CC  
RDSONW  
450  
210  
600  
340  
Ohm IOH> -0.5 mA;  
P_MOS  
Ohm IOL< 0.5 mA;  
N_MOS  
Data Sheet  
83  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 20  
Standard_Pads Class_A1 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
On-Resistance of the  
class A1 pad, medium  
driver  
RDSONM  
CC  
155  
Ohm IOH> -2 mA;  
P_MOS  
110  
150  
Ohm IOL< 2 mA;  
N_MOS  
Fall time, pad type A1  
t
FA1 CC  
ns  
ns  
ns  
ns  
CL= 20 pF; pin  
out  
driver= weak  
50  
CL= 50 pF; pin  
out  
driver= medium  
140  
550  
CL= 150 pF; pin  
out  
driver= medium  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Data Sheet  
84  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 20  
Standard_Pads Class_A1 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Rise time, pad type A1  
t
RA1 CC  
150  
ns  
ns  
ns  
ns  
CL= 20 pF; pin  
out  
driver= weak  
50  
CL= 50 pF; pin  
out  
driver= medium  
140  
550  
CL= 150 pF; pin  
out  
driver= medium  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Input high voltage class  
A1 pads  
VIHA1  
SR  
0.6 x  
VDDP  
min(V  
DDP+  
0.3,3.6  
)
V
V
Input low voltage class A1 VILA1 SR -0.3  
0.36 x  
pads  
VDDP  
Data Sheet  
85  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 20  
Standard_Pads Class_A1 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Output voltage high class VOHA1  
A1 pads CC  
VDDP  
0.4  
-
-
V
V
V
V
V
V
IOH-1.4 mA;  
pin out  
driver= medium  
2.4  
IOH-2 mA; pin  
out  
driver= medium  
VDDP  
0.4  
IOH-400 μA;  
pin out  
driver= weak  
2.4  
IOH-500 μA;  
pin out  
driver= weak  
Output voltage low class VOLA1  
A1 pads CC  
0.4  
0.4  
IOL2 mA; pin  
out  
driver= medium  
IOL500 μA;  
pin out  
driver= weak  
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Table 21  
Standard_Pads Class_A1+  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
Input Hysteresis for A1+  
pads 1)  
HYSA1 0.1 x  
V
+ CC  
VDDP  
Input Leakage Current  
Class A1+  
IOZA1+  
CC  
-1000  
1000  
600  
nA  
On-Resistance of the  
class A1+ pad, weak  
driver  
RDSONW  
CC  
450  
210  
Ohm IOH> -0.5 mA;  
P_MOS  
340  
Ohm IOL< 0.5 mA;  
N_MOS  
Data Sheet  
86  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 21  
Standard_Pads Class_A1+ (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
On-Resistance of the  
class A1+ pad, medium  
driver  
RDSONM  
CC  
155  
Ohm IOH> -2 mA;  
P_MOS  
110  
100  
80  
Ohm IOL< 2 mA;  
N_MOS  
On-Resistance of the  
class A1+ pad, strong  
driver  
RDSON1+  
CC  
Ohm IOH> -2 mA;  
P_MOS  
Ohm IOL< 2 mA;  
N_MOS  
Fall time, pad type A1+  
t
FA1+ CC −  
150  
ns  
ns  
CL= 20 pF; pin  
out  
driver= weak  
28  
16  
CL= 50 pF;  
edge= slow ;  
pin out  
driver= strong  
ns  
CL= 50 pF;  
edge= soft ; pin  
out  
driver= strong  
50  
ns  
ns  
ns  
CL= 50 pF; pin  
out  
driver= medium  
140  
550  
CL= 150 pF; pin  
out  
driver= medium  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Data Sheet  
87  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 21  
Standard_Pads Class_A1+ (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
RA1+ CC −  
Max.  
Rise time, pad type A1+  
t
150  
ns  
CL= 20 pF; pin  
out  
driver= weak  
28  
16  
ns  
CL= 50 pF;  
edge= slow ;  
pin out  
driver= strong  
ns  
CL= 50 pF;  
edge= soft ; pin  
out  
driver= strong  
50  
ns  
ns  
ns  
CL= 50 pF; pin  
out  
driver= medium  
140  
550  
CL= 150 pF; pin  
out  
driver= medium  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Input high voltage, Class VIHA1+  
0.6 x  
VDDP  
min(V  
DDP+  
0.3,3.6  
)
V
V
A1+ pads  
SR  
Input low voltage Class  
A1+ pads  
VILA1+  
SR  
-0.3  
0.6  
0.36 x  
VDDP  
Ratio Vil/Vih, A1+ pads  
VILA1+  
VIHA1+  
CC  
/
Data Sheet  
88  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 21  
Standard_Pads Class_A1+ (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Output voltage high class VOHA1+ VDDP  
A1+ pads  
-
-
V
V
V
V
V
V
V
V
V
IOH-1.4 mA;  
pin out  
driver= medium  
CC  
0.4  
VDDP  
0.4  
IOH-1.4 mA;  
pin out  
driver= strong  
2.4  
2.4  
IOH-2 mA; pin  
out  
driver= medium  
IOH-2 mA; pin  
out  
driver= strong  
VDDP  
0.4  
-
IOH-400 μA;  
pin out  
driver= weak  
2.4  
IOH-500 μA;  
pin out  
driver= weak  
Output voltage low class VOLA1+  
A1+ pads CC  
0.4  
0.4  
0.4  
IOL2 mA; pin  
out  
driver= medium  
IOL2 mA; pin  
out  
driver= strong  
IOL500 μA;  
pin out  
driver= weak  
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Data Sheet  
89  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
Input Hysteresis for A2  
pads 1)  
HYSA2 0.1 x  
V
CC  
VDDP  
Input Leakage current  
Class A2  
IOZA2  
CC  
-6000  
6000  
nA  
Vi< VDDP / 2 -  
1 V; Vi> VDDP /2  
+ 1 V; Vi0 V;  
ViVDDP V  
-3000  
0.6  
3000  
nA  
Vi> VDDP / 2 -  
1 V; Vi< VDDP /2  
+ 1 V  
Ratio Vil/Vih, A2 pads  
On-Resistance of the  
VILA2  
VIHA2  
CC  
/
RDSONW  
450  
210  
600  
340  
155  
110  
28  
Ohm IOH> -0.5 mA;  
class A2 pad, weak driver CC  
P_MOS  
Ohm IOL< 0.5 mA;  
N_MOS  
On-Resistance of the  
class A2 pad, medium  
driver  
RDSONM  
CC  
Ohm IOH> -2 mA;  
P_MOS  
Ohm IOL< 2 mA;  
N_MOS  
On-Resistance of the  
class A2 pad, strong driver CC  
RDSON2  
Ohm IOH> -2 mA;  
P_MOS  
22  
Ohm IOL< 2 mA;  
N_MOS  
Data Sheet  
90  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Fall time, pad type A2  
t
FA2 CC  
150  
ns  
CL= 20 pF; pin  
out  
driver= weak  
7
ns  
CL= 50 pF;  
edge= medium  
; pin out  
driver= strong  
10  
3.7  
5
ns  
ns  
ns  
ns  
CL= 50 pF;  
edge= medium-  
minus ; pin out  
driver= strong  
CL= 50 pF;  
edge= sharp ;  
pin out  
driver= strong  
CL= 50 pF;  
edge= sharp-  
minus ; pin out  
driver= strong  
16  
CL= 50 pF;  
edge= soft ; pin  
out  
driver= strong  
50  
ns  
ns  
CL= 50 pF; pin  
out  
driver= medium  
7.5  
CL= 100 pF;  
edge= sharp ;  
pin out  
driver= strong  
140  
ns  
CL= 150 pF; pin  
out  
driver= medium  
Data Sheet  
91  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
550  
ns  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Data Sheet  
92  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Rise time, pad type A2  
t
RA2 CC  
150  
ns  
CL= 20 pF; pin  
out  
driver= weak  
7.0  
10  
3.7  
5
ns  
CL= 50 pF;  
edge= medium  
; pin out  
driver= strong  
ns  
ns  
ns  
ns  
CL= 50 pF;  
edge= medium-  
minus ; pin out  
driver= strong  
CL= 50 pF;  
edge= sharp ;  
pin out  
driver= strong  
CL= 50 pF;  
edge= sharp-  
minus ; pin out  
driver= strong  
16  
CL= 50 pF;  
edge= soft ; pin  
out  
driver= strong  
50  
ns  
ns  
CL= 50 pF; pin  
out  
driver= medium  
7.5  
CL= 100 pF;  
edge= sharp ;  
pin out  
driver= strong  
140  
ns  
CL= 150 pF; pin  
out  
driver= medium  
Data Sheet  
93  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
550  
ns  
CL= 150 pF; pin  
out  
driver= weak  
18000 ns  
65000 ns  
CL= 20000 pF;  
pin out  
driver= medium  
CL= 20000 pF;  
pin out  
driver= weak  
Input high voltage, class  
A2 pads  
VIHA2  
SR  
0.6 x  
VDDP  
min(V  
DDP+  
0.3,  
V
3.6)  
Input low voltage Class A2 VILA2 SR -0.3  
pads  
0.36 x  
VDDP  
V
V
Output voltage high class VOHA2  
VDDP  
-
-
IOH-1.4 mA;  
pin out  
driver= medium  
A2 pads  
CC  
0.4  
VDDP  
0.4  
V
V
V
V
V
IOH-1.4 mA;  
pin out  
driver= strong  
2.4  
2.4  
IOH-2 mA; pin  
out  
driver= medium  
IOH-2 mA; pin  
out  
driver= strong  
VDDP  
0.4  
-
IOH-400 μA;  
pin out  
driver= weak  
2.4  
IOH-500 μA;  
pin out  
driver= weak  
Data Sheet  
94  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 22  
Standard_Pads Class_A2 (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Output voltage low class VOLA2  
A2 pads CC  
0.4  
V
V
V
IOL2 mA; pin  
out  
driver= medium  
0.4  
0.4  
IOL2 mA; pin  
out  
driver= strong  
IOL500 μA;  
pin out  
driver= weak  
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Table 23  
Standard_Pads Class_F  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Input Hysteresis F1)  
HYSF  
CC  
0.05 x  
VDDP  
V
Input Leakage Current  
Class F  
I
OZF CC -6000  
6000  
3000  
nA  
Vi< VDDP / 2 -  
1 V; Vi> VDDP /2  
+ 1 V; Vi0 V;  
ViVDDP V  
-3000  
nA  
Vi> VDDP / 2 -  
1 V; Vi< VDDP /2  
+ 1 V  
Ratio Vil/ Vih, F pads  
VILF  
/
0.6  
V
IHF CC  
On-Resistance of the  
class F pad, medium  
driver  
RDSONM  
CC  
170  
145  
60  
60  
Ohm IOH> -2 mA;  
P_MOS  
Ohm IOL< 2 mA;  
N_MOS  
Fall time, pad type F,  
CMOS mode  
t
t
FF CC  
RF CC  
ns  
ns  
CL= 50 pF  
Rise time, pad type F,  
CMOS mode  
CL= 50 pF  
Data Sheet  
95  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 23  
Standard_Pads Class_F (cont’d)  
Symbol Values  
Parameter  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
Input high voltage, pad  
class F, CMOS mode  
V
V
IHF SR 0.6 x  
min(V  
DDP+  
0.3,  
V
VDDP  
3.6)  
Input low voltage, Class F  
pads, CMOS mode  
ILF SR -0.3  
0.36 x  
VDDP  
V
V
Output high voltage, class VOHF  
F pads, CMOS mode  
VDDP-  
0.4  
IOH-1.4 mA  
CC  
2.4  
V
V
IOH-2 mA  
IOL2 mA  
Output low voltage, class  
F pads, CMOS mode  
V
OLF CC −  
0.4  
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Table 24  
Standard_Pads Class_I  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Input Hysteresis Class I1) HYSI  
0.1 x  
V
CC  
VDDP  
Input Leakage Current  
I
OZI CC -1000  
ILI / VIHI 0.6  
CC  
1000  
nA  
Ratio between low and  
high input threshold  
V
Input high voltage, class I  
pins  
V
IHI SR 0.6 x  
min(V  
DDP+  
0.3,  
V
VDDP  
3.6)  
Input low voltage, Class I  
pads  
V
ILI SR -0.3  
0.36 x  
VDDP  
V
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V.  
Data Sheet  
96  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 25  
Standard_Pads Class_S  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Input Hysteresis for class HYSS  
0.3  
V
S pads1)  
CC  
Input leakage current  
Input voltage high  
Input voltage low  
I
OZS CC -300  
300  
3.6  
nA  
V
V
V
IHS CC  
ILS CC 1.9  
V
V
ILS Delta 2)  
VILSD  
CC  
-50  
50  
mV Maximum input  
low state  
threshold  
variation over  
1ms  
(VDDP = consta  
nt)  
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
2) VILSD is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to  
external noise.  
Table 26  
LVDS_Pads Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
RO CC 40  
Max.  
Output impedance, pad  
class F, LVDS mode  
140  
Ohm  
ns  
Fall time, pad type LVDS  
t
FL CC  
2
termination  
100 ± 1 %;  
differential  
capacitance = 1  
0 pF; input  
capacitance = 2  
0 pF  
Data Sheet  
97  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 26  
LVDS_Pads Parameters (cont’d)  
Symbol Values  
Parameter  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
Rise time, pad type LVDS tRL CC  
2
ns  
termination  
100 ± 1 %;  
differential  
capacitance = 1  
0 pF; input  
capacitance = 2  
0 pF  
Pad set-up time  
tSET_LVD  
S CC  
13  
μs  
termination  
100 ± 1 %  
Output Differential Voltage VOD CC 150  
400  
1525  
mV termination  
100 ± 1 %  
Output voltage high, pad  
class F, LVDS mode  
V
V
V
OH CC  
mV termination  
100 ± 1 %  
Output voltage low, pad  
class F, LVDS mode  
OL CC 875  
mV termination  
100 ± 1 %  
Output Offset Voltage  
OS CC 1075  
1325  
mV termination  
100 ± 1 %  
Data Sheet  
98  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2.2  
Analog to Digital Converters (ADCx)  
ADC parameter are valid for VDD / DDAF = 1.235 V to 1.365 V; VDDM = 4.5 V to 5.5 V.  
Table 27  
ADC Parameters  
Symbol  
Parameter  
Values  
Typ.  
9
Unit Note /  
Test Condition  
Min.  
Max.  
Switched capacitance at CAINSW  
20  
pF  
pF  
pF  
the analog voltage inputs1) CC  
Total capacitance of an  
analog input  
CAINTOT  
CC  
20  
15  
30  
30  
Switched capacitance at CAREFSW  
the positive reference  
CC  
voltage input2)3)  
Total capacitance of the  
CAREFTO  
20  
40  
3
pF  
voltage reference inputs2) T CC  
Differential Non-Linearity EADNL  
-3  
LSB ADC  
Error4)5)6)7)  
CC  
resolution= 12-  
bit 8) 9)  
LSB ADC  
Gain Error4)5)6)7)  
EAGAIN -3.5  
CC  
3.5  
3
resolution= 12-  
bit 8) 9)  
Integral Non-  
Linearity4)5)6)7)  
EAINL  
CC  
-3  
-4  
4
LSB ADC  
resolution= 12-  
bit 8) 9)  
Offset Error4)5)6)7)  
EAOFF  
CC  
4
LSB ADC  
resolution= 12-  
bit 8) 9)  
Converter clock  
f
f
ADC SR  
100  
18  
MHz fADC= fFPI  
Internal ADC clock  
ADCI CC 1  
MHz ADC0  
MHz ADC1  
MHz ADC2  
1
1
18  
2010)  
Charge consumption per QCONV  
70  
8511)  
100  
pC  
chargeneedsto  
conversion  
Data Sheet  
CC  
be provided via  
VAREF0  
99  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 27  
ADC Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
OZ1 CC -100  
Max.  
Input leakage at analog  
inputs12)  
I
500  
nA  
nA  
nA  
nA  
nA  
ViVDDM V;  
Vi0.97 x  
V
DDM V;  
overlayed= No  
-100  
-500  
-600  
-100  
600  
100  
100  
200  
Vi0.97 x  
V
DDM V;  
ViVDDM V;  
overlayed= Yes  
Vi0.03 x  
V
DDM V;  
Vi0 V;  
overlayed= No  
Vi0.03 x  
V
DDM V;  
Vi0 V;  
overlayed= Yes  
Vi> 0.03 x  
V
DDM V;  
Vi< 0.97 x  
DDM V;  
V
overlayed= No  
-100  
300  
nA  
Vi< 0.97 x  
V
DDM V;  
Vi> 0.03 x  
DDM V;  
V
overlayed= Yes  
Input leakage current at  
I
I
OZ2 CC -1  
1
μA  
VAREFx0 V;  
VAREFxVDDM V  
V
AREF0 / VAREF2  
Input leakage current at  
VAREF1  
-2  
2
μA  
VAREFx0 V;  
VAREFxVDDM V  
Input leakage current at  
OZ3 CC -4  
4
μA  
VAGND00 V;  
VAGND0  
VAGND0VDDM V  
ON resistance of the  
transmission gates in the  
analog voltage path  
R
AIN CC  
900  
1500  
Ohm  
Data Sheet  
100  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 27  
ADC Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
ON resistance for the ADC RAIN7T  
180  
550  
900  
Ohm  
Ohm  
test (pull down for AIN7)  
CC  
Resistance of the  
reference voltage input  
path  
RAREF  
CC  
500  
1000  
Sample time  
tS CC  
2
257  
TADCI  
Calibration time after bit  
ADC_GLOBCFG.SUCAL  
is set  
t
CAL CC  
4352  
cycle  
s
Total Unadjusted  
Error6)5)13)  
TUE CC -4  
414)  
LSB ADC  
resolution= 12-  
bit  
Analog reference ground2) VAGNDx VSSM  
SR 0.05  
AIN SR VAGNDx  
Analog reference voltage2) VAREFx VAGNDx  
-
VAREFx  
- 1  
V
V
Analog input voltage  
V
VAREFx  
V
DDM + V  
SR  
+ 1  
0.0515)  
16)  
Analog reference voltage VAREFx  
-
V
DDM/2 −  
V
0.05  
DDM + V  
range6)5)2)  
VAGNDx  
SR  
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.  
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.  
2) Applies to AINx, when used as auxiliary reference input.  
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage  
at once. Instead smaller capacitances are successively switched to the reference voltage.  
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.  
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in  
the ADC speed and accuracy.  
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,  
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),  
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.  
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.  
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.  
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.  
10) For fADCI between 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits. For  
STC < 2 INL, DNL , and Offset errors can also increase.  
Data Sheet  
101  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
11) For a conversion time of 1 µs a rms value of 85µA result for IAREF0.  
12) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The  
numerical values defined determine the characteristic points of the given continuous linear approximation -  
they do not define step function.  
13) Measured without noise.  
14) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB  
15) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).  
16) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),  
then the accuracy of the ADC decrease by 4LSB12.  
Table 28  
Conversion Time (Operating Conditions apply)  
Symbol Values  
Parameter  
Unit Note  
Conversion  
time with  
tC CC 2 × TADC + (4 + STC + n) × TADCI μs  
n = 8, 10, 12 for  
n - bit conversion  
post-calibration  
T
T
ADC = 1 / fFPI  
ADCI = 1 / fADCI  
Conversion  
2 × TADC + (2 + STC + n) × TADCI  
time without  
post-calibration  
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.  
Analog Input Circuitry  
RAIN, On  
REXT  
ANx  
VAIN  
CEXT  
CAINSW  
=
C
AINTOT - CAINSW  
VAGNDx  
RAIN7T  
Reference Voltage Input Circuitry  
RAREF, On  
VAREFx  
VAREF  
C
AREFTOT - CAREFSW  
CAREFSW  
VAGNDx  
Analog_InpRefDiag  
Figure 8  
ADCx Input Circuits  
Data Sheet  
102  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Ioz1  
Single ADC Input  
500nA  
200nA  
100nA  
VIN[VDDM%]  
-100nA  
3%  
97%100%  
-500nA  
Ioz1  
Overlayed ADC/FADC Input  
600nA  
300nA  
100nA  
VIN[VDDM%]  
-100nA  
3%  
97%100%  
-600nA  
Figure 9  
ADCx Analog Inputs Leakage  
Data Sheet  
103  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2.3  
Fast Analog to Digital Converter (FADC)  
FADC parameter are vaild for VDD / DDAF = 1.235 V to 1.365 V; VDDMF = 2.97 V to 3.6 V.  
Table 29  
FADC Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Input current at VFAREF IFAREF  
120  
μA  
CC  
Input leakage current at  
VFAREF1)  
IFOZ2  
CC  
-500  
-500  
-1  
500  
500  
1
nA  
VFAREFVDDMF  
V; VFAREF0 V  
Input leakage current at  
VFAGND  
IFOZ3  
CC  
nA  
DNL error  
EFDNL  
LSB  
VIN mode=  
CC  
differential;  
Gain = 1 or 2  
-2  
-1  
-2  
2
1
2
5
5
6
6
LSB  
LSB  
LSB  
%
VIN mode=  
differential;  
Gain = 4 or 82)  
V
IN mode=  
single ended;  
Gain = 1 or 2  
V
IN mode=  
single ended;  
Gain = 4 or 82)  
GRADient error  
EFGRAD -5  
VIN mode=  
differential ;  
Gain4  
CC  
-5  
-6  
-6  
%
VIN mode=  
single ended ;  
Gain4  
%
VIN mode=  
differential ;  
Gain= 8  
%
VIN mode=  
single ended ;  
Gain= 8  
Data Sheet  
104  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 29  
FADC Parameters (cont’d)  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
INL error  
EFINL  
-4  
4
LSB  
LSB  
mV  
V
IN mode=  
differential  
IN mode=  
single ended  
IN mode=  
CC  
-4  
4
V
Offset error  
EFOFF  
-90  
90  
V
CC  
differential ;  
Calibration= No  
-90  
-20  
90  
20  
mV  
mV  
VIN mode=  
single ended ;  
Calibration= No  
V
IN mode=  
differential ;  
Calibration= Ye  
s 3)4)  
-20  
20  
mV  
VIN mode=  
single ended ;  
Calibration= Ye  
s 3)4)  
Error of commen mode  
voltage VFAREF/2  
EFREF  
CC  
-60  
2
60  
mV  
Channel amplifier cutoff  
frequency  
fCOFF  
CC  
MHz  
MHz  
1 /  
Converter clock  
fFADC  
SR  
1
100  
21  
200  
f
FADC= fFPI  
Conversion time  
tC CC  
For 10-bit  
fFADC conversion  
Input resistance of the  
analog voltage path (Rn, CC  
RFAIN  
100  
kOh  
m
Rp)  
Settling time of a channel  
amplifier after changing  
ENN or ENP  
t
SET CC  
5
μs  
Analog input voltage  
range  
VAINF  
SR  
VFAGND  
VDDMF  
V
Data Sheet  
105  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 29  
FADC Parameters (cont’d)  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
Analog reference ground VFAGND VSSAF  
SR 0.05  
-
VSSAF  
+ 0.05  
V
V
Analog reference voltage VFAREF 2.97  
3.635)  
6)  
SR  
1) This value applies in power-down mode.  
2) No missing codes.  
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed  
minimium once per week.  
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.  
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum  
of the pulses does not exceed 1 h.  
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage  
overshoots).  
The calibration procedure should run after each power-up, when all power supply  
voltages and the reference voltage have stabilized.  
Data Sheet  
106  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
FADC Analog Input Stage  
RN  
FAINxN  
-
+
VFAREF/2  
VFAGND  
+
-
RP  
FAINxP  
FADC Reference Voltage  
Input Circuitry  
VFAREF  
IFAREF  
VFAREF  
VFAGND  
FADC_InpRefDiag  
Figure 10  
FADC Input Circuits  
Data Sheet  
107  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2.4  
Oscillator Pins  
Table 30  
OSC_XTAL Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
IX1 CC -25  
Max.  
Input current at XTAL1  
Input frequency  
I
25  
μA  
VIN<VDDOSC3  
VIN>0 V  
;
f
OSC SR  
4
8
40  
MHz Direct Input  
Mode selected  
25  
MHz ExternalCrystal  
Mode selected  
Oscillator start-up time1)  
tOSCS  
10  
ms  
CC  
Input high voltage at  
XTAL12)  
V
IHX SR 0.7 x  
VDDOS  
V
VDDOS  
+
C3  
0.5  
C3  
Input low voltage at  
XTAL1  
V
ILX SR -0.5  
0.3 x  
VDDOS  
V
C3  
Input Hysteresis for  
XTAL1 pad 3)  
HYSAX  
CC  
200  
mV  
1)  
tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of  
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative  
resistance as recommended and specified by crystral suppliers.  
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is  
necessary.  
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be  
guaranteed that it suppresses switching due to external system noise.  
Note: It is strongly recommended to measure the oscillation allowance (negative  
resistance) in the final target system (layout) to determine the optimal parameters  
for the oscillator operation. Please refer to the limits specified by the crystal or  
ceramic resonator supplier.  
Data Sheet  
108  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2.5  
Temperature Sensor  
Table 31  
DTS Parameters  
Symbol  
Parameter  
Values  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
100  
Measurement time  
tM CC  
μs  
Temperature sensor  
range  
T
SR SR -40  
150  
°C  
Sensor Accuracy  
(calibrated)  
T
TSA CC -6  
6
°C  
Start-up time after resets  
inactive  
t
TSST SR −  
20  
μs  
The following formula calculates the temperature measured by the DTS in [oC] from the  
RESULT bit field of the DTSSTAT register.  
(1)  
DTSSTATRESULT 596  
Tj = ------------------------------------------------------------------  
2, 03  
Data Sheet  
109  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
5.2.6  
Power Supply Current  
The total power supply current defined below consists of leakage and switching  
component.  
Application relevant values are typically lower than those given in the following  
two tables and depend on the customer's system operating conditions (e.g.  
thermal connection or used application configurations).  
The operating conditions for the parameters in the following table are:  
V
V
DD / VDDOSC / VDDAF / VDDPF = 1.365 V, VDDP / VDDOSC / VDDMF / VDDFL3 / VDDPF = 3.47 V,  
DDM = 5.25 V SRI / CPU=240 / 200 MHz, PCP=120 / 200 MHz, SRI=80 / 100 MHz,  
f
f
f
TJ=150 oC  
The realisic power pattern defines the following conditions:  
TJ=150 oC  
f
f
f
SRI = fCPU = 240 / 200 MHz  
PCP = 120 / 200 MHz  
FPI = 80 / 100MHz  
V
V
V
DD = VDDOSC = VDDAF = VDDPF = 1.326 V  
DDP = VDDOSC3 = VDDFL3 VDDPF3 = VDDMF = 3.366 V  
DDM = 5.1 V  
The max power pattern defines the following conditions:  
TJ=150 oC  
f
f
f
SRI = fCPU = 240 / 200 MHz  
PCP = 120 / 200 MHz  
FPI = 80 / 100MHz  
V
V
V
DD = VDDOSC = VDDAF = VDDPF = 1.43 V  
DDP = VDDOSC3 = VDDFL3  
DDM = 5.5 V  
V
DDPF3 = VDDMF = 3.63 V  
Data Sheet  
110  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 32  
Power Supply Parameters  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
7893)  
Core active mode supply  
current1)2)  
I
DD CC  
mA power  
pattern= max;  
CPU=240 MHz  
mA power  
pattern= realisti  
c;  
f
591  
f
CPU=240 MHz  
7354)  
555  
mA power  
pattern= max;  
CPU=200 MHz  
mA power  
pattern= realisti  
c;  
f
f
CPU=200 MHz  
IDD current at PORST Low IDD_PORS  
298  
249  
4
mA TJ=150 oC  
mA TJ=140 oC  
mA  
T CC  
E-Ray PLL core supply  
current  
IDDPF  
CC  
Oscillator core supply  
current  
IDDOSC  
CC  
3
mA  
Analog core supply  
current  
IDDAF  
CC  
26  
624  
mA  
Sum of all 1.3 V supply  
currents  
IDDSUM  
CC  
mA power  
pattern= realisti  
c;  
f
CPU=240 MHz  
588  
mA power  
pattern= realisti  
c;  
CPU=200 MHz  
f
E-Ray PLL 3.3V supply  
IDDPF3  
CC  
4
mA  
mA  
Oscillator power supply  
current, 3.3V  
IDDOSC3  
CC  
11  
Data Sheet  
111  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 32  
Power Supply Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
FADC analog supply  
current, 3.3V  
IDDMF  
CC  
15  
mA  
mA  
I
DDP current at PORST  
IDDP_POR  
ST CC  
7
Low  
I
DDP current no pad  
I
DDP CC  
IDDP_  
mA including flash  
read current  
activity, LVDS off 5)  
PORST  
+ 25  
IDDP_  
mA including flash  
programming  
current 6)  
PORST  
+ 55  
IDDP_  
mA including flash  
erase verify  
PORST  
+ 40 7)  
current 6)  
Flash memory current 5)  
IDDFL3  
CC  
98  
mA flash read  
current  
29  
mA flash  
programming  
current 6)  
98  
24  
mA flash erase  
current 6)  
Current Consumption of  
LVDS Pad Pairs  
ILVDS  
CC  
mA in total for all  
LVDS pairs  
Sum of all 3.3 V supply  
currents, no pad activity, CC  
IDD3SUM  
160 8) mA including flash  
read current  
LVDS off  
ADC 5V power supply  
current  
I
DDM CC −  
6
mA  
Data Sheet  
112  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
Table 32  
Power Supply Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Maximum power  
dissipation  
PD CC  
1706  
mW power  
pattern= max;  
CPU=240 MHz  
mW power  
pattern= realisti  
c;  
f
1449  
f
CPU=240 MHz  
1523  
1403  
mW power  
pattern= max;  
CPU=200 MHz  
mW power  
pattern= realisti  
c;  
CPU=200 MHz  
f
f
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer  
application will most probably be lower than this value, but must be evaluated seperately.  
2) This current includes the E-Ray module power consumption, including the PCP operation component.  
3) The IDD decreases typically by 102 mA if the fCPU decreases by 50MHz, at constant TJ  
4) The IDD decreases typically by 105 mA if the fCPU decreases by 50MHz, at constant TJ  
5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash  
operation.  
6) Relevant for the power supply dimensioning, not for thermal considerations.  
7) In case of erase of Program Flash PFx, internal flash array loading effects may generate transient current  
spikes of up to 15 mA for maximum 5 ms per flash module.  
8) For power supply dimensioning of VDDP 30 mA have to added for flash programming case.  
Note: In general current consumption for operations with data flash are always lower  
than the defined values for program flash read operation.  
5.2.6.1 Calculating the 1.3 V Current Consumption  
The current consumption of the 1.3 V rail compose out of two parts:  
Static current consumption  
Dynamic current consumption  
The static current consumption is related to the device temperature TJ and the dynamic  
current consumption depends of the configured clocking frequencies and the software  
Data Sheet  
113  
V 1.1, 2014-05  
TC1791  
Electrical ParametersDC Parameters  
application executed. These two parts needs to be added in order to get the rail current  
consumption.  
(2)  
mA  
0, 02041 × T  
--------  
C
I
= 3, 75  
× e  
[C]  
J
0
(3)  
mA  
--------  
0, 01825 × T  
I
= 18, 77  
× e  
[C]  
J
0
C
Function 2 defines the typical static current consumption and Function 3 defines the  
maximum static current consumption. Both functions are valid for VDD = 1.326 V.  
For the dynamic current consumption using the real pattern and fSRI = 2 * fPCP = 3 * fFPI  
the function 4 applies:  
(4)  
mA  
MHz  
------------  
I
= 1, 22  
× f  
[MHz]  
D m  
y
CPU  
For the dynamic current consumption using the real pattern and fSRI = fPCP = 2 * fFPI the  
function 5 applies:  
(5)  
mA  
------------  
MHz  
I
= 1, 305  
× f  
[MHz]  
D m  
y
CPU  
and this finally results in  
(6)  
I
= I + I  
0
DYM  
DD  
Data Sheet  
114  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3  
AC Parameters  
All AC parameters are defined with maximum driver strength unless otherwise noted.  
5.3.1  
Testing Waveforms  
VDDP  
90%  
90%  
10%  
10%  
VSS  
tR  
tF  
rise_fall  
Figure 11  
Rise/Fall Time Parameters  
VDDP  
VDDE / 2  
Test Points  
VDDE / 2  
VSS  
mct04881_a.vsd  
Figure 12  
Testing Waveform, Output Delay  
VLoad+ 0.1 V  
VLoad- 0.1 V  
VOH - 0.1 V  
Timing  
Reference  
Points  
VOL - 0.1 V  
MCT04880_new  
Figure 13  
Testing Waveform, Output High Impedance  
Data Sheet  
115  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.2  
Power Sequencing  
V
5.25V  
5V  
4.75V  
3.47V  
VAREF  
3.3V  
1.3V  
3.0V  
-12%  
1.365V  
1.235V  
0.5V  
-12%  
0.5V  
0.5V  
t
VDDP  
PORST  
power  
down  
power  
fail  
t
Power-Up 10.vsd  
Figure 14  
5 V / 3.3 V / 1.3 V Power-Up/Down Sequence  
The following list of rules applies to the power-up/down sequence:  
All ground pins VSS must be externally connected to one single star point in the  
system. Regarding the DC current component, all ground pins are internally directly  
connected.  
At any moment in time to avoid increased latch-up risk,  
each power supply must be higher then any lower_power_supply - 0.5 V, or:  
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 14.  
– The latch-up risk is minimized if the I/O currents are limited to:  
– 20 mA for one pin group  
– AND 100 mA for the completed device I/Os  
– AND additionally before power-up / after power-down:  
1 mA for one pin in inactive mode (0 V on all power supplies)  
During power-up and power-down, the voltage difference between the power supply  
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example  
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.  
On the other hand, all power supply pins with the same name (for example all VDDP),  
Data Sheet  
116  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
are internally directly connected. It is recommended that the power pins of the same  
voltage are driven by a single power supply.  
1. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF power-  
supplies and the oscillator have reached stable operation, within the normal  
operating conditions.  
2. At normal power down the PORST signal should be activated within the normal  
operating range, and then the power supplies may be switched off. Care must be  
taken that all Flash write or delete sequences have been completed.  
3. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V  
power supply voltage falls 12% below the nominal level. If, under these conditions,  
the PORST is activated during a Flash write, only the memory row that was the target  
of the write at the moment of the power loss will contain unreliable content. In order  
to ensure clean power-down behavior, the PORST signal should be activated as  
close as possible to the normal operating voltage range.  
4. In case of a power-loss at any power-supply, all power supplies must be powered-  
down, conforming at the same time to the rules number 2 and 4.  
5. Although not necessary, it is additionally recommended that all power supplies are  
powered-up/down together in a controlled way, as tight to each other as possible.  
6. Additionally, regarding the ADC reference voltage VAREF  
:
VAREF must power-up at the same time or later then VDDM, and  
VAREF must power-down either earlier or at latest to satisfy the condition  
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter  
capacitance through the ESD diodes through the VDDM power supply. In case of  
discharging the reference capacitance through the ESD diodes, the current must  
be lower than 5 mA.  
Data Sheet  
117  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.3  
Power, Pad and Reset Timing  
Reset Timings Parameters  
Table 33  
Parameter  
Symbol  
Values  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
1015  
1140  
2.5  
Application Reset Boot  
Time1)2)  
tB CC  
μs  
μs  
ms  
f
f
CPU = 240 MHz  
CPU = 200 MHz  
Power on Reset Boot  
Time3)4)  
t
t
BP CC  
HWCFG pins hold time  
from ESR0 rising edge  
HDH SR 16 /  
ns  
ns  
ns  
ns  
ms  
fFPI  
HWCFG pins setup time to tHDS SR  
ESR0 rising edge  
0
Ports inactive after ESR0  
reset active  
t
t
t
PI CC  
8/fFPI  
150  
Ports inactive after  
PIP CC  
PORST reset active5)  
Minimum PORST active  
time after power supplies  
are stable at operating  
levels  
POA SR 10  
TESTMODE / TRST hold  
time from PORST rising  
edge  
t
POH SR 100  
ns  
PORST rise time  
t
t
POR SR  
POS SR  
50  
ms  
ns  
TESTMODE / TRST  
setup time to PORST  
rising edge  
0
Application Reset inactive tPOR_APP  
40 6)  
μs  
after PORST deassertion SR  
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock  
cycle when the first user instruction has entered the CPU pipeline and its processing starts.  
2) The given time includes the time of the internal reset extension for  
SCU_RSTCNTCON.RELSA = 0x05BE.  
a configured value of  
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the  
first user instruction has entered the CPU pipeline and its processing starts.  
4) The given time includes the internal reset extension time for the System and Application Reset which is visible  
through ESR0.  
Data Sheet  
118  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5) This parameter includes the delay of the analog spike filter in the PORST pad.  
6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the  
Application Reset is extended.  
VDDP -12%  
VDDPPA  
VDDPPA  
VDDP  
VDD  
VDD -12%  
tPOA  
tPOA  
PORST  
tPOH  
tPOH  
TRST  
TESTMODE  
thd  
thd  
ESR0  
tHDH  
tHDH  
tHDH  
HWCFG  
tPIP  
t PIP  
tPI  
tPI  
Pads  
tPI  
tPI  
tPI  
t PIP  
Pad-state undefined  
Tri-state or pull device active  
As programmed  
reset_beh2  
Figure 15  
Power, Pad and Reset Timing  
Data Sheet  
119  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.4  
Phase Locked Loop (PLL)  
Table 34  
PLL_SysClk Parameters  
Parameter  
Symbol  
Min.  
Values  
Typ.  
Unit Note /  
Test Condition  
Max.  
7
Accumulated Jitter  
Modulation frequency  
PLL base frequency  
DP CC -7  
MOD SR 50  
ns  
f
200  
320  
kHz  
MHz  
fPLLBASE 50  
200  
CC  
VCO input frequency  
VCO frequency range  
f
f
REF CC  
8
16  
MHz  
VCO CC 400  
720  
MHz with inactive  
modulation  
400  
600  
MHz with active  
modulation  
Modulation jitter  
J
MOD CC −  
2.5  
9.5  
ns  
Total long term jitter  
JTOT CC  
ns  
Sum of DP and  
JMOD  
Modulation Amplitude  
PLL lock-in time  
MA SR  
tL CC  
0
2.5  
%
% of fVCO  
N > 32  
14  
14  
200  
400  
0.01  
μs  
μs  
%
N 32  
System frequency  
deviation  
fSYSD  
CC  
with active  
modulation  
Phase Locked Loop Operation  
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the SRI-  
Bus clock fSRI) is constantly adjusted to the selected frequency. The PLL is constantly  
adjusting its output frequency to correspond to the input frequency (from crystal or clock  
source), resulting in an accumulated jitter that is limited. This means that the relative  
deviation for periods of more than one clock cycle is lower than for a single clock cycle.  
This is especially important for bus cycles using wait states and for the operation of  
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train  
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter  
is negligible.  
Data Sheet  
120  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in  
[ns] dependent on the K2 - factor, the SRI clock frequency fSRI in [MHz], and the number  
m of consecutive fSRI clock periods.  
for  
(K2 100)  
and  
(m ≤ (fSRI[MHz]) ⁄ 2)  
(7)  
(8)  
740  
(1 – 0, 01 × K2) × (m – 1)  
0, 5 × fSRI[MHz] – 1  
+ 5 ×  
-----------------------------------------  
----------------------------------------------------------------  
Dm[ns] =  
+ 0, 01 × K2  
K2 × fSRI[MHz]  
740  
-----------------------------------------  
+ 5  
else  
Dm[ns] =  
K2 × fSRI[MHz]  
With rising number m of clock cycles the maximum jitter increases linearly up to a value  
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum  
accumulated jitter remains at a constant value. Further, a lower SRI-Bus clock frequency  
f
SRI results in a higher absolute maximum jitter value.  
Note: The specified PLL jitter values are valid if the capacitive load per pin does not  
exceed CL = 20 pF with the maximum driver and sharp edge.  
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between  
V
DDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise  
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above  
300 KHz.  
The maximum peak-to peak noise on the pad supply voltage, measured between  
V
DDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise  
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above  
300 KHz.  
These conditions can be achieved by appropriate blocking of the supply voltage  
as near as possible to the supply pins and using PCB supply and ground planes.  
Oscillator Watchdog (OSC_WDT)  
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The  
OSC_WDT checks for too low frequencies and for too high frequencies.  
The frequency that is monitored is fOSCREF which is derived for fOSC  
.
(9)  
f
OSC  
----------------------------------  
f
=
OSCREF  
OSCVAL + 1  
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is  
2.5 MHz.  
Data Sheet  
121  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as  
possible to 2.5 MHz.  
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above  
7.5 MHz. This leads to the following two conditions:  
Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)  
Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)  
Note: The accuracy is 30% for these boundaries.  
Frequency Modulation  
Frequency modulation defines a slow and predictable variation of the clock speed. The  
modulation configuration itself is controlled via register SCU_PLLCON2 where the two  
bit fields define the modulation properties.  
(10)  
f
OSC MODFREQ × 31, 32  
-------------- ----------------------------------------------------  
f
=
×
MOD  
P
MODAMP  
(11)  
MODAMP  
N × 161  
----------------------------  
MA =  
Data Sheet  
122  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.5  
ERAY Phase Locked Loop (ERAY_PLL)  
Table 35  
PLL_ERAY Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
PP CC -0.8  
Max.  
Accumulated jitter at  
SYSCLK pin  
D
0.8  
ns  
Accumulated_Jitter  
DP CC -0.5  
0.5  
ns  
PLL Base Frequency of  
the ERAY PLL  
fPLLBASE_ 50  
ERAY CC  
250  
360  
MHz  
VCO input frequency of  
the ERAY PLL  
f
REF CC 20  
40  
MHz  
MHz  
μs  
VCO frequency range of fVCO_ERA 450  
the ERAY PLL  
500  
200  
Y CC  
PLL lock-in time  
tL CC  
5.6  
Note: The specified PLL jitter values are valid if the capacitive load per pin does not  
exceed CL = 20 pF with the maximum driver and sharp edge.  
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between  
V
DDPF3 and VSSPF, is limited to a peak-to-peak voltage of VPP = 100 mV for noise  
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above  
300 KHz.  
These conditions can be achieved by appropriate blocking of the supply voltage  
as near as possible to the supply pins and using PCB supply and ground planes.  
Data Sheet  
123  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.6  
JTAG Interface Timing  
The following parameters are applicable for communication through the JTAG debug  
interface. The JTAG module is fully compliant with IEEE1149.1-2000.  
Note: These parameters are not subject to production test but verified by design and/or  
characterization.  
Table 36  
JTAG Interface Timing Parameters  
(Operating Conditions apply)  
Parameter  
Symbol  
Values  
Unit Note /  
Test Condition  
Min.  
25  
10  
10  
Typ.  
Max.  
TCK clock period  
TCK high time  
t1 SR  
t2 SR  
t3 SR  
t4 SR  
t5 SR  
t6 SR  
4
4
ns  
ns  
ns  
ns  
ns  
ns  
TCK low time  
TCK clock rise time  
TCK clock fall time  
TDI/TMS setup  
6
to TCK rising edge  
TDI/TMS hold  
t7 SR  
6
ns  
after TCK rising edge  
TDO valid after TCK falling t8 CC  
3
2
13  
ns  
ns  
ns  
CL = 50 pF  
CL = 20 pF  
edge1) (propagation delay)  
t8 CC  
TDO hold after TCK falling t18 CC  
edge1)  
TDO high imped. to valid t9 CC  
14  
ns  
ns  
CL = 50 pF  
CL = 50 pF  
from TCK falling edge1)2)  
TDO valid to high imped.  
from TCK falling edge1)  
t
10 CC  
13.5  
1) The falling edge on TCK is used to generate the TDO timing.  
2) The setup time for TDO is given implicitly by the TCK cycle time.  
Data Sheet  
124  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
t1  
0.9 VDDP  
0.1 VDDP  
0.5 VDDP  
t5  
t4  
t2  
t3  
MC_JTAG_TCK  
Figure 16  
Test Clock Timing (TCK)  
TCK  
t6  
t7  
TMS  
t6  
t7  
TDI  
t9  
t8  
t10  
TDO  
t18  
MC_JTAG  
Figure 17  
JTAG Timing  
Data Sheet  
125  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.7  
DAP Interface Timing  
The following parameters are applicable for communication through the DAP debug  
interface.  
Note: These parameters are not subject to production test but verified by design and/or  
characterization.  
Table 37  
DAP Parameters  
Symbol  
Parameter  
Values  
Unit Note /  
Test Condition  
Min.  
TCK SR 12.5  
Typ.  
Max.  
DAP0 clock period1)  
DAP0 high time  
DAP0 low time1)  
t
t
t
t
t
t
2
2
ns  
ns  
ns  
ns  
ns  
ns  
12 SR  
13 SR  
14 SR  
15 SR  
16 SR  
4
4
DAP0 clock rise time  
DAP0 clock fall time  
DAP1 setup to DAP0  
rising edge  
6.0  
DAP1 hold after DAP0  
rising edge  
t
t
17 SR  
19 CC  
6.0  
8
ns  
ns  
ns  
DAP1 valid per DAP0  
clock period2)  
CL= 20 pF;  
f= 80 MHz  
10  
CL= 50 pF;  
f= 40 MHz  
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.  
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.  
t11  
0.9 VDDP  
0.1 VDDP  
0.5 VDDP  
t15  
t14  
t12  
t13  
MC_DAP0  
Figure 18  
Test Clock Timing (DAP0)  
Data Sheet  
126  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
DAP0  
DAP1  
t16  
t17  
MC_DAP1_RX  
Figure 19  
DAP Timing Host to Device  
t11  
DAP1  
t19  
MC_DAP1_TX  
Figure 20  
5.3.8  
DAP Timing Device to Host  
Micro Link Interface (MLI) Timing  
Data Sheet  
127  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
MLI Transmitter Timing  
t13  
t14  
t10  
t12  
TCLKx  
t11  
t15  
t15  
TDATAx  
TVALIDx  
t16  
t17  
TREADYx  
MLI Receiver Timing  
t23  
t24  
t20  
t22  
RCLKx  
t21  
t25  
t26  
RDATAx  
RVALIDx  
t27  
t27  
RREADYx  
MLI_Tmg_2.vsd  
Figure 21  
MLI Interface Timing  
Note: The generation of RREADYx is in the input clock domain of the receiver. The  
reception of TREADYx is asynchronous to TCLKx.  
The MLI parameters are vaild for CL = 50 pF and strong driver medium edge.  
Data Sheet  
128  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
Table 38  
MLI Receiver  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
1 / fFPI  
Max.  
RCLK clock period  
RCLK high time1)2)  
t
t
20 SR  
21 SR  
ns  
ns  
0.5 x  
t20  
RCLK low time1)2)  
t
22 SR  
0.5 x  
ns  
t20  
RCLK rise time3)  
RCLK fall time3)  
t
t
t
23 SR  
24 SR  
25 SR  
4
4
ns  
ns  
ns  
RDATA/RVALID setup  
time before RCLK falling  
edge  
4.2  
RDATA/RVALID hold time t26 SR  
after RCLK falling edge  
2.2  
0
ns  
ns  
RREADY output delay  
time  
t
27 SR  
16  
1) The following formula is valid: t21 + t22 = t20.  
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver  
timing parameters.  
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower  
input signal rise/fall times can be used for longer RCLK clock periods.  
Table 39  
MLI Transmitter  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
TCLK clock period  
TCLK high time1)2)  
TCLK low time1)2)  
TCLK rise time  
t
10 CC  
11 CC  
12 CC  
13 CC  
14 CC  
2 x 1 /  
fFPI  
ns  
t
t
t
t
0.45 x 0.5 x  
t10 t10  
0.45 x 0.5 x  
0.55 x ns  
t10  
0.55 x ns  
t10  
t10  
t10  
0.3 x  
ns  
ns  
3)  
t10  
TCLK fall time  
0.3 x  
3)  
t10  
Data Sheet  
129  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
Table 39  
MLI Transmitter (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
-3  
Max.  
TDATA/TVALID output  
delay time  
t
t
t
15 CC  
16 SR  
17 SR  
4.4  
ns  
ns  
ns  
TREADY setup time  
before TCLK rising edge  
18  
-2  
TREADY hold time after  
TCLK rising edge  
1) The following formula is valid: t11 + t12 = t10.  
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be  
regarded additionally to t11 / t12.  
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended  
for TCLK.  
5.3.9  
Micro Second Channel (MSC) Interface Timing  
The MSC parameters are vaild for CL = 50 pF.  
Table 40  
MSC Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
FCLP clock period1)2)  
t
40 CC  
45 CC  
2 x  
TMSC  
ns  
ns  
3)  
SOP4)/ENx outputs delay  
from FCLP4) rising edge  
t
-2  
-2  
0
5
ENx with strong  
driver and  
sharp (minus )  
edge  
10  
ns  
ENx with strong  
driver and  
medium  
(minus) edge  
21  
ns  
ns  
ENx with strong  
driver and soft  
edge  
SDI bit time  
Data Sheet  
t
46 CC  
8 x  
TMSC  
130  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
Table 40  
MSC Parameters (cont’d)  
Parameter  
Symbol  
Values  
Unit Note /  
Test Condition  
Min.  
Typ.  
Max.  
200  
SDI rise time  
SDI fall time  
t
t
48 SR  
49 SR  
ns  
ns  
200  
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.  
2) FCLP signal high and low can be minimum 1xTMSC  
3) TMSC = TSYS = 1 / fSYS.  
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.  
t40  
0.9 VDDP  
0.1 VDDP  
FCLP  
t45  
t45  
SOP  
EN  
t48  
t49  
0.9 VDDP  
0.1 VDDP  
SDI  
t46  
MSC Interface Timing  
t46  
MSC_Tmg_1.vsd  
Figure 22  
Note: The data at SOP should be sampled with the falling edge of FCLP in the target  
device.  
Data Sheet  
131  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.10  
SSC Master/Slave Mode Timing  
The SSC parameters are vaild for CL = 50 pF and strong driver medium edge.  
Table 41  
SSC Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
SCLK clock period1)2)3)  
t
50 CC  
51 CC  
52 SR  
53 SR  
54 SR  
2 x 1 /  
fFPI  
ns  
ns  
ns  
ns  
ns  
%
MTSR/SLSOx delay form  
SCLK rising edge  
t
t
t
t
0
8
MRST setup to SCLK  
latching edge3)  
16.5  
0
MRST hold from SCLK  
latching edge3)  
SCLK input clock  
period1)3)  
4 x 1 /  
fFPI  
SCLK input clock duty  
cycle  
t55_t54  
SR  
45  
55  
MTSR setup to SCLK  
latching edge3)4)  
t
t
t
t
t
t
56 SR  
57 SR  
58 SR  
59 SR  
60 CC  
61 CC  
1 / fFPI  
ns  
ns  
ns  
ns  
ns  
ns  
MTSR hold from SCLK  
latching edge  
1 / fFPI  
+ 5  
SLSI setup to first SCLK  
latching edge  
1 / fFPI  
+ 5  
SLSI hold from last SCLK  
latching edge5)  
7
0
MRST delay from SCLK  
shift edge  
16.5  
16.5  
SLSI to valid data on  
MRST  
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.  
2) SCLK signal high and low times can be minimum 1xTSSC.  
3) TSSCmin = TSYS = 1/fSYS.  
4) Fractional divider switched off, SSC internal baud rate generation used.  
Data Sheet  
132  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever  
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair  
of shifting / latching edges.  
t50  
SCLK1)2)  
t51  
t51  
MTSR1)  
t52  
t53  
Data  
valid  
MRST1)  
t51  
SLSOn2)  
1) This timing is based on the following setup: CON.PH = CON.PO = 0.  
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0  
and the first SCLK high pulse is in the first one of a transmission.  
SSC_TmgMM  
Figure 23  
SSC Master Mode Timing  
Data Sheet  
133  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
t54  
First latching  
SCLK edge  
Last latching  
SCLK edge  
First shift  
SCLK edge  
SCLK1)  
t55  
t55  
t56  
t56  
t57  
t57  
Data  
valid  
Data  
valid  
MTSR1)  
MRST1)  
SLSI  
t60  
t60  
t61  
t59  
t58  
1) This timing is based on the following setup: CON.PH = CON.PO = 0.  
SSC_TmgSM  
Figure 24  
SSC Slave Mode Timing  
Data Sheet  
134  
V 1.1, 2014-05  
TC1791  
Electrical ParametersAC Parameters  
5.3.11  
ERAY Interface Timing  
The timings of this section are valid for the strong driver and either sharp edge or medium  
edge settings of the output drivers with CL = 25 pF.  
The ERAY interface is only available for the SAK-TC1791F-512F240EP / SAK-  
TC1791F-512F240EL / SAK-TC1791S-512F240EP / SAK-TC1791F-  
384F200EL / SAK-TC1791F-384F200EP / SAK-TC1791S-384F200EP.  
Table 42  
ERAY Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
Time span from last BSS  
to FES without the  
t
60 CC  
997.75 −  
1002.2 ns  
5
influence of quartz  
tolerancies (d10Bit_TX)1)  
TxD data valid from  
fsample flip flop txd_reg  
TxDA, TxDB  
t61-t62  
CC  
1.5  
ns  
Asymmetrical  
delay of rising  
and falling edge  
(TxDA, TxDB)  
(dTxAsym)2)3)  
Time span between last  
BSS and FES without  
influence of quartz  
tolerancies  
t
63 SR  
966  
1046.1 ns  
(d10Bit_RX)1)4)5)  
RxD capture by fsample  
(RxDA/RxDB sampling  
flip-flop) (dRxAsym)6)  
t64-t65  
CC  
3.0  
ns  
Asymmetrical  
delay of rising  
and falling edge  
(RxDA, RxDB)  
TxD data delay from  
sampling flip-flop  
dTxdly  
CC  
10.0  
15.0  
10.0  
ns  
ns  
ns  
Px_PDR.PDy =  
000B  
Px_PDR.PDy =  
001B  
RxD capture delay by  
sampling flip-flop  
dRxdly  
CC  
1) This includes the PLL_ERAY accumulated jitter.  
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.  
Quarz tolerance and PLL_ERAY accumulated jitter are not included.  
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| 1 ns.  
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input  
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.  
Data Sheet  
135  
V 1.1, 2014-05  
TC1791  
Electrical ParametersFlash Memory Parameters  
5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the  
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming  
signal have to satisfy the following inequality: -1.6ns tFA2 - tRA2 1.3ns.  
6) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the  
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming  
signal have to satisfy the following inequality: -1.6ns tFA2 - tRA2 1.3ns.  
Last CRC Byte  
BSS  
FES  
(Byte Start Sequence)  
(Frame End Sequence)  
0.7 VDD  
0.3 VDD  
TXD  
t60  
tsample  
0.9 VDD  
0.1 VDD  
TXD  
t61  
t62  
Last CRC Byte  
BSS  
FES  
(Byte Start Sequence)  
(Frame End Sequence)  
0.7 VDD  
0.3 VDD  
RXD  
t63  
tsample  
0.7 VDD  
0.3 VDD  
RXD  
t64  
t65  
ERAY_TIMING  
Figure 25  
5.4  
ERAY Timing  
Flash Memory Parameters  
The data retention time of the TC1791’s Flash memory depends on the number of times  
the Flash memory has been erased and programmed.  
Data Sheet  
136  
V 1.1, 2014-05  
TC1791  
Electrical ParametersFlash Memory Parameters  
Table 43  
FLASH32 Parameters  
Symbol  
Parameter  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
4.21)  
Data Flash Erase Time  
per Sector  
t
t
ERD CC  
ERP CC  
s
s
Program Flash Erase  
Time per 256 KByte  
Sector  
5
Program time data flash  
per page2)  
t
t
PRD CC  
5.3  
ms  
ms  
without  
reprogramming  
15.9  
with two  
reprogramming  
cycles  
Program time program  
flash per page3)  
PRP CC  
5.3  
ms  
ms  
without  
reprogramming  
10.6  
with one  
reprogramming  
cycle  
Data Flash Endurance  
Erase suspend delay  
NE CC 60000  
cycle Min. data  
4)  
s
retention time 5  
years  
tFL_ErSusp  
15  
ms  
μs  
CC  
Wait time after margin  
change  
tFL_Margin 10  
Del CC  
Program Flash Retention  
Time, Physical Sector5)6)  
t
t
t
t
RET CC 20  
RETL CC 20  
RTU CC 20  
year Max. 1000  
erase/program  
cycles  
year Max. 100  
erase/program  
cycles  
year Max. 4  
s
Program Flash Retention  
Time, Logical Sector5)6)  
s
UCB Retention Time5)6)  
s
erase/program  
cycles per UCB  
Wake-Up time  
WU CC  
270  
μs  
Data Sheet  
137  
V 1.1, 2014-05  
TC1791  
Electrical ParametersFlash Memory Parameters  
Table 43  
FLASH32 Parameters (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note /  
Test Condition  
Min.  
Max.  
DFlash wait state  
configuration  
WSDF  
CC  
50 ns x  
fFSI  
PFlash wait state  
configuration  
WSPF  
CC  
26 ns x  
fFSI  
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can  
increase by up to 100%.  
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each  
reprogramming takes additional 5 ms.  
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The  
reprogramming takes additional 5 ms.  
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.  
5) Storage and inactive time included.  
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature  
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is  
minimum 0.7 years.  
Data Sheet  
138  
V 1.1, 2014-05  
TC1791  
Electrical ParametersPackage and Reliability  
5.5  
Package and Reliability  
5.5.1  
Package Parameters  
Table 44  
Device  
Thermal Characteristics of the Package  
1)  
1)  
Package  
RΘJCT  
RΘJCB  
RΘJA  
Unit  
Note  
TC1791  
PG-LFBGA- 292-6  
3,73  
4,98  
15,0  
K/W  
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined  
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate  
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between  
the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are  
under user responsibility.  
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA  
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance  
RTJA can be obtained from the upper four partial thermal resistances.  
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).  
Data Sheet  
139  
V 1.1, 2014-05  
TC1791  
Electrical ParametersPackage and Reliability  
5.5.2  
Package Outline  
292x  
0.5 ±0 .0 5  
M
0.15  
0.08  
C
C
A B  
1.7 MAX  
0.1 C  
17 ±0.1  
M
B
A
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
CODE  
8
7
292 x  
0.15  
6
5
4
3
COPLANARITY  
2
1
Y W V U T R P N ML  
K J HG F E D C B A  
INDEX  
INDEX MARKING  
(LASERED )  
0.8  
MARKING  
19 x 0.8 = 15.2  
C
0.33 MIN  
STANDOFF  
Figure 26  
Package Outlines PG-LFBGA- 292-6  
You can find all of our packages, sorts of packing and others in our Infineon Internet  
Page “Products”: http://www.infineon.com/products.  
5.5.3  
Quality Declarations  
Table 45  
Quality Parameters  
Symbol  
Parameter  
Values  
Unit Note / Test Condition  
Min. Typ. Max.  
Operation  
Lifetime1)  
tOP  
24000 hours –2)  
ESD susceptibility VHBM  
according to  
Human Body  
2000  
500  
V
V
Conforming to  
JESD22-A114-B  
Model (HBM)  
ESD susceptibility VHBM1  
of the LVDS pins  
Data Sheet  
140  
V 1.1, 2014-05  
TC1791  
Electrical ParametersPackage and Reliability  
Table 45  
Quality Parameters  
Symbol  
Parameter  
Values  
Unit Note / Test Condition  
Min. Typ. Max.  
ESD susceptibility VCDM  
according to  
500  
V
Conforming to  
JESD22-C101-C  
Charged Device  
Model (CDM)  
Moisture  
Sensitivity Level  
MSL  
3
Conforming to Jedec  
J-STD-020C for 240°C  
1) This lifetime refers only to the time when the device is powered on.  
2)For worst-case temperature profile equivalent to:  
1200 hours at Tj = 125...150oC  
3600 hours at Tj = 110...125oC  
7200 hours at Tj = 100...110oC  
11000 hours at Tj = 25...100oC  
1000 hours at Tj = -40...25oC  
Data Sheet  
141  
V 1.1, 2014-05  
TC1791  
History  
6
History  
The following changes where done between Version 0.6 and 0.62 of this document:  
add footnote to port 4.1 alternate output 3 MTSR2  
change function description for port 4.1 alternate output 3 MTSR2 from Slave to  
Master Transmit  
add footnote to port 6.4 alternate output 1 MTSR1  
add footnote to port 7.1 alternate output 2 MTSR3  
change for port 8.3 the symbol from OUT43 (GPTA1) to CC62 (CCU60)  
change for port 17 the type from S to D / S  
add clarification that table 11 defines the conditions for all other parameters  
add conditions for MLI, MSC, SSC, parameters  
add parameters dTxdly and dRxdly to ERAY parameters  
correct footnotes for ERAY parameters  
split flash parameters tPRD and tPRP in two conditions  
add conditions to LVDS pad parameters  
remove Pin Reliability in Overload section  
add parameters IIN and Sum IIN to absolute ratings  
add parameter HYSX to PSC_XTAL  
added RDSON values for all driver settings (weak, medium, and strong)  
removed footnote 2 of table 10  
change load for timing of SSC, MSC, and MLI from CL = 25 pF to CL = 50 pF (typical)  
add to parameters tRF and tFF condition CL = 50 pF  
add new footnote 7) to ADC parameter table  
add min and max value for QCONV and adapt typ value  
add load conditions for tFF1 and tRF1  
add conditions to PLL parameter tL  
change DAP parameter t19 from SR to CC classification  
remove footnote 2 for the FADC  
adapt IDs for AB step  
removed footnote 2 in table 11  
change max value for ADC parameter tS from 255 to 257  
switch input function ECTT1 and ECTT2  
add input function REQ15 to P9.14  
add alternate output O1 for OUT97 of GPTA0  
changed the name for O3 from EVTO2 to EVTO1 for P0.5  
changed the name for O3 from EVTO3 to EVTO2 for P0.6  
changed the name for O3 from EVTO4 to EVTO3 for P0.7  
add input function SLSI2 for SSC2 to P4.9  
The following changes where done between Version 0.62 and 0.63 of this document:  
Data Sheet  
1
V 1.1, 2014-05  
TC1791  
History  
switch input function ECTT1 and ECTT2  
add input function REQ15 to P9.14  
add alternate output O1 for OUT97 of GPTA0  
changed the name for O3 from EVTO2 to EVTO1 for P0.5  
changed the name for O3 from EVTO3 to EVTO2 for P0.6  
changed the name for O3 from EVTO4 to EVTO3 for P0.7  
add input function SLSI2 for SSC2 to P4.9  
change for port 6.15 the symbol from CC61(CCU60) to CC60(CCU61)  
change for port 8.2 the symbol from CC61(CCU60) to COUT63(CCU61)  
add to all SSC signal the assosiated SSC module where is was missing in the pinning  
add section Pin Reliability in Overload  
incease values for absolute maximium parameters IIN and SumIIN  
correct P14.8 O2 as this was incorrected label as O1  
add to P4.9 output function OUT1 for LTCA2  
The following changes where done between Version 0.63 and 0.7 of this document:  
update value of RTID registers in section Identification Registers for AB step  
remove sentence ‘Exposure to conditions within the maximum ratings will not affect  
device reliability. To replace this sentence section Pin Reliability in Overload was  
added.  
add footnote 1 to table 12 (Operating Conditions)  
increase values for absolute maximum parameters IIN and SumIIN  
remove capacitance conditions for LVDS pad parameters as loads are defined by  
interface (MSC) timings  
add parameter VILSD for class S pads  
add VDDM supply limitation for class S parameters  
add footnote 10 to table 23 (ADC parameters)  
remove old footnote 2 from table 24 (FADC parameters)  
remove term typical from load of Peripheral Timings  
add definition of driver strength settings for ERAY Interface Timing  
update formulas for frequency modulation  
change SSC parameter from t59 CC to SR  
change footnote 4 wording for ERAY timing back to TC1797 wording  
increase flash parameters tPRD and tPRP values  
increase flash parameter tERD  
add section 5.2.6.1.  
change in legende of table 2 definition of class S pad  
correct section Extended Range Operating Conditions for the 3.3 V area  
increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours  
specify wording for limitation of pad performance in section Extended Range  
Operating Conditions  
remove incorrect test conditions for RDSONx parameters  
adjust typo in temperature profile  
Data Sheet  
2
V 1.1, 2014-05  
TC1791  
History  
removed RDSON parameters for class F pads weak driver as only medium is  
available  
add parameter fSYSD for the SYSPLL  
update all current values of table 28 (Power Supply Parameters)  
rework the 3.3 V current part of the Power Supply Parameters for better description  
and usage  
– Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following  
way  
IDDP_FP is replaced by IDDP with the condition including flash programming current  
IDDFL3E is replaced by IDDP with the condition including flash erase verify current  
IDDFL3R is replaced by IDDP with the condition including flash read current  
– parameter IDDFL3R was renamed to IDDFL3  
The rework of the 3.3 V current part of the Power Supply Parameters was done for  
simplification and clarification. Former given values could still be used if liked, the new  
definition results in the same resulting values or slightly better values. The flash module  
is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case  
different allocations for the two domains resulting.  
The application typical case ‘flash read’ has max IDDP of 25 mA and max IDDFL3 of 98 mA  
resulting is a sum of 123 mA.  
The case ‘flash programming’ has max IDDP of 55 mA and max IDDFL3 of 29 mA resulting  
is a sum of 84 mA.  
The case ‘flash erase verify’ has max IDDP of 40 mA and max IDDFL3 of 98 mA resulting  
is a sum of 138 mA.  
So for the old parameter IDDP with 35 mA, the new version reads as  
I
DDP = 25+IDDP_PORST = 32 mA for the same application relevant case.  
The following changes where done between Version 0.7 and 1.0 of this document:  
add product options SAK-TC1791S-512F240EP, SAK-TC1791S-384F200EP, and  
SAK-TC1791N-384F200EP  
update block diagrams to cover new options  
add note to TC1791 Logic Symbol figure and pin list for E-RAY pins availability  
add identification registers for new options  
adapt Absolute Maximum Rating  
clarify pad supply levels in Pin Reliability in Overload section  
correct errors for analog inputs in tables 12 and 13  
add note at the end of Pin Reliability in Overload section  
clarify wording for valid operating conditions  
add negative limit for class S pad leakage  
change description of parameter tCAL for the ADC  
update footnote 10 for the ADC  
split FADC DNL parameter into two conditions and change value for gain 4 and 8  
add footnote 5 to IDDP  
Data Sheet  
3
V 1.1, 2014-05  
TC1791  
History  
improve parameters IDDFL3  
add footnote for D-Flash currents in power section  
rework first sentence for chapter 5.3  
increase max values for parameter tB  
reduce min value for tL for both PLLs  
split fVCO for the system PLL into two conditions  
change formula 10  
add for MLI and SSC timing parameter: valid strong driver medium edge only  
change MLI parameter t17 min value  
update parameter description for SSC parameters t52, t53, t56, t57, t58, and t59  
change SSC parameters from CC to SR Symbol for t56, t57, t58 and t59  
add note to ERAY parameters for availability  
add footnote to Flash parameter tERD  
change for parameter NE note from Max. data retention to Min.  
The following changes where done between Version 1.0 and 1.1 of this document:  
remove the following product options:  
– SAK-TC1791N-384F200EL  
change VILS from 2.1V to 1.9V in table 25  
change t48 from 100ns to 200ns in table 40  
change t49 from 100ns to 200ns in table 40  
extend KOVAN conditon from IOV0 mA; IOV-1 mA to IOV0 mA; IOV-2 mA  
change package version from PG-LFBGA-292-3 to PG-LFBGA-292-6  
Data Sheet  
4
V 1.1, 2014-05  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  

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